content stringlengths 1 1.04M ⌀ |
|---|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/24/2017 06:40:21 PM
-- Design Name:
-- Module Name: DemoInterconnect_TestBench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
package fifo_pkg is
end package;
PACKAGE fifo_pkg is
end package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:37 11/17/2016
-- Design Name:
-- Module Name: DMA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
... |
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <dl3yc@darc.de>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with some test cases
-- - known bug: don't use the phase!
--
-- !!! because o... |
-- AMBA settings
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
const... |
-- AMBA settings
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
const... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOW... |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOW... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
-- Used only for midi_note_t and midi_note_arr_t
use virtual_button_lib.midi_pkg.all;
-- Used for sine_addr_max
use virtual_... |
library ieee;
use ieee.std_logic_1164.all;
entity Mux32to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 dow... |
------------------------------------------------------------------------------
---- ----
---- 64 bits clock counter ----
---- ----
----... |
-- file: clk_video.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not ... |
ENTITY CHIP9684 IS
PORT(SIGNAL_IN9685 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9686 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9687 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9688 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9689 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9690 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9691... |
-- $Id: pdp11_dmpcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmpcnt - syn
-- Description: pdp11:... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--mu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--mu... |
-- NEED RESULT: ARCH00019: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00019... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package vga_counter_comp is
type vga_counter_out_t is
record
sync : std_logic;
enable : std_logic;
pix : natural;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:59:42 08/18/2010
-- Design Name:
-- Module Name: PCFG_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundati... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights re... |
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
ass... |
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
ass... |
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
ass... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-- *** bhe_comparator.vhd *** --
-- structural comparator as described in prof. Graziano documents
-- extended in order to handle both signed and unsigned comparisons
-- sum is computed outside of the comparator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bhe_comparator is
gener... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY FINAL IS
PORT(Clock,CLK,CLKBAT,CLR : IN STD_LOGIC;
scan_ready : IN STD_LOGIC;
SERVE1, SERVE2 : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 ... |
-------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
--------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
--------------------------------------... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:20:57 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_di
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
architecture RTL of FIFO is
begin
process
begin
LOOP_LABEL: loop end loop;
LOOP_LABEL: while condition loop end loop;
LOOP_LABEL: for x in range(15 downto 0) loop end loop;
LOOP_LABEL:
loop end loop;
LOOP_LABEL:
while condition loop end loop;
LOOP_LABEL:
for x in ... |
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : edit_msg.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created ... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k1_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: i... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
----------------------------------------------------------------------------------------------------
-- TOP LEVEL ENTITY - ECDSA
-- FPDA implementation of ECDSA algorithm
--
-- Ports:
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 02.07.2017
-- Last Change: 10.11.2017
---------... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_406;
architecture augh of cmp_406 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_406;
architecture augh of cmp_406 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity motores is
Port ( CLK : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (0 downto 3);
Entrada : in STD_LOGIC);
end motores;
architecture Behavioral of motores is
begin
end Behavioral;
|
--比较两个二进制数是否相等
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COMPARE IS
PORT(A,B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EQ:OUT STD_LOGIC);
END ENTITY COMPARE;
ARCHITECTURE ART OF COMPARE IS
BEGIN
EQ<='1' WHEN A=B ELSE '0';
END ARCHITECTURE ART; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use ... |
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