content stringlengths 1 1.04M ⌀ |
|---|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
begin
return "" & std_logic'image(sl)(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
begin
return "" & std_logic'image(sl)(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
begin
return "" & std_logic'image(sl)(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_03 is
end entity ch_03_03;
architecture test of ch_03_03 is
begin
process_3_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_3_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_3_1_c;
begin
mode := immediate;
procedure_3_1_c;
mode := other_mode;
opcode := load;
procedure_3_1_c;
opcode := add;
procedure_3_1_c;
opcode := subtract;
procedure_3_1_c;
opcode := other_opcode;
procedure_3_1_c;
wait;
end process process_3_1_c;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_03 is
end entity ch_03_03;
architecture test of ch_03_03 is
begin
process_3_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_3_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_3_1_c;
begin
mode := immediate;
procedure_3_1_c;
mode := other_mode;
opcode := load;
procedure_3_1_c;
opcode := add;
procedure_3_1_c;
opcode := subtract;
procedure_3_1_c;
opcode := other_opcode;
procedure_3_1_c;
wait;
end process process_3_1_c;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_03 is
end entity ch_03_03;
architecture test of ch_03_03 is
begin
process_3_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_3_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_3_1_c;
begin
mode := immediate;
procedure_3_1_c;
mode := other_mode;
opcode := load;
procedure_3_1_c;
opcode := add;
procedure_3_1_c;
opcode := subtract;
procedure_3_1_c;
opcode := other_opcode;
procedure_3_1_c;
wait;
end process process_3_1_c;
end architecture test;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/24/2017 06:40:21 PM
-- Design Name:
-- Module Name: DemoInterconnect_TestBench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DemoInterconnect_TestBench is
Generic(
CLKFREQ : integer := 72000000;
UARTFREQ : integer := 12000000;
SYSCLK_PERIOD : time := 83.333 ns; -- 12MHZ
BAUD_RATE : integer := 115200;
TRACE_DLY : time := 3 ns
);
Port (
UART_TX_0_wire : out STD_LOGIC;
UART_TX_1_wire : out STD_LOGIC;
spi_0_mosi_wire : out STD_LOGIC;
spi_0_sck_wire : out STD_LOGIC;
spi_0_ss_wire : out STD_LOGIC;
spi_1_mosi_wire : out STD_LOGIC;
spi_1_sck_wire : out STD_LOGIC;
spi_1_ss_wire : out STD_LOGIC;
spi_2_mosi_wire : out STD_LOGIC;
spi_2_sck_wire : out STD_LOGIC;
spi_2_ss_wire : out STD_LOGIC;
spi_3_mosi_wire : out STD_LOGIC;
spi_3_sck_wire : out STD_LOGIC;
spi_3_ss_wire : out STD_LOGIC
);
end DemoInterconnect_TestBench;
architecture Behavioral of DemoInterconnect_TestBench is
--comopennt declaration
component DemoInterconnect_wrapper is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
end component;
component parallel2serial is
generic (
DATA_WIDTH : integer := 8;
TX_WIDTH : integer := 1
);
port (
clk_i : in std_logic;
en_i : in std_logic;
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(TX_WIDTH-1 downto 0);
ss_o : out std_logic
) ;
end component;
component UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end component;
--constant declaration
constant c_CLKS_PER_BIT : integer := CLKFREQ/BAUD_RATE; -- Needs to be set correctly
--signal declaration
signal SYSCLK : std_logic := '0';
signal AXICLK : std_logic := '0';
signal UARTCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal UART_RX_0_wire, UART_RX_1_wire : std_logic := 'Z';
signal spi_0_miso_wire, spi_1_miso_wire, spi_2_miso_wire, spi_3_miso_wire : STD_LOGIC := 'Z';
signal dest_address : unsigned(4 downto 0) := (others=>'0'); --5bits
signal dest_data : unsigned(31 downto 0) := (others=>'0'); --32bits
signal dest_ctrl : std_logic_vector(2 downto 0) := "011"; --3bits
signal master_packet : std_logic_vector(39 downto 0) := (others=>'0'); --40bits
signal master_packet_send_en : std_logic := '0';
signal p2s_en, p2s_send, p2s_busy, p2s_done, p2s_ss : std_logic := '0';
signal uart_tx_en, uart_tx_done, uart_tx_active : std_logic := '0';
signal uart_tx_byte : std_logic_vector(7 downto 0) := (others=>'0');
signal resetn_ext_logic : std_logic := '1';
constant slave_0_addr : unsigned(4 downto 0) := "00000";
constant slave_1_addr : unsigned(4 downto 0) := "00001";
constant slave_2_addr : unsigned(4 downto 0) := "00010";
constant slave_3_addr : unsigned(4 downto 0) := "00011";
begin
drive_miso: process(dest_address)
begin
spi_0_miso_wire <= SYSCLK;
spi_1_miso_wire <= SYSCLK;
spi_2_miso_wire <= SYSCLK;
spi_3_miso_wire <= SYSCLK;
end process;
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
--Address Generator
addr_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
dest_address <= (others=>'0');
elsif (p2s_done = '1') then
if (dest_address = slave_0_addr) then
dest_address <= slave_1_addr;
elsif (dest_address = slave_1_addr) then
dest_address <= slave_2_addr;
elsif (dest_address = slave_2_addr) then
dest_address <= slave_3_addr;
else
dest_ctrl(2) <= not(dest_ctrl(2));
dest_address <= slave_0_addr;
end if;
end if;
end if;
end process;
--Data Generator
data_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
dest_data <= X"4433_2211";
else
dest_data <= X"4433_2211";
end if;
end if;
end process;
--Packet generate
packet_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
master_packet <= (others=>'0');
else
master_packet <= dest_ctrl & std_logic_vector(dest_address) & std_logic_vector(dest_data);
end if;
end if;
end process;
--Send packet
send_packet: process(AXICLK)
variable send_delay_countdown : integer := 32;
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
master_packet_send_en <= '0';
p2s_en <= '0';
else
if (master_packet_send_en='0' and p2s_en='0' and p2s_busy='0' and uart_tx_active='0' and uart_tx_en='0') then
if (send_delay_countdown = 0) then
master_packet_send_en <= '1';
send_delay_countdown := 32;
else
send_delay_countdown := send_delay_countdown - 1;
end if;
else
master_packet_send_en <= '0';
end if;
if (master_packet_send_en = '1' and p2s_en='0' and p2s_busy='0' and uart_tx_en='0') then
p2s_en <= '1';
else
p2s_en <= '0';
end if;
end if;
end if;
end process;
--signal connection
p2s_send <= not(uart_tx_active) and not(uart_tx_en);
uart_tx_en <= not(p2s_ss);
UART_RX_1_wire <= 'Z';
--component instances
p2s_inst: parallel2serial
generic map(
DATA_WIDTH => 40,
TX_WIDTH => 8
)
port map(
clk_i => AXICLK,
en_i => p2s_en,
send_i => p2s_send,
data_i => master_packet,
busy_o => p2s_busy,
done_o => p2s_done,
shift_o => uart_tx_byte,
ss_o => p2s_ss
);
uart_tx_inst: uart_tx
generic map(
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map(
i_Clk => AXICLK,
i_TX_DV => uart_tx_en,
i_TX_Byte => uart_tx_byte,
o_TX_Active => uart_tx_active,
o_TX_Serial => UART_RX_0_wire,
o_TX_Done => uart_tx_done
);
DemoInterconnect_Inst: DemoInterconnect_wrapper
port map(
UART_RX_0 => UART_RX_0_wire,
UART_RX_1 => UART_RX_1_wire,
UART_TX_0 => UART_TX_0_wire,
UART_TX_1 => UART_TX_1_wire,
LED0_pll_aclk => AXICLK,
LED2_pll_lock => resetn_ext_logic,
LED1_pll_uart => UARTCLK,
m_spi_mosi => spi_0_mosi_wire,
m_spi_miso => spi_0_miso_wire,
m_spi_sclk => spi_0_sck_wire,
m_spi_ss => spi_0_ss_wire,
m_spi_mosi_1 => spi_1_mosi_wire,
m_spi_miso_1 => spi_1_miso_wire,
m_spi_sclk_1 => spi_1_sck_wire,
m_spi_ss_1 => spi_1_ss_wire,
m_spi_mosi_2 => spi_2_mosi_wire,
m_spi_miso_2 => spi_2_miso_wire,
m_spi_sclk_2 => spi_2_sck_wire,
m_spi_ss_2 => spi_2_ss_wire,
m_spi_mosi_3 => spi_3_mosi_wire,
m_spi_miso_3 => spi_3_miso_wire,
m_spi_sclk_3 => spi_3_sck_wire,
m_spi_ss_3 => spi_3_ss_wire,
sys_clk => SYSCLK,
sys_reset => not(NSYSRESET)
);
end Behavioral;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- SYM_DEC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The SYM_DEC module is a symbol decoder for the 2-byte
-- Aurora Lane. Its inputs are the raw data from the MGT.
-- It word-aligns the regular data and decodes all of the
-- Aurora control symbols. Its outputs are the word-aligned
-- data and signals indicating the arrival of specific
-- control characters.
--
-- This module supports Immediate Mode Native Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity SYM_DEC is
port (
-- RX_LL Interface
RX_PAD : out std_logic; -- LSByte is PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- Word aligned data from channel partner.
RX_PE_DATA_V : out std_logic; -- Data is valid data and not a control character.
RX_SCP : out std_logic; -- SCP symbol received.
RX_ECP : out std_logic; -- ECP symbol received.
RX_SNF : out std_logic; -- SNF symbol received.
RX_FC_NB : out std_logic_vector(0 to 3); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-- Lane Init SM Interface
DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
RX_SP : out std_logic; -- SP sequence received with positive or negative data.
RX_SPA : out std_logic; -- SPA sequence received.
RX_NEG : out std_logic; -- Intverted data for SP or SPA received.
-- Global Logic Interface
GOT_A : out std_logic_vector(0 to 1); -- A character received on indicated byte(s).
GOT_V : out std_logic; -- V sequence received.
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- Raw RX data from MGT.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Bits indicating which bytes are control characters.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Rx'ed a comma.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic
);
end SYM_DEC;
architecture RTL of SYM_DEC is
-- Parameter Declarations --
constant DLY : time := 1 ns;
constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B";
constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4";
constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A";
constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2";
constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C";
constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B";
constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5";
constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D";
constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3";
constant PAD_0 : std_logic_vector(0 to 3) := X"9";
constant PAD_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_0 : std_logic_vector(0 to 3) := X"5";
constant SCP_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_2 : std_logic_vector(0 to 3) := X"F";
constant SCP_3 : std_logic_vector(0 to 3) := X"B";
constant ECP_0 : std_logic_vector(0 to 3) := X"F";
constant ECP_1 : std_logic_vector(0 to 3) := X"D";
constant ECP_2 : std_logic_vector(0 to 3) := X"F";
constant ECP_3 : std_logic_vector(0 to 3) := X"E";
constant SNF_0 : std_logic_vector(0 to 3) := X"D";
constant SNF_1 : std_logic_vector(0 to 3) := X"C";
constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7";
constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E";
constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8";
-- External Register Declarations --
signal RX_PAD_Buffer : std_logic;
signal RX_PE_DATA_Buffer : std_logic_vector(0 to 15);
signal RX_PE_DATA_V_Buffer : std_logic;
signal RX_SCP_Buffer : std_logic;
signal RX_ECP_Buffer : std_logic;
signal RX_SNF_Buffer : std_logic;
signal RX_FC_NB_Buffer : std_logic_vector(0 to 3);
signal RX_SP_Buffer : std_logic;
signal RX_SPA_Buffer : std_logic;
signal RX_NEG_Buffer : std_logic;
signal GOT_A_Buffer : std_logic_vector(0 to 1);
signal GOT_V_Buffer : std_logic;
-- Internal Register Declarations --
signal left_aligned_r : std_logic;
signal previous_cycle_data_r : std_logic_vector(0 to 7);
signal previous_cycle_control_r : std_logic;
signal prev_beat_sp_r : std_logic;
signal prev_beat_spa_r : std_logic;
signal word_aligned_data_r : std_logic_vector(0 to 15);
signal word_aligned_control_bits_r : std_logic_vector(0 to 1);
signal rx_pe_data_r : std_logic_vector(0 to 15);
signal rx_pe_control_r : std_logic_vector(0 to 1);
signal rx_pad_d_r : std_logic_vector(0 to 1);
signal rx_scp_d_r : std_logic_vector(0 to 3);
signal rx_ecp_d_r : std_logic_vector(0 to 3);
signal rx_snf_d_r : std_logic_vector(0 to 1);
signal prev_beat_sp_d_r : std_logic_vector(0 to 3);
signal prev_beat_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_d_r : std_logic_vector(0 to 3);
signal rx_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_neg_d_r : std_logic_vector(0 to 1);
signal rx_spa_neg_d_r : std_logic_vector(0 to 1);
signal prev_beat_v_d_r : std_logic_vector(0 to 3);
signal prev_beat_v_r : std_logic;
signal rx_v_d_r : std_logic_vector(0 to 3);
signal got_a_d_r : std_logic_vector(0 to 3);
signal first_v_received_r : std_logic := '0';
-- Wire Declarations --
signal got_v_c : std_logic;
begin
RX_PAD <= RX_PAD_Buffer;
RX_PE_DATA <= RX_PE_DATA_Buffer;
RX_PE_DATA_V <= RX_PE_DATA_V_Buffer;
RX_SCP <= RX_SCP_Buffer;
RX_ECP <= RX_ECP_Buffer;
RX_SNF <= RX_SNF_Buffer;
RX_FC_NB <= RX_FC_NB_Buffer;
RX_SP <= RX_SP_Buffer;
RX_SPA <= RX_SPA_Buffer;
RX_NEG <= RX_NEG_Buffer;
GOT_A <= GOT_A_Buffer;
GOT_V <= GOT_V_Buffer;
-- Main Body of Code --
-- Word Alignment --
-- Determine whether the lane is aligned to the left byte (MS byte) or the
-- right byte (LS byte). This information is used for word alignment. To
-- prevent the word align from changing during normal operation, we do word
-- alignment only when it is allowed by the lane_init_sm.
process (USER_CLK)
variable vec : std_logic_vector(0 to 3);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then
vec := RX_CHAR_IS_COMMA & RX_CHAR_IS_K;
case vec is
when "1010" => left_aligned_r <= '1' after DLY;
when "0101" => left_aligned_r <= '0' after DLY;
when others => left_aligned_r <= left_aligned_r after DLY;
end case;
end if;
end if;
end process;
-- Store the LS byte from the previous cycle. If the lane is aligned on
-- the LS byte, we use it as the MS byte on the current cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_data_r(0) <= RX_DATA(7) after DLY;
previous_cycle_data_r(1) <= RX_DATA(6) after DLY;
previous_cycle_data_r(2) <= RX_DATA(5) after DLY;
previous_cycle_data_r(3) <= RX_DATA(4) after DLY;
previous_cycle_data_r(4) <= RX_DATA(3) after DLY;
previous_cycle_data_r(5) <= RX_DATA(2) after DLY;
previous_cycle_data_r(6) <= RX_DATA(1) after DLY;
previous_cycle_data_r(7) <= RX_DATA(0) after DLY;
end if;
end process;
-- Store the control bit from the previous cycle LS byte. It becomes the
-- control bit for the MS byte on this cycle if the lane is aligned to the
-- LS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_control_r <= RX_CHAR_IS_K(0) after DLY;
end if;
end process;
-- Select the word-aligned MS byte. Use the current MS byte if the data is
-- left-aligned, otherwise use the LS byte from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(0) <= RX_DATA(15) after DLY;
word_aligned_data_r(1) <= RX_DATA(14) after DLY;
word_aligned_data_r(2) <= RX_DATA(13) after DLY;
word_aligned_data_r(3) <= RX_DATA(12) after DLY;
word_aligned_data_r(4) <= RX_DATA(11) after DLY;
word_aligned_data_r(5) <= RX_DATA(10) after DLY;
word_aligned_data_r(6) <= RX_DATA(9) after DLY;
word_aligned_data_r(7) <= RX_DATA(8) after DLY;
else
word_aligned_data_r(0 to 7) <= previous_cycle_data_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte. Use the current LSByte if the data is
-- right-aligned, otherwise use the current MS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(8) <= RX_DATA(7) after DLY;
word_aligned_data_r(9) <= RX_DATA(6) after DLY;
word_aligned_data_r(10) <= RX_DATA(5) after DLY;
word_aligned_data_r(11) <= RX_DATA(4) after DLY;
word_aligned_data_r(12) <= RX_DATA(3) after DLY;
word_aligned_data_r(13) <= RX_DATA(2) after DLY;
word_aligned_data_r(14) <= RX_DATA(1) after DLY;
word_aligned_data_r(15) <= RX_DATA(0) after DLY;
else
word_aligned_data_r(8) <= RX_DATA(15) after DLY;
word_aligned_data_r(9) <= RX_DATA(14) after DLY;
word_aligned_data_r(10) <= RX_DATA(13) after DLY;
word_aligned_data_r(11) <= RX_DATA(12) after DLY;
word_aligned_data_r(12) <= RX_DATA(11) after DLY;
word_aligned_data_r(13) <= RX_DATA(10) after DLY;
word_aligned_data_r(14) <= RX_DATA(9) after DLY;
word_aligned_data_r(15) <= RX_DATA(8) after DLY;
end if;
end if;
end process;
-- Select the word-aligned MS byte control bit. Use the current MSByte's
-- control bit if the data is left-aligned, otherwise use the LS byte's
-- control bit from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(1) after DLY;
else
word_aligned_control_bits_r(0) <= previous_cycle_control_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte control bit. Use the current LSByte's control
-- bit if the data is left-aligned, otherwise use the current MS byte's control bit.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(0) after DLY;
else
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(1) after DLY;
end if;
end if;
end process;
-- Pipeline the word-aligned data for 1 cycle to match the Decodes.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_data_r <= word_aligned_data_r after DLY;
end if;
end process;
-- Register the pipelined word-aligned data for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_Buffer <= rx_pe_data_r after DLY;
end if;
end process;
-- Decode Control Symbols --
-- All decodes are pipelined to keep the number of logic levels to a minimum.
-- Delay the control bits: they are most often used in the second stage of
-- the decoding process.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_control_r <= word_aligned_control_bits_r after DLY;
end if;
end process;
-- Decode PAD
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY;
rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PAD_Buffer <= std_bool((rx_pad_d_r = "11") and (rx_pe_control_r = "01")) after DLY;
end if;
end process;
-- Decode RX_PE_DATA_V
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_V_Buffer <= not rx_pe_control_r(0) after DLY;
end if;
end process;
-- Decode RX_SCP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY;
rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY;
rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY;
rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SCP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_scp_d_r(0) and
rx_scp_d_r(1) and
rx_scp_d_r(2) and
rx_scp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_ECP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY;
rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY;
rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY;
rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_ECP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_ecp_d_r(0) and
rx_ecp_d_r(1) and
rx_ecp_d_r(2) and
rx_ecp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_SNF
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_snf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SNF_0) after DLY;
rx_snf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SNF_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SNF_Buffer <= rx_pe_control_r(0) and
rx_snf_d_r(0) and
rx_snf_d_r(1) after DLY;
end if;
end process;
-- Extract the Flow Control Size code and register it for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_FC_NB_Buffer <= rx_pe_data_r(8 to 11) after DLY;
end if;
end process;
-- For an SP sequence to be valid, there must be 2 bytes of SP Data preceded
-- by a Comma and an SP Data byte in the MS byte and LS byte positions
-- respectively. This flop stores the decode of the Comma and SP Data byte
-- combination from the previous cycle. Data can be positive or negative.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_sp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
prev_beat_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_sp_d_r = "1111")) after DLY;
end if;
end process;
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
prev_beat_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_d_r(0) <= std_bool((word_aligned_data_r(0 to 3) = SP_DATA_0) or
(word_aligned_data_r(0 to 3) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(1) <= std_bool((word_aligned_data_r(4 to 7) = SP_DATA_1) or
(word_aligned_data_r(4 to 7) = SP_NEG_DATA_1)) after DLY;
rx_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SP_Buffer <= prev_beat_sp_r and
std_bool((rx_pe_control_r = "00") and
(rx_sp_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SPA_DATA_0) after DLY;
rx_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SPA_DATA_1) after DLY;
rx_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
rx_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SPA_Buffer <= prev_beat_spa_r and
std_bool((rx_pe_control_r = "00") and
(rx_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate reversed data received. We look only at the word-aligned LS byte
-- which, during an /SP/ or /SPA/ sequence, will always contain a data byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY;
rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY;
rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY;
rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_NEG_Buffer <= not rx_pe_control_r(1) and
std_bool((rx_sp_neg_d_r = "11") or
(rx_spa_neg_d_r = "11")) after DLY;
end if;
end process;
-- GOT_A is decoded from the non_word-aligned input.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
got_a_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = A_CHAR_0) after DLY;
got_a_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = A_CHAR_1) after DLY;
got_a_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = A_CHAR_0) after DLY;
got_a_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = A_CHAR_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_A_Buffer(0) <= rx_pe_control_r(0) and std_bool(got_a_d_r(0 to 1) = "11") after DLY;
GOT_A_Buffer(1) <= rx_pe_control_r(1) and std_bool(got_a_d_r(2 to 3) = "11") after DLY;
end if;
end process;
-- Verification symbol decode --
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
prev_beat_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_v_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = VER_DATA_0) after DLY;
rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = VER_DATA_1) after DLY;
rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
got_v_c <= prev_beat_v_r and
std_bool((rx_pe_control_r = "00") and
(rx_v_d_r = "1111"));
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_V_Buffer <= got_v_c after DLY;
end if;
end process;
-- Remember that the first V sequence has been detected.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
first_v_received_r <= '0' after DLY;
else
if (got_v_c = '1') then
first_v_received_r <= '1' after DLY;
end if;
end if;
end if;
end process;
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- SYM_DEC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The SYM_DEC module is a symbol decoder for the 2-byte
-- Aurora Lane. Its inputs are the raw data from the MGT.
-- It word-aligns the regular data and decodes all of the
-- Aurora control symbols. Its outputs are the word-aligned
-- data and signals indicating the arrival of specific
-- control characters.
--
-- This module supports Immediate Mode Native Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity SYM_DEC is
port (
-- RX_LL Interface
RX_PAD : out std_logic; -- LSByte is PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- Word aligned data from channel partner.
RX_PE_DATA_V : out std_logic; -- Data is valid data and not a control character.
RX_SCP : out std_logic; -- SCP symbol received.
RX_ECP : out std_logic; -- ECP symbol received.
RX_SNF : out std_logic; -- SNF symbol received.
RX_FC_NB : out std_logic_vector(0 to 3); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-- Lane Init SM Interface
DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
RX_SP : out std_logic; -- SP sequence received with positive or negative data.
RX_SPA : out std_logic; -- SPA sequence received.
RX_NEG : out std_logic; -- Intverted data for SP or SPA received.
-- Global Logic Interface
GOT_A : out std_logic_vector(0 to 1); -- A character received on indicated byte(s).
GOT_V : out std_logic; -- V sequence received.
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- Raw RX data from MGT.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Bits indicating which bytes are control characters.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Rx'ed a comma.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic
);
end SYM_DEC;
architecture RTL of SYM_DEC is
-- Parameter Declarations --
constant DLY : time := 1 ns;
constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B";
constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4";
constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A";
constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2";
constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C";
constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B";
constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5";
constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D";
constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3";
constant PAD_0 : std_logic_vector(0 to 3) := X"9";
constant PAD_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_0 : std_logic_vector(0 to 3) := X"5";
constant SCP_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_2 : std_logic_vector(0 to 3) := X"F";
constant SCP_3 : std_logic_vector(0 to 3) := X"B";
constant ECP_0 : std_logic_vector(0 to 3) := X"F";
constant ECP_1 : std_logic_vector(0 to 3) := X"D";
constant ECP_2 : std_logic_vector(0 to 3) := X"F";
constant ECP_3 : std_logic_vector(0 to 3) := X"E";
constant SNF_0 : std_logic_vector(0 to 3) := X"D";
constant SNF_1 : std_logic_vector(0 to 3) := X"C";
constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7";
constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E";
constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8";
-- External Register Declarations --
signal RX_PAD_Buffer : std_logic;
signal RX_PE_DATA_Buffer : std_logic_vector(0 to 15);
signal RX_PE_DATA_V_Buffer : std_logic;
signal RX_SCP_Buffer : std_logic;
signal RX_ECP_Buffer : std_logic;
signal RX_SNF_Buffer : std_logic;
signal RX_FC_NB_Buffer : std_logic_vector(0 to 3);
signal RX_SP_Buffer : std_logic;
signal RX_SPA_Buffer : std_logic;
signal RX_NEG_Buffer : std_logic;
signal GOT_A_Buffer : std_logic_vector(0 to 1);
signal GOT_V_Buffer : std_logic;
-- Internal Register Declarations --
signal left_aligned_r : std_logic;
signal previous_cycle_data_r : std_logic_vector(0 to 7);
signal previous_cycle_control_r : std_logic;
signal prev_beat_sp_r : std_logic;
signal prev_beat_spa_r : std_logic;
signal word_aligned_data_r : std_logic_vector(0 to 15);
signal word_aligned_control_bits_r : std_logic_vector(0 to 1);
signal rx_pe_data_r : std_logic_vector(0 to 15);
signal rx_pe_control_r : std_logic_vector(0 to 1);
signal rx_pad_d_r : std_logic_vector(0 to 1);
signal rx_scp_d_r : std_logic_vector(0 to 3);
signal rx_ecp_d_r : std_logic_vector(0 to 3);
signal rx_snf_d_r : std_logic_vector(0 to 1);
signal prev_beat_sp_d_r : std_logic_vector(0 to 3);
signal prev_beat_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_d_r : std_logic_vector(0 to 3);
signal rx_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_neg_d_r : std_logic_vector(0 to 1);
signal rx_spa_neg_d_r : std_logic_vector(0 to 1);
signal prev_beat_v_d_r : std_logic_vector(0 to 3);
signal prev_beat_v_r : std_logic;
signal rx_v_d_r : std_logic_vector(0 to 3);
signal got_a_d_r : std_logic_vector(0 to 3);
signal first_v_received_r : std_logic := '0';
-- Wire Declarations --
signal got_v_c : std_logic;
begin
RX_PAD <= RX_PAD_Buffer;
RX_PE_DATA <= RX_PE_DATA_Buffer;
RX_PE_DATA_V <= RX_PE_DATA_V_Buffer;
RX_SCP <= RX_SCP_Buffer;
RX_ECP <= RX_ECP_Buffer;
RX_SNF <= RX_SNF_Buffer;
RX_FC_NB <= RX_FC_NB_Buffer;
RX_SP <= RX_SP_Buffer;
RX_SPA <= RX_SPA_Buffer;
RX_NEG <= RX_NEG_Buffer;
GOT_A <= GOT_A_Buffer;
GOT_V <= GOT_V_Buffer;
-- Main Body of Code --
-- Word Alignment --
-- Determine whether the lane is aligned to the left byte (MS byte) or the
-- right byte (LS byte). This information is used for word alignment. To
-- prevent the word align from changing during normal operation, we do word
-- alignment only when it is allowed by the lane_init_sm.
process (USER_CLK)
variable vec : std_logic_vector(0 to 3);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then
vec := RX_CHAR_IS_COMMA & RX_CHAR_IS_K;
case vec is
when "1010" => left_aligned_r <= '1' after DLY;
when "0101" => left_aligned_r <= '0' after DLY;
when others => left_aligned_r <= left_aligned_r after DLY;
end case;
end if;
end if;
end process;
-- Store the LS byte from the previous cycle. If the lane is aligned on
-- the LS byte, we use it as the MS byte on the current cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_data_r(0) <= RX_DATA(7) after DLY;
previous_cycle_data_r(1) <= RX_DATA(6) after DLY;
previous_cycle_data_r(2) <= RX_DATA(5) after DLY;
previous_cycle_data_r(3) <= RX_DATA(4) after DLY;
previous_cycle_data_r(4) <= RX_DATA(3) after DLY;
previous_cycle_data_r(5) <= RX_DATA(2) after DLY;
previous_cycle_data_r(6) <= RX_DATA(1) after DLY;
previous_cycle_data_r(7) <= RX_DATA(0) after DLY;
end if;
end process;
-- Store the control bit from the previous cycle LS byte. It becomes the
-- control bit for the MS byte on this cycle if the lane is aligned to the
-- LS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_control_r <= RX_CHAR_IS_K(0) after DLY;
end if;
end process;
-- Select the word-aligned MS byte. Use the current MS byte if the data is
-- left-aligned, otherwise use the LS byte from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(0) <= RX_DATA(15) after DLY;
word_aligned_data_r(1) <= RX_DATA(14) after DLY;
word_aligned_data_r(2) <= RX_DATA(13) after DLY;
word_aligned_data_r(3) <= RX_DATA(12) after DLY;
word_aligned_data_r(4) <= RX_DATA(11) after DLY;
word_aligned_data_r(5) <= RX_DATA(10) after DLY;
word_aligned_data_r(6) <= RX_DATA(9) after DLY;
word_aligned_data_r(7) <= RX_DATA(8) after DLY;
else
word_aligned_data_r(0 to 7) <= previous_cycle_data_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte. Use the current LSByte if the data is
-- right-aligned, otherwise use the current MS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(8) <= RX_DATA(7) after DLY;
word_aligned_data_r(9) <= RX_DATA(6) after DLY;
word_aligned_data_r(10) <= RX_DATA(5) after DLY;
word_aligned_data_r(11) <= RX_DATA(4) after DLY;
word_aligned_data_r(12) <= RX_DATA(3) after DLY;
word_aligned_data_r(13) <= RX_DATA(2) after DLY;
word_aligned_data_r(14) <= RX_DATA(1) after DLY;
word_aligned_data_r(15) <= RX_DATA(0) after DLY;
else
word_aligned_data_r(8) <= RX_DATA(15) after DLY;
word_aligned_data_r(9) <= RX_DATA(14) after DLY;
word_aligned_data_r(10) <= RX_DATA(13) after DLY;
word_aligned_data_r(11) <= RX_DATA(12) after DLY;
word_aligned_data_r(12) <= RX_DATA(11) after DLY;
word_aligned_data_r(13) <= RX_DATA(10) after DLY;
word_aligned_data_r(14) <= RX_DATA(9) after DLY;
word_aligned_data_r(15) <= RX_DATA(8) after DLY;
end if;
end if;
end process;
-- Select the word-aligned MS byte control bit. Use the current MSByte's
-- control bit if the data is left-aligned, otherwise use the LS byte's
-- control bit from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(1) after DLY;
else
word_aligned_control_bits_r(0) <= previous_cycle_control_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte control bit. Use the current LSByte's control
-- bit if the data is left-aligned, otherwise use the current MS byte's control bit.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(0) after DLY;
else
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(1) after DLY;
end if;
end if;
end process;
-- Pipeline the word-aligned data for 1 cycle to match the Decodes.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_data_r <= word_aligned_data_r after DLY;
end if;
end process;
-- Register the pipelined word-aligned data for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_Buffer <= rx_pe_data_r after DLY;
end if;
end process;
-- Decode Control Symbols --
-- All decodes are pipelined to keep the number of logic levels to a minimum.
-- Delay the control bits: they are most often used in the second stage of
-- the decoding process.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_control_r <= word_aligned_control_bits_r after DLY;
end if;
end process;
-- Decode PAD
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY;
rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PAD_Buffer <= std_bool((rx_pad_d_r = "11") and (rx_pe_control_r = "01")) after DLY;
end if;
end process;
-- Decode RX_PE_DATA_V
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_V_Buffer <= not rx_pe_control_r(0) after DLY;
end if;
end process;
-- Decode RX_SCP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY;
rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY;
rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY;
rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SCP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_scp_d_r(0) and
rx_scp_d_r(1) and
rx_scp_d_r(2) and
rx_scp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_ECP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY;
rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY;
rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY;
rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_ECP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_ecp_d_r(0) and
rx_ecp_d_r(1) and
rx_ecp_d_r(2) and
rx_ecp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_SNF
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_snf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SNF_0) after DLY;
rx_snf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SNF_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SNF_Buffer <= rx_pe_control_r(0) and
rx_snf_d_r(0) and
rx_snf_d_r(1) after DLY;
end if;
end process;
-- Extract the Flow Control Size code and register it for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_FC_NB_Buffer <= rx_pe_data_r(8 to 11) after DLY;
end if;
end process;
-- For an SP sequence to be valid, there must be 2 bytes of SP Data preceded
-- by a Comma and an SP Data byte in the MS byte and LS byte positions
-- respectively. This flop stores the decode of the Comma and SP Data byte
-- combination from the previous cycle. Data can be positive or negative.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_sp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
prev_beat_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_sp_d_r = "1111")) after DLY;
end if;
end process;
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
prev_beat_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_d_r(0) <= std_bool((word_aligned_data_r(0 to 3) = SP_DATA_0) or
(word_aligned_data_r(0 to 3) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(1) <= std_bool((word_aligned_data_r(4 to 7) = SP_DATA_1) or
(word_aligned_data_r(4 to 7) = SP_NEG_DATA_1)) after DLY;
rx_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SP_Buffer <= prev_beat_sp_r and
std_bool((rx_pe_control_r = "00") and
(rx_sp_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SPA_DATA_0) after DLY;
rx_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SPA_DATA_1) after DLY;
rx_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
rx_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SPA_Buffer <= prev_beat_spa_r and
std_bool((rx_pe_control_r = "00") and
(rx_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate reversed data received. We look only at the word-aligned LS byte
-- which, during an /SP/ or /SPA/ sequence, will always contain a data byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY;
rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY;
rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY;
rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_NEG_Buffer <= not rx_pe_control_r(1) and
std_bool((rx_sp_neg_d_r = "11") or
(rx_spa_neg_d_r = "11")) after DLY;
end if;
end process;
-- GOT_A is decoded from the non_word-aligned input.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
got_a_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = A_CHAR_0) after DLY;
got_a_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = A_CHAR_1) after DLY;
got_a_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = A_CHAR_0) after DLY;
got_a_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = A_CHAR_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_A_Buffer(0) <= rx_pe_control_r(0) and std_bool(got_a_d_r(0 to 1) = "11") after DLY;
GOT_A_Buffer(1) <= rx_pe_control_r(1) and std_bool(got_a_d_r(2 to 3) = "11") after DLY;
end if;
end process;
-- Verification symbol decode --
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
prev_beat_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_v_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = VER_DATA_0) after DLY;
rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = VER_DATA_1) after DLY;
rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
got_v_c <= prev_beat_v_r and
std_bool((rx_pe_control_r = "00") and
(rx_v_d_r = "1111"));
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_V_Buffer <= got_v_c after DLY;
end if;
end process;
-- Remember that the first V sequence has been detected.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
first_v_received_r <= '0' after DLY;
else
if (got_v_c = '1') then
first_v_received_r <= '1' after DLY;
end if;
end if;
end if;
end process;
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2382.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02382ent IS
END c07s03b02x00p06n02i02382ent;
ARCHITECTURE c07s03b02x00p06n02i02382arch OF c07s03b02x00p06n02i02382ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', 6 | 5 | 4 | 3 | 2 | 1 | 0 => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 | 3 | 2 | 4 | 1 | 5 | 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 | 2 | 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 2 | 3 => '0', 0 downto 0 | 1 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '1' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02382"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02382 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02382arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2382.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02382ent IS
END c07s03b02x00p06n02i02382ent;
ARCHITECTURE c07s03b02x00p06n02i02382arch OF c07s03b02x00p06n02i02382ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', 6 | 5 | 4 | 3 | 2 | 1 | 0 => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 | 3 | 2 | 4 | 1 | 5 | 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 | 2 | 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 2 | 3 => '0', 0 downto 0 | 1 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '1' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02382"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02382 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02382arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2382.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02382ent IS
END c07s03b02x00p06n02i02382ent;
ARCHITECTURE c07s03b02x00p06n02i02382arch OF c07s03b02x00p06n02i02382ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', 6 | 5 | 4 | 3 | 2 | 1 | 0 => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 | 3 | 2 | 4 | 1 | 5 | 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 | 2 | 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 2 | 3 => '0', 0 downto 0 | 1 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '1' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02382"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '1' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02382 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02382arch;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package complex_const_mult_pkg is
/* function 1 */
/**************************************************************************************************/
--returns the output signals' low index, which is the lowest of the low indexes of the partial output signals
function complex_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
min_output_bit : integer_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer;
--returns the output signals' high index, which is the highest of the high indexes of the partial output signals
function complex_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
max_output_bit : integer_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body complex_const_mult_pkg is
/********************************************************************************************** 1 */
--returns the output signals' low index, which is the lowest of the low indexes of the partial output signals
function complex_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
min_output_bit : integer_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer is
variable result : integer := real_const_mult_OL(round_style_opt => round_style_opt,
round_to_bit_opt => round_to_bit_opt,
max_error_pct_opt => max_error_pct_opt,
constants => constants,
input_low => input_low,
is_signed => is_signed);
begin
if min_output_bit /= integer'low then
return maximum(result, min_output_bit);
else
return result;
end if;
end function;
--returns the output signals' high index, which is the highest of the high indexes of the partial output signals
function complex_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
max_output_bit : integer_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer is
variable result : integer := real_const_mult_OH(round_style_opt => round_style_opt,
round_to_bit_opt => round_to_bit_opt,
max_error_pct_opt => max_error_pct_opt,
constants => constants,
input_high => input_high,
input_low => input_low,
is_signed => is_signed);
begin
--if not (
-- (constants(0) = 0.0 and constants(1)>-1.0 and constants(1)<=1.0)
-- or
-- (constants(1) = 0.0 and constants(0)>-1.0 and constants(0)<=1.0)
-- )
--then
-- result := result + 1;
--end if;
if max_output_bit /= integer'low then
return minimum(result, max_output_bit);
else
return result;
end if;
end function;
end package body; |
package fifo_pkg is
end package;
PACKAGE fifo_pkg is
end package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:37 11/17/2016
-- Design Name:
-- Module Name: DMA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
RCVD_Data : in STD_LOGIC_VECTOR (7 downto 0);
RX_Full : in STD_LOGIC;
RX_Empty : in STD_LOGIC;
Data_Read : out STD_LOGIC;
ACK_out : in STD_LOGIC;
TX_RDY : in STD_LOGIC;
Valid_D : out STD_LOGIC;
TX_Data : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Write_en : out STD_LOGIC;
OE : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Send_comm : in STD_LOGIC;
READY : out STD_LOGIC;
FF_Count : in STD_LOGIC_VECTOR(5 downto 0));
end DMA;
architecture Behavioral of DMA is
type State is
(Idle, Tx, Wait_Buses, Rx);
signal current_state, next_state : State;
signal end_reception : STD_LOGIC;
signal begin_tx : STD_LOGIC;
component data_counter
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(2 downto 0));
end component;
signal reset_counter : STD_LOGIC;
signal enable_counter : STD_LOGIC;
signal count : STD_LOGIC_VECTOR (2 downto 0);
begin
-- Contador de bytes a transmitir o recibir
BitCounter: data_counter
port map (
clk => Clk,
reset => reset_counter,
enable => enable_counter,
count => count);
clock : process (Reset, Clk)
begin
if Reset = '0' then
current_state <= Idle;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
changes : process (clk, current_state, RX_Empty, Send_comm, DMA_ACK, end_reception, begin_tx, FF_Count)
begin
case current_state is
when Idle =>
-- Cuando hay tres bytes en la fifo, tomamos los buses y los guardamos en la ram
if FF_Count = "000011" then
next_state <= Wait_Buses;
elsif Send_comm = '1' then
next_state <= Tx;
else
next_state <= Idle;
end if;
-- Reception --
when Wait_Buses =>
if DMA_ACK = '1' then
next_state <= Rx;
else
next_state <= Wait_Buses;
end if;
when Rx =>
if DMA_ACK = '0' then
next_state <= Idle;
else
next_state <= Rx;
end if;
-- Transmission --
when Tx =>
if Send_comm = '0' then
next_state <= Idle;
else
next_State <= Tx;
end if;
end case;
end process;
outputs : process (current_state, RCVD_Data, Databus, Send_comm, count)
begin
Data_Read <= '0';
Valid_D <= '1';
Address <= (others => 'Z');
Databus <= (others => 'Z');
TX_Data <= (others => '0');
Write_en <= 'Z';
OE <= 'Z';
READY <= '1';
enable_counter <= '0';
reset_counter <= '1';
case current_state is
-- Reception --
when Idle =>
DMA_RQ <= '0';
if Send_comm = '1' then
READY <= not Send_comm;
end if;
when Wait_Buses =>
DMA_RQ <= '1';
when Rx =>
Databus <= RCVD_Data;
enable_counter <= '1';
reset_counter <= '0';
case count is
when "000" =>
Data_Read <= '1';
when "001" =>
Address <= DMA_RX_BUFFER_MSB;
DMA_RQ <= '1';
Data_Read <= '1';
Write_en <= '1';
when "010" =>
Address <= DMA_RX_BUFFER_MID;
DMA_RQ <= '1';
Data_Read <= '1';
Write_en <= '1';
when "011" =>
Address <= DMA_RX_BUFFER_LSB;
DMA_RQ <= '0';
Data_Read <= '1';
Write_en <= '1';
when others =>
enable_counter <= '0';
DMA_RQ <= '0';
end case;
--Transmission --
when Tx =>
Valid_D <= '0';
OE <= '0';
enable_counter <= '1';
reset_counter <= '0';
DMA_RQ <= '0';
case count is
when "000" =>
TX_Data <= Databus;
Address <= DMA_TX_BUFFER_MSB;
READY <= not Send_comm;
when "001" =>
TX_Data <= Databus;
Address <= DMA_TX_BUFFER_LSB;
READY <= '1';
when others =>
enable_counter <= '0';
end case;
when others =>
Data_Read <= '0';
Valid_D <= '1';
Address <= (others => 'Z');
Databus <= (others => 'Z');
TX_Data <= (others => '0');
Write_en <= 'Z';
OE <= 'Z';
DMA_RQ <= '0';
READY <= '1';
enable_counter <= '0';
reset_counter <= '1';
end case;
end process;
end Behavioral;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.avalon_mm_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity avalon_mm_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- Avalon MM address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- Avalon MM data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this AVALON_MM_VVCT instance
GC_AVALON_MM_CONFIG : t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
avalon_mm_vvc_master_if : inout t_avalon_mm_if := init_avalon_mm_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (avalon_mm_vvc_master_if.address'length = GC_ADDR_WIDTH) report "avalon_mm_vvc_master_if.address'length /= GC_ADDR_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.writedata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.writedata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.readdata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.readdata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.byte_enable'length = GC_DATA_WIDTH/8) report "avalon_mm_vvc_master_if.byte_enable'length /= GC_DATA_WIDTH/8" severity failure;
end entity avalon_mm_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of avalon_mm_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal read_response_is_busy : boolean := false;
signal response_queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal last_read_response_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of element dedicated Queues
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable command_response_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_avalon_mm_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_avalon_mm_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_avalon_mm_transaction_info(GC_INSTANCE_IDX);
-- Propagation delayed interface signal used when reading data from the slave in the read_response process.
signal avalon_mm_vvc_master_if_pd : t_avalon_mm_if(address(GC_ADDR_WIDTH-1 downto 0),
byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
writedata(GC_DATA_WIDTH-1 downto 0),
readdata(GC_DATA_WIDTH-1 downto 0)) := avalon_mm_vvc_master_if;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AVALON_MM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed,ID_IMMEDIATE_CMD_WAIT,ID_NEVER);
-- Await completion of all commands in the read_response queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_response_queue, vvc_config, read_response_is_busy, C_VVC_LABELS, last_read_response_idx_executed, ID_NEVER, ID_IMMEDIATE_CMD);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands.
-- - Note that the read response is handled in the read_response process.
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_byte_ena : std_logic_vector((GC_DATA_WIDTH/8)-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for insert_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = RESET then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_write() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_write() called with to wide data. " & v_cmd.msg);
if (v_cmd.byte_enable = (0 to v_cmd.byte_enable'length-1 => '1')) then
v_normalised_byte_ena := (others => '1');
else
v_normalised_byte_ena := normalize_and_check(v_cmd.byte_enable, v_normalised_byte_ena, ALLOW_WIDER_NARROWER, "v_cmd.byte_enable", "v_normalised_byte_ena", "avalon_mm_write() called with to wide byte_enable. " & v_cmd.msg);
end if;
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
transaction_info.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0) := v_cmd.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0);
-- Call the corresponding procedure in the BFM package.
avalon_mm_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
byte_enable => v_cmd.byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_read() called with to wide address. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Stall until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_read( addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data );
end if;
when CHECK =>
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_check() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Wait until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config,
ext_proc_call => "avalon_mm_check(A:" & to_string(v_normalised_addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(v_normalised_data, HEX, AS_IS, INCL_RADIX) & ")"
);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
end if;
when RESET =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_reset(clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
num_rst_cycles => v_cmd.gen_integer_array(0),
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when LOCK =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_lock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when UNLOCK =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_unlock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Add a delta cycle to the read response interface signals to avoid reading wrong data.
--===============================================================================================
avalon_mm_vvc_master_if_pd <= transport avalon_mm_vvc_master_if after std.env.resolution_limit;
--===============================================================================================
-- Read response command execution.
-- - READ (and CHECK) data received from the slave after the command executor has issued an
-- read request (or check).
-- - Note the use of propagation delayed avalon_mm_vv_master_if signal
--===============================================================================================
read_response : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Set the command response queue up to the same settings as the command queue
command_response_queue.set_scope(C_SCOPE & ":RQ");
command_response_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
command_response_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
command_response_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
wait for 0 ns; -- Wait for command response queue to initialize completely
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_response_queue, vvc_config, vvc_status, response_queue_is_increasing, read_response_is_busy, C_VVC_LABELS);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "Function called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "Function called with to wide data. " & v_cmd.msg);
case v_cmd.operation is
when READ =>
-- Initiate read response
avalon_mm_read_response(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Initiate check response
avalon_mm_check_response( addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
last_read_response_idx_executed <= v_cmd.cmd_idx;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end Case;
end process PROC_3;
end architecture ARCH;
|
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <dl3yc@darc.de>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with some test cases
-- - known bug: don't use the phase!
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of -99.7° to 99.7°
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q >= 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-2),P);-- 90°
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-2),P);-- -90°
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
-- AMBA settings
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
|
-- AMBA settings
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_m;
----------------
block_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_n;
----------------
stimulus_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_3_m_n;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_m;
----------------
block_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_n;
----------------
stimulus_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_3_m_n;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_m;
----------------
block_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_n;
----------------
stimulus_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_3_m_n;
end architecture test;
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- soma dos valores e propagação do carry --
Sum<=val1 xor val2;
Prop<=val1 or val2;
Gen<=val1 and val2;
PROCESS (Gen,Prop,Carry)
BEGIN
Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn);
inst: FOR i IN 1 TO 2 LOOP
Carry(i+1) <= Gen(i) OR (Prop(i) AND Carry(i));
END LOOP;
END PROCESS;
SomaResult(0) <= Sum(0) XOR CarryIn;
SomaResult(3 DOWNTO 1) <= Sum(3 DOWNTO 1) XOR Carry(3 DOWNTO 1);
P <= Prop(3) AND Prop(2) AND Prop(1) AND Prop(0);
G <= Gen(3) OR (Prop(3) AND Gen(2)) OR (Prop(3) AND Prop(2) AND Gen(1)) OR (Prop(3) AND Prop(2) AND Prop(1) AND Gen(0));
END strc_cla4bits; |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- soma dos valores e propagação do carry --
Sum<=val1 xor val2;
Prop<=val1 or val2;
Gen<=val1 and val2;
PROCESS (Gen,Prop,Carry)
BEGIN
Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn);
inst: FOR i IN 1 TO 2 LOOP
Carry(i+1) <= Gen(i) OR (Prop(i) AND Carry(i));
END LOOP;
END PROCESS;
SomaResult(0) <= Sum(0) XOR CarryIn;
SomaResult(3 DOWNTO 1) <= Sum(3 DOWNTO 1) XOR Carry(3 DOWNTO 1);
P <= Prop(3) AND Prop(2) AND Prop(1) AND Prop(0);
G <= Gen(3) OR (Prop(3) AND Gen(2)) OR (Prop(3) AND Prop(2) AND Gen(1)) OR (Prop(3) AND Prop(2) AND Prop(1) AND Gen(0));
END strc_cla4bits; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc957.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p11n01i00957ent IS
END c06s01b00x00p11n01i00957ent;
ARCHITECTURE c06s01b00x00p11n01i00957arch OF c06s01b00x00p11n01i00957ent IS
BEGIN
TESTING: PROCESS
type z is
record
y : integer;
p,q : boolean;
end record;
type ptrtype is access z;
procedure P ( x : out Ptrtype) is
begin
x.y := 1; -- The prefix is of access type of which
-- denotes a formal parameter of mode
end;
BEGIN
assert FALSE
report "***FAILED TEST: c06s01b00x00p11n01i00957 - Prefix of a name cannot be a formal parameter of mode out if the prefix is an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p11n01i00957arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc957.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p11n01i00957ent IS
END c06s01b00x00p11n01i00957ent;
ARCHITECTURE c06s01b00x00p11n01i00957arch OF c06s01b00x00p11n01i00957ent IS
BEGIN
TESTING: PROCESS
type z is
record
y : integer;
p,q : boolean;
end record;
type ptrtype is access z;
procedure P ( x : out Ptrtype) is
begin
x.y := 1; -- The prefix is of access type of which
-- denotes a formal parameter of mode
end;
BEGIN
assert FALSE
report "***FAILED TEST: c06s01b00x00p11n01i00957 - Prefix of a name cannot be a formal parameter of mode out if the prefix is an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p11n01i00957arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc957.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p11n01i00957ent IS
END c06s01b00x00p11n01i00957ent;
ARCHITECTURE c06s01b00x00p11n01i00957arch OF c06s01b00x00p11n01i00957ent IS
BEGIN
TESTING: PROCESS
type z is
record
y : integer;
p,q : boolean;
end record;
type ptrtype is access z;
procedure P ( x : out Ptrtype) is
begin
x.y := 1; -- The prefix is of access type of which
-- denotes a formal parameter of mode
end;
BEGIN
assert FALSE
report "***FAILED TEST: c06s01b00x00p11n01i00957 - Prefix of a name cannot be a formal parameter of mode out if the prefix is an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p11n01i00957arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
-- Used only for midi_note_t and midi_note_arr_t
use virtual_button_lib.midi_pkg.all;
-- Used for sine_addr_max
use virtual_button_lib.sine_lut_pkg.all;
entity many_sines is
port(
ctrl : in ctrl_t;
midi_nos : in midi_note_arr_t;
pcm_out : out signed(15 downto 0);
new_pcm_out : out std_logic
);
end;
architecture rtl of many_sines is
type sine_rom_read_address_arr_t is array(0 to num_sines - 1) of integer range 0 to sine_addr_max;
type sine_rom_read_out_arr_t is array(0 to num_sines - 1) of signed(15 downto 0);
type strides_arr_t is array(0 to num_sines - 1) of integer range 0 to calc_midi_note_strides(midi_note_t'high);
type sine_driver_counter_arr_t is array(0 to num_sines - 1) of unsigned (midi_counter_width - 1 downto 0);
signal sine_rom_read_addresses : sine_rom_read_address_arr_t;
signal sine_rom_read_outs : sine_rom_read_out_arr_t;
signal strides : strides_arr_t;
signal sine_driver_counters : sine_driver_counter_arr_t := (others => (others => '0'));
constant stride_lut : stride_arr_t := calc_midi_note_strides;
-- These signals delay the current sine to allow sine_rom_read_out to be read
-- into the correct internals.
signal current_sine, current_sine_d1, current_sine_d2 : integer range 0 to num_sines - 1;
signal read_address : integer range 0 to sine_addr_max;
signal read_out : signed(15 downto 0);
-- Signals for generating the audio sampling frequency
constant audio_freq_counter_max : integer := sample_period / clk_period;
signal audio_freq_counter : integer range 0 to audio_freq_counter_max;
signal audio_freq_counter_done : std_logic;
-- stride signals
signal stride_read_addr : midi_note_t;
begin
sine_counter_runners : for j in 0 to num_sines - 1 generate
sine_driver : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
sine_driver_counters(j) <= (others => '0');
elsif audio_freq_counter_done = '1' then
sine_driver_counters(j) <= sine_driver_counters(j) + strides(j);
end if;
end if;
end process;
-- todo Make this prettier. Also I realised that sine_rom_read_address does
-- not need its own register. It is really just a truncation of sine_rom_read_address.
--
-- Note that the width of sine_driver counter is determined by the need to
-- maintain a correct output frequency granularity. This line removes the
-- bits which are not necessary for an address lookup.
sine_rom_read_addresses(j) <=
to_integer(sine_driver_counters(j)) / (2**(midi_counter_width - integer(log2(real(sine_addr_max)))));
end generate;
-- A single lookup table for sinewave generators.
sine_rom_1 : entity virtual_button_lib.sine_rom
port map (
ctrl => ctrl,
read_address_d0 => read_address,
read_out_d1 => read_out
);
-- A round robin multiplexer.
-- Cycles once per clock
sine_lookup_mux : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if current_sine = num_sines - 1 then
current_sine <= 0;
else
current_sine <= current_sine + 1;
end if;
current_sine_d1 <= current_sine;
read_address <= sine_rom_read_addresses(current_sine);
sine_rom_read_outs(current_sine_d1) <= read_out;
end if;
end process;
stride_lookup_mux : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
stride_read_addr <= midi_note_t'low;
else
stride_read_addr <= midi_nos(current_sine);
strides(current_sine_d1) <= stride_lut(stride_read_addr);
end if;
end if;
end process;
-- This is just a 44.1khz strobe.
count_audio_freq : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if audio_freq_counter >= audio_freq_counter_max then
audio_freq_counter <= 0;
audio_freq_counter_done <= '1';
else
audio_freq_counter <= audio_freq_counter + 1;
audio_freq_counter_done <= '0';
end if;
end if;
end process;
-- todo ugly will this synthesizable?
gen_pcm_out : process(ctrl.clk)
variable pcm_out_int : signed(15 + num_sines - 1 downto 0);
begin
if rising_edge(ctrl.clk) then
pcm_out_int := to_signed(0, pcm_out_int'length);
for i in 0 to num_sines - 1 loop
pcm_out_int := resize(sine_rom_read_outs(i), pcm_out_int'length) + pcm_out_int;
pcm_out <= pcm_out_int(pcm_out_int'left downto pcm_out_int'left - 15);
end loop;
end if;
end process;
new_pcm_out <= audio_freq_counter_done;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity Mux32to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 downto 0);
i07: in std_logic_vector(15 downto 0);
i08: in std_logic_vector(15 downto 0);
i09: in std_logic_vector(15 downto 0);
i10: in std_logic_vector(15 downto 0);
i11: in std_logic_vector(15 downto 0);
i12: in std_logic_vector(15 downto 0);
i13: in std_logic_vector(15 downto 0);
i14: in std_logic_vector(15 downto 0);
i15: in std_logic_vector(15 downto 0);
i16: in std_logic_vector(15 downto 0);
i17: in std_logic_vector(15 downto 0);
i18: in std_logic_vector(15 downto 0);
i19: in std_logic_vector(15 downto 0);
i20: in std_logic_vector(15 downto 0);
i21: in std_logic_vector(15 downto 0);
i22: in std_logic_vector(15 downto 0);
i23: in std_logic_vector(15 downto 0);
i24: in std_logic_vector(15 downto 0);
i25: in std_logic_vector(15 downto 0);
i26: in std_logic_vector(15 downto 0);
i27: in std_logic_vector(15 downto 0);
i28: in std_logic_vector(15 downto 0);
i29: in std_logic_vector(15 downto 0);
i30: in std_logic_vector(15 downto 0);
i31: in std_logic_vector(15 downto 0);
i32: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(4 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Mux32to1 is
component Mux16to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 downto 0);
i07: in std_logic_vector(15 downto 0);
i08: in std_logic_vector(15 downto 0);
i09: in std_logic_vector(15 downto 0);
i10: in std_logic_vector(15 downto 0);
i11: in std_logic_vector(15 downto 0);
i12: in std_logic_vector(15 downto 0);
i13: in std_logic_vector(15 downto 0);
i14: in std_logic_vector(15 downto 0);
i15: in std_logic_vector(15 downto 0);
i16: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end component;
signal mux_sel: std_logic_vector(3 downto 0);
signal mux1_o: std_logic_vector(15 downto 0);
signal mux2_o: std_logic_vector(15 downto 0);
begin
mux1: Mux16to1 port map(i01,i02,i03,i04,i05,i06,i07,i08,i09,i10,i11,i12,i13,i14,i15,i16,mux_sel,mux1_o);
mux2: Mux16to1 port map(i17,i18,i19,i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30,i31,i32,mux_sel,mux2_o);
process(sel, mux1_o, mux2_o)
begin
mux_sel <= sel(3 downto 0);
if sel(4) = '0' then
mux_out <= mux1_o;
else
mux_out <= mux2_o;
end if;
end process;
end architecture; |
------------------------------------------------------------------------------
---- ----
---- 64 bits clock counter ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a peripheral used by the PHI I/O layout. It just counts the ----
---- elapsed number of clocks. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Timer(Behave) (Entity and architecture) ----
---- File name: timer.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end entity Timer;
architecture Behave of Timer is
signal sample : std_logic;
signal reset : std_logic;
signal cnt : unsigned(63 downto 0);
signal cnt_smp : unsigned(63 downto 0);
begin
reset <= '1' when (we_i='1' and data_i(0)='1') else '0';
sample <= '1' when (we_i='1' and data_i(1)='1') else '0';
-- Carry generation
do_timer:
process (clk_i)
begin
if rising_edge(clk_i) then
if reset_i='1' or reset='1' then
cnt <= (others => '0');
cnt_smp <= (others => '0');
else
cnt <= cnt+1;
if sample='1' then
-- report "sampling" severity failure;
cnt_smp <= cnt;
end if;
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process do_timer;
data_o <= cnt_smp(31 downto 0) when to_01(addr_i)="0" else
cnt_smp(63 downto 32);
end architecture Behave; -- Entity: Timer
|
-- file: clk_video.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___193.158______0.000______50.0______236.796____297.965
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video;
architecture xilinx of clk_video is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_video_clk_wiz
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_video_clk_wiz
port map (
-- Clock in ports
clk_100MHz => clk_100MHz,
-- Clock out ports
clk_193MHz => clk_193MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
ENTITY CHIP9684 IS
PORT(SIGNAL_IN9685 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9686 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9687 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9688 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9689 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9690 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9691 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9692 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9693 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9684;
ARCHITECTURE ARCH OF CHIP9684 IS
SIGNAL SIGNAL9694 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9694 <= SIGNAL_IN9688;
SIGNAL_OUT9693 <= SIGNAL_IN9687;
SIGNAL_OUT9692 <= SIGNAL_IN9686;
SIGNAL_OUT9691 <= (SIGNAL_IN9686 + ((((SIGNAL_IN9685 + ((SIGNAL_IN9686 and SIGNAL_IN9687) or ((not SIGNAL_IN9686) and SIGNAL_IN9688))) + TO_UNSIGNED(3614090360, 32)) + SIGNAL_IN9689) rol 7));
SIGNAL9694 <= SIGNAL_IN9688;
END ARCHITECTURE ARCH;
ENTITY CHIP9695 IS
PORT(SIGNAL_IN9696 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9697 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9698 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9699 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9700 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9701 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9702 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9703 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9704 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9695;
ARCHITECTURE ARCH OF CHIP9695 IS
SIGNAL SIGNAL9705 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9705 <= SIGNAL_IN9699;
SIGNAL_OUT9704 <= SIGNAL_IN9698;
SIGNAL_OUT9703 <= SIGNAL_IN9697;
SIGNAL_OUT9702 <= (SIGNAL_IN9697 + ((((SIGNAL_IN9696 + ((SIGNAL_IN9697 and SIGNAL_IN9698) or ((not SIGNAL_IN9697) and SIGNAL_IN9699))) + TO_UNSIGNED(3905402710, 32)) + SIGNAL_IN9700) rol 12));
SIGNAL9705 <= SIGNAL_IN9699;
END ARCHITECTURE ARCH;
ENTITY CHIP9706 IS
PORT(SIGNAL_IN9707 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9708 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9709 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9710 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9711 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9712 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9713 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9714 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9715 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9706;
ARCHITECTURE ARCH OF CHIP9706 IS
SIGNAL SIGNAL9716 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9716 <= SIGNAL_IN9710;
SIGNAL_OUT9715 <= SIGNAL_IN9709;
SIGNAL_OUT9714 <= SIGNAL_IN9708;
SIGNAL_OUT9713 <= (SIGNAL_IN9708 + ((((SIGNAL_IN9707 + ((SIGNAL_IN9708 and SIGNAL_IN9709) or ((not SIGNAL_IN9708) and SIGNAL_IN9710))) + TO_UNSIGNED(606105819, 32)) + SIGNAL_IN9711) rol 17));
SIGNAL9716 <= SIGNAL_IN9710;
END ARCHITECTURE ARCH;
ENTITY CHIP9717 IS
PORT(SIGNAL_IN9718 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9719 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9720 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9721 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9722 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9723 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9724 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9725 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9726 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9717;
ARCHITECTURE ARCH OF CHIP9717 IS
SIGNAL SIGNAL9727 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9727 <= SIGNAL_IN9721;
SIGNAL_OUT9726 <= SIGNAL_IN9720;
SIGNAL_OUT9725 <= SIGNAL_IN9719;
SIGNAL_OUT9724 <= (SIGNAL_IN9719 + ((((SIGNAL_IN9718 + ((SIGNAL_IN9719 and SIGNAL_IN9720) or ((not SIGNAL_IN9719) and SIGNAL_IN9721))) + TO_UNSIGNED(3250441966, 32)) + SIGNAL_IN9722) rol 22));
SIGNAL9727 <= SIGNAL_IN9721;
END ARCHITECTURE ARCH;
ENTITY CHIP9728 IS
PORT(SIGNAL_IN9729 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9730 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9731 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9732 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9733 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9734 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9735 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9736 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9737 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9728;
ARCHITECTURE ARCH OF CHIP9728 IS
SIGNAL SIGNAL9738 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9738 <= SIGNAL_IN9732;
SIGNAL_OUT9737 <= SIGNAL_IN9731;
SIGNAL_OUT9736 <= SIGNAL_IN9730;
SIGNAL_OUT9735 <= (SIGNAL_IN9730 + ((((SIGNAL_IN9729 + ((SIGNAL_IN9730 and SIGNAL_IN9731) or ((not SIGNAL_IN9730) and SIGNAL_IN9732))) + TO_UNSIGNED(4118548399, 32)) + SIGNAL_IN9733) rol 7));
SIGNAL9738 <= SIGNAL_IN9732;
END ARCHITECTURE ARCH;
ENTITY CHIP9739 IS
PORT(SIGNAL_IN9740 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9741 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9742 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9743 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9744 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9745 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9746 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9747 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9748 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9739;
ARCHITECTURE ARCH OF CHIP9739 IS
SIGNAL SIGNAL9749 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9749 <= SIGNAL_IN9743;
SIGNAL_OUT9748 <= SIGNAL_IN9742;
SIGNAL_OUT9747 <= SIGNAL_IN9741;
SIGNAL_OUT9746 <= (SIGNAL_IN9741 + ((((SIGNAL_IN9740 + ((SIGNAL_IN9741 and SIGNAL_IN9742) or ((not SIGNAL_IN9741) and SIGNAL_IN9743))) + TO_UNSIGNED(1200080426, 32)) + SIGNAL_IN9744) rol 12));
SIGNAL9749 <= SIGNAL_IN9743;
END ARCHITECTURE ARCH;
ENTITY CHIP9750 IS
PORT(SIGNAL_IN9751 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9752 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9753 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9754 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9755 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9756 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9757 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9758 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9759 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9750;
ARCHITECTURE ARCH OF CHIP9750 IS
SIGNAL SIGNAL9760 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9760 <= SIGNAL_IN9754;
SIGNAL_OUT9759 <= SIGNAL_IN9753;
SIGNAL_OUT9758 <= SIGNAL_IN9752;
SIGNAL_OUT9757 <= (SIGNAL_IN9752 + ((((SIGNAL_IN9751 + ((SIGNAL_IN9752 and SIGNAL_IN9753) or ((not SIGNAL_IN9752) and SIGNAL_IN9754))) + TO_UNSIGNED(2821735955, 32)) + SIGNAL_IN9755) rol 17));
SIGNAL9760 <= SIGNAL_IN9754;
END ARCHITECTURE ARCH;
ENTITY CHIP9761 IS
PORT(SIGNAL_IN9762 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9763 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9764 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9765 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9766 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9767 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9768 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9769 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9770 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9761;
ARCHITECTURE ARCH OF CHIP9761 IS
SIGNAL SIGNAL9771 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9771 <= SIGNAL_IN9765;
SIGNAL_OUT9770 <= SIGNAL_IN9764;
SIGNAL_OUT9769 <= SIGNAL_IN9763;
SIGNAL_OUT9768 <= (SIGNAL_IN9763 + ((((SIGNAL_IN9762 + ((SIGNAL_IN9763 and SIGNAL_IN9764) or ((not SIGNAL_IN9763) and SIGNAL_IN9765))) + TO_UNSIGNED(4249261313, 32)) + SIGNAL_IN9766) rol 22));
SIGNAL9771 <= SIGNAL_IN9765;
END ARCHITECTURE ARCH;
ENTITY CHIP9772 IS
PORT(SIGNAL_IN9773 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9774 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9775 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9776 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9777 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9778 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9779 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9780 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9781 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9772;
ARCHITECTURE ARCH OF CHIP9772 IS
SIGNAL SIGNAL9782 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9782 <= SIGNAL_IN9776;
SIGNAL_OUT9781 <= SIGNAL_IN9775;
SIGNAL_OUT9780 <= SIGNAL_IN9774;
SIGNAL_OUT9779 <= (SIGNAL_IN9774 + ((((SIGNAL_IN9773 + ((SIGNAL_IN9774 and SIGNAL_IN9775) or ((not SIGNAL_IN9774) and SIGNAL_IN9776))) + TO_UNSIGNED(1770035416, 32)) + SIGNAL_IN9777) rol 7));
SIGNAL9782 <= SIGNAL_IN9776;
END ARCHITECTURE ARCH;
ENTITY CHIP9783 IS
PORT(SIGNAL_IN9784 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9785 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9786 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9787 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9788 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9789 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9790 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9791 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9792 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9783;
ARCHITECTURE ARCH OF CHIP9783 IS
SIGNAL SIGNAL9793 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9793 <= SIGNAL_IN9787;
SIGNAL_OUT9792 <= SIGNAL_IN9786;
SIGNAL_OUT9791 <= SIGNAL_IN9785;
SIGNAL_OUT9790 <= (SIGNAL_IN9785 + ((((SIGNAL_IN9784 + ((SIGNAL_IN9785 and SIGNAL_IN9786) or ((not SIGNAL_IN9785) and SIGNAL_IN9787))) + TO_UNSIGNED(2336552879, 32)) + SIGNAL_IN9788) rol 12));
SIGNAL9793 <= SIGNAL_IN9787;
END ARCHITECTURE ARCH;
ENTITY CHIP9794 IS
PORT(SIGNAL_IN9795 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9796 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9797 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9798 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9799 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9800 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9801 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9802 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9803 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9794;
ARCHITECTURE ARCH OF CHIP9794 IS
SIGNAL SIGNAL9804 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9804 <= SIGNAL_IN9798;
SIGNAL_OUT9803 <= SIGNAL_IN9797;
SIGNAL_OUT9802 <= SIGNAL_IN9796;
SIGNAL_OUT9801 <= (SIGNAL_IN9796 + ((((SIGNAL_IN9795 + ((SIGNAL_IN9796 and SIGNAL_IN9797) or ((not SIGNAL_IN9796) and SIGNAL_IN9798))) + TO_UNSIGNED(4294925233, 32)) + SIGNAL_IN9799) rol 17));
SIGNAL9804 <= SIGNAL_IN9798;
END ARCHITECTURE ARCH;
ENTITY CHIP9805 IS
PORT(SIGNAL_IN9806 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9807 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9808 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9809 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9810 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9811 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9812 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9813 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9814 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9805;
ARCHITECTURE ARCH OF CHIP9805 IS
SIGNAL SIGNAL9815 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9815 <= SIGNAL_IN9809;
SIGNAL_OUT9814 <= SIGNAL_IN9808;
SIGNAL_OUT9813 <= SIGNAL_IN9807;
SIGNAL_OUT9812 <= (SIGNAL_IN9807 + ((((SIGNAL_IN9806 + ((SIGNAL_IN9807 and SIGNAL_IN9808) or ((not SIGNAL_IN9807) and SIGNAL_IN9809))) + TO_UNSIGNED(2304563134, 32)) + SIGNAL_IN9810) rol 22));
SIGNAL9815 <= SIGNAL_IN9809;
END ARCHITECTURE ARCH;
ENTITY CHIP9816 IS
PORT(SIGNAL_IN9817 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9818 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9819 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9820 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9821 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9822 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9823 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9824 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9825 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9816;
ARCHITECTURE ARCH OF CHIP9816 IS
SIGNAL SIGNAL9826 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9826 <= SIGNAL_IN9820;
SIGNAL_OUT9825 <= SIGNAL_IN9819;
SIGNAL_OUT9824 <= SIGNAL_IN9818;
SIGNAL_OUT9823 <= (SIGNAL_IN9818 + ((((SIGNAL_IN9817 + ((SIGNAL_IN9818 and SIGNAL_IN9819) or ((not SIGNAL_IN9818) and SIGNAL_IN9820))) + TO_UNSIGNED(1804603682, 32)) + SIGNAL_IN9821) rol 7));
SIGNAL9826 <= SIGNAL_IN9820;
END ARCHITECTURE ARCH;
ENTITY CHIP9827 IS
PORT(SIGNAL_IN9828 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9829 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9830 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9831 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9832 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9833 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9834 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9835 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9836 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9827;
ARCHITECTURE ARCH OF CHIP9827 IS
SIGNAL SIGNAL9837 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9837 <= SIGNAL_IN9831;
SIGNAL_OUT9836 <= SIGNAL_IN9830;
SIGNAL_OUT9835 <= SIGNAL_IN9829;
SIGNAL_OUT9834 <= (SIGNAL_IN9829 + ((((SIGNAL_IN9828 + ((SIGNAL_IN9829 and SIGNAL_IN9830) or ((not SIGNAL_IN9829) and SIGNAL_IN9831))) + TO_UNSIGNED(4254626195, 32)) + SIGNAL_IN9832) rol 12));
SIGNAL9837 <= SIGNAL_IN9831;
END ARCHITECTURE ARCH;
ENTITY CHIP9838 IS
PORT(SIGNAL_IN9839 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9840 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9841 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9842 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9843 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9844 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9845 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9846 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9847 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9838;
ARCHITECTURE ARCH OF CHIP9838 IS
SIGNAL SIGNAL9848 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9848 <= SIGNAL_IN9842;
SIGNAL_OUT9847 <= SIGNAL_IN9841;
SIGNAL_OUT9846 <= SIGNAL_IN9840;
SIGNAL_OUT9845 <= (SIGNAL_IN9840 + ((((SIGNAL_IN9839 + ((SIGNAL_IN9840 and SIGNAL_IN9841) or ((not SIGNAL_IN9840) and SIGNAL_IN9842))) + TO_UNSIGNED(2792965006, 32)) + SIGNAL_IN9843) rol 17));
SIGNAL9848 <= SIGNAL_IN9842;
END ARCHITECTURE ARCH;
ENTITY CHIP9849 IS
PORT(SIGNAL_IN9850 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9851 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9852 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9853 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9854 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9855 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9856 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9857 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9858 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9849;
ARCHITECTURE ARCH OF CHIP9849 IS
SIGNAL SIGNAL9859 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9859 <= SIGNAL_IN9853;
SIGNAL_OUT9858 <= SIGNAL_IN9852;
SIGNAL_OUT9857 <= SIGNAL_IN9851;
SIGNAL_OUT9856 <= (SIGNAL_IN9851 + ((((SIGNAL_IN9850 + ((SIGNAL_IN9851 and SIGNAL_IN9852) or ((not SIGNAL_IN9851) and SIGNAL_IN9853))) + TO_UNSIGNED(1236535329, 32)) + SIGNAL_IN9854) rol 22));
SIGNAL9859 <= SIGNAL_IN9853;
END ARCHITECTURE ARCH;
ENTITY CHIP9860 IS
PORT(SIGNAL_IN9861 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9862 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9863 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9864 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9865 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9866 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9867 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9868 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9869 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9860;
ARCHITECTURE ARCH OF CHIP9860 IS
SIGNAL SIGNAL9870 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9870 <= SIGNAL_IN9864;
SIGNAL_OUT9869 <= SIGNAL_IN9863;
SIGNAL_OUT9868 <= SIGNAL_IN9862;
SIGNAL_OUT9867 <= (SIGNAL_IN9862 + ((((SIGNAL_IN9861 + ((SIGNAL_IN9864 and SIGNAL_IN9862) or ((not SIGNAL_IN9864) and SIGNAL_IN9863))) + TO_UNSIGNED(4129170786, 32)) + SIGNAL_IN9865) rol 5));
SIGNAL9870 <= SIGNAL_IN9864;
END ARCHITECTURE ARCH;
ENTITY CHIP9871 IS
PORT(SIGNAL_IN9872 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9873 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9874 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9875 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9876 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9877 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9878 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9879 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9880 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9871;
ARCHITECTURE ARCH OF CHIP9871 IS
SIGNAL SIGNAL9881 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9881 <= SIGNAL_IN9875;
SIGNAL_OUT9880 <= SIGNAL_IN9874;
SIGNAL_OUT9879 <= SIGNAL_IN9873;
SIGNAL_OUT9878 <= (SIGNAL_IN9873 + ((((SIGNAL_IN9872 + ((SIGNAL_IN9875 and SIGNAL_IN9873) or ((not SIGNAL_IN9875) and SIGNAL_IN9874))) + TO_UNSIGNED(3225465664, 32)) + SIGNAL_IN9876) rol 9));
SIGNAL9881 <= SIGNAL_IN9875;
END ARCHITECTURE ARCH;
ENTITY CHIP9882 IS
PORT(SIGNAL_IN9883 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9884 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9885 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9886 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9887 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9888 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9889 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9890 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9891 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9882;
ARCHITECTURE ARCH OF CHIP9882 IS
SIGNAL SIGNAL9892 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9892 <= SIGNAL_IN9886;
SIGNAL_OUT9891 <= SIGNAL_IN9885;
SIGNAL_OUT9890 <= SIGNAL_IN9884;
SIGNAL_OUT9889 <= (SIGNAL_IN9884 + ((((SIGNAL_IN9883 + ((SIGNAL_IN9886 and SIGNAL_IN9884) or ((not SIGNAL_IN9886) and SIGNAL_IN9885))) + TO_UNSIGNED(643717713, 32)) + SIGNAL_IN9887) rol 14));
SIGNAL9892 <= SIGNAL_IN9886;
END ARCHITECTURE ARCH;
ENTITY CHIP9893 IS
PORT(SIGNAL_IN9894 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9895 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9896 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9897 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9898 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9899 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9900 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9901 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9902 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9893;
ARCHITECTURE ARCH OF CHIP9893 IS
SIGNAL SIGNAL9903 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9903 <= SIGNAL_IN9897;
SIGNAL_OUT9902 <= SIGNAL_IN9896;
SIGNAL_OUT9901 <= SIGNAL_IN9895;
SIGNAL_OUT9900 <= (SIGNAL_IN9895 + ((((SIGNAL_IN9894 + ((SIGNAL_IN9897 and SIGNAL_IN9895) or ((not SIGNAL_IN9897) and SIGNAL_IN9896))) + TO_UNSIGNED(3921069994, 32)) + SIGNAL_IN9898) rol 20));
SIGNAL9903 <= SIGNAL_IN9897;
END ARCHITECTURE ARCH;
ENTITY CHIP9904 IS
PORT(SIGNAL_IN9905 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9906 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9907 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9908 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9909 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9910 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9911 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9912 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9913 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9904;
ARCHITECTURE ARCH OF CHIP9904 IS
SIGNAL SIGNAL9914 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9914 <= SIGNAL_IN9908;
SIGNAL_OUT9913 <= SIGNAL_IN9907;
SIGNAL_OUT9912 <= SIGNAL_IN9906;
SIGNAL_OUT9911 <= (SIGNAL_IN9906 + ((((SIGNAL_IN9905 + ((SIGNAL_IN9908 and SIGNAL_IN9906) or ((not SIGNAL_IN9908) and SIGNAL_IN9907))) + TO_UNSIGNED(3593408605, 32)) + SIGNAL_IN9909) rol 5));
SIGNAL9914 <= SIGNAL_IN9908;
END ARCHITECTURE ARCH;
ENTITY CHIP9915 IS
PORT(SIGNAL_IN9916 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9917 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9918 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9919 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9920 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9921 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9922 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9923 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9924 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9915;
ARCHITECTURE ARCH OF CHIP9915 IS
SIGNAL SIGNAL9925 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9925 <= SIGNAL_IN9919;
SIGNAL_OUT9924 <= SIGNAL_IN9918;
SIGNAL_OUT9923 <= SIGNAL_IN9917;
SIGNAL_OUT9922 <= (SIGNAL_IN9917 + ((((SIGNAL_IN9916 + ((SIGNAL_IN9919 and SIGNAL_IN9917) or ((not SIGNAL_IN9919) and SIGNAL_IN9918))) + TO_UNSIGNED(38016083, 32)) + SIGNAL_IN9920) rol 9));
SIGNAL9925 <= SIGNAL_IN9919;
END ARCHITECTURE ARCH;
ENTITY CHIP9926 IS
PORT(SIGNAL_IN9927 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9928 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9929 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9930 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9931 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9932 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9933 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9934 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9935 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9926;
ARCHITECTURE ARCH OF CHIP9926 IS
SIGNAL SIGNAL9936 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9936 <= SIGNAL_IN9930;
SIGNAL_OUT9935 <= SIGNAL_IN9929;
SIGNAL_OUT9934 <= SIGNAL_IN9928;
SIGNAL_OUT9933 <= (SIGNAL_IN9928 + ((((SIGNAL_IN9927 + ((SIGNAL_IN9930 and SIGNAL_IN9928) or ((not SIGNAL_IN9930) and SIGNAL_IN9929))) + TO_UNSIGNED(3634488961, 32)) + SIGNAL_IN9931) rol 14));
SIGNAL9936 <= SIGNAL_IN9930;
END ARCHITECTURE ARCH;
ENTITY CHIP9937 IS
PORT(SIGNAL_IN9938 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9939 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9940 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9941 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9942 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9943 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9944 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9945 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9946 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9937;
ARCHITECTURE ARCH OF CHIP9937 IS
SIGNAL SIGNAL9947 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9947 <= SIGNAL_IN9941;
SIGNAL_OUT9946 <= SIGNAL_IN9940;
SIGNAL_OUT9945 <= SIGNAL_IN9939;
SIGNAL_OUT9944 <= (SIGNAL_IN9939 + ((((SIGNAL_IN9938 + ((SIGNAL_IN9941 and SIGNAL_IN9939) or ((not SIGNAL_IN9941) and SIGNAL_IN9940))) + TO_UNSIGNED(3889429448, 32)) + SIGNAL_IN9942) rol 20));
SIGNAL9947 <= SIGNAL_IN9941;
END ARCHITECTURE ARCH;
ENTITY CHIP9948 IS
PORT(SIGNAL_IN9949 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9950 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9951 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9952 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9953 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9954 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9955 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9956 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9957 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9948;
ARCHITECTURE ARCH OF CHIP9948 IS
SIGNAL SIGNAL9958 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9958 <= SIGNAL_IN9952;
SIGNAL_OUT9957 <= SIGNAL_IN9951;
SIGNAL_OUT9956 <= SIGNAL_IN9950;
SIGNAL_OUT9955 <= (SIGNAL_IN9950 + ((((SIGNAL_IN9949 + ((SIGNAL_IN9952 and SIGNAL_IN9950) or ((not SIGNAL_IN9952) and SIGNAL_IN9951))) + TO_UNSIGNED(568446438, 32)) + SIGNAL_IN9953) rol 5));
SIGNAL9958 <= SIGNAL_IN9952;
END ARCHITECTURE ARCH;
ENTITY CHIP9959 IS
PORT(SIGNAL_IN9960 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9961 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9962 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9963 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9964 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9965 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9966 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9967 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9968 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9959;
ARCHITECTURE ARCH OF CHIP9959 IS
SIGNAL SIGNAL9969 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9969 <= SIGNAL_IN9963;
SIGNAL_OUT9968 <= SIGNAL_IN9962;
SIGNAL_OUT9967 <= SIGNAL_IN9961;
SIGNAL_OUT9966 <= (SIGNAL_IN9961 + ((((SIGNAL_IN9960 + ((SIGNAL_IN9963 and SIGNAL_IN9961) or ((not SIGNAL_IN9963) and SIGNAL_IN9962))) + TO_UNSIGNED(3275163606, 32)) + SIGNAL_IN9964) rol 9));
SIGNAL9969 <= SIGNAL_IN9963;
END ARCHITECTURE ARCH;
ENTITY CHIP9970 IS
PORT(SIGNAL_IN9971 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9972 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9973 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9974 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9975 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9976 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9977 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9978 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9979 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9970;
ARCHITECTURE ARCH OF CHIP9970 IS
SIGNAL SIGNAL9980 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9980 <= SIGNAL_IN9974;
SIGNAL_OUT9979 <= SIGNAL_IN9973;
SIGNAL_OUT9978 <= SIGNAL_IN9972;
SIGNAL_OUT9977 <= (SIGNAL_IN9972 + ((((SIGNAL_IN9971 + ((SIGNAL_IN9974 and SIGNAL_IN9972) or ((not SIGNAL_IN9974) and SIGNAL_IN9973))) + TO_UNSIGNED(4107603335, 32)) + SIGNAL_IN9975) rol 14));
SIGNAL9980 <= SIGNAL_IN9974;
END ARCHITECTURE ARCH;
ENTITY CHIP9981 IS
PORT(SIGNAL_IN9982 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9983 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9984 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9985 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9986 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9987 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9988 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9989 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9990 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9981;
ARCHITECTURE ARCH OF CHIP9981 IS
SIGNAL SIGNAL9991 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9991 <= SIGNAL_IN9985;
SIGNAL_OUT9990 <= SIGNAL_IN9984;
SIGNAL_OUT9989 <= SIGNAL_IN9983;
SIGNAL_OUT9988 <= (SIGNAL_IN9983 + ((((SIGNAL_IN9982 + ((SIGNAL_IN9985 and SIGNAL_IN9983) or ((not SIGNAL_IN9985) and SIGNAL_IN9984))) + TO_UNSIGNED(1163531501, 32)) + SIGNAL_IN9986) rol 20));
SIGNAL9991 <= SIGNAL_IN9985;
END ARCHITECTURE ARCH;
ENTITY CHIP9992 IS
PORT(SIGNAL_IN9993 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9994 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9995 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9996 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9997 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9998 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9999 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10000 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10001 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9992;
ARCHITECTURE ARCH OF CHIP9992 IS
SIGNAL SIGNAL10002 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10002 <= SIGNAL_IN9996;
SIGNAL_OUT10001 <= SIGNAL_IN9995;
SIGNAL_OUT10000 <= SIGNAL_IN9994;
SIGNAL_OUT9999 <= (SIGNAL_IN9994 + ((((SIGNAL_IN9993 + ((SIGNAL_IN9996 and SIGNAL_IN9994) or ((not SIGNAL_IN9996) and SIGNAL_IN9995))) + TO_UNSIGNED(2850285829, 32)) + SIGNAL_IN9997) rol 5));
SIGNAL10002 <= SIGNAL_IN9996;
END ARCHITECTURE ARCH;
ENTITY CHIP10003 IS
PORT(SIGNAL_IN10004 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10005 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10006 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10007 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10008 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10009 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10010 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10011 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10012 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10003;
ARCHITECTURE ARCH OF CHIP10003 IS
SIGNAL SIGNAL10013 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10013 <= SIGNAL_IN10007;
SIGNAL_OUT10012 <= SIGNAL_IN10006;
SIGNAL_OUT10011 <= SIGNAL_IN10005;
SIGNAL_OUT10010 <= (SIGNAL_IN10005 + ((((SIGNAL_IN10004 + ((SIGNAL_IN10007 and SIGNAL_IN10005) or ((not SIGNAL_IN10007) and SIGNAL_IN10006))) + TO_UNSIGNED(4243563512, 32)) + SIGNAL_IN10008) rol 9));
SIGNAL10013 <= SIGNAL_IN10007;
END ARCHITECTURE ARCH;
ENTITY CHIP10014 IS
PORT(SIGNAL_IN10015 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10016 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10017 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10018 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10019 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10020 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10021 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10022 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10023 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10014;
ARCHITECTURE ARCH OF CHIP10014 IS
SIGNAL SIGNAL10024 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10024 <= SIGNAL_IN10018;
SIGNAL_OUT10023 <= SIGNAL_IN10017;
SIGNAL_OUT10022 <= SIGNAL_IN10016;
SIGNAL_OUT10021 <= (SIGNAL_IN10016 + ((((SIGNAL_IN10015 + ((SIGNAL_IN10018 and SIGNAL_IN10016) or ((not SIGNAL_IN10018) and SIGNAL_IN10017))) + TO_UNSIGNED(1735328473, 32)) + SIGNAL_IN10019) rol 14));
SIGNAL10024 <= SIGNAL_IN10018;
END ARCHITECTURE ARCH;
ENTITY CHIP10025 IS
PORT(SIGNAL_IN10026 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10027 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10028 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10029 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10030 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10031 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10032 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10033 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10034 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10025;
ARCHITECTURE ARCH OF CHIP10025 IS
SIGNAL SIGNAL10035 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10035 <= SIGNAL_IN10029;
SIGNAL_OUT10034 <= SIGNAL_IN10028;
SIGNAL_OUT10033 <= SIGNAL_IN10027;
SIGNAL_OUT10032 <= (SIGNAL_IN10027 + ((((SIGNAL_IN10026 + ((SIGNAL_IN10029 and SIGNAL_IN10027) or ((not SIGNAL_IN10029) and SIGNAL_IN10028))) + TO_UNSIGNED(2368359562, 32)) + SIGNAL_IN10030) rol 20));
SIGNAL10035 <= SIGNAL_IN10029;
END ARCHITECTURE ARCH;
ENTITY CHIP10036 IS
PORT(SIGNAL_IN10037 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10038 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10039 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10040 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10041 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10042 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10043 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10044 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10045 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10036;
ARCHITECTURE ARCH OF CHIP10036 IS
SIGNAL SIGNAL10046 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10046 <= SIGNAL_IN10040;
SIGNAL_OUT10045 <= SIGNAL_IN10039;
SIGNAL_OUT10044 <= SIGNAL_IN10038;
SIGNAL_OUT10043 <= (SIGNAL_IN10038 + ((((SIGNAL_IN10037 + (SIGNAL_IN10038 xor (SIGNAL_IN10039 xor SIGNAL_IN10040))) + TO_UNSIGNED(4294588738, 32)) + SIGNAL_IN10041) rol 4));
SIGNAL10046 <= SIGNAL_IN10040;
END ARCHITECTURE ARCH;
ENTITY CHIP10047 IS
PORT(SIGNAL_IN10048 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10049 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10050 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10051 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10052 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10053 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10054 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10055 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10056 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10047;
ARCHITECTURE ARCH OF CHIP10047 IS
SIGNAL SIGNAL10057 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10057 <= SIGNAL_IN10051;
SIGNAL_OUT10056 <= SIGNAL_IN10050;
SIGNAL_OUT10055 <= SIGNAL_IN10049;
SIGNAL_OUT10054 <= (SIGNAL_IN10049 + ((((SIGNAL_IN10048 + (SIGNAL_IN10049 xor (SIGNAL_IN10050 xor SIGNAL_IN10051))) + TO_UNSIGNED(2272392833, 32)) + SIGNAL_IN10052) rol 11));
SIGNAL10057 <= SIGNAL_IN10051;
END ARCHITECTURE ARCH;
ENTITY CHIP10058 IS
PORT(SIGNAL_IN10059 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10060 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10061 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10062 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10063 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10064 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10065 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10066 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10067 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10058;
ARCHITECTURE ARCH OF CHIP10058 IS
SIGNAL SIGNAL10068 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10068 <= SIGNAL_IN10062;
SIGNAL_OUT10067 <= SIGNAL_IN10061;
SIGNAL_OUT10066 <= SIGNAL_IN10060;
SIGNAL_OUT10065 <= (SIGNAL_IN10060 + ((((SIGNAL_IN10059 + (SIGNAL_IN10060 xor (SIGNAL_IN10061 xor SIGNAL_IN10062))) + TO_UNSIGNED(1839030562, 32)) + SIGNAL_IN10063) rol 16));
SIGNAL10068 <= SIGNAL_IN10062;
END ARCHITECTURE ARCH;
ENTITY CHIP10069 IS
PORT(SIGNAL_IN10070 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10071 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10072 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10073 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10074 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10075 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10076 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10077 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10078 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10069;
ARCHITECTURE ARCH OF CHIP10069 IS
SIGNAL SIGNAL10079 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10079 <= SIGNAL_IN10073;
SIGNAL_OUT10078 <= SIGNAL_IN10072;
SIGNAL_OUT10077 <= SIGNAL_IN10071;
SIGNAL_OUT10076 <= (SIGNAL_IN10071 + ((((SIGNAL_IN10070 + (SIGNAL_IN10071 xor (SIGNAL_IN10072 xor SIGNAL_IN10073))) + TO_UNSIGNED(4259657740, 32)) + SIGNAL_IN10074) rol 23));
SIGNAL10079 <= SIGNAL_IN10073;
END ARCHITECTURE ARCH;
ENTITY CHIP10080 IS
PORT(SIGNAL_IN10081 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10082 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10083 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10084 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10085 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10086 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10087 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10088 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10089 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10080;
ARCHITECTURE ARCH OF CHIP10080 IS
SIGNAL SIGNAL10090 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10090 <= SIGNAL_IN10084;
SIGNAL_OUT10089 <= SIGNAL_IN10083;
SIGNAL_OUT10088 <= SIGNAL_IN10082;
SIGNAL_OUT10087 <= (SIGNAL_IN10082 + ((((SIGNAL_IN10081 + (SIGNAL_IN10082 xor (SIGNAL_IN10083 xor SIGNAL_IN10084))) + TO_UNSIGNED(2763975236, 32)) + SIGNAL_IN10085) rol 4));
SIGNAL10090 <= SIGNAL_IN10084;
END ARCHITECTURE ARCH;
ENTITY CHIP10091 IS
PORT(SIGNAL_IN10092 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10093 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10094 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10095 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10096 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10097 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10098 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10099 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10100 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10091;
ARCHITECTURE ARCH OF CHIP10091 IS
SIGNAL SIGNAL10101 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10101 <= SIGNAL_IN10095;
SIGNAL_OUT10100 <= SIGNAL_IN10094;
SIGNAL_OUT10099 <= SIGNAL_IN10093;
SIGNAL_OUT10098 <= (SIGNAL_IN10093 + ((((SIGNAL_IN10092 + (SIGNAL_IN10093 xor (SIGNAL_IN10094 xor SIGNAL_IN10095))) + TO_UNSIGNED(1272893353, 32)) + SIGNAL_IN10096) rol 11));
SIGNAL10101 <= SIGNAL_IN10095;
END ARCHITECTURE ARCH;
ENTITY CHIP10102 IS
PORT(SIGNAL_IN10103 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10104 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10105 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10106 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10107 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10108 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10109 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10110 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10111 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10102;
ARCHITECTURE ARCH OF CHIP10102 IS
SIGNAL SIGNAL10112 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10112 <= SIGNAL_IN10106;
SIGNAL_OUT10111 <= SIGNAL_IN10105;
SIGNAL_OUT10110 <= SIGNAL_IN10104;
SIGNAL_OUT10109 <= (SIGNAL_IN10104 + ((((SIGNAL_IN10103 + (SIGNAL_IN10104 xor (SIGNAL_IN10105 xor SIGNAL_IN10106))) + TO_UNSIGNED(4139469664, 32)) + SIGNAL_IN10107) rol 16));
SIGNAL10112 <= SIGNAL_IN10106;
END ARCHITECTURE ARCH;
ENTITY CHIP10113 IS
PORT(SIGNAL_IN10114 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10115 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10116 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10117 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10118 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10119 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10120 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10121 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10122 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10113;
ARCHITECTURE ARCH OF CHIP10113 IS
SIGNAL SIGNAL10123 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10123 <= SIGNAL_IN10117;
SIGNAL_OUT10122 <= SIGNAL_IN10116;
SIGNAL_OUT10121 <= SIGNAL_IN10115;
SIGNAL_OUT10120 <= (SIGNAL_IN10115 + ((((SIGNAL_IN10114 + (SIGNAL_IN10115 xor (SIGNAL_IN10116 xor SIGNAL_IN10117))) + TO_UNSIGNED(3200236656, 32)) + SIGNAL_IN10118) rol 23));
SIGNAL10123 <= SIGNAL_IN10117;
END ARCHITECTURE ARCH;
ENTITY CHIP10124 IS
PORT(SIGNAL_IN10125 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10126 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10127 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10128 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10129 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10130 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10131 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10132 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10133 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10124;
ARCHITECTURE ARCH OF CHIP10124 IS
SIGNAL SIGNAL10134 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10134 <= SIGNAL_IN10128;
SIGNAL_OUT10133 <= SIGNAL_IN10127;
SIGNAL_OUT10132 <= SIGNAL_IN10126;
SIGNAL_OUT10131 <= (SIGNAL_IN10126 + ((((SIGNAL_IN10125 + (SIGNAL_IN10126 xor (SIGNAL_IN10127 xor SIGNAL_IN10128))) + TO_UNSIGNED(681279174, 32)) + SIGNAL_IN10129) rol 4));
SIGNAL10134 <= SIGNAL_IN10128;
END ARCHITECTURE ARCH;
ENTITY CHIP10135 IS
PORT(SIGNAL_IN10136 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10137 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10138 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10139 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10140 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10141 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10142 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10143 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10144 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10135;
ARCHITECTURE ARCH OF CHIP10135 IS
SIGNAL SIGNAL10145 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10145 <= SIGNAL_IN10139;
SIGNAL_OUT10144 <= SIGNAL_IN10138;
SIGNAL_OUT10143 <= SIGNAL_IN10137;
SIGNAL_OUT10142 <= (SIGNAL_IN10137 + ((((SIGNAL_IN10136 + (SIGNAL_IN10137 xor (SIGNAL_IN10138 xor SIGNAL_IN10139))) + TO_UNSIGNED(3936430074, 32)) + SIGNAL_IN10140) rol 11));
SIGNAL10145 <= SIGNAL_IN10139;
END ARCHITECTURE ARCH;
ENTITY CHIP10146 IS
PORT(SIGNAL_IN10147 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10148 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10149 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10150 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10151 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10152 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10153 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10154 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10155 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10146;
ARCHITECTURE ARCH OF CHIP10146 IS
SIGNAL SIGNAL10156 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10156 <= SIGNAL_IN10150;
SIGNAL_OUT10155 <= SIGNAL_IN10149;
SIGNAL_OUT10154 <= SIGNAL_IN10148;
SIGNAL_OUT10153 <= (SIGNAL_IN10148 + ((((SIGNAL_IN10147 + (SIGNAL_IN10148 xor (SIGNAL_IN10149 xor SIGNAL_IN10150))) + TO_UNSIGNED(3572445317, 32)) + SIGNAL_IN10151) rol 16));
SIGNAL10156 <= SIGNAL_IN10150;
END ARCHITECTURE ARCH;
ENTITY CHIP10157 IS
PORT(SIGNAL_IN10158 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10159 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10160 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10161 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10162 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10163 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10164 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10165 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10166 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10157;
ARCHITECTURE ARCH OF CHIP10157 IS
SIGNAL SIGNAL10167 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10167 <= SIGNAL_IN10161;
SIGNAL_OUT10166 <= SIGNAL_IN10160;
SIGNAL_OUT10165 <= SIGNAL_IN10159;
SIGNAL_OUT10164 <= (SIGNAL_IN10159 + ((((SIGNAL_IN10158 + (SIGNAL_IN10159 xor (SIGNAL_IN10160 xor SIGNAL_IN10161))) + TO_UNSIGNED(76029189, 32)) + SIGNAL_IN10162) rol 23));
SIGNAL10167 <= SIGNAL_IN10161;
END ARCHITECTURE ARCH;
ENTITY CHIP10168 IS
PORT(SIGNAL_IN10169 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10170 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10171 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10172 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10173 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10174 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10175 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10176 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10177 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10168;
ARCHITECTURE ARCH OF CHIP10168 IS
SIGNAL SIGNAL10178 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10178 <= SIGNAL_IN10172;
SIGNAL_OUT10177 <= SIGNAL_IN10171;
SIGNAL_OUT10176 <= SIGNAL_IN10170;
SIGNAL_OUT10175 <= (SIGNAL_IN10170 + ((((SIGNAL_IN10169 + (SIGNAL_IN10170 xor (SIGNAL_IN10171 xor SIGNAL_IN10172))) + TO_UNSIGNED(3654602809, 32)) + SIGNAL_IN10173) rol 4));
SIGNAL10178 <= SIGNAL_IN10172;
END ARCHITECTURE ARCH;
ENTITY CHIP10179 IS
PORT(SIGNAL_IN10180 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10181 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10182 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10183 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10184 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10185 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10186 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10187 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10188 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10179;
ARCHITECTURE ARCH OF CHIP10179 IS
SIGNAL SIGNAL10189 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10189 <= SIGNAL_IN10183;
SIGNAL_OUT10188 <= SIGNAL_IN10182;
SIGNAL_OUT10187 <= SIGNAL_IN10181;
SIGNAL_OUT10186 <= (SIGNAL_IN10181 + ((((SIGNAL_IN10180 + (SIGNAL_IN10181 xor (SIGNAL_IN10182 xor SIGNAL_IN10183))) + TO_UNSIGNED(3873151461, 32)) + SIGNAL_IN10184) rol 11));
SIGNAL10189 <= SIGNAL_IN10183;
END ARCHITECTURE ARCH;
ENTITY CHIP10190 IS
PORT(SIGNAL_IN10191 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10192 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10193 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10194 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10195 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10196 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10197 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10198 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10199 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10190;
ARCHITECTURE ARCH OF CHIP10190 IS
SIGNAL SIGNAL10200 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10200 <= SIGNAL_IN10194;
SIGNAL_OUT10199 <= SIGNAL_IN10193;
SIGNAL_OUT10198 <= SIGNAL_IN10192;
SIGNAL_OUT10197 <= (SIGNAL_IN10192 + ((((SIGNAL_IN10191 + (SIGNAL_IN10192 xor (SIGNAL_IN10193 xor SIGNAL_IN10194))) + TO_UNSIGNED(530742520, 32)) + SIGNAL_IN10195) rol 16));
SIGNAL10200 <= SIGNAL_IN10194;
END ARCHITECTURE ARCH;
ENTITY CHIP10201 IS
PORT(SIGNAL_IN10202 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10203 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10204 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10205 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10206 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10207 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10208 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10209 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10210 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10201;
ARCHITECTURE ARCH OF CHIP10201 IS
SIGNAL SIGNAL10211 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10211 <= SIGNAL_IN10205;
SIGNAL_OUT10210 <= SIGNAL_IN10204;
SIGNAL_OUT10209 <= SIGNAL_IN10203;
SIGNAL_OUT10208 <= (SIGNAL_IN10203 + ((((SIGNAL_IN10202 + (SIGNAL_IN10203 xor (SIGNAL_IN10204 xor SIGNAL_IN10205))) + TO_UNSIGNED(3299628645, 32)) + SIGNAL_IN10206) rol 23));
SIGNAL10211 <= SIGNAL_IN10205;
END ARCHITECTURE ARCH;
ENTITY CHIP10212 IS
PORT(SIGNAL_IN10213 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10214 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10215 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10216 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10217 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10218 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10219 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10220 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10221 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10212;
ARCHITECTURE ARCH OF CHIP10212 IS
SIGNAL SIGNAL10222 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10222 <= SIGNAL_IN10216;
SIGNAL_OUT10221 <= SIGNAL_IN10215;
SIGNAL_OUT10220 <= SIGNAL_IN10214;
SIGNAL_OUT10219 <= (SIGNAL_IN10214 + ((((SIGNAL_IN10213 + (SIGNAL_IN10215 xor (SIGNAL_IN10214 or (not SIGNAL_IN10216)))) + TO_UNSIGNED(4096336452, 32)) + SIGNAL_IN10217) rol 6));
SIGNAL10222 <= SIGNAL_IN10216;
END ARCHITECTURE ARCH;
ENTITY CHIP10223 IS
PORT(SIGNAL_IN10224 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10225 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10226 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10227 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10228 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10229 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10230 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10231 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10232 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10223;
ARCHITECTURE ARCH OF CHIP10223 IS
SIGNAL SIGNAL10233 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10233 <= SIGNAL_IN10227;
SIGNAL_OUT10232 <= SIGNAL_IN10226;
SIGNAL_OUT10231 <= SIGNAL_IN10225;
SIGNAL_OUT10230 <= (SIGNAL_IN10225 + ((((SIGNAL_IN10224 + (SIGNAL_IN10226 xor (SIGNAL_IN10225 or (not SIGNAL_IN10227)))) + TO_UNSIGNED(1126891415, 32)) + SIGNAL_IN10228) rol 10));
SIGNAL10233 <= SIGNAL_IN10227;
END ARCHITECTURE ARCH;
ENTITY CHIP10234 IS
PORT(SIGNAL_IN10235 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10236 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10237 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10238 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10239 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10240 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10241 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10242 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10243 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10234;
ARCHITECTURE ARCH OF CHIP10234 IS
SIGNAL SIGNAL10244 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10244 <= SIGNAL_IN10238;
SIGNAL_OUT10243 <= SIGNAL_IN10237;
SIGNAL_OUT10242 <= SIGNAL_IN10236;
SIGNAL_OUT10241 <= (SIGNAL_IN10236 + ((((SIGNAL_IN10235 + (SIGNAL_IN10237 xor (SIGNAL_IN10236 or (not SIGNAL_IN10238)))) + TO_UNSIGNED(2878612391, 32)) + SIGNAL_IN10239) rol 15));
SIGNAL10244 <= SIGNAL_IN10238;
END ARCHITECTURE ARCH;
ENTITY CHIP10245 IS
PORT(SIGNAL_IN10246 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10247 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10248 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10249 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10250 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10251 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10252 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10253 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10254 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10245;
ARCHITECTURE ARCH OF CHIP10245 IS
SIGNAL SIGNAL10255 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10255 <= SIGNAL_IN10249;
SIGNAL_OUT10254 <= SIGNAL_IN10248;
SIGNAL_OUT10253 <= SIGNAL_IN10247;
SIGNAL_OUT10252 <= (SIGNAL_IN10247 + ((((SIGNAL_IN10246 + (SIGNAL_IN10248 xor (SIGNAL_IN10247 or (not SIGNAL_IN10249)))) + TO_UNSIGNED(4237533241, 32)) + SIGNAL_IN10250) rol 21));
SIGNAL10255 <= SIGNAL_IN10249;
END ARCHITECTURE ARCH;
ENTITY CHIP10256 IS
PORT(SIGNAL_IN10257 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10258 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10259 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10260 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10261 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10262 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10263 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10264 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10265 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10256;
ARCHITECTURE ARCH OF CHIP10256 IS
SIGNAL SIGNAL10266 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10266 <= SIGNAL_IN10260;
SIGNAL_OUT10265 <= SIGNAL_IN10259;
SIGNAL_OUT10264 <= SIGNAL_IN10258;
SIGNAL_OUT10263 <= (SIGNAL_IN10258 + ((((SIGNAL_IN10257 + (SIGNAL_IN10259 xor (SIGNAL_IN10258 or (not SIGNAL_IN10260)))) + TO_UNSIGNED(1700485571, 32)) + SIGNAL_IN10261) rol 6));
SIGNAL10266 <= SIGNAL_IN10260;
END ARCHITECTURE ARCH;
ENTITY CHIP10267 IS
PORT(SIGNAL_IN10268 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10269 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10270 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10271 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10272 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10273 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10274 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10275 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10276 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10267;
ARCHITECTURE ARCH OF CHIP10267 IS
SIGNAL SIGNAL10277 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10277 <= SIGNAL_IN10271;
SIGNAL_OUT10276 <= SIGNAL_IN10270;
SIGNAL_OUT10275 <= SIGNAL_IN10269;
SIGNAL_OUT10274 <= (SIGNAL_IN10269 + ((((SIGNAL_IN10268 + (SIGNAL_IN10270 xor (SIGNAL_IN10269 or (not SIGNAL_IN10271)))) + TO_UNSIGNED(2399980690, 32)) + SIGNAL_IN10272) rol 10));
SIGNAL10277 <= SIGNAL_IN10271;
END ARCHITECTURE ARCH;
ENTITY CHIP10278 IS
PORT(SIGNAL_IN10279 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10280 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10281 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10282 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10283 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10284 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10285 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10286 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10287 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10278;
ARCHITECTURE ARCH OF CHIP10278 IS
SIGNAL SIGNAL10288 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10288 <= SIGNAL_IN10282;
SIGNAL_OUT10287 <= SIGNAL_IN10281;
SIGNAL_OUT10286 <= SIGNAL_IN10280;
SIGNAL_OUT10285 <= (SIGNAL_IN10280 + ((((SIGNAL_IN10279 + (SIGNAL_IN10281 xor (SIGNAL_IN10280 or (not SIGNAL_IN10282)))) + TO_UNSIGNED(4293915773, 32)) + SIGNAL_IN10283) rol 15));
SIGNAL10288 <= SIGNAL_IN10282;
END ARCHITECTURE ARCH;
ENTITY CHIP10289 IS
PORT(SIGNAL_IN10290 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10291 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10292 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10293 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10294 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10295 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10296 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10297 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10298 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10289;
ARCHITECTURE ARCH OF CHIP10289 IS
SIGNAL SIGNAL10299 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10299 <= SIGNAL_IN10293;
SIGNAL_OUT10298 <= SIGNAL_IN10292;
SIGNAL_OUT10297 <= SIGNAL_IN10291;
SIGNAL_OUT10296 <= (SIGNAL_IN10291 + ((((SIGNAL_IN10290 + (SIGNAL_IN10292 xor (SIGNAL_IN10291 or (not SIGNAL_IN10293)))) + TO_UNSIGNED(2240044497, 32)) + SIGNAL_IN10294) rol 21));
SIGNAL10299 <= SIGNAL_IN10293;
END ARCHITECTURE ARCH;
ENTITY CHIP10300 IS
PORT(SIGNAL_IN10301 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10302 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10303 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10304 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10305 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10306 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10307 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10308 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10309 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10300;
ARCHITECTURE ARCH OF CHIP10300 IS
SIGNAL SIGNAL10310 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10310 <= SIGNAL_IN10304;
SIGNAL_OUT10309 <= SIGNAL_IN10303;
SIGNAL_OUT10308 <= SIGNAL_IN10302;
SIGNAL_OUT10307 <= (SIGNAL_IN10302 + ((((SIGNAL_IN10301 + (SIGNAL_IN10303 xor (SIGNAL_IN10302 or (not SIGNAL_IN10304)))) + TO_UNSIGNED(1873313359, 32)) + SIGNAL_IN10305) rol 6));
SIGNAL10310 <= SIGNAL_IN10304;
END ARCHITECTURE ARCH;
ENTITY CHIP10311 IS
PORT(SIGNAL_IN10312 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10313 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10314 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10315 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10316 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10317 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10318 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10319 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10320 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10311;
ARCHITECTURE ARCH OF CHIP10311 IS
SIGNAL SIGNAL10321 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10321 <= SIGNAL_IN10315;
SIGNAL_OUT10320 <= SIGNAL_IN10314;
SIGNAL_OUT10319 <= SIGNAL_IN10313;
SIGNAL_OUT10318 <= (SIGNAL_IN10313 + ((((SIGNAL_IN10312 + (SIGNAL_IN10314 xor (SIGNAL_IN10313 or (not SIGNAL_IN10315)))) + TO_UNSIGNED(4264355552, 32)) + SIGNAL_IN10316) rol 10));
SIGNAL10321 <= SIGNAL_IN10315;
END ARCHITECTURE ARCH;
ENTITY CHIP10322 IS
PORT(SIGNAL_IN10323 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10324 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10325 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10326 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10327 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10328 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10329 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10330 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10331 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10322;
ARCHITECTURE ARCH OF CHIP10322 IS
SIGNAL SIGNAL10332 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10332 <= SIGNAL_IN10326;
SIGNAL_OUT10331 <= SIGNAL_IN10325;
SIGNAL_OUT10330 <= SIGNAL_IN10324;
SIGNAL_OUT10329 <= (SIGNAL_IN10324 + ((((SIGNAL_IN10323 + (SIGNAL_IN10325 xor (SIGNAL_IN10324 or (not SIGNAL_IN10326)))) + TO_UNSIGNED(2734768916, 32)) + SIGNAL_IN10327) rol 15));
SIGNAL10332 <= SIGNAL_IN10326;
END ARCHITECTURE ARCH;
ENTITY CHIP10333 IS
PORT(SIGNAL_IN10334 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10335 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10336 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10337 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10338 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10339 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10340 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10341 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10342 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10333;
ARCHITECTURE ARCH OF CHIP10333 IS
SIGNAL SIGNAL10343 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10343 <= SIGNAL_IN10337;
SIGNAL_OUT10342 <= SIGNAL_IN10336;
SIGNAL_OUT10341 <= SIGNAL_IN10335;
SIGNAL_OUT10340 <= (SIGNAL_IN10335 + ((((SIGNAL_IN10334 + (SIGNAL_IN10336 xor (SIGNAL_IN10335 or (not SIGNAL_IN10337)))) + TO_UNSIGNED(1309151649, 32)) + SIGNAL_IN10338) rol 21));
SIGNAL10343 <= SIGNAL_IN10337;
END ARCHITECTURE ARCH;
ENTITY CHIP10344 IS
PORT(SIGNAL_IN10345 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10346 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10347 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10348 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10349 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10350 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10351 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10352 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10353 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10344;
ARCHITECTURE ARCH OF CHIP10344 IS
SIGNAL SIGNAL10354 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10354 <= SIGNAL_IN10348;
SIGNAL_OUT10353 <= SIGNAL_IN10347;
SIGNAL_OUT10352 <= SIGNAL_IN10346;
SIGNAL_OUT10351 <= (SIGNAL_IN10346 + ((((SIGNAL_IN10345 + (SIGNAL_IN10347 xor (SIGNAL_IN10346 or (not SIGNAL_IN10348)))) + TO_UNSIGNED(4149444226, 32)) + SIGNAL_IN10349) rol 6));
SIGNAL10354 <= SIGNAL_IN10348;
END ARCHITECTURE ARCH;
ENTITY CHIP10355 IS
PORT(SIGNAL_IN10356 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10357 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10358 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10359 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10360 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10361 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10362 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10363 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10364 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10355;
ARCHITECTURE ARCH OF CHIP10355 IS
SIGNAL SIGNAL10365 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10365 <= SIGNAL_IN10359;
SIGNAL_OUT10364 <= SIGNAL_IN10358;
SIGNAL_OUT10363 <= SIGNAL_IN10357;
SIGNAL_OUT10362 <= (SIGNAL_IN10357 + ((((SIGNAL_IN10356 + (SIGNAL_IN10358 xor (SIGNAL_IN10357 or (not SIGNAL_IN10359)))) + TO_UNSIGNED(3174756917, 32)) + SIGNAL_IN10360) rol 10));
SIGNAL10365 <= SIGNAL_IN10359;
END ARCHITECTURE ARCH;
ENTITY CHIP10366 IS
PORT(SIGNAL_IN10367 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10368 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10369 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10370 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10371 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10372 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10373 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10374 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10375 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10366;
ARCHITECTURE ARCH OF CHIP10366 IS
SIGNAL SIGNAL10376 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10376 <= SIGNAL_IN10370;
SIGNAL_OUT10375 <= SIGNAL_IN10369;
SIGNAL_OUT10374 <= SIGNAL_IN10368;
SIGNAL_OUT10373 <= (SIGNAL_IN10368 + ((((SIGNAL_IN10367 + (SIGNAL_IN10369 xor (SIGNAL_IN10368 or (not SIGNAL_IN10370)))) + TO_UNSIGNED(718787259, 32)) + SIGNAL_IN10371) rol 15));
SIGNAL10376 <= SIGNAL_IN10370;
END ARCHITECTURE ARCH;
ENTITY CHIP10377 IS
PORT(SIGNAL_IN10378 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10379 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10380 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10381 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10382 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10383 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10384 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10385 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10386 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10377;
ARCHITECTURE ARCH OF CHIP10377 IS
SIGNAL SIGNAL10387 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10387 <= SIGNAL_IN10381;
SIGNAL_OUT10386 <= SIGNAL_IN10380;
SIGNAL_OUT10385 <= SIGNAL_IN10379;
SIGNAL_OUT10384 <= (SIGNAL_IN10379 + ((((SIGNAL_IN10378 + (SIGNAL_IN10380 xor (SIGNAL_IN10379 or (not SIGNAL_IN10381)))) + TO_UNSIGNED(3951481745, 32)) + SIGNAL_IN10382) rol 21));
SIGNAL10387 <= SIGNAL_IN10381;
END ARCHITECTURE ARCH;
ENTITY CHIP9398 IS
PORT(SIGNAL_IN9399 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9400 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9401 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9402 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9403 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
SIGNAL_OUT9404 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9405 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9406 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9407 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9398;
ARCHITECTURE ARCH OF CHIP9398 IS
SIGNAL SIGNAL9408 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9409 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9410 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9411 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9412 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9413 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9414 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9415 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9416 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9417 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9418 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9419 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9420 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9421 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9422 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9423 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9424 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9425 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9426 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9427 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9428 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9429 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9430 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9431 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9432 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9433 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9434 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9435 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9436 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9437 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9438 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9439 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9440 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9441 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9442 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9443 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9444 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9445 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9446 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9447 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9448 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9449 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9450 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9451 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9452 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9453 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9454 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9455 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9456 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9457 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9458 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9459 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9460 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9461 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9462 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9463 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9464 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9465 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9466 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9467 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9468 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9469 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9470 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9471 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9472 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9473 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9474 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9475 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9476 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9477 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9478 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9479 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9480 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9481 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9482 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9483 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9484 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9485 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9486 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9487 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9488 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9489 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9490 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9491 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9492 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9493 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9494 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9495 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9496 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9497 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9498 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9499 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9500 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9501 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9502 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9503 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9504 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9505 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9506 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9507 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9508 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9509 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9510 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9511 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9512 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9513 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9514 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9515 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9516 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9517 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9518 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9519 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9520 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9521 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9522 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9523 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9524 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9525 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9526 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9527 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9528 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9529 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9530 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9531 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9532 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9533 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9534 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9535 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9536 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9537 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9538 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9539 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9540 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9541 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9542 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9543 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9544 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9545 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9546 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9547 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9548 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9549 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9550 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9551 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9552 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9553 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9554 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9555 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9556 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9557 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9558 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9559 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9560 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9561 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9562 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9563 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9564 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9565 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9566 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9567 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9568 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9569 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9570 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9571 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9572 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9573 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9574 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9575 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9576 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9577 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9578 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9579 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9580 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9581 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9582 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9583 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9584 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9585 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9586 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9587 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9588 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9589 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9590 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9591 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9592 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9593 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9594 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9595 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9596 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9597 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9598 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9599 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9600 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9601 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9602 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9603 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9604 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9605 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9606 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9607 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9608 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9609 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9610 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9611 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9612 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9613 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9614 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9615 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9616 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9617 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9618 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9619 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9620 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9621 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9622 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9623 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9624 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9625 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9626 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9627 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9628 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9629 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9630 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9631 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9632 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9633 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9634 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9635 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9636 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9637 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9638 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9639 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9640 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9641 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9642 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9643 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9644 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9645 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9646 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9647 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9648 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9649 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9650 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9651 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9652 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9653 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9654 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9655 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9656 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9657 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9658 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9659 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9660 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9661 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9662 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9663 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9664 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9665 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9666 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9667 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9668 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9669 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9670 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9671 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9672 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9673 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9674 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9675 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9676 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9677 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9678 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9679 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9408 <= UNSIGNED(SIGNAL_IN9403(31 DOWNTO 0));
SIGNAL9409 <= UNSIGNED(SIGNAL_IN9403(63 DOWNTO 32));
SIGNAL9410 <= UNSIGNED(SIGNAL_IN9403(95 DOWNTO 64));
SIGNAL9411 <= UNSIGNED(SIGNAL_IN9403(127 DOWNTO 96));
SIGNAL9412 <= UNSIGNED(SIGNAL_IN9403(159 DOWNTO 128));
SIGNAL9413 <= UNSIGNED(SIGNAL_IN9403(191 DOWNTO 160));
SIGNAL9414 <= UNSIGNED(SIGNAL_IN9403(223 DOWNTO 192));
SIGNAL9415 <= UNSIGNED(SIGNAL_IN9403(255 DOWNTO 224));
SIGNAL9416 <= UNSIGNED(SIGNAL_IN9403(287 DOWNTO 256));
SIGNAL9417 <= UNSIGNED(SIGNAL_IN9403(319 DOWNTO 288));
SIGNAL9418 <= UNSIGNED(SIGNAL_IN9403(351 DOWNTO 320));
SIGNAL9419 <= UNSIGNED(SIGNAL_IN9403(383 DOWNTO 352));
SIGNAL9420 <= UNSIGNED(SIGNAL_IN9403(415 DOWNTO 384));
SIGNAL9421 <= UNSIGNED(SIGNAL_IN9403(447 DOWNTO 416));
SIGNAL9422 <= UNSIGNED(SIGNAL_IN9403(479 DOWNTO 448));
SIGNAL9423 <= UNSIGNED(SIGNAL_IN9403(511 DOWNTO 480));
CHIP_INST10388 : ENTITY CHIP9684(ARCH) PORT MAP(SIGNAL_IN9685 => SIGNAL_IN9399
, SIGNAL_IN9686 => SIGNAL_IN9400
, SIGNAL_IN9687 => SIGNAL_IN9401
, SIGNAL_IN9688 => SIGNAL_IN9402
, SIGNAL_IN9689 => SIGNAL9408
, SIGNAL_OUT9690 => SIGNAL9425
, SIGNAL_OUT9691 => SIGNAL9489
, SIGNAL_OUT9692 => SIGNAL9553
, SIGNAL_OUT9693 => SIGNAL9617
);
CHIP_INST10389 : ENTITY CHIP9695(ARCH) PORT MAP(SIGNAL_IN9696 => SIGNAL9425
, SIGNAL_IN9697 => SIGNAL9489
, SIGNAL_IN9698 => SIGNAL9553
, SIGNAL_IN9699 => SIGNAL9617
, SIGNAL_IN9700 => SIGNAL9409
, SIGNAL_OUT9701 => SIGNAL9426
, SIGNAL_OUT9702 => SIGNAL9490
, SIGNAL_OUT9703 => SIGNAL9554
, SIGNAL_OUT9704 => SIGNAL9618
);
CHIP_INST10390 : ENTITY CHIP9706(ARCH) PORT MAP(SIGNAL_IN9707 => SIGNAL9426
, SIGNAL_IN9708 => SIGNAL9490
, SIGNAL_IN9709 => SIGNAL9554
, SIGNAL_IN9710 => SIGNAL9618
, SIGNAL_IN9711 => SIGNAL9410
, SIGNAL_OUT9712 => SIGNAL9427
, SIGNAL_OUT9713 => SIGNAL9491
, SIGNAL_OUT9714 => SIGNAL9555
, SIGNAL_OUT9715 => SIGNAL9619
);
CHIP_INST10391 : ENTITY CHIP9717(ARCH) PORT MAP(SIGNAL_IN9718 => SIGNAL9427
, SIGNAL_IN9719 => SIGNAL9491
, SIGNAL_IN9720 => SIGNAL9555
, SIGNAL_IN9721 => SIGNAL9619
, SIGNAL_IN9722 => SIGNAL9411
, SIGNAL_OUT9723 => SIGNAL9428
, SIGNAL_OUT9724 => SIGNAL9492
, SIGNAL_OUT9725 => SIGNAL9556
, SIGNAL_OUT9726 => SIGNAL9620
);
CHIP_INST10392 : ENTITY CHIP9728(ARCH) PORT MAP(SIGNAL_IN9729 => SIGNAL9428
, SIGNAL_IN9730 => SIGNAL9492
, SIGNAL_IN9731 => SIGNAL9556
, SIGNAL_IN9732 => SIGNAL9620
, SIGNAL_IN9733 => SIGNAL9412
, SIGNAL_OUT9734 => SIGNAL9429
, SIGNAL_OUT9735 => SIGNAL9493
, SIGNAL_OUT9736 => SIGNAL9557
, SIGNAL_OUT9737 => SIGNAL9621
);
CHIP_INST10393 : ENTITY CHIP9739(ARCH) PORT MAP(SIGNAL_IN9740 => SIGNAL9429
, SIGNAL_IN9741 => SIGNAL9493
, SIGNAL_IN9742 => SIGNAL9557
, SIGNAL_IN9743 => SIGNAL9621
, SIGNAL_IN9744 => SIGNAL9413
, SIGNAL_OUT9745 => SIGNAL9430
, SIGNAL_OUT9746 => SIGNAL9494
, SIGNAL_OUT9747 => SIGNAL9558
, SIGNAL_OUT9748 => SIGNAL9622
);
CHIP_INST10394 : ENTITY CHIP9750(ARCH) PORT MAP(SIGNAL_IN9751 => SIGNAL9430
, SIGNAL_IN9752 => SIGNAL9494
, SIGNAL_IN9753 => SIGNAL9558
, SIGNAL_IN9754 => SIGNAL9622
, SIGNAL_IN9755 => SIGNAL9414
, SIGNAL_OUT9756 => SIGNAL9431
, SIGNAL_OUT9757 => SIGNAL9495
, SIGNAL_OUT9758 => SIGNAL9559
, SIGNAL_OUT9759 => SIGNAL9623
);
CHIP_INST10395 : ENTITY CHIP9761(ARCH) PORT MAP(SIGNAL_IN9762 => SIGNAL9431
, SIGNAL_IN9763 => SIGNAL9495
, SIGNAL_IN9764 => SIGNAL9559
, SIGNAL_IN9765 => SIGNAL9623
, SIGNAL_IN9766 => SIGNAL9415
, SIGNAL_OUT9767 => SIGNAL9432
, SIGNAL_OUT9768 => SIGNAL9496
, SIGNAL_OUT9769 => SIGNAL9560
, SIGNAL_OUT9770 => SIGNAL9624
);
CHIP_INST10396 : ENTITY CHIP9772(ARCH) PORT MAP(SIGNAL_IN9773 => SIGNAL9432
, SIGNAL_IN9774 => SIGNAL9496
, SIGNAL_IN9775 => SIGNAL9560
, SIGNAL_IN9776 => SIGNAL9624
, SIGNAL_IN9777 => SIGNAL9416
, SIGNAL_OUT9778 => SIGNAL9433
, SIGNAL_OUT9779 => SIGNAL9497
, SIGNAL_OUT9780 => SIGNAL9561
, SIGNAL_OUT9781 => SIGNAL9625
);
CHIP_INST10397 : ENTITY CHIP9783(ARCH) PORT MAP(SIGNAL_IN9784 => SIGNAL9433
, SIGNAL_IN9785 => SIGNAL9497
, SIGNAL_IN9786 => SIGNAL9561
, SIGNAL_IN9787 => SIGNAL9625
, SIGNAL_IN9788 => SIGNAL9417
, SIGNAL_OUT9789 => SIGNAL9434
, SIGNAL_OUT9790 => SIGNAL9498
, SIGNAL_OUT9791 => SIGNAL9562
, SIGNAL_OUT9792 => SIGNAL9626
);
CHIP_INST10398 : ENTITY CHIP9794(ARCH) PORT MAP(SIGNAL_IN9795 => SIGNAL9434
, SIGNAL_IN9796 => SIGNAL9498
, SIGNAL_IN9797 => SIGNAL9562
, SIGNAL_IN9798 => SIGNAL9626
, SIGNAL_IN9799 => SIGNAL9418
, SIGNAL_OUT9800 => SIGNAL9435
, SIGNAL_OUT9801 => SIGNAL9499
, SIGNAL_OUT9802 => SIGNAL9563
, SIGNAL_OUT9803 => SIGNAL9627
);
CHIP_INST10399 : ENTITY CHIP9805(ARCH) PORT MAP(SIGNAL_IN9806 => SIGNAL9435
, SIGNAL_IN9807 => SIGNAL9499
, SIGNAL_IN9808 => SIGNAL9563
, SIGNAL_IN9809 => SIGNAL9627
, SIGNAL_IN9810 => SIGNAL9419
, SIGNAL_OUT9811 => SIGNAL9436
, SIGNAL_OUT9812 => SIGNAL9500
, SIGNAL_OUT9813 => SIGNAL9564
, SIGNAL_OUT9814 => SIGNAL9628
);
CHIP_INST10400 : ENTITY CHIP9816(ARCH) PORT MAP(SIGNAL_IN9817 => SIGNAL9436
, SIGNAL_IN9818 => SIGNAL9500
, SIGNAL_IN9819 => SIGNAL9564
, SIGNAL_IN9820 => SIGNAL9628
, SIGNAL_IN9821 => SIGNAL9420
, SIGNAL_OUT9822 => SIGNAL9437
, SIGNAL_OUT9823 => SIGNAL9501
, SIGNAL_OUT9824 => SIGNAL9565
, SIGNAL_OUT9825 => SIGNAL9629
);
CHIP_INST10401 : ENTITY CHIP9827(ARCH) PORT MAP(SIGNAL_IN9828 => SIGNAL9437
, SIGNAL_IN9829 => SIGNAL9501
, SIGNAL_IN9830 => SIGNAL9565
, SIGNAL_IN9831 => SIGNAL9629
, SIGNAL_IN9832 => SIGNAL9421
, SIGNAL_OUT9833 => SIGNAL9438
, SIGNAL_OUT9834 => SIGNAL9502
, SIGNAL_OUT9835 => SIGNAL9566
, SIGNAL_OUT9836 => SIGNAL9630
);
CHIP_INST10402 : ENTITY CHIP9838(ARCH) PORT MAP(SIGNAL_IN9839 => SIGNAL9438
, SIGNAL_IN9840 => SIGNAL9502
, SIGNAL_IN9841 => SIGNAL9566
, SIGNAL_IN9842 => SIGNAL9630
, SIGNAL_IN9843 => SIGNAL9422
, SIGNAL_OUT9844 => SIGNAL9439
, SIGNAL_OUT9845 => SIGNAL9503
, SIGNAL_OUT9846 => SIGNAL9567
, SIGNAL_OUT9847 => SIGNAL9631
);
CHIP_INST10403 : ENTITY CHIP9849(ARCH) PORT MAP(SIGNAL_IN9850 => SIGNAL9439
, SIGNAL_IN9851 => SIGNAL9503
, SIGNAL_IN9852 => SIGNAL9567
, SIGNAL_IN9853 => SIGNAL9631
, SIGNAL_IN9854 => SIGNAL9423
, SIGNAL_OUT9855 => SIGNAL9440
, SIGNAL_OUT9856 => SIGNAL9504
, SIGNAL_OUT9857 => SIGNAL9568
, SIGNAL_OUT9858 => SIGNAL9632
);
CHIP_INST10404 : ENTITY CHIP9860(ARCH) PORT MAP(SIGNAL_IN9861 => SIGNAL9440
, SIGNAL_IN9862 => SIGNAL9504
, SIGNAL_IN9863 => SIGNAL9568
, SIGNAL_IN9864 => SIGNAL9632
, SIGNAL_IN9865 => SIGNAL9409
, SIGNAL_OUT9866 => SIGNAL9441
, SIGNAL_OUT9867 => SIGNAL9505
, SIGNAL_OUT9868 => SIGNAL9569
, SIGNAL_OUT9869 => SIGNAL9633
);
CHIP_INST10405 : ENTITY CHIP9871(ARCH) PORT MAP(SIGNAL_IN9872 => SIGNAL9441
, SIGNAL_IN9873 => SIGNAL9505
, SIGNAL_IN9874 => SIGNAL9569
, SIGNAL_IN9875 => SIGNAL9633
, SIGNAL_IN9876 => SIGNAL9414
, SIGNAL_OUT9877 => SIGNAL9442
, SIGNAL_OUT9878 => SIGNAL9506
, SIGNAL_OUT9879 => SIGNAL9570
, SIGNAL_OUT9880 => SIGNAL9634
);
CHIP_INST10406 : ENTITY CHIP9882(ARCH) PORT MAP(SIGNAL_IN9883 => SIGNAL9442
, SIGNAL_IN9884 => SIGNAL9506
, SIGNAL_IN9885 => SIGNAL9570
, SIGNAL_IN9886 => SIGNAL9634
, SIGNAL_IN9887 => SIGNAL9419
, SIGNAL_OUT9888 => SIGNAL9443
, SIGNAL_OUT9889 => SIGNAL9507
, SIGNAL_OUT9890 => SIGNAL9571
, SIGNAL_OUT9891 => SIGNAL9635
);
CHIP_INST10407 : ENTITY CHIP9893(ARCH) PORT MAP(SIGNAL_IN9894 => SIGNAL9443
, SIGNAL_IN9895 => SIGNAL9507
, SIGNAL_IN9896 => SIGNAL9571
, SIGNAL_IN9897 => SIGNAL9635
, SIGNAL_IN9898 => SIGNAL9408
, SIGNAL_OUT9899 => SIGNAL9444
, SIGNAL_OUT9900 => SIGNAL9508
, SIGNAL_OUT9901 => SIGNAL9572
, SIGNAL_OUT9902 => SIGNAL9636
);
CHIP_INST10408 : ENTITY CHIP9904(ARCH) PORT MAP(SIGNAL_IN9905 => SIGNAL9444
, SIGNAL_IN9906 => SIGNAL9508
, SIGNAL_IN9907 => SIGNAL9572
, SIGNAL_IN9908 => SIGNAL9636
, SIGNAL_IN9909 => SIGNAL9413
, SIGNAL_OUT9910 => SIGNAL9445
, SIGNAL_OUT9911 => SIGNAL9509
, SIGNAL_OUT9912 => SIGNAL9573
, SIGNAL_OUT9913 => SIGNAL9637
);
CHIP_INST10409 : ENTITY CHIP9915(ARCH) PORT MAP(SIGNAL_IN9916 => SIGNAL9445
, SIGNAL_IN9917 => SIGNAL9509
, SIGNAL_IN9918 => SIGNAL9573
, SIGNAL_IN9919 => SIGNAL9637
, SIGNAL_IN9920 => SIGNAL9418
, SIGNAL_OUT9921 => SIGNAL9446
, SIGNAL_OUT9922 => SIGNAL9510
, SIGNAL_OUT9923 => SIGNAL9574
, SIGNAL_OUT9924 => SIGNAL9638
);
CHIP_INST10410 : ENTITY CHIP9926(ARCH) PORT MAP(SIGNAL_IN9927 => SIGNAL9446
, SIGNAL_IN9928 => SIGNAL9510
, SIGNAL_IN9929 => SIGNAL9574
, SIGNAL_IN9930 => SIGNAL9638
, SIGNAL_IN9931 => SIGNAL9423
, SIGNAL_OUT9932 => SIGNAL9447
, SIGNAL_OUT9933 => SIGNAL9511
, SIGNAL_OUT9934 => SIGNAL9575
, SIGNAL_OUT9935 => SIGNAL9639
);
CHIP_INST10411 : ENTITY CHIP9937(ARCH) PORT MAP(SIGNAL_IN9938 => SIGNAL9447
, SIGNAL_IN9939 => SIGNAL9511
, SIGNAL_IN9940 => SIGNAL9575
, SIGNAL_IN9941 => SIGNAL9639
, SIGNAL_IN9942 => SIGNAL9412
, SIGNAL_OUT9943 => SIGNAL9448
, SIGNAL_OUT9944 => SIGNAL9512
, SIGNAL_OUT9945 => SIGNAL9576
, SIGNAL_OUT9946 => SIGNAL9640
);
CHIP_INST10412 : ENTITY CHIP9948(ARCH) PORT MAP(SIGNAL_IN9949 => SIGNAL9448
, SIGNAL_IN9950 => SIGNAL9512
, SIGNAL_IN9951 => SIGNAL9576
, SIGNAL_IN9952 => SIGNAL9640
, SIGNAL_IN9953 => SIGNAL9417
, SIGNAL_OUT9954 => SIGNAL9449
, SIGNAL_OUT9955 => SIGNAL9513
, SIGNAL_OUT9956 => SIGNAL9577
, SIGNAL_OUT9957 => SIGNAL9641
);
CHIP_INST10413 : ENTITY CHIP9959(ARCH) PORT MAP(SIGNAL_IN9960 => SIGNAL9449
, SIGNAL_IN9961 => SIGNAL9513
, SIGNAL_IN9962 => SIGNAL9577
, SIGNAL_IN9963 => SIGNAL9641
, SIGNAL_IN9964 => SIGNAL9422
, SIGNAL_OUT9965 => SIGNAL9450
, SIGNAL_OUT9966 => SIGNAL9514
, SIGNAL_OUT9967 => SIGNAL9578
, SIGNAL_OUT9968 => SIGNAL9642
);
CHIP_INST10414 : ENTITY CHIP9970(ARCH) PORT MAP(SIGNAL_IN9971 => SIGNAL9450
, SIGNAL_IN9972 => SIGNAL9514
, SIGNAL_IN9973 => SIGNAL9578
, SIGNAL_IN9974 => SIGNAL9642
, SIGNAL_IN9975 => SIGNAL9411
, SIGNAL_OUT9976 => SIGNAL9451
, SIGNAL_OUT9977 => SIGNAL9515
, SIGNAL_OUT9978 => SIGNAL9579
, SIGNAL_OUT9979 => SIGNAL9643
);
CHIP_INST10415 : ENTITY CHIP9981(ARCH) PORT MAP(SIGNAL_IN9982 => SIGNAL9451
, SIGNAL_IN9983 => SIGNAL9515
, SIGNAL_IN9984 => SIGNAL9579
, SIGNAL_IN9985 => SIGNAL9643
, SIGNAL_IN9986 => SIGNAL9416
, SIGNAL_OUT9987 => SIGNAL9452
, SIGNAL_OUT9988 => SIGNAL9516
, SIGNAL_OUT9989 => SIGNAL9580
, SIGNAL_OUT9990 => SIGNAL9644
);
CHIP_INST10416 : ENTITY CHIP9992(ARCH) PORT MAP(SIGNAL_IN9993 => SIGNAL9452
, SIGNAL_IN9994 => SIGNAL9516
, SIGNAL_IN9995 => SIGNAL9580
, SIGNAL_IN9996 => SIGNAL9644
, SIGNAL_IN9997 => SIGNAL9421
, SIGNAL_OUT9998 => SIGNAL9453
, SIGNAL_OUT9999 => SIGNAL9517
, SIGNAL_OUT10000 => SIGNAL9581
, SIGNAL_OUT10001 => SIGNAL9645
);
CHIP_INST10417 : ENTITY CHIP10003(ARCH) PORT MAP(SIGNAL_IN10004 => SIGNAL9453
, SIGNAL_IN10005 => SIGNAL9517
, SIGNAL_IN10006 => SIGNAL9581
, SIGNAL_IN10007 => SIGNAL9645
, SIGNAL_IN10008 => SIGNAL9410
, SIGNAL_OUT10009 => SIGNAL9454
, SIGNAL_OUT10010 => SIGNAL9518
, SIGNAL_OUT10011 => SIGNAL9582
, SIGNAL_OUT10012 => SIGNAL9646
);
CHIP_INST10418 : ENTITY CHIP10014(ARCH) PORT MAP(SIGNAL_IN10015 => SIGNAL9454
, SIGNAL_IN10016 => SIGNAL9518
, SIGNAL_IN10017 => SIGNAL9582
, SIGNAL_IN10018 => SIGNAL9646
, SIGNAL_IN10019 => SIGNAL9415
, SIGNAL_OUT10020 => SIGNAL9455
, SIGNAL_OUT10021 => SIGNAL9519
, SIGNAL_OUT10022 => SIGNAL9583
, SIGNAL_OUT10023 => SIGNAL9647
);
CHIP_INST10419 : ENTITY CHIP10025(ARCH) PORT MAP(SIGNAL_IN10026 => SIGNAL9455
, SIGNAL_IN10027 => SIGNAL9519
, SIGNAL_IN10028 => SIGNAL9583
, SIGNAL_IN10029 => SIGNAL9647
, SIGNAL_IN10030 => SIGNAL9420
, SIGNAL_OUT10031 => SIGNAL9456
, SIGNAL_OUT10032 => SIGNAL9520
, SIGNAL_OUT10033 => SIGNAL9584
, SIGNAL_OUT10034 => SIGNAL9648
);
CHIP_INST10420 : ENTITY CHIP10036(ARCH) PORT MAP(SIGNAL_IN10037 => SIGNAL9456
, SIGNAL_IN10038 => SIGNAL9520
, SIGNAL_IN10039 => SIGNAL9584
, SIGNAL_IN10040 => SIGNAL9648
, SIGNAL_IN10041 => SIGNAL9413
, SIGNAL_OUT10042 => SIGNAL9457
, SIGNAL_OUT10043 => SIGNAL9521
, SIGNAL_OUT10044 => SIGNAL9585
, SIGNAL_OUT10045 => SIGNAL9649
);
CHIP_INST10421 : ENTITY CHIP10047(ARCH) PORT MAP(SIGNAL_IN10048 => SIGNAL9457
, SIGNAL_IN10049 => SIGNAL9521
, SIGNAL_IN10050 => SIGNAL9585
, SIGNAL_IN10051 => SIGNAL9649
, SIGNAL_IN10052 => SIGNAL9416
, SIGNAL_OUT10053 => SIGNAL9458
, SIGNAL_OUT10054 => SIGNAL9522
, SIGNAL_OUT10055 => SIGNAL9586
, SIGNAL_OUT10056 => SIGNAL9650
);
CHIP_INST10422 : ENTITY CHIP10058(ARCH) PORT MAP(SIGNAL_IN10059 => SIGNAL9458
, SIGNAL_IN10060 => SIGNAL9522
, SIGNAL_IN10061 => SIGNAL9586
, SIGNAL_IN10062 => SIGNAL9650
, SIGNAL_IN10063 => SIGNAL9419
, SIGNAL_OUT10064 => SIGNAL9459
, SIGNAL_OUT10065 => SIGNAL9523
, SIGNAL_OUT10066 => SIGNAL9587
, SIGNAL_OUT10067 => SIGNAL9651
);
CHIP_INST10423 : ENTITY CHIP10069(ARCH) PORT MAP(SIGNAL_IN10070 => SIGNAL9459
, SIGNAL_IN10071 => SIGNAL9523
, SIGNAL_IN10072 => SIGNAL9587
, SIGNAL_IN10073 => SIGNAL9651
, SIGNAL_IN10074 => SIGNAL9422
, SIGNAL_OUT10075 => SIGNAL9460
, SIGNAL_OUT10076 => SIGNAL9524
, SIGNAL_OUT10077 => SIGNAL9588
, SIGNAL_OUT10078 => SIGNAL9652
);
CHIP_INST10424 : ENTITY CHIP10080(ARCH) PORT MAP(SIGNAL_IN10081 => SIGNAL9460
, SIGNAL_IN10082 => SIGNAL9524
, SIGNAL_IN10083 => SIGNAL9588
, SIGNAL_IN10084 => SIGNAL9652
, SIGNAL_IN10085 => SIGNAL9409
, SIGNAL_OUT10086 => SIGNAL9461
, SIGNAL_OUT10087 => SIGNAL9525
, SIGNAL_OUT10088 => SIGNAL9589
, SIGNAL_OUT10089 => SIGNAL9653
);
CHIP_INST10425 : ENTITY CHIP10091(ARCH) PORT MAP(SIGNAL_IN10092 => SIGNAL9461
, SIGNAL_IN10093 => SIGNAL9525
, SIGNAL_IN10094 => SIGNAL9589
, SIGNAL_IN10095 => SIGNAL9653
, SIGNAL_IN10096 => SIGNAL9412
, SIGNAL_OUT10097 => SIGNAL9462
, SIGNAL_OUT10098 => SIGNAL9526
, SIGNAL_OUT10099 => SIGNAL9590
, SIGNAL_OUT10100 => SIGNAL9654
);
CHIP_INST10426 : ENTITY CHIP10102(ARCH) PORT MAP(SIGNAL_IN10103 => SIGNAL9462
, SIGNAL_IN10104 => SIGNAL9526
, SIGNAL_IN10105 => SIGNAL9590
, SIGNAL_IN10106 => SIGNAL9654
, SIGNAL_IN10107 => SIGNAL9415
, SIGNAL_OUT10108 => SIGNAL9463
, SIGNAL_OUT10109 => SIGNAL9527
, SIGNAL_OUT10110 => SIGNAL9591
, SIGNAL_OUT10111 => SIGNAL9655
);
CHIP_INST10427 : ENTITY CHIP10113(ARCH) PORT MAP(SIGNAL_IN10114 => SIGNAL9463
, SIGNAL_IN10115 => SIGNAL9527
, SIGNAL_IN10116 => SIGNAL9591
, SIGNAL_IN10117 => SIGNAL9655
, SIGNAL_IN10118 => SIGNAL9418
, SIGNAL_OUT10119 => SIGNAL9464
, SIGNAL_OUT10120 => SIGNAL9528
, SIGNAL_OUT10121 => SIGNAL9592
, SIGNAL_OUT10122 => SIGNAL9656
);
CHIP_INST10428 : ENTITY CHIP10124(ARCH) PORT MAP(SIGNAL_IN10125 => SIGNAL9464
, SIGNAL_IN10126 => SIGNAL9528
, SIGNAL_IN10127 => SIGNAL9592
, SIGNAL_IN10128 => SIGNAL9656
, SIGNAL_IN10129 => SIGNAL9421
, SIGNAL_OUT10130 => SIGNAL9465
, SIGNAL_OUT10131 => SIGNAL9529
, SIGNAL_OUT10132 => SIGNAL9593
, SIGNAL_OUT10133 => SIGNAL9657
);
CHIP_INST10429 : ENTITY CHIP10135(ARCH) PORT MAP(SIGNAL_IN10136 => SIGNAL9465
, SIGNAL_IN10137 => SIGNAL9529
, SIGNAL_IN10138 => SIGNAL9593
, SIGNAL_IN10139 => SIGNAL9657
, SIGNAL_IN10140 => SIGNAL9408
, SIGNAL_OUT10141 => SIGNAL9466
, SIGNAL_OUT10142 => SIGNAL9530
, SIGNAL_OUT10143 => SIGNAL9594
, SIGNAL_OUT10144 => SIGNAL9658
);
CHIP_INST10430 : ENTITY CHIP10146(ARCH) PORT MAP(SIGNAL_IN10147 => SIGNAL9466
, SIGNAL_IN10148 => SIGNAL9530
, SIGNAL_IN10149 => SIGNAL9594
, SIGNAL_IN10150 => SIGNAL9658
, SIGNAL_IN10151 => SIGNAL9411
, SIGNAL_OUT10152 => SIGNAL9467
, SIGNAL_OUT10153 => SIGNAL9531
, SIGNAL_OUT10154 => SIGNAL9595
, SIGNAL_OUT10155 => SIGNAL9659
);
CHIP_INST10431 : ENTITY CHIP10157(ARCH) PORT MAP(SIGNAL_IN10158 => SIGNAL9467
, SIGNAL_IN10159 => SIGNAL9531
, SIGNAL_IN10160 => SIGNAL9595
, SIGNAL_IN10161 => SIGNAL9659
, SIGNAL_IN10162 => SIGNAL9414
, SIGNAL_OUT10163 => SIGNAL9468
, SIGNAL_OUT10164 => SIGNAL9532
, SIGNAL_OUT10165 => SIGNAL9596
, SIGNAL_OUT10166 => SIGNAL9660
);
CHIP_INST10432 : ENTITY CHIP10168(ARCH) PORT MAP(SIGNAL_IN10169 => SIGNAL9468
, SIGNAL_IN10170 => SIGNAL9532
, SIGNAL_IN10171 => SIGNAL9596
, SIGNAL_IN10172 => SIGNAL9660
, SIGNAL_IN10173 => SIGNAL9417
, SIGNAL_OUT10174 => SIGNAL9469
, SIGNAL_OUT10175 => SIGNAL9533
, SIGNAL_OUT10176 => SIGNAL9597
, SIGNAL_OUT10177 => SIGNAL9661
);
CHIP_INST10433 : ENTITY CHIP10179(ARCH) PORT MAP(SIGNAL_IN10180 => SIGNAL9469
, SIGNAL_IN10181 => SIGNAL9533
, SIGNAL_IN10182 => SIGNAL9597
, SIGNAL_IN10183 => SIGNAL9661
, SIGNAL_IN10184 => SIGNAL9420
, SIGNAL_OUT10185 => SIGNAL9470
, SIGNAL_OUT10186 => SIGNAL9534
, SIGNAL_OUT10187 => SIGNAL9598
, SIGNAL_OUT10188 => SIGNAL9662
);
CHIP_INST10434 : ENTITY CHIP10190(ARCH) PORT MAP(SIGNAL_IN10191 => SIGNAL9470
, SIGNAL_IN10192 => SIGNAL9534
, SIGNAL_IN10193 => SIGNAL9598
, SIGNAL_IN10194 => SIGNAL9662
, SIGNAL_IN10195 => SIGNAL9423
, SIGNAL_OUT10196 => SIGNAL9471
, SIGNAL_OUT10197 => SIGNAL9535
, SIGNAL_OUT10198 => SIGNAL9599
, SIGNAL_OUT10199 => SIGNAL9663
);
CHIP_INST10435 : ENTITY CHIP10201(ARCH) PORT MAP(SIGNAL_IN10202 => SIGNAL9471
, SIGNAL_IN10203 => SIGNAL9535
, SIGNAL_IN10204 => SIGNAL9599
, SIGNAL_IN10205 => SIGNAL9663
, SIGNAL_IN10206 => SIGNAL9410
, SIGNAL_OUT10207 => SIGNAL9472
, SIGNAL_OUT10208 => SIGNAL9536
, SIGNAL_OUT10209 => SIGNAL9600
, SIGNAL_OUT10210 => SIGNAL9664
);
CHIP_INST10436 : ENTITY CHIP10212(ARCH) PORT MAP(SIGNAL_IN10213 => SIGNAL9472
, SIGNAL_IN10214 => SIGNAL9536
, SIGNAL_IN10215 => SIGNAL9600
, SIGNAL_IN10216 => SIGNAL9664
, SIGNAL_IN10217 => SIGNAL9408
, SIGNAL_OUT10218 => SIGNAL9473
, SIGNAL_OUT10219 => SIGNAL9537
, SIGNAL_OUT10220 => SIGNAL9601
, SIGNAL_OUT10221 => SIGNAL9665
);
CHIP_INST10437 : ENTITY CHIP10223(ARCH) PORT MAP(SIGNAL_IN10224 => SIGNAL9473
, SIGNAL_IN10225 => SIGNAL9537
, SIGNAL_IN10226 => SIGNAL9601
, SIGNAL_IN10227 => SIGNAL9665
, SIGNAL_IN10228 => SIGNAL9415
, SIGNAL_OUT10229 => SIGNAL9474
, SIGNAL_OUT10230 => SIGNAL9538
, SIGNAL_OUT10231 => SIGNAL9602
, SIGNAL_OUT10232 => SIGNAL9666
);
CHIP_INST10438 : ENTITY CHIP10234(ARCH) PORT MAP(SIGNAL_IN10235 => SIGNAL9474
, SIGNAL_IN10236 => SIGNAL9538
, SIGNAL_IN10237 => SIGNAL9602
, SIGNAL_IN10238 => SIGNAL9666
, SIGNAL_IN10239 => SIGNAL9422
, SIGNAL_OUT10240 => SIGNAL9475
, SIGNAL_OUT10241 => SIGNAL9539
, SIGNAL_OUT10242 => SIGNAL9603
, SIGNAL_OUT10243 => SIGNAL9667
);
CHIP_INST10439 : ENTITY CHIP10245(ARCH) PORT MAP(SIGNAL_IN10246 => SIGNAL9475
, SIGNAL_IN10247 => SIGNAL9539
, SIGNAL_IN10248 => SIGNAL9603
, SIGNAL_IN10249 => SIGNAL9667
, SIGNAL_IN10250 => SIGNAL9413
, SIGNAL_OUT10251 => SIGNAL9476
, SIGNAL_OUT10252 => SIGNAL9540
, SIGNAL_OUT10253 => SIGNAL9604
, SIGNAL_OUT10254 => SIGNAL9668
);
CHIP_INST10440 : ENTITY CHIP10256(ARCH) PORT MAP(SIGNAL_IN10257 => SIGNAL9476
, SIGNAL_IN10258 => SIGNAL9540
, SIGNAL_IN10259 => SIGNAL9604
, SIGNAL_IN10260 => SIGNAL9668
, SIGNAL_IN10261 => SIGNAL9420
, SIGNAL_OUT10262 => SIGNAL9477
, SIGNAL_OUT10263 => SIGNAL9541
, SIGNAL_OUT10264 => SIGNAL9605
, SIGNAL_OUT10265 => SIGNAL9669
);
CHIP_INST10441 : ENTITY CHIP10267(ARCH) PORT MAP(SIGNAL_IN10268 => SIGNAL9477
, SIGNAL_IN10269 => SIGNAL9541
, SIGNAL_IN10270 => SIGNAL9605
, SIGNAL_IN10271 => SIGNAL9669
, SIGNAL_IN10272 => SIGNAL9411
, SIGNAL_OUT10273 => SIGNAL9478
, SIGNAL_OUT10274 => SIGNAL9542
, SIGNAL_OUT10275 => SIGNAL9606
, SIGNAL_OUT10276 => SIGNAL9670
);
CHIP_INST10442 : ENTITY CHIP10278(ARCH) PORT MAP(SIGNAL_IN10279 => SIGNAL9478
, SIGNAL_IN10280 => SIGNAL9542
, SIGNAL_IN10281 => SIGNAL9606
, SIGNAL_IN10282 => SIGNAL9670
, SIGNAL_IN10283 => SIGNAL9418
, SIGNAL_OUT10284 => SIGNAL9479
, SIGNAL_OUT10285 => SIGNAL9543
, SIGNAL_OUT10286 => SIGNAL9607
, SIGNAL_OUT10287 => SIGNAL9671
);
CHIP_INST10443 : ENTITY CHIP10289(ARCH) PORT MAP(SIGNAL_IN10290 => SIGNAL9479
, SIGNAL_IN10291 => SIGNAL9543
, SIGNAL_IN10292 => SIGNAL9607
, SIGNAL_IN10293 => SIGNAL9671
, SIGNAL_IN10294 => SIGNAL9409
, SIGNAL_OUT10295 => SIGNAL9480
, SIGNAL_OUT10296 => SIGNAL9544
, SIGNAL_OUT10297 => SIGNAL9608
, SIGNAL_OUT10298 => SIGNAL9672
);
CHIP_INST10444 : ENTITY CHIP10300(ARCH) PORT MAP(SIGNAL_IN10301 => SIGNAL9480
, SIGNAL_IN10302 => SIGNAL9544
, SIGNAL_IN10303 => SIGNAL9608
, SIGNAL_IN10304 => SIGNAL9672
, SIGNAL_IN10305 => SIGNAL9416
, SIGNAL_OUT10306 => SIGNAL9481
, SIGNAL_OUT10307 => SIGNAL9545
, SIGNAL_OUT10308 => SIGNAL9609
, SIGNAL_OUT10309 => SIGNAL9673
);
CHIP_INST10445 : ENTITY CHIP10311(ARCH) PORT MAP(SIGNAL_IN10312 => SIGNAL9481
, SIGNAL_IN10313 => SIGNAL9545
, SIGNAL_IN10314 => SIGNAL9609
, SIGNAL_IN10315 => SIGNAL9673
, SIGNAL_IN10316 => SIGNAL9423
, SIGNAL_OUT10317 => SIGNAL9482
, SIGNAL_OUT10318 => SIGNAL9546
, SIGNAL_OUT10319 => SIGNAL9610
, SIGNAL_OUT10320 => SIGNAL9674
);
CHIP_INST10446 : ENTITY CHIP10322(ARCH) PORT MAP(SIGNAL_IN10323 => SIGNAL9482
, SIGNAL_IN10324 => SIGNAL9546
, SIGNAL_IN10325 => SIGNAL9610
, SIGNAL_IN10326 => SIGNAL9674
, SIGNAL_IN10327 => SIGNAL9414
, SIGNAL_OUT10328 => SIGNAL9483
, SIGNAL_OUT10329 => SIGNAL9547
, SIGNAL_OUT10330 => SIGNAL9611
, SIGNAL_OUT10331 => SIGNAL9675
);
CHIP_INST10447 : ENTITY CHIP10333(ARCH) PORT MAP(SIGNAL_IN10334 => SIGNAL9483
, SIGNAL_IN10335 => SIGNAL9547
, SIGNAL_IN10336 => SIGNAL9611
, SIGNAL_IN10337 => SIGNAL9675
, SIGNAL_IN10338 => SIGNAL9421
, SIGNAL_OUT10339 => SIGNAL9484
, SIGNAL_OUT10340 => SIGNAL9548
, SIGNAL_OUT10341 => SIGNAL9612
, SIGNAL_OUT10342 => SIGNAL9676
);
CHIP_INST10448 : ENTITY CHIP10344(ARCH) PORT MAP(SIGNAL_IN10345 => SIGNAL9484
, SIGNAL_IN10346 => SIGNAL9548
, SIGNAL_IN10347 => SIGNAL9612
, SIGNAL_IN10348 => SIGNAL9676
, SIGNAL_IN10349 => SIGNAL9412
, SIGNAL_OUT10350 => SIGNAL9485
, SIGNAL_OUT10351 => SIGNAL9549
, SIGNAL_OUT10352 => SIGNAL9613
, SIGNAL_OUT10353 => SIGNAL9677
);
CHIP_INST10449 : ENTITY CHIP10355(ARCH) PORT MAP(SIGNAL_IN10356 => SIGNAL9485
, SIGNAL_IN10357 => SIGNAL9549
, SIGNAL_IN10358 => SIGNAL9613
, SIGNAL_IN10359 => SIGNAL9677
, SIGNAL_IN10360 => SIGNAL9419
, SIGNAL_OUT10361 => SIGNAL9486
, SIGNAL_OUT10362 => SIGNAL9550
, SIGNAL_OUT10363 => SIGNAL9614
, SIGNAL_OUT10364 => SIGNAL9678
);
CHIP_INST10450 : ENTITY CHIP10366(ARCH) PORT MAP(SIGNAL_IN10367 => SIGNAL9486
, SIGNAL_IN10368 => SIGNAL9550
, SIGNAL_IN10369 => SIGNAL9614
, SIGNAL_IN10370 => SIGNAL9678
, SIGNAL_IN10371 => SIGNAL9410
, SIGNAL_OUT10372 => SIGNAL9487
, SIGNAL_OUT10373 => SIGNAL9551
, SIGNAL_OUT10374 => SIGNAL9615
, SIGNAL_OUT10375 => SIGNAL9679
);
CHIP_INST10451 : ENTITY CHIP10377(ARCH) PORT MAP(SIGNAL_IN10378 => SIGNAL9487
, SIGNAL_IN10379 => SIGNAL9551
, SIGNAL_IN10380 => SIGNAL9615
, SIGNAL_IN10381 => SIGNAL9679
, SIGNAL_IN10382 => SIGNAL9417
, SIGNAL_OUT10383 => SIGNAL_OUT9404
, SIGNAL_OUT10384 => SIGNAL_OUT9405
, SIGNAL_OUT10385 => SIGNAL_OUT9406
, SIGNAL_OUT10386 => SIGNAL_OUT9407
);
END ARCHITECTURE ARCH;
|
-- $Id: pdp11_dmpcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmpcnt - syn
-- Description: pdp11: debug&moni: performance counters
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2-2019.1; ghdl 0.34-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-09-23 1050 14.7 131013 xc6slx16-2 250 337 20 121 s 6.5
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2018-09-29 1051 1.0 Initial version
-- 2018-09-23 1050 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 cntl -/w/f Control register
-- 15 ainc -/w/- enable address autoinc
-- 13:09 caddr -/w/- counter address
-- 07:00 vers r/-/- counter layout version
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start
-- 110 clr clear
-- 111 loa load caddr
-- 01 stat r/-/- Status register
-- 15 ainc r/-/- enable address autoinc
-- 13:09 caddr r/-/- counter address
-- 08 waddr r/-/- word address
-- 00 run r/-/- running
-- 10 data r/-/- Data register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmpcnt_precnt is -- pre-counter
port (
CLK : in slbit; -- clock
CLR : in slbit; -- clear
ENA : in slbit; -- count
DOUT : out slv5 -- data
);
end pdp11_dmpcnt_precnt;
architecture syn of pdp11_dmpcnt_precnt is
signal R_CNT : slv5 := (others=>'0');
begin
proc_cnt: process (CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
R_CNT <= (others=>'0');
else
if ENA = '1' then
R_CNT <= slv(unsigned(R_CNT) + 1);
end if;
end if;
end if;
end process proc_cnt;
DOUT <= R_CNT;
end syn;
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
entity pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(1, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
PERFSIG : in slv32 -- signals to count
);
end pdp11_dmpcnt;
architecture syn of pdp11_dmpcnt is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_stat : slv2 := "01"; -- stat address offset
constant rbaddr_data : slv2 := "10"; -- data address offset
constant cntl_rbf_ainc : integer := 15;
subtype cntl_rbf_caddr is integer range 13 downto 9;
subtype cntl_rbf_vers is integer range 7 downto 0;
subtype cntl_rbf_func is integer range 2 downto 0;
constant stat_rbf_ainc : integer := 15;
subtype stat_rbf_caddr is integer range 13 downto 9;
constant stat_rbf_waddr : integer := 8;
constant stat_rbf_run : integer := 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_clr : slv3 := "110"; -- func: clear
constant func_loa : slv3 := "111"; -- func: load
type regs_type is record
rbsel : slbit; -- rbus select
run : slbit; -- run flag
saddr : slv5; -- scan address
raddr : slv5; -- read address (counter)
waddr : slbit; -- read address (word)
ainc : slbit; -- enable ddress autoinc
zbusy : slbit; -- clear in progress
dval : slbit; -- data valid
dout : slv32; -- read data (valid if dval=1)
psig : slv32; -- signals, floped
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- rbsel,run
(others=>'0'), -- saddr
(others=>'0'), -- raddr
'0','0','0','0', -- waddr,ainc,zbusy,dval
(others=>'0'), -- dout
(others=>'0') -- psig
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
type pre_do_type is array (31 downto 0) of slv5;
signal PRE_CLR : slv32 := (others=>'0');
signal PRE_DO : pre_do_type := (others=> (others => '0'));
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
begin
MEM : ram_1swar_gen
generic map (
AWIDTH => 5,
DWIDTH => 32)
port map (
CLK => CLK,
WE => '1',
ADDR => R_REGS.saddr,
DI => MEM_DI,
DO => MEM_DO
);
PRE: for i in 31 downto 0 generate
ENA: if CENA(i)='1' generate
CNT : entity work.pdp11_dmpcnt_precnt
port map (
CLK => CLK,
CLR => PRE_CLR(i),
ENA => R_REGS.psig(i),
DOUT => PRE_DO(i)
);
end generate ENA;
end generate PRE;
proc_cnt: process (R_REGS, PRE_DO, MEM_DO)
variable iclr : slv32 := (others=>'0');
variable ipdo : slv32 := (others=>'0');
variable icnt : slv32 := (others=>'0');
variable imdi : slv32 := (others=>'0');
constant ipdo_pad : slv(31 downto 5) := (others=>'0');
constant icnt_pad : slv(31 downto 1) := (others=>'0');
begin
iclr := (others=>'0');
iclr(to_integer(unsigned(R_REGS.saddr))) := '1';
ipdo := ipdo_pad & PRE_DO(to_integer(unsigned(R_REGS.saddr)));
icnt := icnt_pad & R_REGS.psig(to_integer(unsigned(R_REGS.saddr)));
PRE_CLR <= iclr;
if R_REGS.zbusy = '0' then
imdi := slv(unsigned(MEM_DO) + unsigned(ipdo) + unsigned(icnt));
else
imdi := (others=>'0');
end if;
MEM_DI <= imdi;
end process proc_cnt;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, PERFSIG, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
end if;
if r.run = '1' then -- if running
n.psig := PERFSIG; -- capture performance signals
else
n.psig := (others=>'0'); -- otherwise ignore them
end if;
n.saddr := slv(unsigned(r.saddr) + 1); -- scan counter (always running)
-- capture data in dout buffer if scan=read address and looking at lsb and
-- if either data not valid or no rbus cycle active. this ensures that
-- dval waits end, and also that data isn't changing during rbus active.
if r.saddr = r.raddr and r.waddr = '0' and
(r.dval='0' or r.rbsel='0') then
n.dout := MEM_DO; -- capture data
n.dval := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.run := '0';
when func_sta => -- func: start -----------
n.run := '1';
when func_clr => -- func: clear -----------
n.run := '0';
if r.zbusy = '0' then
n.zbusy := '1';
n.saddr := (others=>'0');
n.raddr := (others=>'0');
n.waddr := '0';
n.ainc := '0';
irb_busy := '1';
else
if r.saddr = "11111" then
n.zbusy := '0';
n.dval := '0';
else
irb_busy := '1';
end if;
end if;
when func_loa => -- func: load ------------
n.ainc := RB_MREQ.din(cntl_rbf_ainc);
n.raddr := RB_MREQ.din(cntl_rbf_caddr);
n.waddr := '0';
n.dval := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => -- stat ------------------
irb_err := RB_MREQ.we;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1'; -- error
end if;
if RB_MREQ.re = '1' then
if r.dval = '0' then
irb_busy := '1';
else
n.waddr := not r.waddr;
if r.ainc='1' and r.waddr = '1' then -- autoinc and wrap ?
n.raddr := slv(unsigned(r.raddr) + 1);
n.dval := '0';
end if;
end if;
end if;
when others => irb_err := '1'; -- <> --------------------
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => null; -- cntl ------------------
irb_dout(cntl_rbf_vers) := VERS;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_ainc) := r.ainc;
irb_dout(stat_rbf_caddr) := r.raddr;
irb_dout(stat_rbf_waddr) := r.waddr;
irb_dout(stat_rbf_run) := r.run;
when rbaddr_data => -- data ------------------
if r.waddr = '0' then
irb_dout := r.dout(15 downto 0);
else
irb_dout := r.dout(31 downto 16);
end if;
when others => null;
end case;
end if;
N_REGS <= n;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
|
-- NEED RESULT: ARCH00019: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P3_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in R1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in R1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC2_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC2_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC3_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC3_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC4_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC4_2 did resume passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00019
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (9)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00019(ARCH00019)
-- ENT00019_Test_Bench(ARCH00019_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00019 is
generic ( G1 : Time := 10 ns ) ;
port ( P1 : in Time := 10 ns ) ;
end ENT00019 ;
architecture ARCH00019 of ENT00019 is
signal Pulse1, Pulse2, Pulse3 : Boolean := false ;
signal TestIt : Boolean := false;
signal P1_1_Did_Resume, P1_2_Did_Resume : Boolean := false ;
signal P2_1_Did_Resume, P2_2_Did_Resume : Boolean := false ;
signal P3_1_Did_Resume, P3_2_Did_Resume : Boolean := false ;
signal R1_1_Did_Resume, R1_2_Did_Resume : Boolean := false ;
signal PROC1_1_Did_Resume, PROC1_2_Did_Resume : Boolean := false ;
signal PROC2_1_Did_Resume, PROC2_2_Did_Resume : Boolean := false ;
signal PROC3_1_Did_Resume, PROC3_2_Did_Resume : Boolean := false ;
signal PROC4_1_Did_Resume, PROC4_2_Did_Resume : Boolean := false ;
constant Time_To_Wait : Time := 10 ns ;
procedure PROC1_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC1_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC1_1 ;
procedure PROC1_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC1_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC1_2 ;
procedure PROC2_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC2_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC2_1 ;
procedure PROC2_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC2_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC2_2 ;
procedure PROC3_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC3_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC3_1 ;
procedure PROC3_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC3_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC3_2 ;
procedure PROC4_1 (Time_To_Wait : Time ;
signal Pulse1, Pulse2, Pulse3 : Boolean ;
signal Resume_Chk : inout boolean) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC4_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC4_1 ;
procedure PROC4_2 (Time_To_Wait : Time;
signal Pulse1, Pulse2, Pulse3 : Boolean ;
signal Resume_Chk : inout boolean) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC4_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC4_2 ;
begin
Test_Control :
process ( Pulse1, Pulse2, Pulse3, TestIt)
begin
if not Pulse1 then
Pulse1 <= transport not Pulse1 after 1 ns ;
elsif not Pulse2 then
Pulse2 <= transport not Pulse2 after 1 ns ;
elsif not Pulse3 then
Pulse3 <= transport not Pulse3 after 1 ns ;
TestIt <= transport TRUE after 2 ns;
elsif TestIt then
-- Verify that in fact, all of the wait statements resumed
test_report ( "ARCH00019" ,
"Wait in P1_1 did resume" ,
P1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P1_2 did resume" ,
P1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P2_1 did resume" ,
P2_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P2_2 did resume" ,
P2_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P3_1 did resume" ,
P3_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P3_2 did resume" ,
P3_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in R1_1 did resume" ,
R1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in R1_2 did resume" ,
R1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC1_1 did resume" ,
PROC1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC1_2 did resume" ,
PROC1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC2_1 did resume" ,
PROC2_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC2_2 did resume" ,
PROC2_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC3_1 did resume" ,
PROC3_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC3_2 did resume" ,
PROC3_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC4_1 did resume" ,
PROC4_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC4_2 did resume" ,
PROC4_2_Did_Resume ) ;
end if ;
end process Test_Control ;
P1_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
P1_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P1_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P1_1 ;
P1_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
P1_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P1_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P1_2 ;
P2_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
P2_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P2_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P2_1 ;
P2_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
P2_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P2_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P2_2 ;
P3_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
P3_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P3_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P3_1 ;
P3_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
P3_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P3_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P3_2 ;
Q1_1 :
process
begin
PROC1_1 (PROC1_1_Did_Resume) ;
wait;
end process Q1_1 ;
Q1_2 :
process
begin
PROC1_2 (PROC1_2_Did_Resume) ;
wait;
end process Q1_2 ;
Q2_1 :
process
begin
PROC2_1 (PROC2_1_Did_Resume) ;
wait;
end process Q2_1 ;
Q2_2 :
process
begin
PROC2_2 (PROC2_2_Did_Resume) ;
wait;
end process Q2_2 ;
Q3_1 :
process
begin
PROC3_1 (PROC3_1_Did_Resume) ;
wait;
end process Q3_1 ;
Q3_2 :
process
begin
PROC3_2 (PROC3_2_Did_Resume) ;
wait;
end process Q3_2 ;
Q4_1 :
process
begin
PROC4_1 (Time_To_Wait, Pulse1, Pulse2, Pulse3, PROC4_1_Did_Resume) ;
wait;
end process Q4_1 ;
Q4_2 :
process
begin
PROC4_2 (P1, Pulse1, Pulse2, Pulse3, PROC4_2_Did_Resume) ;
wait;
end process Q4_2 ;
R1_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3) ;
if Pulse1 and Pulse2 and Pulse3 then
R1_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in R1_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process R1_1 ;
R1_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) ;
if Pulse1 and Pulse2 and Pulse3 then
R1_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in R1_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process R1_2 ;
end ARCH00019 ;
entity ENT00019_Test_Bench is
end ENT00019_Test_Bench ;
architecture ARCH00019_Test_Bench of ENT00019_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00019 ( ARCH00019 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00019_Test_Bench ;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package vga_counter_comp is
type vga_counter_out_t is
record
sync : std_logic;
enable : std_logic;
pix : natural;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_counter_comp.all;
entity vga_counter is
generic(FP : natural;
PW : natural;
DT : natural;
BP : natural);
port(clk : in std_logic;
reset : in std_logic;
output : out vga_counter_out_t);
end vga_counter;
architecture rtl of vga_counter is
constant COUNT_MAX : natural := FP + PW + DT + BP;
subtype counter_t is natural range 0 to COUNT_MAX - 1;
signal counter_s : counter_t;
signal counter_next_s : counter_t;
signal output_next_s : vga_counter_out_t;
begin
comb : process(counter_s)
begin
counter_next_s <= (counter_s + 1) mod COUNT_MAX;
if counter_s < DT then output_next_s <= ('1', '1', counter_s); -- Display Time
elsif counter_s < DT + FP then output_next_s <= ('1', '0', counter_s); -- Front Porch
elsif counter_s < DT + FP + PW then output_next_s <= ('0', '0', counter_s); -- Pulse Width
else output_next_s <= ('1', '0', counter_s); -- Back Porce
end if;
end process;
seq : process(clk, reset)
begin
if reset = '1' then
output <= ('1', '1', 0);
counter_s <= 0;
elsif rising_edge(clk) then
output <= output_next_s;
counter_s <= counter_next_s;
end if;
end process;
end rtl;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package vga_comp is
subtype width_t is natural range 0 to 640 - 1;
subtype height_t is natural range 0 to 480 - 1;
type vga_out_t is
record
en : std_logic;
hs : std_logic;
vs : std_logic;
pix_x : width_t;
pix_y : height_t;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_comp.all;
use work.vga_counter_comp.all;
entity vga is
port(clk : in std_logic;
reset : in std_logic;
output : out vga_out_t);
end vga;
architecture rtl of vga is
component vga_counter is
generic(FP : natural;
PW : natural;
DT : natural;
BP : natural);
port(clk : in std_logic;
reset : in std_logic;
output : out vga_counter_out_t);
end component;
signal h_counter_out_s : vga_counter_out_t;
signal v_counter_out_s : vga_counter_out_t;
begin
HS_counter : vga_counter
generic map (16, 96, 640, 48)
port map (clk, reset, h_counter_out_s);
VS_counter : vga_counter
generic map (10, 2, 480, 29)
port map (h_counter_out_s.sync, reset, v_counter_out_s);
comb: process(h_counter_out_s, v_counter_out_s)
begin
output.en <= h_counter_out_s.enable and v_counter_out_s.enable;
output.hs <= h_counter_out_s.sync;
output.vs <= v_counter_out_s.sync;
if h_counter_out_s.pix < 640 then
output.pix_x <= h_counter_out_s.pix;
else
output.pix_x <= 0;
end if;
if v_counter_out_s.pix < 480 then
output.pix_y <= v_counter_out_s.pix;
else
output.pix_y <= 0;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:59:42 08/18/2010
-- Design Name:
-- Module Name: PCFG_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PCFG_TOP is
PORT( ---------------------------------------------INPUT
m_reset_b : IN std_logic;
m_clk : IN std_logic;
m_address : IN std_logic_vector(8 downto 0);
m_cmd_data : IN std_logic;
m_wen : IN std_logic;
m_ren : IN std_logic;
m_ADC_data : IN std_logic_vector(7 downto 0);
---------------------------------------------OUTPUT
m_ready : OUT std_logic;
m_DAC_data : OUT std_logic_vector(7 downto 0);
m_DAC_clk : OUT std_logic;
m_AD9283_clk : OUT std_logic;
-------------------------------------------------INOUT
m_data : INOUT std_logic_vector(7 downto 0);
-------------------------------------------------simulationÀ§ÇÑ port
m_led : OUT std_logic_vector(7 downto 0);
m_TP : out std_logic_vector(1 downto 0)
);
end PCFG_TOP;
architecture Behavioral of PCFG_TOP is
---8254
signal s_m_8254_gate0 : std_logic;
signal s_m_8254_gate1 : std_logic;
signal s_m_8254_gate2 : std_logic;
begin
-- signalµéÀ» 8254 gateµé°ú ¿¬°áÇÏ¿© ÁÖ¼¼¿ä
s_m_8254_gate0 <= '1';
s_m_8254_gate1 <= '1';
s_m_8254_gate2 <= '1';
m_TP(0) <= m_clk;
m_TP(1) <= sys_clk; --- Àǹ« (sys_clk Àº signal·Î ¼±¾ðÇϽŠÈÄ 8254 module¿¡¼ ºÐÁÖµÇ¾î ³ª¿À´Â clkÀ» ¿¬°áÇÏ½Ã¸é µÇ¿ä~)
m_led(0) <= m_ready;--- Àǹ«
-- m_led 1ºÎÅÍ 7±îÁö´Â DEBUGGING ÇÏ°í ½ÍÀº ÇÉÀ» MAPPINGÇϼ¼¿ä
m_led(1) <=
m_led(2) <=
m_led(3) <=
m_led(4) <=
m_led(5) <=
m_led(6) <=
m_led(7) <=
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
|
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2917.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p05n01i02917ent IS
END c02s01b01x02p05n01i02917ent;
ARCHITECTURE c02s01b01x02p05n01i02917arch OF c02s01b01x02p05n01i02917ent IS
type t1 is (one,two,three);
signal s1 : t1;
signal s2 : integer;
procedure proc1(signal ss1:inout t1; signal ss2:out integer) is
begin
ss1<=two after 5 ns;
ss2<=2 after 5 ns;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
s1<=three;
s2<=3;
wait for 5 ns;
assert (s1=three)
report "Error in initial conditions detected"
severity failure;
assert (s2=3)
report "Error in initial conditions detected"
severity failure;
proc1(s1,s2);
wait for 10 ns;
assert (s1=two)
report "Error detected in signal assignment for S1"
severity failure;
assert (s2=2)
report "Error detected in signal assignment for S2"
severity failure;
assert NOT( s1=two and s2=2 )
report "***PASSED TEST: c02s01b01x02p05n01i02917"
severity NOTE;
assert ( s1=two and s2=2 )
report "***FAILED TEST: c02s01b01x02p05n01i02917 - Error detected in signal assignemnts."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p05n01i02917arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2917.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p05n01i02917ent IS
END c02s01b01x02p05n01i02917ent;
ARCHITECTURE c02s01b01x02p05n01i02917arch OF c02s01b01x02p05n01i02917ent IS
type t1 is (one,two,three);
signal s1 : t1;
signal s2 : integer;
procedure proc1(signal ss1:inout t1; signal ss2:out integer) is
begin
ss1<=two after 5 ns;
ss2<=2 after 5 ns;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
s1<=three;
s2<=3;
wait for 5 ns;
assert (s1=three)
report "Error in initial conditions detected"
severity failure;
assert (s2=3)
report "Error in initial conditions detected"
severity failure;
proc1(s1,s2);
wait for 10 ns;
assert (s1=two)
report "Error detected in signal assignment for S1"
severity failure;
assert (s2=2)
report "Error detected in signal assignment for S2"
severity failure;
assert NOT( s1=two and s2=2 )
report "***PASSED TEST: c02s01b01x02p05n01i02917"
severity NOTE;
assert ( s1=two and s2=2 )
report "***FAILED TEST: c02s01b01x02p05n01i02917 - Error detected in signal assignemnts."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p05n01i02917arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2917.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p05n01i02917ent IS
END c02s01b01x02p05n01i02917ent;
ARCHITECTURE c02s01b01x02p05n01i02917arch OF c02s01b01x02p05n01i02917ent IS
type t1 is (one,two,three);
signal s1 : t1;
signal s2 : integer;
procedure proc1(signal ss1:inout t1; signal ss2:out integer) is
begin
ss1<=two after 5 ns;
ss2<=2 after 5 ns;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
s1<=three;
s2<=3;
wait for 5 ns;
assert (s1=three)
report "Error in initial conditions detected"
severity failure;
assert (s2=3)
report "Error in initial conditions detected"
severity failure;
proc1(s1,s2);
wait for 10 ns;
assert (s1=two)
report "Error detected in signal assignment for S1"
severity failure;
assert (s2=2)
report "Error detected in signal assignment for S2"
severity failure;
assert NOT( s1=two and s2=2 )
report "***PASSED TEST: c02s01b01x02p05n01i02917"
severity NOTE;
assert ( s1=two and s2=2 )
report "***FAILED TEST: c02s01b01x02p05n01i02917 - Error detected in signal assignemnts."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p05n01i02917arch;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0;
use lib_bmg_v1_0.blk_mem_gen_wrapper;
--use proc_common_v4_0.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end implementation;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0;
use lib_bmg_v1_0.blk_mem_gen_wrapper;
--use proc_common_v4_0.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end implementation;
|
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
assert returns_last( "11" ) = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
assert returns_last( "11" ) = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- onlty
doit: process
function returns_last( p : bit_vector )
return bit is
begin
return p( p'length - 1 );
end function;
begin -- process doit
assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
assert returns_last( "11" ) = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process doit;
end only;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002F#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- *** bhe_comparator.vhd *** --
-- structural comparator as described in prof. Graziano documents
-- extended in order to handle both signed and unsigned comparisons
-- sum is computed outside of the comparator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bhe_comparator is
generic (M : integer := 32);
port (
A : in std_logic_vector(M-1 downto 0); -- carry out
B : in std_logic_vector(M-1 downto 0);
sign : in std_logic;
sel : in std_logic_vector(2 downto 0); -- selection
S : out std_logic
);
end bhe_comparator;
architecture bhe_2 of bhe_comparator is
signal NC : std_logic;
signal Z : std_logic;
signal N : std_logic;
signal G : std_logic;
signal GE : std_logic;
signal L : std_logic;
signal LE : std_logic;
signal E : std_logic;
signal NE : std_logic;
begin
G <= '1' when signed(A) > signed(B) and sign = '1' else
'1' when unsigned(A) > unsigned(B) and sign = '0' else
'0';
GE <= '1' when signed(A) >= signed(B) and sign = '1' else
'1' when unsigned(A) >= unsigned(B) and sign = '0' else
'0';
L <= '1' when signed(A) < signed(B) and sign = '1' else
'1' when unsigned(A) < unsigned(B) and sign = '0' else
'0';
LE <= '1' when signed(A) <= signed(B) and sign = '1' else
'1' when unsigned(A) <= unsigned(B) and sign = '0' else
'0';
E <= '1' when signed(A) = signed(B) else
'0';
NE <= '1' when signed(A) /= signed(B) else
'0';
S <= G when sel="000" else
GE when sel="001" else
L when sel="010" else
LE when sel="011" else
E when sel="100" else
NE when sel="101" else
'X';
end bhe_2;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 1;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 1;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_cols_V_channel is
component FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_cols_V_channel_shiftReg : FIFO_image_filter_p_dst_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_cols_V_channel is
component FIFO_image_filter_p_dst_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_cols_V_channel_shiftReg : FIFO_image_filter_p_dst_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3004.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p06n02i03004pkg is
constant C1 : integer := 10;
end c02s06b00x00p06n02i03004pkg;
package body c02s06b00x00p06n02i03004pkg is
constant C2 : integer := 0;
end;
use work.c02s06b00x00p06n02i03004pkg.all;
ENTITY c02s06b00x00p06n02i03004ent IS
END c02s06b00x00p06n02i03004ent;
ARCHITECTURE c02s06b00x00p06n02i03004arch OF c02s06b00x00p06n02i03004ent IS
BEGIN
TESTING: PROCESS
variable A1 : integer := work.c02s06b00x00p06n02i03004pkg.C1;
variable A2 : integer := workc02s06b00x00p06n02i03004pkg.C2; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p06n02i03004 - Items declared in the body of the package cannot be made visible outside the package body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p06n02i03004arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3004.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p06n02i03004pkg is
constant C1 : integer := 10;
end c02s06b00x00p06n02i03004pkg;
package body c02s06b00x00p06n02i03004pkg is
constant C2 : integer := 0;
end;
use work.c02s06b00x00p06n02i03004pkg.all;
ENTITY c02s06b00x00p06n02i03004ent IS
END c02s06b00x00p06n02i03004ent;
ARCHITECTURE c02s06b00x00p06n02i03004arch OF c02s06b00x00p06n02i03004ent IS
BEGIN
TESTING: PROCESS
variable A1 : integer := work.c02s06b00x00p06n02i03004pkg.C1;
variable A2 : integer := workc02s06b00x00p06n02i03004pkg.C2; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p06n02i03004 - Items declared in the body of the package cannot be made visible outside the package body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p06n02i03004arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3004.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p06n02i03004pkg is
constant C1 : integer := 10;
end c02s06b00x00p06n02i03004pkg;
package body c02s06b00x00p06n02i03004pkg is
constant C2 : integer := 0;
end;
use work.c02s06b00x00p06n02i03004pkg.all;
ENTITY c02s06b00x00p06n02i03004ent IS
END c02s06b00x00p06n02i03004ent;
ARCHITECTURE c02s06b00x00p06n02i03004arch OF c02s06b00x00p06n02i03004ent IS
BEGIN
TESTING: PROCESS
variable A1 : integer := work.c02s06b00x00p06n02i03004pkg.C1;
variable A2 : integer := workc02s06b00x00p06n02i03004pkg.C2; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p06n02i03004 - Items declared in the body of the package cannot be made visible outside the package body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p06n02i03004arch;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY FINAL IS
PORT(Clock,CLK,CLKBAT,CLR : IN STD_LOGIC;
scan_ready : IN STD_LOGIC;
SERVE1, SERVE2 : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Hexout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
read : OUT STD_LOGIC;
Horiz_sync, Vert_sync : OUT STD_LOGIC;
RED, GREEN, BLUE : OUT STD_LOGIC);
END FINAL;
ARCHITECTURE NEW1 OF FINAL IS
SIGNAL PADDLE1, PADDLE2 : INTEGER RANGE 0 TO 48;
SIGNAL POSITION1, POSITION2 : INTEGER RANGE 0 TO 48;
SIGNAL SCORE11, SCORE22 : INTEGER RANGE 0 TO 9;
SIGNAL ROW, COLUMN : INTEGER RANGE 0 TO 64;
SIGNAL OUT1,OUT2 : STD_LOGIC_VECTOR(6 DOWNTO 0);
COMPONENT bat
PORT ( clr, CLKbat : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : IN std_logic;
read : OUT std_logic;
paddle_1, paddle_2 : OUT INTEGER RANGE 0 to 48);
END COMPONENT;
COMPONENT random
PORT ( clk,clr : IN STD_LOGIC;
POSITION1, POSITION2 : OUT INTEGER RANGE 0 TO 48);
END COMPONENT;
COMPONENT PING
PORT( CLK,CLR : IN STD_LOGIC;
SERVE1, SERVE2 : IN STD_LOGIC;
POSITION1, PADDLE1 : IN INTEGER RANGE 0 TO 48;
POSITION2, PADDLE2 : IN INTEGER RANGE 0 TO 48;
SCORE11,SCORE22 : INOUT INTEGER RANGE 0 TO 9;
ROW, COLUMN : OUT INTEGER RANGE 0 TO 64;
OUT1,OUT2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEXOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0));
END COMPONENT;
COMPONENT display
PORT(Clock : IN STD_LOGIC;
ROW, COLUMN : IN INTEGER RANGE 0 TO 64;
PADDLE1,PADDLE2 : IN INTEGER RANGE 0 TO 48;
OUT1,OUT2 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Horiz_sync, Vert_sync : OUT STD_LOGIC;
RED, GREEN, BLUE : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: bat
PORT MAP(clr,CLKBAT, scan_code, scan_ready, read, PADDLE1,PADDLE2);
U2: random
PORT MAP(clk,clr,POSITION1,POSITION2);
U3: PING
PORT MAP(CLK,CLR,SERVE1,SERVE2, POSITION1,PADDLE1,POSITION2,PADDLE2,SCORE11,SCORE22,ROW,COLUMN,OUT1,OUT2,HEXOUT);
U4: display
PORT MAP(Clock,ROW,COLUMN,PADDLE1,PADDLE2,OUT1,OUT2,Horiz_sync,Vert_sync,RED,GREEN,BLUE);
END NEW1;
|
-------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal. Multiple channels and frequencies are
-- calculated pipelined to save resources (especially hardware multiplier).
--
-- This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipelined is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations. Set in the signalprocessing_pkg.vhd
-- INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are at most 18 bits wide (in Xilinx Spartan)
-- CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13;
-- Number of samples used to detect a frequency.
-- After SAMPLES samples new samples are available.
SAMPLES : natural := 250;
-- Number of Channels
CHANNELS : natural := 12;
-- Number of Frequencies
FREQUENCIES : natural := 2
);
port (
-- Goertzel Coefficient calculated by
-- c = 2 cos(2 pi f_signal / f_sample)
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
-- Values from ADC
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
-- clock enable input, is high when new value from ADC is available.
start_p : in std_logic;
results_p : out goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- clock enable outut, is high when new results are available
done_p : out std_logic;
clk : in std_logic
);
end goertzel_pipelined;
architecture behavioural of goertzel_pipelined is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type goertzel_state_type is (
IDLE,
CALC
);
type goertzel_type is record
state : goertzel_state_type;
channel : natural range 0 to CHANNELS-1;
frequency : natural range 0 to FREQUENCIES-1;
sample_count : natural range 0 to SAMPLES-1;
done : std_logic;
delay_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
-- results : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- delays : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
end record;
----------------------------------------------------------------------------
-- Internal signals
----------------------------------------------------------------------------
signal r, rin : goertzel_type := (
state => IDLE,
channel => 0,
frequency => 0,
sample_count => 0,
done => '0',
delay_ch0_f0_0 => (others => '0'),
delay_ch0_f0_1 => (others => '0'),
delay_ch1_f0_0 => (others => '0'),
delay_ch1_f0_1 => (others => '0'),
delay_ch2_f0_0 => (others => '0'),
delay_ch2_f0_1 => (others => '0'),
delay_ch3_f0_0 => (others => '0'),
delay_ch3_f0_1 => (others => '0'),
delay_ch4_f0_0 => (others => '0'),
delay_ch4_f0_1 => (others => '0'),
delay_ch5_f0_0 => (others => '0'),
delay_ch5_f0_1 => (others => '0'),
delay_ch6_f0_0 => (others => '0'),
delay_ch6_f0_1 => (others => '0'),
delay_ch7_f0_0 => (others => '0'),
delay_ch7_f0_1 => (others => '0'),
delay_ch8_f0_0 => (others => '0'),
delay_ch8_f0_1 => (others => '0'),
delay_ch9_f0_0 => (others => '0'),
delay_ch9_f0_1 => (others => '0'),
delay_ch10_f0_0 => (others => '0'),
delay_ch10_f0_1 => (others => '0'),
delay_ch11_f0_0 => (others => '0'),
delay_ch11_f0_1 => (others => '0'),
delay_ch0_f1_0 => (others => '0'),
delay_ch0_f1_1 => (others => '0'),
delay_ch1_f1_0 => (others => '0'),
delay_ch1_f1_1 => (others => '0'),
delay_ch2_f1_0 => (others => '0'),
delay_ch2_f1_1 => (others => '0'),
delay_ch3_f1_0 => (others => '0'),
delay_ch3_f1_1 => (others => '0'),
delay_ch4_f1_0 => (others => '0'),
delay_ch4_f1_1 => (others => '0'),
delay_ch5_f1_0 => (others => '0'),
delay_ch5_f1_1 => (others => '0'),
delay_ch6_f1_0 => (others => '0'),
delay_ch6_f1_1 => (others => '0'),
delay_ch7_f1_0 => (others => '0'),
delay_ch7_f1_1 => (others => '0'),
delay_ch8_f1_0 => (others => '0'),
delay_ch8_f1_1 => (others => '0'),
delay_ch9_f1_0 => (others => '0'),
delay_ch9_f1_1 => (others => '0'),
delay_ch10_f1_0 => (others => '0'),
delay_ch10_f1_1 => (others => '0'),
delay_ch11_f1_0 => (others => '0'),
delay_ch11_f1_1 => (others => '0'),
result_ch0_f0_0 => (others => '0'),
result_ch0_f0_1 => (others => '0'),
result_ch1_f0_0 => (others => '0'),
result_ch1_f0_1 => (others => '0'),
result_ch2_f0_0 => (others => '0'),
result_ch2_f0_1 => (others => '0'),
result_ch3_f0_0 => (others => '0'),
result_ch3_f0_1 => (others => '0'),
result_ch4_f0_0 => (others => '0'),
result_ch4_f0_1 => (others => '0'),
result_ch5_f0_0 => (others => '0'),
result_ch5_f0_1 => (others => '0'),
result_ch6_f0_0 => (others => '0'),
result_ch6_f0_1 => (others => '0'),
result_ch7_f0_0 => (others => '0'),
result_ch7_f0_1 => (others => '0'),
result_ch8_f0_0 => (others => '0'),
result_ch8_f0_1 => (others => '0'),
result_ch9_f0_0 => (others => '0'),
result_ch9_f0_1 => (others => '0'),
result_ch10_f0_0 => (others => '0'),
result_ch10_f0_1 => (others => '0'),
result_ch11_f0_0 => (others => '0'),
result_ch11_f0_1 => (others => '0'),
result_ch0_f1_0 => (others => '0'),
result_ch0_f1_1 => (others => '0'),
result_ch1_f1_0 => (others => '0'),
result_ch1_f1_1 => (others => '0'),
result_ch2_f1_0 => (others => '0'),
result_ch2_f1_1 => (others => '0'),
result_ch3_f1_0 => (others => '0'),
result_ch3_f1_1 => (others => '0'),
result_ch4_f1_0 => (others => '0'),
result_ch4_f1_1 => (others => '0'),
result_ch5_f1_0 => (others => '0'),
result_ch5_f1_1 => (others => '0'),
result_ch6_f1_0 => (others => '0'),
result_ch6_f1_1 => (others => '0'),
result_ch7_f1_0 => (others => '0'),
result_ch7_f1_1 => (others => '0'),
result_ch8_f1_0 => (others => '0'),
result_ch8_f1_1 => (others => '0'),
result_ch9_f1_0 => (others => '0'),
result_ch9_f1_1 => (others => '0'),
result_ch10_f1_0 => (others => '0'),
result_ch10_f1_1 => (others => '0'),
result_ch11_f1_0 => (others => '0'),
result_ch11_f1_1 => (others => '0')
-- results => (others => (others => (others => (others => '0')))),
-- delays => (others => (others => (others => (others => '0'))))
);
----------------------------------------------------------------------------
-- Debugging signals (variables can't be plotted in GTKwave)
----------------------------------------------------------------------------
signal dbg_coef_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_input_s : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay1_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay2_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
begin -- behavioural
----------------------------------------------------------------------------
-- Mapping of signals
----------------------------------------------------------------------------
done_p <= r.done;
-- results_p <= r.results;
results_p(0, 0)(0) <= r.result_ch0_f0_0;
results_p(0, 0)(1) <= r.result_ch0_f0_1;
results_p(1, 0)(0) <= r.result_ch1_f0_0;
results_p(1, 0)(1) <= r.result_ch1_f0_1;
results_p(2, 0)(0) <= r.result_ch2_f0_0;
results_p(2, 0)(1) <= r.result_ch2_f0_1;
results_p(3, 0)(0) <= r.result_ch3_f0_0;
results_p(3, 0)(1) <= r.result_ch3_f0_1;
results_p(4, 0)(0) <= r.result_ch4_f0_0;
results_p(4, 0)(1) <= r.result_ch4_f0_1;
results_p(5, 0)(0) <= r.result_ch5_f0_0;
results_p(5, 0)(1) <= r.result_ch5_f0_1;
results_p(6, 0)(0) <= r.result_ch6_f0_0;
results_p(6, 0)(1) <= r.result_ch6_f0_1;
results_p(7, 0)(0) <= r.result_ch7_f0_0;
results_p(7, 0)(1) <= r.result_ch7_f0_1;
results_p(8, 0)(0) <= r.result_ch8_f0_0;
results_p(8, 0)(1) <= r.result_ch8_f0_1;
results_p(9, 0)(0) <= r.result_ch9_f0_0;
results_p(9, 0)(1) <= r.result_ch9_f0_1;
results_p(10, 0)(0) <= r.result_ch10_f0_0;
results_p(10, 0)(1) <= r.result_ch10_f0_1;
results_p(11, 0)(0) <= r.result_ch11_f0_0;
results_p(11, 0)(1) <= r.result_ch11_f0_1;
results_p(0, 1)(0) <= r.result_ch0_f1_0;
results_p(0, 1)(1) <= r.result_ch0_f1_1;
results_p(1, 1)(0) <= r.result_ch1_f1_0;
results_p(1, 1)(1) <= r.result_ch1_f1_1;
results_p(2, 1)(0) <= r.result_ch2_f1_0;
results_p(2, 1)(1) <= r.result_ch2_f1_1;
results_p(3, 1)(0) <= r.result_ch3_f1_0;
results_p(3, 1)(1) <= r.result_ch3_f1_1;
results_p(4, 1)(0) <= r.result_ch4_f1_0;
results_p(4, 1)(1) <= r.result_ch4_f1_1;
results_p(5, 1)(0) <= r.result_ch5_f1_0;
results_p(5, 1)(1) <= r.result_ch5_f1_1;
results_p(6, 1)(0) <= r.result_ch6_f1_0;
results_p(6, 1)(1) <= r.result_ch6_f1_1;
results_p(7, 1)(0) <= r.result_ch7_f1_0;
results_p(7, 1)(1) <= r.result_ch7_f1_1;
results_p(8, 1)(0) <= r.result_ch8_f1_0;
results_p(8, 1)(1) <= r.result_ch8_f1_1;
results_p(9, 1)(0) <= r.result_ch9_f1_0;
results_p(9, 1)(1) <= r.result_ch9_f1_1;
results_p(10, 1)(0) <= r.result_ch10_f1_0;
results_p(10, 1)(1) <= r.result_ch10_f1_1;
results_p(11, 1)(0) <= r.result_ch11_f1_0;
results_p(11, 1)(1) <= r.result_ch11_f1_1;
----------------------------------------------------------------------------
-- Sequential part of FSM
----------------------------------------------------------------------------
seq_proc : process (clk)
begin -- process seq_proc
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Transitions and actions of FSM
----------------------------------------------------------------------------
comb_proc : process (coefs_p, inputs_p, r, start_p)
variable v : goertzel_type;
variable prod1 : signed(2*CALC_WIDTH-1 downto 0) := (others => '0');
variable prod1_sc : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable sum1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable coef : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay2 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable input : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
variable channel : natural range CHANNELS-1 downto 0 := 0;
variable frequency : natural range FREQUENCIES-1 downto 0 := 0;
begin -- process comb_proc
v := r;
channel := r.channel;
frequency := r.frequency;
v.done := '0'; -- done is a clock enable and is only
-- high for one period
-- multiplex inputs
coef := signed(coefs_p(r.frequency));
input := inputs_p(r.channel);
-- This does not work with ISE
-- delay1 := r.delays(r.channel, r.frequency)(0);
-- delay2 := r.delays(r.channel, r.frequency)(1);
-- Do it manually instaed:
case frequency is
when 0 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f0_0;
delay2 := r.delay_ch0_f0_1;
when 1 =>
delay1 := r.delay_ch1_f0_0;
delay2 := r.delay_ch1_f0_1;
when 2 =>
delay1 := r.delay_ch2_f0_0;
delay2 := r.delay_ch2_f0_1;
when 3 =>
delay1 := r.delay_ch3_f0_0;
delay2 := r.delay_ch3_f0_1;
when 4 =>
delay1 := r.delay_ch4_f0_0;
delay2 := r.delay_ch4_f0_1;
when 5 =>
delay1 := r.delay_ch5_f0_0;
delay2 := r.delay_ch5_f0_1;
when 6 =>
delay1 := r.delay_ch6_f0_0;
delay2 := r.delay_ch6_f0_1;
when 7 =>
delay1 := r.delay_ch7_f0_0;
delay2 := r.delay_ch7_f0_1;
when 8 =>
delay1 := r.delay_ch8_f0_0;
delay2 := r.delay_ch8_f0_1;
when 9 =>
delay1 := r.delay_ch9_f0_0;
delay2 := r.delay_ch9_f0_1;
when 10 =>
delay1 := r.delay_ch10_f0_0;
delay2 := r.delay_ch10_f0_1;
when 11 =>
delay1 := r.delay_ch11_f0_0;
delay2 := r.delay_ch11_f0_1;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f1_0;
delay2 := r.delay_ch0_f1_1;
when 1 =>
delay1 := r.delay_ch1_f1_0;
delay2 := r.delay_ch1_f1_1;
when 2 =>
delay1 := r.delay_ch2_f1_0;
delay2 := r.delay_ch2_f1_1;
when 3 =>
delay1 := r.delay_ch3_f1_0;
delay2 := r.delay_ch3_f1_1;
when 4 =>
delay1 := r.delay_ch4_f1_0;
delay2 := r.delay_ch4_f1_1;
when 5 =>
delay1 := r.delay_ch5_f1_0;
delay2 := r.delay_ch5_f1_1;
when 6 =>
delay1 := r.delay_ch6_f1_0;
delay2 := r.delay_ch6_f1_1;
when 7 =>
delay1 := r.delay_ch7_f1_0;
delay2 := r.delay_ch7_f1_1;
when 8 =>
delay1 := r.delay_ch8_f1_0;
delay2 := r.delay_ch8_f1_1;
when 9 =>
delay1 := r.delay_ch9_f1_0;
delay2 := r.delay_ch9_f1_1;
when 10 =>
delay1 := r.delay_ch10_f1_0;
delay2 := r.delay_ch10_f1_1;
when 11 =>
delay1 := r.delay_ch11_f1_0;
delay2 := r.delay_ch11_f1_1;
when others => null;
end case;
when others => null;
end case;
-- debug signals
dbg_coef_s <= coef;
dbg_input_s <= input;
dbg_delay1_s <= delay1;
dbg_delay2_s <= delay2;
-- iterate channels and frquencies
case r.state is
when IDLE =>
if start_p = '1' then
v.state := CALC;
if r.sample_count = SAMPLES-1 then
v.sample_count := 0;
-- one packet of SAMPLES samples done, store results of current packet
-- v.results := v.delays;
v.result_ch0_f0_0 := v.delay_ch0_f0_0;
v.result_ch0_f0_1 := v.delay_ch0_f0_1;
v.result_ch1_f0_0 := v.delay_ch1_f0_0;
v.result_ch1_f0_1 := v.delay_ch1_f0_1;
v.result_ch2_f0_0 := v.delay_ch2_f0_0;
v.result_ch2_f0_1 := v.delay_ch2_f0_1;
v.result_ch3_f0_0 := v.delay_ch3_f0_0;
v.result_ch3_f0_1 := v.delay_ch3_f0_1;
v.result_ch4_f0_0 := v.delay_ch4_f0_0;
v.result_ch4_f0_1 := v.delay_ch4_f0_1;
v.result_ch5_f0_0 := v.delay_ch5_f0_0;
v.result_ch5_f0_1 := v.delay_ch5_f0_1;
v.result_ch6_f0_0 := v.delay_ch6_f0_0;
v.result_ch6_f0_1 := v.delay_ch6_f0_1;
v.result_ch7_f0_0 := v.delay_ch7_f0_0;
v.result_ch7_f0_1 := v.delay_ch7_f0_1;
v.result_ch8_f0_0 := v.delay_ch8_f0_0;
v.result_ch8_f0_1 := v.delay_ch8_f0_1;
v.result_ch9_f0_0 := v.delay_ch9_f0_0;
v.result_ch9_f0_1 := v.delay_ch9_f0_1;
v.result_ch10_f0_0 := v.delay_ch10_f0_0;
v.result_ch10_f0_1 := v.delay_ch10_f0_1;
v.result_ch11_f0_0 := v.delay_ch11_f0_0;
v.result_ch11_f0_1 := v.delay_ch11_f0_1;
v.result_ch0_f1_0 := v.delay_ch0_f1_0;
v.result_ch0_f1_1 := v.delay_ch0_f1_1;
v.result_ch1_f1_0 := v.delay_ch1_f1_0;
v.result_ch1_f1_1 := v.delay_ch1_f1_1;
v.result_ch2_f1_0 := v.delay_ch2_f1_0;
v.result_ch2_f1_1 := v.delay_ch2_f1_1;
v.result_ch3_f1_0 := v.delay_ch3_f1_0;
v.result_ch3_f1_1 := v.delay_ch3_f1_1;
v.result_ch4_f1_0 := v.delay_ch4_f1_0;
v.result_ch4_f1_1 := v.delay_ch4_f1_1;
v.result_ch5_f1_0 := v.delay_ch5_f1_0;
v.result_ch5_f1_1 := v.delay_ch5_f1_1;
v.result_ch6_f1_0 := v.delay_ch6_f1_0;
v.result_ch6_f1_1 := v.delay_ch6_f1_1;
v.result_ch7_f1_0 := v.delay_ch7_f1_0;
v.result_ch7_f1_1 := v.delay_ch7_f1_1;
v.result_ch8_f1_0 := v.delay_ch8_f1_0;
v.result_ch8_f1_1 := v.delay_ch8_f1_1;
v.result_ch9_f1_0 := v.delay_ch9_f1_0;
v.result_ch9_f1_1 := v.delay_ch9_f1_1;
v.result_ch10_f1_0 := v.delay_ch10_f1_0;
v.result_ch10_f1_1 := v.delay_ch10_f1_1;
v.result_ch11_f1_0 := v.delay_ch11_f1_0;
v.result_ch11_f1_1 := v.delay_ch11_f1_1;
v.done := '1';
-- reset all delay registers
-- v.delays := (others => (others => (others => (others => '0'))));
v.delay_ch0_f0_0 := (others => '0');
v.delay_ch0_f0_1 := (others => '0');
v.delay_ch1_f0_0 := (others => '0');
v.delay_ch1_f0_1 := (others => '0');
v.delay_ch2_f0_0 := (others => '0');
v.delay_ch2_f0_1 := (others => '0');
v.delay_ch3_f0_0 := (others => '0');
v.delay_ch3_f0_1 := (others => '0');
v.delay_ch4_f0_0 := (others => '0');
v.delay_ch4_f0_1 := (others => '0');
v.delay_ch5_f0_0 := (others => '0');
v.delay_ch5_f0_1 := (others => '0');
v.delay_ch6_f0_0 := (others => '0');
v.delay_ch6_f0_1 := (others => '0');
v.delay_ch7_f0_0 := (others => '0');
v.delay_ch7_f0_1 := (others => '0');
v.delay_ch8_f0_0 := (others => '0');
v.delay_ch8_f0_1 := (others => '0');
v.delay_ch9_f0_0 := (others => '0');
v.delay_ch9_f0_1 := (others => '0');
v.delay_ch10_f0_0 := (others => '0');
v.delay_ch10_f0_1 := (others => '0');
v.delay_ch11_f0_0 := (others => '0');
v.delay_ch11_f0_1 := (others => '0');
v.delay_ch0_f1_0 := (others => '0');
v.delay_ch0_f1_1 := (others => '0');
v.delay_ch1_f1_0 := (others => '0');
v.delay_ch1_f1_1 := (others => '0');
v.delay_ch2_f1_0 := (others => '0');
v.delay_ch2_f1_1 := (others => '0');
v.delay_ch3_f1_0 := (others => '0');
v.delay_ch3_f1_1 := (others => '0');
v.delay_ch4_f1_0 := (others => '0');
v.delay_ch4_f1_1 := (others => '0');
v.delay_ch5_f1_0 := (others => '0');
v.delay_ch5_f1_1 := (others => '0');
v.delay_ch6_f1_0 := (others => '0');
v.delay_ch6_f1_1 := (others => '0');
v.delay_ch7_f1_0 := (others => '0');
v.delay_ch7_f1_1 := (others => '0');
v.delay_ch8_f1_0 := (others => '0');
v.delay_ch8_f1_1 := (others => '0');
v.delay_ch9_f1_0 := (others => '0');
v.delay_ch9_f1_1 := (others => '0');
v.delay_ch10_f1_0 := (others => '0');
v.delay_ch10_f1_1 := (others => '0');
v.delay_ch11_f1_0 := (others => '0');
v.delay_ch11_f1_1 := (others => '0');
else
v.sample_count := r.sample_count + 1;
end if;
end if;
when CALC =>
-- calculating, only use the multiplexed signals
prod1 := delay1 * coef;
prod1_sc := prod1((Q + CALC_WIDTH - 1) downto Q);
-- TODO detect overflow
sum1 := input + prod1_sc - delay2;
delay2 := delay1;
delay1 := sum1;
-- advance frequency and channel
if r.channel = CHANNELS-1 then
v.channel := 0;
if r.frequency = FREQUENCIES-1 then
v.frequency := 0;
v.state := IDLE;
else
v.frequency := r.frequency + 1;
end if;
else
v.channel := r.channel + 1;
end if;
end case;
-- multiplex output
-- This crashes lame ISE
-- v.delays(r.channel, r.frequency)(0) := delay1;
-- v.delays(r.channel, r.frequency)(1) := delay2;
case frequency is
when 0 =>
case channel is
when 0 =>
v.delay_ch0_f0_0 := delay1;
v.delay_ch0_f0_1 := delay2;
when 1 =>
v.delay_ch1_f0_0 := delay1;
v.delay_ch1_f0_1 := delay2;
when 2 =>
v.delay_ch2_f0_0 := delay1;
v.delay_ch2_f0_1 := delay2;
when 3 =>
v.delay_ch3_f0_0 := delay1;
v.delay_ch3_f0_1 := delay2;
when 4 =>
v.delay_ch4_f0_0 := delay1;
v.delay_ch4_f0_1 := delay2;
when 5 =>
v.delay_ch5_f0_0 := delay1;
v.delay_ch5_f0_1 := delay2;
when 6 =>
v.delay_ch6_f0_0 := delay1;
v.delay_ch6_f0_1 := delay2;
when 7 =>
v.delay_ch7_f0_0 := delay1;
v.delay_ch7_f0_1 := delay2;
when 8 =>
v.delay_ch8_f0_0 := delay1;
v.delay_ch8_f0_1 := delay2;
when 9 =>
v.delay_ch9_f0_0 := delay1;
v.delay_ch9_f0_1 := delay2;
when 10 =>
v.delay_ch10_f0_0 := delay1;
v.delay_ch10_f0_1 := delay2;
when 11 =>
v.delay_ch11_f0_0 := delay1;
v.delay_ch11_f0_1 := delay2;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
v.delay_ch0_f1_0 := delay1;
v.delay_ch0_f1_1 := delay2;
when 1 =>
v.delay_ch1_f1_0 := delay1;
v.delay_ch1_f1_1 := delay2;
when 2 =>
v.delay_ch2_f1_0 := delay1;
v.delay_ch2_f1_1 := delay2;
when 3 =>
v.delay_ch3_f1_0 := delay1;
v.delay_ch3_f1_1 := delay2;
when 4 =>
v.delay_ch4_f1_0 := delay1;
v.delay_ch4_f1_1 := delay2;
when 5 =>
v.delay_ch5_f1_0 := delay1;
v.delay_ch5_f1_1 := delay2;
when 6 =>
v.delay_ch6_f1_0 := delay1;
v.delay_ch6_f1_1 := delay2;
when 7 =>
v.delay_ch7_f1_0 := delay1;
v.delay_ch7_f1_1 := delay2;
when 8 =>
v.delay_ch8_f1_0 := delay1;
v.delay_ch8_f1_1 := delay2;
when 9 =>
v.delay_ch9_f1_0 := delay1;
v.delay_ch9_f1_1 := delay2;
when 10 =>
v.delay_ch10_f1_0 := delay1;
v.delay_ch10_f1_1 := delay2;
when 11 =>
v.delay_ch11_f1_0 := delay1;
v.delay_ch11_f1_1 := delay2;
when others => null;
end case;
when others => null;
end case;
rin <= v;
end process comb_proc;
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal. Multiple channels and frequencies are
-- calculated pipelined to save resources (especially hardware multiplier).
--
-- This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipelined is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations. Set in the signalprocessing_pkg.vhd
-- INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are at most 18 bits wide (in Xilinx Spartan)
-- CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13;
-- Number of samples used to detect a frequency.
-- After SAMPLES samples new samples are available.
SAMPLES : natural := 250;
-- Number of Channels
CHANNELS : natural := 12;
-- Number of Frequencies
FREQUENCIES : natural := 2
);
port (
-- Goertzel Coefficient calculated by
-- c = 2 cos(2 pi f_signal / f_sample)
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
-- Values from ADC
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
-- clock enable input, is high when new value from ADC is available.
start_p : in std_logic;
results_p : out goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- clock enable outut, is high when new results are available
done_p : out std_logic;
clk : in std_logic
);
end goertzel_pipelined;
architecture behavioural of goertzel_pipelined is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type goertzel_state_type is (
IDLE,
CALC
);
type goertzel_type is record
state : goertzel_state_type;
channel : natural range 0 to CHANNELS-1;
frequency : natural range 0 to FREQUENCIES-1;
sample_count : natural range 0 to SAMPLES-1;
done : std_logic;
delay_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
-- results : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- delays : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
end record;
----------------------------------------------------------------------------
-- Internal signals
----------------------------------------------------------------------------
signal r, rin : goertzel_type := (
state => IDLE,
channel => 0,
frequency => 0,
sample_count => 0,
done => '0',
delay_ch0_f0_0 => (others => '0'),
delay_ch0_f0_1 => (others => '0'),
delay_ch1_f0_0 => (others => '0'),
delay_ch1_f0_1 => (others => '0'),
delay_ch2_f0_0 => (others => '0'),
delay_ch2_f0_1 => (others => '0'),
delay_ch3_f0_0 => (others => '0'),
delay_ch3_f0_1 => (others => '0'),
delay_ch4_f0_0 => (others => '0'),
delay_ch4_f0_1 => (others => '0'),
delay_ch5_f0_0 => (others => '0'),
delay_ch5_f0_1 => (others => '0'),
delay_ch6_f0_0 => (others => '0'),
delay_ch6_f0_1 => (others => '0'),
delay_ch7_f0_0 => (others => '0'),
delay_ch7_f0_1 => (others => '0'),
delay_ch8_f0_0 => (others => '0'),
delay_ch8_f0_1 => (others => '0'),
delay_ch9_f0_0 => (others => '0'),
delay_ch9_f0_1 => (others => '0'),
delay_ch10_f0_0 => (others => '0'),
delay_ch10_f0_1 => (others => '0'),
delay_ch11_f0_0 => (others => '0'),
delay_ch11_f0_1 => (others => '0'),
delay_ch0_f1_0 => (others => '0'),
delay_ch0_f1_1 => (others => '0'),
delay_ch1_f1_0 => (others => '0'),
delay_ch1_f1_1 => (others => '0'),
delay_ch2_f1_0 => (others => '0'),
delay_ch2_f1_1 => (others => '0'),
delay_ch3_f1_0 => (others => '0'),
delay_ch3_f1_1 => (others => '0'),
delay_ch4_f1_0 => (others => '0'),
delay_ch4_f1_1 => (others => '0'),
delay_ch5_f1_0 => (others => '0'),
delay_ch5_f1_1 => (others => '0'),
delay_ch6_f1_0 => (others => '0'),
delay_ch6_f1_1 => (others => '0'),
delay_ch7_f1_0 => (others => '0'),
delay_ch7_f1_1 => (others => '0'),
delay_ch8_f1_0 => (others => '0'),
delay_ch8_f1_1 => (others => '0'),
delay_ch9_f1_0 => (others => '0'),
delay_ch9_f1_1 => (others => '0'),
delay_ch10_f1_0 => (others => '0'),
delay_ch10_f1_1 => (others => '0'),
delay_ch11_f1_0 => (others => '0'),
delay_ch11_f1_1 => (others => '0'),
result_ch0_f0_0 => (others => '0'),
result_ch0_f0_1 => (others => '0'),
result_ch1_f0_0 => (others => '0'),
result_ch1_f0_1 => (others => '0'),
result_ch2_f0_0 => (others => '0'),
result_ch2_f0_1 => (others => '0'),
result_ch3_f0_0 => (others => '0'),
result_ch3_f0_1 => (others => '0'),
result_ch4_f0_0 => (others => '0'),
result_ch4_f0_1 => (others => '0'),
result_ch5_f0_0 => (others => '0'),
result_ch5_f0_1 => (others => '0'),
result_ch6_f0_0 => (others => '0'),
result_ch6_f0_1 => (others => '0'),
result_ch7_f0_0 => (others => '0'),
result_ch7_f0_1 => (others => '0'),
result_ch8_f0_0 => (others => '0'),
result_ch8_f0_1 => (others => '0'),
result_ch9_f0_0 => (others => '0'),
result_ch9_f0_1 => (others => '0'),
result_ch10_f0_0 => (others => '0'),
result_ch10_f0_1 => (others => '0'),
result_ch11_f0_0 => (others => '0'),
result_ch11_f0_1 => (others => '0'),
result_ch0_f1_0 => (others => '0'),
result_ch0_f1_1 => (others => '0'),
result_ch1_f1_0 => (others => '0'),
result_ch1_f1_1 => (others => '0'),
result_ch2_f1_0 => (others => '0'),
result_ch2_f1_1 => (others => '0'),
result_ch3_f1_0 => (others => '0'),
result_ch3_f1_1 => (others => '0'),
result_ch4_f1_0 => (others => '0'),
result_ch4_f1_1 => (others => '0'),
result_ch5_f1_0 => (others => '0'),
result_ch5_f1_1 => (others => '0'),
result_ch6_f1_0 => (others => '0'),
result_ch6_f1_1 => (others => '0'),
result_ch7_f1_0 => (others => '0'),
result_ch7_f1_1 => (others => '0'),
result_ch8_f1_0 => (others => '0'),
result_ch8_f1_1 => (others => '0'),
result_ch9_f1_0 => (others => '0'),
result_ch9_f1_1 => (others => '0'),
result_ch10_f1_0 => (others => '0'),
result_ch10_f1_1 => (others => '0'),
result_ch11_f1_0 => (others => '0'),
result_ch11_f1_1 => (others => '0')
-- results => (others => (others => (others => (others => '0')))),
-- delays => (others => (others => (others => (others => '0'))))
);
----------------------------------------------------------------------------
-- Debugging signals (variables can't be plotted in GTKwave)
----------------------------------------------------------------------------
signal dbg_coef_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_input_s : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay1_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay2_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
begin -- behavioural
----------------------------------------------------------------------------
-- Mapping of signals
----------------------------------------------------------------------------
done_p <= r.done;
-- results_p <= r.results;
results_p(0, 0)(0) <= r.result_ch0_f0_0;
results_p(0, 0)(1) <= r.result_ch0_f0_1;
results_p(1, 0)(0) <= r.result_ch1_f0_0;
results_p(1, 0)(1) <= r.result_ch1_f0_1;
results_p(2, 0)(0) <= r.result_ch2_f0_0;
results_p(2, 0)(1) <= r.result_ch2_f0_1;
results_p(3, 0)(0) <= r.result_ch3_f0_0;
results_p(3, 0)(1) <= r.result_ch3_f0_1;
results_p(4, 0)(0) <= r.result_ch4_f0_0;
results_p(4, 0)(1) <= r.result_ch4_f0_1;
results_p(5, 0)(0) <= r.result_ch5_f0_0;
results_p(5, 0)(1) <= r.result_ch5_f0_1;
results_p(6, 0)(0) <= r.result_ch6_f0_0;
results_p(6, 0)(1) <= r.result_ch6_f0_1;
results_p(7, 0)(0) <= r.result_ch7_f0_0;
results_p(7, 0)(1) <= r.result_ch7_f0_1;
results_p(8, 0)(0) <= r.result_ch8_f0_0;
results_p(8, 0)(1) <= r.result_ch8_f0_1;
results_p(9, 0)(0) <= r.result_ch9_f0_0;
results_p(9, 0)(1) <= r.result_ch9_f0_1;
results_p(10, 0)(0) <= r.result_ch10_f0_0;
results_p(10, 0)(1) <= r.result_ch10_f0_1;
results_p(11, 0)(0) <= r.result_ch11_f0_0;
results_p(11, 0)(1) <= r.result_ch11_f0_1;
results_p(0, 1)(0) <= r.result_ch0_f1_0;
results_p(0, 1)(1) <= r.result_ch0_f1_1;
results_p(1, 1)(0) <= r.result_ch1_f1_0;
results_p(1, 1)(1) <= r.result_ch1_f1_1;
results_p(2, 1)(0) <= r.result_ch2_f1_0;
results_p(2, 1)(1) <= r.result_ch2_f1_1;
results_p(3, 1)(0) <= r.result_ch3_f1_0;
results_p(3, 1)(1) <= r.result_ch3_f1_1;
results_p(4, 1)(0) <= r.result_ch4_f1_0;
results_p(4, 1)(1) <= r.result_ch4_f1_1;
results_p(5, 1)(0) <= r.result_ch5_f1_0;
results_p(5, 1)(1) <= r.result_ch5_f1_1;
results_p(6, 1)(0) <= r.result_ch6_f1_0;
results_p(6, 1)(1) <= r.result_ch6_f1_1;
results_p(7, 1)(0) <= r.result_ch7_f1_0;
results_p(7, 1)(1) <= r.result_ch7_f1_1;
results_p(8, 1)(0) <= r.result_ch8_f1_0;
results_p(8, 1)(1) <= r.result_ch8_f1_1;
results_p(9, 1)(0) <= r.result_ch9_f1_0;
results_p(9, 1)(1) <= r.result_ch9_f1_1;
results_p(10, 1)(0) <= r.result_ch10_f1_0;
results_p(10, 1)(1) <= r.result_ch10_f1_1;
results_p(11, 1)(0) <= r.result_ch11_f1_0;
results_p(11, 1)(1) <= r.result_ch11_f1_1;
----------------------------------------------------------------------------
-- Sequential part of FSM
----------------------------------------------------------------------------
seq_proc : process (clk)
begin -- process seq_proc
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Transitions and actions of FSM
----------------------------------------------------------------------------
comb_proc : process (coefs_p, inputs_p, r, start_p)
variable v : goertzel_type;
variable prod1 : signed(2*CALC_WIDTH-1 downto 0) := (others => '0');
variable prod1_sc : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable sum1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable coef : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay2 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable input : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
variable channel : natural range CHANNELS-1 downto 0 := 0;
variable frequency : natural range FREQUENCIES-1 downto 0 := 0;
begin -- process comb_proc
v := r;
channel := r.channel;
frequency := r.frequency;
v.done := '0'; -- done is a clock enable and is only
-- high for one period
-- multiplex inputs
coef := signed(coefs_p(r.frequency));
input := inputs_p(r.channel);
-- This does not work with ISE
-- delay1 := r.delays(r.channel, r.frequency)(0);
-- delay2 := r.delays(r.channel, r.frequency)(1);
-- Do it manually instaed:
case frequency is
when 0 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f0_0;
delay2 := r.delay_ch0_f0_1;
when 1 =>
delay1 := r.delay_ch1_f0_0;
delay2 := r.delay_ch1_f0_1;
when 2 =>
delay1 := r.delay_ch2_f0_0;
delay2 := r.delay_ch2_f0_1;
when 3 =>
delay1 := r.delay_ch3_f0_0;
delay2 := r.delay_ch3_f0_1;
when 4 =>
delay1 := r.delay_ch4_f0_0;
delay2 := r.delay_ch4_f0_1;
when 5 =>
delay1 := r.delay_ch5_f0_0;
delay2 := r.delay_ch5_f0_1;
when 6 =>
delay1 := r.delay_ch6_f0_0;
delay2 := r.delay_ch6_f0_1;
when 7 =>
delay1 := r.delay_ch7_f0_0;
delay2 := r.delay_ch7_f0_1;
when 8 =>
delay1 := r.delay_ch8_f0_0;
delay2 := r.delay_ch8_f0_1;
when 9 =>
delay1 := r.delay_ch9_f0_0;
delay2 := r.delay_ch9_f0_1;
when 10 =>
delay1 := r.delay_ch10_f0_0;
delay2 := r.delay_ch10_f0_1;
when 11 =>
delay1 := r.delay_ch11_f0_0;
delay2 := r.delay_ch11_f0_1;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f1_0;
delay2 := r.delay_ch0_f1_1;
when 1 =>
delay1 := r.delay_ch1_f1_0;
delay2 := r.delay_ch1_f1_1;
when 2 =>
delay1 := r.delay_ch2_f1_0;
delay2 := r.delay_ch2_f1_1;
when 3 =>
delay1 := r.delay_ch3_f1_0;
delay2 := r.delay_ch3_f1_1;
when 4 =>
delay1 := r.delay_ch4_f1_0;
delay2 := r.delay_ch4_f1_1;
when 5 =>
delay1 := r.delay_ch5_f1_0;
delay2 := r.delay_ch5_f1_1;
when 6 =>
delay1 := r.delay_ch6_f1_0;
delay2 := r.delay_ch6_f1_1;
when 7 =>
delay1 := r.delay_ch7_f1_0;
delay2 := r.delay_ch7_f1_1;
when 8 =>
delay1 := r.delay_ch8_f1_0;
delay2 := r.delay_ch8_f1_1;
when 9 =>
delay1 := r.delay_ch9_f1_0;
delay2 := r.delay_ch9_f1_1;
when 10 =>
delay1 := r.delay_ch10_f1_0;
delay2 := r.delay_ch10_f1_1;
when 11 =>
delay1 := r.delay_ch11_f1_0;
delay2 := r.delay_ch11_f1_1;
when others => null;
end case;
when others => null;
end case;
-- debug signals
dbg_coef_s <= coef;
dbg_input_s <= input;
dbg_delay1_s <= delay1;
dbg_delay2_s <= delay2;
-- iterate channels and frquencies
case r.state is
when IDLE =>
if start_p = '1' then
v.state := CALC;
if r.sample_count = SAMPLES-1 then
v.sample_count := 0;
-- one packet of SAMPLES samples done, store results of current packet
-- v.results := v.delays;
v.result_ch0_f0_0 := v.delay_ch0_f0_0;
v.result_ch0_f0_1 := v.delay_ch0_f0_1;
v.result_ch1_f0_0 := v.delay_ch1_f0_0;
v.result_ch1_f0_1 := v.delay_ch1_f0_1;
v.result_ch2_f0_0 := v.delay_ch2_f0_0;
v.result_ch2_f0_1 := v.delay_ch2_f0_1;
v.result_ch3_f0_0 := v.delay_ch3_f0_0;
v.result_ch3_f0_1 := v.delay_ch3_f0_1;
v.result_ch4_f0_0 := v.delay_ch4_f0_0;
v.result_ch4_f0_1 := v.delay_ch4_f0_1;
v.result_ch5_f0_0 := v.delay_ch5_f0_0;
v.result_ch5_f0_1 := v.delay_ch5_f0_1;
v.result_ch6_f0_0 := v.delay_ch6_f0_0;
v.result_ch6_f0_1 := v.delay_ch6_f0_1;
v.result_ch7_f0_0 := v.delay_ch7_f0_0;
v.result_ch7_f0_1 := v.delay_ch7_f0_1;
v.result_ch8_f0_0 := v.delay_ch8_f0_0;
v.result_ch8_f0_1 := v.delay_ch8_f0_1;
v.result_ch9_f0_0 := v.delay_ch9_f0_0;
v.result_ch9_f0_1 := v.delay_ch9_f0_1;
v.result_ch10_f0_0 := v.delay_ch10_f0_0;
v.result_ch10_f0_1 := v.delay_ch10_f0_1;
v.result_ch11_f0_0 := v.delay_ch11_f0_0;
v.result_ch11_f0_1 := v.delay_ch11_f0_1;
v.result_ch0_f1_0 := v.delay_ch0_f1_0;
v.result_ch0_f1_1 := v.delay_ch0_f1_1;
v.result_ch1_f1_0 := v.delay_ch1_f1_0;
v.result_ch1_f1_1 := v.delay_ch1_f1_1;
v.result_ch2_f1_0 := v.delay_ch2_f1_0;
v.result_ch2_f1_1 := v.delay_ch2_f1_1;
v.result_ch3_f1_0 := v.delay_ch3_f1_0;
v.result_ch3_f1_1 := v.delay_ch3_f1_1;
v.result_ch4_f1_0 := v.delay_ch4_f1_0;
v.result_ch4_f1_1 := v.delay_ch4_f1_1;
v.result_ch5_f1_0 := v.delay_ch5_f1_0;
v.result_ch5_f1_1 := v.delay_ch5_f1_1;
v.result_ch6_f1_0 := v.delay_ch6_f1_0;
v.result_ch6_f1_1 := v.delay_ch6_f1_1;
v.result_ch7_f1_0 := v.delay_ch7_f1_0;
v.result_ch7_f1_1 := v.delay_ch7_f1_1;
v.result_ch8_f1_0 := v.delay_ch8_f1_0;
v.result_ch8_f1_1 := v.delay_ch8_f1_1;
v.result_ch9_f1_0 := v.delay_ch9_f1_0;
v.result_ch9_f1_1 := v.delay_ch9_f1_1;
v.result_ch10_f1_0 := v.delay_ch10_f1_0;
v.result_ch10_f1_1 := v.delay_ch10_f1_1;
v.result_ch11_f1_0 := v.delay_ch11_f1_0;
v.result_ch11_f1_1 := v.delay_ch11_f1_1;
v.done := '1';
-- reset all delay registers
-- v.delays := (others => (others => (others => (others => '0'))));
v.delay_ch0_f0_0 := (others => '0');
v.delay_ch0_f0_1 := (others => '0');
v.delay_ch1_f0_0 := (others => '0');
v.delay_ch1_f0_1 := (others => '0');
v.delay_ch2_f0_0 := (others => '0');
v.delay_ch2_f0_1 := (others => '0');
v.delay_ch3_f0_0 := (others => '0');
v.delay_ch3_f0_1 := (others => '0');
v.delay_ch4_f0_0 := (others => '0');
v.delay_ch4_f0_1 := (others => '0');
v.delay_ch5_f0_0 := (others => '0');
v.delay_ch5_f0_1 := (others => '0');
v.delay_ch6_f0_0 := (others => '0');
v.delay_ch6_f0_1 := (others => '0');
v.delay_ch7_f0_0 := (others => '0');
v.delay_ch7_f0_1 := (others => '0');
v.delay_ch8_f0_0 := (others => '0');
v.delay_ch8_f0_1 := (others => '0');
v.delay_ch9_f0_0 := (others => '0');
v.delay_ch9_f0_1 := (others => '0');
v.delay_ch10_f0_0 := (others => '0');
v.delay_ch10_f0_1 := (others => '0');
v.delay_ch11_f0_0 := (others => '0');
v.delay_ch11_f0_1 := (others => '0');
v.delay_ch0_f1_0 := (others => '0');
v.delay_ch0_f1_1 := (others => '0');
v.delay_ch1_f1_0 := (others => '0');
v.delay_ch1_f1_1 := (others => '0');
v.delay_ch2_f1_0 := (others => '0');
v.delay_ch2_f1_1 := (others => '0');
v.delay_ch3_f1_0 := (others => '0');
v.delay_ch3_f1_1 := (others => '0');
v.delay_ch4_f1_0 := (others => '0');
v.delay_ch4_f1_1 := (others => '0');
v.delay_ch5_f1_0 := (others => '0');
v.delay_ch5_f1_1 := (others => '0');
v.delay_ch6_f1_0 := (others => '0');
v.delay_ch6_f1_1 := (others => '0');
v.delay_ch7_f1_0 := (others => '0');
v.delay_ch7_f1_1 := (others => '0');
v.delay_ch8_f1_0 := (others => '0');
v.delay_ch8_f1_1 := (others => '0');
v.delay_ch9_f1_0 := (others => '0');
v.delay_ch9_f1_1 := (others => '0');
v.delay_ch10_f1_0 := (others => '0');
v.delay_ch10_f1_1 := (others => '0');
v.delay_ch11_f1_0 := (others => '0');
v.delay_ch11_f1_1 := (others => '0');
else
v.sample_count := r.sample_count + 1;
end if;
end if;
when CALC =>
-- calculating, only use the multiplexed signals
prod1 := delay1 * coef;
prod1_sc := prod1((Q + CALC_WIDTH - 1) downto Q);
-- TODO detect overflow
sum1 := input + prod1_sc - delay2;
delay2 := delay1;
delay1 := sum1;
-- advance frequency and channel
if r.channel = CHANNELS-1 then
v.channel := 0;
if r.frequency = FREQUENCIES-1 then
v.frequency := 0;
v.state := IDLE;
else
v.frequency := r.frequency + 1;
end if;
else
v.channel := r.channel + 1;
end if;
end case;
-- multiplex output
-- This crashes lame ISE
-- v.delays(r.channel, r.frequency)(0) := delay1;
-- v.delays(r.channel, r.frequency)(1) := delay2;
case frequency is
when 0 =>
case channel is
when 0 =>
v.delay_ch0_f0_0 := delay1;
v.delay_ch0_f0_1 := delay2;
when 1 =>
v.delay_ch1_f0_0 := delay1;
v.delay_ch1_f0_1 := delay2;
when 2 =>
v.delay_ch2_f0_0 := delay1;
v.delay_ch2_f0_1 := delay2;
when 3 =>
v.delay_ch3_f0_0 := delay1;
v.delay_ch3_f0_1 := delay2;
when 4 =>
v.delay_ch4_f0_0 := delay1;
v.delay_ch4_f0_1 := delay2;
when 5 =>
v.delay_ch5_f0_0 := delay1;
v.delay_ch5_f0_1 := delay2;
when 6 =>
v.delay_ch6_f0_0 := delay1;
v.delay_ch6_f0_1 := delay2;
when 7 =>
v.delay_ch7_f0_0 := delay1;
v.delay_ch7_f0_1 := delay2;
when 8 =>
v.delay_ch8_f0_0 := delay1;
v.delay_ch8_f0_1 := delay2;
when 9 =>
v.delay_ch9_f0_0 := delay1;
v.delay_ch9_f0_1 := delay2;
when 10 =>
v.delay_ch10_f0_0 := delay1;
v.delay_ch10_f0_1 := delay2;
when 11 =>
v.delay_ch11_f0_0 := delay1;
v.delay_ch11_f0_1 := delay2;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
v.delay_ch0_f1_0 := delay1;
v.delay_ch0_f1_1 := delay2;
when 1 =>
v.delay_ch1_f1_0 := delay1;
v.delay_ch1_f1_1 := delay2;
when 2 =>
v.delay_ch2_f1_0 := delay1;
v.delay_ch2_f1_1 := delay2;
when 3 =>
v.delay_ch3_f1_0 := delay1;
v.delay_ch3_f1_1 := delay2;
when 4 =>
v.delay_ch4_f1_0 := delay1;
v.delay_ch4_f1_1 := delay2;
when 5 =>
v.delay_ch5_f1_0 := delay1;
v.delay_ch5_f1_1 := delay2;
when 6 =>
v.delay_ch6_f1_0 := delay1;
v.delay_ch6_f1_1 := delay2;
when 7 =>
v.delay_ch7_f1_0 := delay1;
v.delay_ch7_f1_1 := delay2;
when 8 =>
v.delay_ch8_f1_0 := delay1;
v.delay_ch8_f1_1 := delay2;
when 9 =>
v.delay_ch9_f1_0 := delay1;
v.delay_ch9_f1_1 := delay2;
when 10 =>
v.delay_ch10_f1_0 := delay1;
v.delay_ch10_f1_1 := delay2;
when 11 =>
v.delay_ch11_f1_0 := delay1;
v.delay_ch11_f1_1 := delay2;
when others => null;
end case;
when others => null;
end case;
rin <= v;
end process comb_proc;
end behavioural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:20:57 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-e.vhd,v 1.4 2005/12/14 12:38:04 wig Exp $
-- $Date: 2005/12/14 12:38:04 $
-- $Log: ioblock0_e-e.vhd,v $
-- Revision 1.4 2005/12/14 12:38:04 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ioblock0_e
--
entity ioblock0_e is
-- Generics:
-- No Generated Generics for Entity ioblock0_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end ioblock0_e;
--
-- End of Generated Entity ioblock0_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_di
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_di-struct-conf-c.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: vgca_di-struct-conf-c.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vgca_di_struct_conf / vgca_di
--
configuration vgca_di_struct_conf of vgca_di is
for struct
-- Generated Configuration
for i_di_m : di_m
use configuration work.di_m_struct_conf;
end for;
for i_di_s : di_s
use configuration work.di_s_struct_conf;
end for;
end for;
end vgca_di_struct_conf;
--
-- End of Generated Configuration vgca_di_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
architecture RTL of FIFO is
begin
process
begin
LOOP_LABEL: loop end loop;
LOOP_LABEL: while condition loop end loop;
LOOP_LABEL: for x in range(15 downto 0) loop end loop;
LOOP_LABEL:
loop end loop;
LOOP_LABEL:
while condition loop end loop;
LOOP_LABEL:
for x in range(15 downto 0) loop end loop;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : edit_msg.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-17
-- Last update : 2015-05-20
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description : Edit_msg Implementation
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-17 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity edit_msg is
port (
data_o : out std_logic_vector (31 downto 0);
stb_i : in std_logic;
sysclk : in std_logic; -- global clock
reset_n : in std_logic -- global reset
);
end entity edit_msg;
architecture edit_msg_rtl of edit_msg is
type MSG_ST_TYPE is (ST_INIT, ST_VERIFY);
attribute syn_enconding : string;
attribute syn_enconding of MSG_ST_TYPE : type is "safe"; -- FSM para n
type MSG_BUFFER_TYPE is array(0 to 7) of std_logic_vector(31 downto 0);
signal state_reg : MSG_ST_TYPE;
signal state_next : MSG_ST_TYPE;
signal msg_buffer_reg : MSG_BUFFER_TYPE;
signal msg_buffer_next : MSG_BUFFER_TYPE;
signal cont_reg : unsigned(2 downto 0);
signal cont_next : unsigned(2 downto 0);
signal dataout_reg : std_logic_vector(31 downto 0);
signal dataout_next : std_logic_vector(31 downto 0);
begin -- architecture edit_msg_rtl
data_o <= dataout_reg;
process(reset_n, sysclk)
begin
if reset_n = '0' then
state_reg <= ST_INIT;
for i in 0 to 7 loop
msg_buffer_reg(i) <= (others => '0');
end loop; -- i
dataout_reg <= (others => '0');
cont_reg <= (others => '0');
elsif rising_edge(sysclk) then
state_reg <= state_next;
msg_buffer_reg <= msg_buffer_next;
dataout_reg <= dataout_next;
cont_reg <= cont_next;
end if;
end process;
process (cont_reg, msg_buffer_reg, state_reg, stb_i)
begin
state_next <= state_reg;
msg_buffer_next <= msg_buffer_reg;
dataout_next <= msg_buffer_reg(to_integer(cont_reg));
cont_next <= cont_reg;
case state_reg is
when ST_INIT =>
state_next <= ST_VERIFY;
when ST_VERIFY =>
if stb_i = '1' then
cont_next <= cont_reg + 1;
end if;
end case;
msg_buffer_next(0) <= x"10000001";
msg_buffer_next(1) <= x"02222222";
msg_buffer_next(2) <= x"04333333";
msg_buffer_next(3) <= x"08444444";
msg_buffer_next(4) <= x"10555555";
msg_buffer_next(5) <= x"20666666";
msg_buffer_next(6) <= x"40777777";
msg_buffer_next(7) <= x"80888888";
end process;
end architecture edit_msg_rtl;
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
entity alu_inputs is
port (
Aadd, Badd : in integer;
Q, D : in MVL7_vector(3 downto 0);
I : in MVL7_vector(8 downto 0);
RE, S : out MVL7_vector(3 downto 0)
);
end alu_inputs;
architecture alu_inputs of alu_inputs is
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
signal RAM : Memory(15 downto 0) := (
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0000"),
("0100"),
("1000"));
signal A, B : MVL7_vector(3 downto 0);
begin
A <= RAM(Aadd);
B <= RAM(Badd);
-- SELECT THE SOURCE OPERANDS FOR ALU. SELECTED OPERANDS ARE "RE" AND "S".
with I(2 downto 0) select
RE <= A when "000" | "001",
"0000" when "010" | "011" | "100",
D when others;
with I(2 downto 0) select
S <= A when "100" | "101",
B when "001" | "011",
"0000" when "111",
Q when others;
end alu_inputs; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
constant FPURFHARD : integer := 1-is_fpga(memtech);
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (gclk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (gclk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (gclk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (gclk, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (FPURFHARD*fabtech, FPURFHARD*memtech, (fpuarch-1), pclow, dsu, disas, fpunet)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
mfpw0gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
grlfpc0gen : if (fpuarch >= 8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas, (fpuarch-8))
port map (rst, gclk, holdn, fpi, fpo);
end generate;
-- 1-clock reset delay
rstreg : process(gclk)
begin if rising_edge(gclk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3CG SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
constant FPURFHARD : integer := 1-is_fpga(memtech);
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (gclk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (gclk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (gclk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (gclk, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (FPURFHARD*fabtech, FPURFHARD*memtech, (fpuarch-1), pclow, dsu, disas, fpunet)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
mfpw0gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
grlfpc0gen : if (fpuarch >= 8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas, (fpuarch-8))
port map (rst, gclk, holdn, fpi, fpo);
end generate;
-- 1-clock reset delay
rstreg : process(gclk)
begin if rising_edge(gclk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3CG SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k1_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k1_k2_e-c.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_k1_k2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k1_k2_rtl_conf / inst_k1_k2_e
--
configuration inst_k1_k2_rtl_conf of inst_k1_k2_e is
for rtl
-- Generated Configuration
end for;
end inst_k1_k2_rtl_conf;
--
-- End of Generated Configuration inst_k1_k2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1 : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
word10b_array_rdy_s1 <= word10b_array_rdy_s;
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1 : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
word10b_array_rdy_s1 <= word10b_array_rdy_s;
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
----------------------------------------------------------------------------------------------------
-- TOP LEVEL ENTITY - ECDSA
-- FPDA implementation of ECDSA algorithm
--
-- Ports:
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 02.07.2017
-- Last Change: 10.11.2017
----------------------------------------------------------------------------------------------------
--
-- Pin Assignment:
--
-- clk_i : PIN_N2 (Clock 50 Mhz)
-- rst_i : PIN_G26 (Key 0)
-- uart_rx_i : PIN_C25 (UART Receiver)
-- uart_wx_i : PIN_B25 (UART Transmitter)
-- rst_led : PIN_Y18 (LEDG7)
--
------------------------------------------------------------
-- GF(2^M) ecdsa top level entity
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tld_ecdsa IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Uart read/write
uart_rx_i : IN std_logic;
uart_wx_i : OUT std_logic;
rst_led : OUT std_logic
);
END tld_ecdsa;
ARCHITECTURE rtl OF tld_ecdsa IS
-- Components -----------------------------------------
-- Import entity e_ecdsa
COMPONENT e_ecdsa IS
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
mode_i: IN std_logic;
hash_i: IN std_logic_vector(M-1 DOWNTO 0);
r_i: IN std_logic_vector(M-1 DOWNTO 0);
s_i: IN std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic;
valid_o: OUT std_logic;
sign_r_o: OUT std_logic_vector(M-1 DOWNTO 0);
sign_s_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Import entity e_uart_receive_mux
COMPONENT e_uart_receive_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
uart_i : IN std_logic;
mode_o : OUT std_logic;
r_o : OUT std_logic_vector(M-1 DOWNTO 0);
s_o : OUT std_logic_vector(M-1 DOWNTO 0);
m_o : OUT std_logic_vector(M-1 DOWNTO 0);
ready_o : OUT std_logic
);
END COMPONENT;
-- Import entity e_uart_transmit_mux
COMPONENT e_uart_transmit_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
enable_i : IN std_logic;
r_i : IN std_logic_vector(M-1 DOWNTO 0);
s_i : IN std_logic_vector(M-1 DOWNTO 0);
v_i : IN std_logic;
uart_o : OUT std_logic
);
END COMPONENT;
-- Internal signals -----------------------------------------
SIGNAL s_rst : std_logic;
-- ECDSA Entity
SIGNAL ecdsa_enable, ecdsa_mode, ecdsa_done, ecdsa_valid: std_logic := '0';
SIGNAL ecdsa_r_in, ecdsa_s_in, ecdsa_r_out, ecdsa_s_out, ecdsa_hash: std_logic_vector(M-1 DOWNTO 0);
BEGIN
-- Instantiate ecdsa entity
ecdsa: e_ecdsa PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
enable_i => ecdsa_enable,
mode_i => ecdsa_mode,
hash_i => ecdsa_hash,
r_i => ecdsa_r_in,
s_i => ecdsa_s_in,
ready_o => ecdsa_done,
valid_o => ecdsa_valid,
sign_r_o => ecdsa_r_out,
sign_s_o => ecdsa_s_out
);
-- Instantiate uart entity to receive data
uart_receive: e_uart_receive_mux PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
uart_i => uart_rx_i,
mode_o => ecdsa_mode,
r_o => ecdsa_r_in,
s_o => ecdsa_s_in,
m_o => ecdsa_hash,
ready_o => ecdsa_enable
);
-- Instantiate uart entity to send data
uart_transmit: e_uart_transmit_mux PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
mode_i => ecdsa_mode,
enable_i => ecdsa_done,
r_i => ecdsa_r_out,
s_i => ecdsa_s_out,
v_i => ecdsa_valid,
uart_o => uart_wx_i
);
s_rst <= NOT rst_i;
rst_led <= s_rst;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_406;
architecture augh of cmp_406 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_406;
architecture augh of cmp_406 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity motores is
Port ( CLK : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (0 downto 3);
Entrada : in STD_LOGIC);
end motores;
architecture Behavioral of motores is
begin
end Behavioral;
|
--比较两个二进制数是否相等
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COMPARE IS
PORT(A,B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EQ:OUT STD_LOGIC);
END ENTITY COMPARE;
ARCHITECTURE ART OF COMPARE IS
BEGIN
EQ<='1' WHEN A=B ELSE '0';
END ARCHITECTURE ART; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity get_gmem_m_axi;
architecture behave of get_gmem_m_axi is
component get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_write;
component get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_read;
component get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component get_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : get_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : get_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity get_gmem_m_axi_fifo;
architecture behave of get_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity get_gmem_m_axi_decoder;
architecture behav of get_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity get_gmem_m_axi_throttl;
architecture behav of get_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_read;
architecture behave of get_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_write;
architecture behave of get_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component get_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : get_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.