content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Reception_8bits IS
END TB_Reception_8bits;
ARCHITECTURE behavior OF TB_Reception_8bits IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Reception_8bits
PORT(
Divisor_Frecuencia : IN std_logic;
En... |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
--! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Xilinx
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
------------------------------------------------... |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Common definitions pertaining to the structure of Ethernet frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.al... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
--! @file mixMatrix.vhd
--! @brief AES state MixColumn
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyri... |
---------------------------------------------------------------------------------
-- TZX player
-- by György Szombathelyi
-- basic idea for the structure based on c1530 tap player by darfpga
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_11... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
library verilog;
use verilog.vl_types.all;
entity FORWARD is
port(
Rs_ID_EX : in vl_logic_vector(4 downto 0);
Rt_ID_EX : in vl_logic_vector(4 downto 0);
Rd_EX_MEM : in vl_logic_vector(4 downto 0);
Rs_IF_ID : in vl_logic_vector(4 downto 0);
... |
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8
-- Date: Fri May 17 10:15:39 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_log... |
--------------------------------------------------------------------------------
-- file name : pack_16to12.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -pack_16to12
-- arch_itecture - arch_pack_16to12
--
-- language : vhdl
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CharRam is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(10 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
... |
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60 is
port(Clk,Ldn:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60;
architecture Behavior of H24_Min60_Sec60 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 dow... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: dcm_sfs_unisim_s3e.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eithe... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
entity RegisterFile is
generic (BitWidth: integer);
port ( clk : in std_logic;
rst: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_CU: in std_logic_vector (BitWidth-1 downto 0);
Data_in_ACC: in std_logic_ve... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
entity RegisterFile is
generic (BitWidth: integer);
port ( clk : in std_logic;
rst: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_CU: in std_logic_vector (BitWidth-1 downto 0);
Data_in_ACC: in std_logic_ve... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
architecture RTL of FIFO is begin end architecture;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture;
-- This should not fail
architecture RTL... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Dec 23 11:06:46 2016
-- Host : KLight-PC running 64-bit major relea... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i2s is
generic (
I2S_SIZE : integer := 8
);
port (
-- Control
clk : in std_logic; -- Main clock
rst : in std_logic; ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file ... |
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- Single Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity SinglePortRAM is
generic (
AWIDTH : posi... |
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESU... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
entity signal25 is
end entity;
architecture test of signal25 is
type rec is record
f : bit_vector;
end record;
signal v : bit_vector(1 to 3);
signal r : rec(f(1 to 2));
begin
v(1 to r.f'right) <= (others => '1');
v(r.f'right + 1 to 3) <= (others => '0');
check: process is
beg... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_multiplier - Structural
-- Description: Multiplies two IEEE-754 floating point numbers
----------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_multiplier - Structural
-- Description: Multiplies two IEEE-754 floating point numbers
----------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_multiplier - Structural
-- Description: Multiplies two IEEE-754 floating point numbers
----------------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrit... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- rgb_grayscale_tb.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rgb_grayscale_tb is
end entity;
architecture testbench of rgb_grayscale_tb is
signal clk : s... |
entity bounds_case is
end entity;
architecture test of bounds_case is
begin
process is
type letter is (A, B, C);
subtype ab is letter range B to letter'right;
variable l : letter;
variable m : ab;
begin
case l is -- Choice C not covered
... |
entity bounds_case is
end entity;
architecture test of bounds_case is
begin
process is
type letter is (A, B, C);
subtype ab is letter range B to letter'right;
variable l : letter;
variable m : ab;
begin
case l is -- Choice C not covered
... |
library ieee;
use ieee.numeric_bit.all;
entity View_output is
port(clk:in bit; reset:in bit;
hex0_out:out bit_vector(7 downto 0);
hex1_out:out bit_vector(7 downto 0);
hex2_out:out bit_vector(7 downto 0));
end entity View_output;
architecture combination_of_View of View_output is
--type
component Threebit_BCD_cou... |
library ieee;
use ieee.std_logic_1164.all;
ENTITY DecodeHex IS
PORT(
BitInput: IN std_logic_vector(3 downto 0);
HexOutput: OUT std_logic_vector(6 downto 0));
END DecodeHex;
ARCHITECTURE Behavior OF DecodeHex IS
BEGIN
WITH BitInput SELECT
HexOutput <= "1000000" WHEN "0000",
"1111001" W... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:53 10/01/2013
-- Design Name:
-- Module Name: uart_transmit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
library ieee;
use ieee.std_logic_1164.all;
entity asgn09 is
port (a, b, c, d : std_logic_vector (1 downto 0);
sel : std_logic_vector(1 downto 0);
o : out std_logic_vector (3 downto 0));
end asgn09;
architecture behav of asgn09 is
begin
with sel select
o (1 downto 0) <= a when "00",
b when ... |
/********************************************************************
* *
* THIS FILE IS PART OF THE OggVorbis SOFTWARE CODEC SOURCE CODE. *
* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
* GOVERNED BY A BSD-STYLE SOURCE LICENS... |
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity Shifter_tb is
end Shifter_tb;
architecture simu of Shifter_tb is
signal shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, cin : std_logic;
signal shift_val :std_logic_vector (4 downto 0);
signal din :std... |
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.a... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.reset_types.all;
entity reset_testbench is
end reset_testbench;
architecture behavior of reset_testbench is
component power_on_reset
port (
clk: in std_logic;
reset: in std_logic;
core_en: out std_logic;
sys_... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.reset_types.all;
entity reset_testbench is
end reset_testbench;
architecture behavior of reset_testbench is
component power_on_reset
port (
clk: in std_logic;
reset: in std_logic;
core_en: out std_logic;
sys_... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.reset_types.all;
entity reset_testbench is
end reset_testbench;
architecture behavior of reset_testbench is
component power_on_reset
port (
clk: in std_logic;
reset: in std_logic;
core_en: out std_logic;
sys_... |
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