content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc687.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00687ent IS
END c03s04b01x00p23n01i00687ent;
ARCHITECTURE c03s04b01x00p23n01i00687arch OF c03s04b01x00p23n01i00687ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.52";
-- Declare a variable.
constant CON : TIME := 1 ns;
variable VAR : TIME := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00687 - The output file will tested by test file s010416.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00687arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc687.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00687ent IS
END c03s04b01x00p23n01i00687ent;
ARCHITECTURE c03s04b01x00p23n01i00687arch OF c03s04b01x00p23n01i00687ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.52";
-- Declare a variable.
constant CON : TIME := 1 ns;
variable VAR : TIME := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00687 - The output file will tested by test file s010416.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00687arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc687.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00687ent IS
END c03s04b01x00p23n01i00687ent;
ARCHITECTURE c03s04b01x00p23n01i00687arch OF c03s04b01x00p23n01i00687ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.52";
-- Declare a variable.
constant CON : TIME := 1 ns;
variable VAR : TIME := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00687 - The output file will tested by test file s010416.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00687arch;
|
entity test is
end entity test;
architecture test_arch of test is
type arr01 is array (0 to 1) of integer;
function p1(a1 : arr01) return integer is
begin
return a1(0);
end function;
begin
main: process
variable x : integer := 10;
begin
x := p1( (others => 0) ); -- <- HERE
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
|
-- Declaração dos sinais.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
--current status: unfinished, not compiled
--this contains the structure of the "inner loop" required for bitcoin mining. The next level up should increment the nonce every cycle and provide new mid_state/message values every time the nonce rolls over
--a hit will be reported with significant latency (currently looking like 178 and change cycles) after the associated nonce is provided,
-- so some subtraction (and possibly fetching the previous message) is required to get the complete valid header.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mining_loop is
port (
clk : in std_logic;
mid_state : in std_logic_vector(255 downto 0);--hash result from the first 64-byte word of the header (that doesn't change per nonce)
message : in std_logic_vector( 95 downto 0);
nonce : in std_logic_vector( 31 downto 0); --only this input should change every cycle
target : in std_logic_vector(223 downto 0); --probably most efficient to have a constant or very small variability in permitted target numbers since 224x 224:1 muxes is super expensive (technically a 255 bit number, but top 32 bits are 0 at easiest difficulty)
hit : out std_logic
);
end entity mining_loop;
architecture struct of mining_loop is
component sha256 is
port(
clk : in std_logic;
chunk : in std_logic_vector(511 downto 0);
state : in std_logic_vector(255 downto 0);
hash : out std_logic_vector(255 downto 0) --65 cycle delay
);
end component;
component wide_uns_comparator_dsp is
generic (
n : positive := 48
);
port (
clk : in std_logic;
a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
gt : out std_logic; --3 cycle delay
eq : out std_logic
);
end component;
function f_word_reverse (a : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(a'range);
begin
assert a'length mod 32 = 0 report "invalid width input" severity failure;
for i in 0 to a'length/32-1 loop
for j in 0 to 31 loop
temp(32*i+j) := a(a'high-i*32-31+j);
end loop;
end loop;
return temp;
end f_word_reverse;
constant c_init_state : std_logic_vector(255 downto 0) := x"6a09e667" & x"bb67ae85" & x"3c6ef372" & x"a54ff53a" & x"510e527f" & x"9b05688c" & x"1f83d9ab" & x"5be0cd19"; --word 0 is msb slot, word 7 is lsb
constant c_padding_1 : std_logic_vector(383 downto 0) := '1' & 319UX"0" & 64d"128";
constant c_padding_2 : std_logic_vector(255 downto 0) := '1' & 191UX"0" & 64d"256";
signal chunk1 : std_logic_vector( 511 downto 0);
signal hash1 : std_logic_vector( 255 downto 0);
signal chunk2 : std_logic_vector( 511 downto 0);
signal hash2 : std_logic_vector( 255 downto 0);
signal target_ext : std_logic_vector( 239 downto 0);
signal gt : std_logic;
signal top0 : std_logic_vector(1 to 3);
begin
chunk1 <= f_word_reverse(message & nonce & c_padding_1);
u_sha256_1 : sha256
port map (
clk => clk,
chunk => chunk1,
state => mid_state, --TODO: needs to be delayed to match expansion
hash => hash1
);
chunk2 <= f_word_reverse(hash1 & c_padding_2);
u_sha256_2 : sha256
port map (
clk => clk,
chunk => chunk2,
state => c_init_state,
hash => hash2
);
target_ext(239 downto 224) <= (others=>'0');
target_ext(223 downto 0) <= target; --TODO: this needs to be delayed to match hash
u_wide_uns_comparator_dsp : wide_uns_comparator_dsp
generic map (
n => 240 --comparison happens in groups of 48, so any n where n mod 48 /= 0 is wasting free resources. We actually only need 224 bits for the dynamic portion of the target
)
port map (
clk => clk,
a => hash2(239 downto 0),
b => target_ext(239 downto 0),
gt => gt, --3 cycles latency
eq => open
);
process(clk)
begin
if rising_edge(clk) then
if unsigned(hash2(255 downto 240)) = 0 then --check the top few bits with LUTs since it would take a whole extra DSP and checking for 0 is easier than a proper gt/lt comparison.
top0(1) <= '1';
else
top0(1) <= '0';
end if;
top0(2 to 3) <= top0(1 to 2); --latency match to the comparator DSPs
hit <= not gt and top0(3);
end if;
end process;
end architecture struct; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_tb IS
END ENTITY;
ARCHITECTURE RAM_tb_ARCH OF RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_synth_inst:ENTITY work.RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Quad 2-input AND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7408 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : out ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : out ttl_t;
p12 : in ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7408 is
signal p3_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p11_loc : ttl_t;
begin
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p3_loc <= p1 and p2;
p6_loc <= p4 and p5;
p8_loc <= p9 and p10;
p11_loc <= p12 and p13;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group
-- Engineer: Florian Huemer
--
-- Create Date: 2011
-- Design Name: textmode_controller
-- Module Name: textmode_controller_fsm
-- Project Name: graphic_lib
-- Description:
--
--
-- Color information is always stored in the bits 15-8 of instr_data.
--
--
-- video ram layout: (also data layout for set char/clear screen instruction)
--
-- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-- | fg-color | bg-color | character code |
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
--
--
--
--
-- data layout for config instruction
--
-- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-- |XX|XX|XX|XX|cursorcolor|XX|XX|XX|XX|ac|as|c1|c0|
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
--
--
-- XX: Don't care
--
-- ac: Auto Increment Cursor
-- If activated the cursor will automaticly move to the next position after each SET_CHAR instruction.
--
-- as: Auto scroll
-- This flag enables/disables the automatic scroll function of the controller.
-- If activated, this feature will also clear the complete line after a newline event occurred (e.g. INSTR_NEW_LINE).
--
-- c0-c1:
-- Cursor state
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.textmode_controller_pkg.all;
use work.math_pkg.all;
----------------------------------------------------------------------------------
-- ENTITY --
----------------------------------------------------------------------------------
entity textmode_controller_fsm is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100
);
port
(
clk : in std_logic;
res_n : in std_logic;
wr : in std_logic;
busy : out std_logic;
instr : in std_logic_vector(7 downto 0);
instr_data : in std_logic_vector(15 downto 0);
scroll_offset : out std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
cursor_position_row : out std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
cursor_position_colum : out std_logic_vector(log2c(COLUM_COUNT)-1 downto 0);
cursor_color : out std_logic_vector(3 downto 0);
cursor_state : out std_logic_vector(1 downto 0);
video_ram_addr : out std_logic_vector( (log2c(COLUM_COUNT)+log2c(ROW_COUNT)-1) downto 0);
video_ram_data : out std_logic_vector(15 downto 0);
video_ram_wr : out std_logic
);
end entity textmode_controller_fsm;
----------------------------------------------------------------------------------
-- ARCHITECTURE --
----------------------------------------------------------------------------------
architecture beh of textmode_controller_fsm is
constant CHAR_LINEFEED : std_logic_vector(7 downto 0) := x"0A";
constant CHAR_BACKSPACE : std_logic_vector(7 downto 0) := x"08";
constant CHAR_CARRIAGE_RETURN : std_logic_vector(7 downto 0) := x"0D";
constant VIDEO_RAM_ADDRESSWIDTH : integer := log2c(COLUM_COUNT) + log2c(ROW_COUNT);
type TEXTMODE_CONTROLLER_STATE_TYPE is (IDLE, CLEAR_SCREEN, SET_CHAR, DELETE, DELETE_NEXT, SET_CURSOR_POSITION, NEW_LINE, CLEAR_LINE, SET_CFG, MOVE_CURSOR_NEXT, NOP);
signal textmode_controller_state : TEXTMODE_CONTROLLER_STATE_TYPE;
signal textmode_controller_state_next : TEXTMODE_CONTROLLER_STATE_TYPE;
signal instr_data_buffer : std_logic_vector(15 downto 0);
signal instr_data_buffer_next : std_logic_vector(15 downto 0);
-- colum
signal x_cursor : integer range 0 to COLUM_COUNT;
signal x_cursor_next : integer range 0 to COLUM_COUNT;
-- row
signal y_cursor : integer range 0 to ROW_COUNT;
signal y_cursor_next : integer range 0 to ROW_COUNT;
-- scoll counter
signal sig_scroll_offset : integer range 0 to ROW_COUNT;
signal sig_scroll_offset_next : integer range 0 to ROW_COUNT;
-- flags
signal cfg_register : std_logic_vector(3 downto 0);
signal cfg_register_next : std_logic_vector(3 downto 0);
alias cursor_mode : std_logic_vector(1 downto 0) is cfg_register(1 downto 0);
alias cursor_mode_next : std_logic_vector(1 downto 0) is cfg_register_next(1 downto 0);
alias auto_scroll : std_logic is cfg_register(2);
alias auto_scroll_next : std_logic is cfg_register_next(2);
alias auto_inc_cursor : std_logic is cfg_register(3);
alias auto_inc_cursor_next : std_logic is cfg_register_next(3);
signal sig_cursor_color : std_logic_vector(3 downto 0);
signal sig_cursor_color_next : std_logic_vector(3 downto 0);
begin
--------------------------------------------------------------------
-- PROCESS : SYNC --
--------------------------------------------------------------------
sync : process(res_n, clk)
begin
if res_n = '0' then
textmode_controller_state <= CLEAR_SCREEN;--IDLE;
x_cursor <= 0;
y_cursor <= 0;
auto_inc_cursor <= '0';
auto_scroll <= '0';
sig_scroll_offset <= 0;
cursor_mode <= CURSOR_STATE_BLINK;
sig_cursor_color <= "1010";
instr_data_buffer <= (others=>'0');
elsif rising_edge(clk) then
textmode_controller_state <= textmode_controller_state_next;
instr_data_buffer <= instr_data_buffer_next;
x_cursor <= x_cursor_next;
y_cursor <= y_cursor_next;
sig_scroll_offset <= sig_scroll_offset_next;
cfg_register <= cfg_register_next;
sig_cursor_color <= sig_cursor_color_next;
end if;
end process sync;
--------------------------------------------------------------------
-- PROCESS : NEXT_STATE --
--------------------------------------------------------------------
next_state : process (textmode_controller_state, wr, instr, x_cursor, y_cursor, instr_data)
begin
textmode_controller_state_next <= textmode_controller_state;
case textmode_controller_state is
---------------------------------------------------
when IDLE =>
if wr = '1' then
case instr is
when INSTR_CLEAR_SCREEN => textmode_controller_state_next <= CLEAR_SCREEN;
when INSTR_SET_CHAR =>
if instr_data(7 downto 0) = CHAR_LINEFEED or
instr_data(7 downto 0) = CHAR_CARRIAGE_RETURN then --new line
textmode_controller_state_next <= NEW_LINE;
elsif instr_data(7 downto 0) = CHAR_BACKSPACE then
textmode_controller_state_next <= DELETE;
else
textmode_controller_state_next <= SET_CHAR;
end if;
when INSTR_DELETE => textmode_controller_state_next <= DELETE;
when INSTR_SET_CURSOR_POSITION => textmode_controller_state_next <= SET_CURSOR_POSITION;
when INSTR_CFG => textmode_controller_state_next <= SET_CFG;
when INSTR_MOVE_CURSOR_NEXT => textmode_controller_state_next <= MOVE_CURSOR_NEXT;
when INSTR_NEW_LINE => textmode_controller_state_next <= NEW_LINE;
when INSTR_NOP => textmode_controller_state_next <= NOP;
when others =>
end case;
end if;
---------------------------------------------------
when NOP =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when CLEAR_SCREEN =>
if (x_cursor = (COLUM_COUNT-1) and y_cursor = (ROW_COUNT-1)) then
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when SET_CHAR =>
if auto_inc_cursor = '0' then
textmode_controller_state_next <= MOVE_CURSOR_NEXT;
end if;
---------------------------------------------------
when DELETE =>
textmode_controller_state_next <= DELETE_NEXT;
---------------------------------------------------
when DELETE_NEXT =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when SET_CURSOR_POSITION =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when NEW_LINE =>
if auto_scroll = '0' then
textmode_controller_state_next <= CLEAR_LINE;
else
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when CLEAR_LINE =>
if x_cursor = COLUM_COUNT-1 then
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when SET_CFG =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when MOVE_CURSOR_NEXT =>
if x_cursor = COLUM_COUNT-1 then
textmode_controller_state_next <= NEW_LINE;
else
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when others =>
null;
end case;
end process next_state;
--------------------------------------------------------------------
-- PROCESS : OUTPUT --
--------------------------------------------------------------------
output : process (cfg_register, wr, auto_inc_cursor, sig_cursor_color, instr_data, instr_data_buffer, textmode_controller_state, x_cursor, y_cursor, auto_scroll, sig_scroll_offset)
begin
busy <= '1';
video_ram_wr <= '0';
instr_data_buffer_next <= instr_data_buffer;
x_cursor_next <= x_cursor;
y_cursor_next <= y_cursor;
video_ram_data <= (others => '0');
video_ram_addr <= (others => '0');
cfg_register_next <= cfg_register;
sig_scroll_offset_next <= sig_scroll_offset;
sig_cursor_color_next <= sig_cursor_color;
case textmode_controller_state is
---------------------------------------------------
when IDLE =>
busy <= '0';
if wr = '1' then
instr_data_buffer_next <= instr_data; --buffer input value
end if;
---------------------------------------------------
when CLEAR_SCREEN =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 0);
video_ram_wr <= '1';
sig_scroll_offset_next <= 0;
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
if y_cursor = ROW_COUNT-1 then
y_cursor_next <= 0;
else
y_cursor_next <= y_cursor + 1;
end if;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when SET_CHAR =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 0);
video_ram_wr <= '1';
---------------------------------------------------
when DELETE =>
if x_cursor = 0 then
if y_cursor = 0 then
-- do nothing
else
y_cursor_next <= y_cursor - 1;
x_cursor_next <= COLUM_COUNT - 1;
end if;
else
x_cursor_next <= x_cursor - 1;
end if;
---------------------------------------------------
when DELETE_NEXT =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 8) & x"00";
video_ram_wr <= '1';
---------------------------------------------------
when SET_CURSOR_POSITION =>
x_cursor_next <= to_integer(unsigned( instr_data_buffer(log2c(COLUM_COUNT)+8 downto 8) ));
y_cursor_next <= to_integer(unsigned( instr_data_buffer(log2c(ROW_COUNT) downto 0) ));
---------------------------------------------------
when NEW_LINE =>
x_cursor_next <= 0;
if auto_scroll = '0' then --auto-scroll
if y_cursor = ROW_COUNT-1 then
if sig_scroll_offset = ROW_COUNT-1 then
sig_scroll_offset_next <= 0;
else
sig_scroll_offset_next <= sig_scroll_offset + 1;
end if;
else
y_cursor_next <= y_cursor + 1;
end if;
else -- no auto-scroll
if y_cursor = ROW_COUNT-1 then
y_cursor_next <= 0;
else
y_cursor_next <= y_cursor + 1;
end if;
end if;
---------------------------------------------------
when CLEAR_LINE =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 8) & x"00";
video_ram_wr <= '1';
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when SET_CFG =>
sig_cursor_color_next <= instr_data_buffer(11 downto 8);
cfg_register_next <= instr_data_buffer(3 downto 0);
---------------------------------------------------
when MOVE_CURSOR_NEXT =>
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when others =>
end case;
end process output;
scroll_offset <= std_logic_vector(to_unsigned(sig_scroll_offset, log2c(ROW_COUNT)));
cursor_position_colum <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT)));
cursor_position_row <= std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
cursor_state <= cursor_mode;
cursor_color <= sig_cursor_color;
end architecture beh;
-- EOF --
|
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group
-- Engineer: Florian Huemer
--
-- Create Date: 2011
-- Design Name: textmode_controller
-- Module Name: textmode_controller_fsm
-- Project Name: graphic_lib
-- Description:
--
--
-- Color information is always stored in the bits 15-8 of instr_data.
--
--
-- video ram layout: (also data layout for set char/clear screen instruction)
--
-- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-- | fg-color | bg-color | character code |
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
--
--
--
--
-- data layout for config instruction
--
-- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-- |XX|XX|XX|XX|cursorcolor|XX|XX|XX|XX|ac|as|c1|c0|
-- +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
--
--
-- XX: Don't care
--
-- ac: Auto Increment Cursor
-- If activated the cursor will automaticly move to the next position after each SET_CHAR instruction.
--
-- as: Auto scroll
-- This flag enables/disables the automatic scroll function of the controller.
-- If activated, this feature will also clear the complete line after a newline event occurred (e.g. INSTR_NEW_LINE).
--
-- c0-c1:
-- Cursor state
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.textmode_controller_pkg.all;
use work.math_pkg.all;
----------------------------------------------------------------------------------
-- ENTITY --
----------------------------------------------------------------------------------
entity textmode_controller_fsm is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100
);
port
(
clk : in std_logic;
res_n : in std_logic;
wr : in std_logic;
busy : out std_logic;
instr : in std_logic_vector(7 downto 0);
instr_data : in std_logic_vector(15 downto 0);
scroll_offset : out std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
cursor_position_row : out std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
cursor_position_colum : out std_logic_vector(log2c(COLUM_COUNT)-1 downto 0);
cursor_color : out std_logic_vector(3 downto 0);
cursor_state : out std_logic_vector(1 downto 0);
video_ram_addr : out std_logic_vector( (log2c(COLUM_COUNT)+log2c(ROW_COUNT)-1) downto 0);
video_ram_data : out std_logic_vector(15 downto 0);
video_ram_wr : out std_logic
);
end entity textmode_controller_fsm;
----------------------------------------------------------------------------------
-- ARCHITECTURE --
----------------------------------------------------------------------------------
architecture beh of textmode_controller_fsm is
constant CHAR_LINEFEED : std_logic_vector(7 downto 0) := x"0A";
constant CHAR_BACKSPACE : std_logic_vector(7 downto 0) := x"08";
constant CHAR_CARRIAGE_RETURN : std_logic_vector(7 downto 0) := x"0D";
constant VIDEO_RAM_ADDRESSWIDTH : integer := log2c(COLUM_COUNT) + log2c(ROW_COUNT);
type TEXTMODE_CONTROLLER_STATE_TYPE is (IDLE, CLEAR_SCREEN, SET_CHAR, DELETE, DELETE_NEXT, SET_CURSOR_POSITION, NEW_LINE, CLEAR_LINE, SET_CFG, MOVE_CURSOR_NEXT, NOP);
signal textmode_controller_state : TEXTMODE_CONTROLLER_STATE_TYPE;
signal textmode_controller_state_next : TEXTMODE_CONTROLLER_STATE_TYPE;
signal instr_data_buffer : std_logic_vector(15 downto 0);
signal instr_data_buffer_next : std_logic_vector(15 downto 0);
-- colum
signal x_cursor : integer range 0 to COLUM_COUNT;
signal x_cursor_next : integer range 0 to COLUM_COUNT;
-- row
signal y_cursor : integer range 0 to ROW_COUNT;
signal y_cursor_next : integer range 0 to ROW_COUNT;
-- scoll counter
signal sig_scroll_offset : integer range 0 to ROW_COUNT;
signal sig_scroll_offset_next : integer range 0 to ROW_COUNT;
-- flags
signal cfg_register : std_logic_vector(3 downto 0);
signal cfg_register_next : std_logic_vector(3 downto 0);
alias cursor_mode : std_logic_vector(1 downto 0) is cfg_register(1 downto 0);
alias cursor_mode_next : std_logic_vector(1 downto 0) is cfg_register_next(1 downto 0);
alias auto_scroll : std_logic is cfg_register(2);
alias auto_scroll_next : std_logic is cfg_register_next(2);
alias auto_inc_cursor : std_logic is cfg_register(3);
alias auto_inc_cursor_next : std_logic is cfg_register_next(3);
signal sig_cursor_color : std_logic_vector(3 downto 0);
signal sig_cursor_color_next : std_logic_vector(3 downto 0);
begin
--------------------------------------------------------------------
-- PROCESS : SYNC --
--------------------------------------------------------------------
sync : process(res_n, clk)
begin
if res_n = '0' then
textmode_controller_state <= CLEAR_SCREEN;--IDLE;
x_cursor <= 0;
y_cursor <= 0;
auto_inc_cursor <= '0';
auto_scroll <= '0';
sig_scroll_offset <= 0;
cursor_mode <= CURSOR_STATE_BLINK;
sig_cursor_color <= "1010";
instr_data_buffer <= (others=>'0');
elsif rising_edge(clk) then
textmode_controller_state <= textmode_controller_state_next;
instr_data_buffer <= instr_data_buffer_next;
x_cursor <= x_cursor_next;
y_cursor <= y_cursor_next;
sig_scroll_offset <= sig_scroll_offset_next;
cfg_register <= cfg_register_next;
sig_cursor_color <= sig_cursor_color_next;
end if;
end process sync;
--------------------------------------------------------------------
-- PROCESS : NEXT_STATE --
--------------------------------------------------------------------
next_state : process (textmode_controller_state, wr, instr, x_cursor, y_cursor, instr_data)
begin
textmode_controller_state_next <= textmode_controller_state;
case textmode_controller_state is
---------------------------------------------------
when IDLE =>
if wr = '1' then
case instr is
when INSTR_CLEAR_SCREEN => textmode_controller_state_next <= CLEAR_SCREEN;
when INSTR_SET_CHAR =>
if instr_data(7 downto 0) = CHAR_LINEFEED or
instr_data(7 downto 0) = CHAR_CARRIAGE_RETURN then --new line
textmode_controller_state_next <= NEW_LINE;
elsif instr_data(7 downto 0) = CHAR_BACKSPACE then
textmode_controller_state_next <= DELETE;
else
textmode_controller_state_next <= SET_CHAR;
end if;
when INSTR_DELETE => textmode_controller_state_next <= DELETE;
when INSTR_SET_CURSOR_POSITION => textmode_controller_state_next <= SET_CURSOR_POSITION;
when INSTR_CFG => textmode_controller_state_next <= SET_CFG;
when INSTR_MOVE_CURSOR_NEXT => textmode_controller_state_next <= MOVE_CURSOR_NEXT;
when INSTR_NEW_LINE => textmode_controller_state_next <= NEW_LINE;
when INSTR_NOP => textmode_controller_state_next <= NOP;
when others =>
end case;
end if;
---------------------------------------------------
when NOP =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when CLEAR_SCREEN =>
if (x_cursor = (COLUM_COUNT-1) and y_cursor = (ROW_COUNT-1)) then
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when SET_CHAR =>
if auto_inc_cursor = '0' then
textmode_controller_state_next <= MOVE_CURSOR_NEXT;
end if;
---------------------------------------------------
when DELETE =>
textmode_controller_state_next <= DELETE_NEXT;
---------------------------------------------------
when DELETE_NEXT =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when SET_CURSOR_POSITION =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when NEW_LINE =>
if auto_scroll = '0' then
textmode_controller_state_next <= CLEAR_LINE;
else
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when CLEAR_LINE =>
if x_cursor = COLUM_COUNT-1 then
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when SET_CFG =>
textmode_controller_state_next <= IDLE;
---------------------------------------------------
when MOVE_CURSOR_NEXT =>
if x_cursor = COLUM_COUNT-1 then
textmode_controller_state_next <= NEW_LINE;
else
textmode_controller_state_next <= IDLE;
end if;
---------------------------------------------------
when others =>
null;
end case;
end process next_state;
--------------------------------------------------------------------
-- PROCESS : OUTPUT --
--------------------------------------------------------------------
output : process (cfg_register, wr, auto_inc_cursor, sig_cursor_color, instr_data, instr_data_buffer, textmode_controller_state, x_cursor, y_cursor, auto_scroll, sig_scroll_offset)
begin
busy <= '1';
video_ram_wr <= '0';
instr_data_buffer_next <= instr_data_buffer;
x_cursor_next <= x_cursor;
y_cursor_next <= y_cursor;
video_ram_data <= (others => '0');
video_ram_addr <= (others => '0');
cfg_register_next <= cfg_register;
sig_scroll_offset_next <= sig_scroll_offset;
sig_cursor_color_next <= sig_cursor_color;
case textmode_controller_state is
---------------------------------------------------
when IDLE =>
busy <= '0';
if wr = '1' then
instr_data_buffer_next <= instr_data; --buffer input value
end if;
---------------------------------------------------
when CLEAR_SCREEN =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 0);
video_ram_wr <= '1';
sig_scroll_offset_next <= 0;
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
if y_cursor = ROW_COUNT-1 then
y_cursor_next <= 0;
else
y_cursor_next <= y_cursor + 1;
end if;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when SET_CHAR =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 0);
video_ram_wr <= '1';
---------------------------------------------------
when DELETE =>
if x_cursor = 0 then
if y_cursor = 0 then
-- do nothing
else
y_cursor_next <= y_cursor - 1;
x_cursor_next <= COLUM_COUNT - 1;
end if;
else
x_cursor_next <= x_cursor - 1;
end if;
---------------------------------------------------
when DELETE_NEXT =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 8) & x"00";
video_ram_wr <= '1';
---------------------------------------------------
when SET_CURSOR_POSITION =>
x_cursor_next <= to_integer(unsigned( instr_data_buffer(log2c(COLUM_COUNT)+8 downto 8) ));
y_cursor_next <= to_integer(unsigned( instr_data_buffer(log2c(ROW_COUNT) downto 0) ));
---------------------------------------------------
when NEW_LINE =>
x_cursor_next <= 0;
if auto_scroll = '0' then --auto-scroll
if y_cursor = ROW_COUNT-1 then
if sig_scroll_offset = ROW_COUNT-1 then
sig_scroll_offset_next <= 0;
else
sig_scroll_offset_next <= sig_scroll_offset + 1;
end if;
else
y_cursor_next <= y_cursor + 1;
end if;
else -- no auto-scroll
if y_cursor = ROW_COUNT-1 then
y_cursor_next <= 0;
else
y_cursor_next <= y_cursor + 1;
end if;
end if;
---------------------------------------------------
when CLEAR_LINE =>
video_ram_addr <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT))) &
std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
video_ram_data <= instr_data_buffer(15 downto 8) & x"00";
video_ram_wr <= '1';
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when SET_CFG =>
sig_cursor_color_next <= instr_data_buffer(11 downto 8);
cfg_register_next <= instr_data_buffer(3 downto 0);
---------------------------------------------------
when MOVE_CURSOR_NEXT =>
if x_cursor = COLUM_COUNT-1 then
x_cursor_next <= 0;
else
x_cursor_next <= x_cursor + 1;
end if;
---------------------------------------------------
when others =>
end case;
end process output;
scroll_offset <= std_logic_vector(to_unsigned(sig_scroll_offset, log2c(ROW_COUNT)));
cursor_position_colum <= std_logic_vector(to_unsigned(x_cursor, log2c(COLUM_COUNT)));
cursor_position_row <= std_logic_vector(to_unsigned(y_cursor, log2c(ROW_COUNT)));
cursor_state <= cursor_mode;
cursor_color <= sig_cursor_color;
end architecture beh;
-- EOF --
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Task3 is
port (
CLK: in STD_LOGIC;
IP: in STD_LOGIC_VECTOR (3 downto 0);
RST: in STD_LOGIC;
OP: out STD_LOGIC_VECTOR (1 downto 0));
end Task3;
architecture Beh of Task3 is
type state_type is (
S0, S1, S2, S3, S4
);
signal state: state_type;
begin
state_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
state <= S0;
else
case state is
when S0 =>
if IP="0011" then
state <= S1;
end if;
when S1 =>
if IP="1111" then
state <= S4;
end if;
when S2 =>
if IP="1100" then
state <= S1;
end if;
when S3 =>
if IP="0000" then
state <= S2;
end if;
when S4 =>
if IP="1101" then
state <= S3;
end if;
when others =>
state <= S0;
end case;
end if;
end if;
end process;
OP_assignment:
OP <= "01" when (state = S0) else
"01" when (state = S1) else
"00" when (state = S2) else
"00" when (state = S3) else
"11" when (state = S4) else
"01";
end Beh;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000017#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--
-- MMCM Testbench
--
-- Author:
-- * Rodrigo A. Melo, rmelo@inti.gob.ar
--
-- Copyright (c) 2016 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Test of Top_tb is
constant PERIOD : time := 5 ns;
signal clk, nclk, rst : std_logic;
signal stop : boolean;
signal leds : std_logic_vector(5 downto 0);
begin
nclk <= not (clk);
do_clk: Clock
generic map(PERIOD => PERIOD)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: entity work.Top
port map (clk_p_i => clk, clk_n_i => nclk, rst_i => rst, leds_o => leds);
stimulus: process
begin
wait until rising_edge(clk) and rst='0';
for i in 0 to 255 loop
wait until rising_edge(clk);
end loop;
stop <= TRUE;
wait;
end process stimulus;
end architecture Test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lvov is
Port (
CLK50 : IN STD_LOGIC;
RESET_BTN : IN STD_LOGIC;
PS2_CLK : in STD_LOGIC;
PS2_DATA : in STD_LOGIC;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CS : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
LED : OUT std_logic;
TAPE_IN : IN std_logic;
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC );
end lvov;
architecture Behavioral of lvov is
-- Verilog Modules
----------------------------------------------------------
component k580wm80a is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
intr : in std_logic;
idata : in std_logic_vector(7 downto 0);
addr : out std_logic_vector(15 downto 0);
sync : out std_logic;
rd : out std_logic;
wr_n : out std_logic;
inta_n : out std_logic;
odata : out std_logic_vector(7 downto 0);
inte_o : out std_logic );
end component;
----------------------------------------------------------
signal CLK : std_logic;
signal RESET : std_logic := '0';
signal TICK : std_logic_vector(3 downto 0) := "0000";
signal SRAM_DI : std_logic_vector(7 downto 0);
signal SRAM_DO : std_logic_vector(7 downto 0);
signal VRAM_CS : std_logic;
signal CACHE_SWAP : std_logic;
signal CACHE_WE : std_logic;
signal CACHE_A : std_logic_vector(5 downto 0);
signal CACHE_DI : std_logic_vector(7 downto 0);
signal CACHE_VA : std_logic_vector(5 downto 0);
signal CACHE_VD : std_logic_vector(7 downto 0);
signal SCANLINE : std_logic_vector(7 downto 0);
signal CACHE_RD : std_logic;
signal CACHE_CNT : std_logic_vector (5 downto 0);
signal KEYB_A : std_logic_vector(7 downto 0);
signal KEYB_D : std_logic_vector(7 downto 0);
signal KEYB_A2 : std_logic_vector(3 downto 0);
signal KEYB_D2 : std_logic_vector(3 downto 0);
signal COLORS : std_logic_vector(6 downto 0);
signal ROM_D : std_logic_vector(7 downto 0);
signal ROM_INIT : std_logic;
signal CPU_CLK : std_logic;
signal CPU_SYNC : std_logic;
signal CPU_RD : std_logic;
signal CPU_WR_N : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal IO_RD : std_logic;
signal IO_WR : std_logic;
signal MEM_RD : std_logic;
signal MEM_WR : std_logic;
signal XSD_EN : std_logic;
signal XSDROM_D : std_logic_vector(7 downto 0);
signal SD_CLK_R : std_logic;
signal SD_DATA : std_logic_vector(6 downto 0);
signal SD_O : std_logic_vector(7 downto 0);
-- FSM States
type STATE_TYPE is ( IDLE, RAMREAD1,
RAMWRITE1, RAMWRITE2,
CACHE1, CACHE2, CACHE3, CACHE4 );
signal STATE : STATE_TYPE := IDLE;
begin
u_CLOCK : entity work.clock
port map(
CLK_IN => CLK50,
CLK_OUT => CLK );
u_ROM : entity work.rom
port map(
CLKA => CLK,
ADDRA => CPU_A(13 downto 0),
DOUTA => ROM_D );
u_XSDROM : entity work.xsd_rom
port map(
CLKA => CLK,
ADDRA => CPU_A(10 downto 0),
DOUTA => XSDROM_D );
u_CPU : k580wm80a
port map(
clk => CLK,
ce => CPU_CLK,
reset => not RESET,
intr => '0',
idata => CPU_DI,
addr => CPU_A,
sync => CPU_SYNC,
rd => CPU_RD,
wr_n => CPU_WR_N,
inta_n => OPEN,
odata => CPU_DO,
inte_o => OPEN );
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => '1',
CACHE_SWAP => CACHE_SWAP,
CACHE_A => CACHE_VA,
CACHE_D => CACHE_VD,
CURRENT_LINE=> SCANLINE,
COLORS => COLORS,
R => VGA_R,
G => VGA_G,
B => VGA_B,
HSYNC => VGA_HSYNC,
VSYNC => VGA_VSYNC );
u_CACHE : entity work.cache
port map(
CLK => CLK,
AI => CACHE_A,
DI => CACHE_DI,
WE => CACHE_WE,
AO => CACHE_VA,
DO => CACHE_VD,
CACHE => CACHE_SWAP );
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
KEYB_A => KEYB_A,
KEYB_D => KEYB_D,
KEYB_A2 => KEYB_A2,
KEYB_D2 => KEYB_D2 );
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_D <= "ZZZZZZZZ" & SRAM_DI;
SRAM_DO <= SRAM_D(7 downto 0);
--
----------------------------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
else
if CPU_SYNC = '1' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
if CPU_DO(4) = '1' then
IO_WR <= '0';
elsif CPU_DO(6) = '1' then
IO_RD <= '0';
elsif CPU_DO(7) = '1' then
MEM_RD <= '0';
elsif CPU_DO(7) = '0' then
MEM_WR <= '0';
end if;
end if;
end if;
end if;
end process;
-- LED <= TAPE_IN;
-- reset & first ROM access
CLOCK : process(CLK)
begin
if rising_edge(CLK) then
if RESET_BTN = '0' then
TICK <= (others => '0');
RESET <= '0';
ROM_INIT <= '1';
else
TICK <= TICK + 1;
CPU_CLK <= '0';
if TICK = "1111" then -- Generate 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
CPU_CLK <= '1';
TICK <= (others => '0');
RESET <= '1';
if IO_WR = '0' or IO_RD = '0' then
ROM_INIT <= '0';
end if;
end if;
end if;
end if;
end process;
FSM : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_DI <= (others => 'Z');
CACHE_RD <= '0';
CACHE_CNT <= "000000";
XSD_EN <= '0';
LED <= '1';
else
CACHE_WE <= '1';
if CACHE_SWAP = '1' then
CACHE_RD <= '1';
CACHE_CNT <= "000000";
end if;
case STATE is
when IDLE =>
if TICK = 1 then
if MEM_RD = '0' and CPU_RD = '1' then ------------------------------------------------------------------------- Read from Memory
if (CPU_A(15) = '1' and CPU_A(14) = '1') or ROM_INIT = '1' then -- Read from ROM
CPU_DI <= ROM_D;
elsif CPU_A(15 downto 11) = "00000" and XSD_EN = '1' then
CPU_DI <= XSDROM_D;
else -- Read from RAM
if CPU_A(15) = '0' and VRAM_CS = '0' then
SRAM_A <= "01" & CPU_A;
else
SRAM_A <= "00" & CPU_A;
end if;
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= RAMREAD1;
end if;
elsif MEM_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to Memory
if CPU_A(15) = '0' and VRAM_CS = '0' then
SRAM_A <= "01" & CPU_A;
else
SRAM_A <= "00" & CPU_A;
end if;
SRAM_WE <= '0';
SRAM_CS <= '0';
SRAM_DI <= CPU_DO;
STATE <= RAMWRITE1;
elsif IO_RD = '0' and CPU_RD = '1' then ---------------------------------------------------------------------- Read from I/O-Ports
CPU_DI <= (others => '1');
if CPU_A(7 downto 0) = X"F1" then
CPU_DI <= SD_O;
elsif CPU_A(4) ='0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
CPU_DI <= "111" & TAPE_IN & "1111";
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
CPU_DI <= KEYB_D;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
CPU_DI <= KEYB_D2 & KEYB_A2;
end if;
elsif IO_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to I/O-Ports
if CPU_A(7 downto 0) = X"FF" then
XSD_EN <= CPU_DO(1);
LED <= '0';
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
COLORS <= CPU_DO(6 downto 0);
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
VRAM_CS <= CPU_DO(1);
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "00" then
KEYB_A <= CPU_DO;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
KEYB_A2 <= CPU_DO(3 downto 0);
end if;
else
if CACHE_RD = '1' then
SRAM_A <= "0101" & SCANLINE & CACHE_CNT;
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= CACHE1;
end if;
end if;
end if;
when CACHE1 =>
CACHE_A <= CACHE_CNT;
CACHE_DI <= SRAM_DO;
SRAM_OE <= '1';
SRAM_CS <= '1';
CACHE_WE <= '0';
if CACHE_CNT = "111111" then
CACHE_RD <= '0';
else
CACHE_CNT <= CACHE_CNT + '1';
end if;
STATE <= IDLE;
when RAMREAD1 =>
SRAM_OE <= '1';
SRAM_CS <= '1';
CPU_DI <= SRAM_DO;
STATE <= IDLE;
when RAMWRITE1 =>
SRAM_WE <= '1';
SRAM_CS <= '1';
STATE <= RAMWRITE2;
when RAMWRITE2 =>
SRAM_DI <= (others => 'Z');
STATE <= IDLE;
when OTHERS =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
--//////////////////// SD CARD ////////////////////
--reg sdcs;
--reg sdclk;
--reg sdcmd;
--reg[6:0] sddata;
--wire[7:0] sd_o = {sddata, SD_DAT};
--
--assign SD_DAT3 = ~sdcs;
--assign SD_CMD = sdcmd;
--assign SD_CLK = sdclk;
--
--always @(posedge clk50 or posedge reset) begin
-- if (reset) begin
-- sdcs <= 1'b0;
-- sdclk <= 1'b0;
-- sdcmd <= 1'h1;
-- end else begin
-- if (addrbus[4:0]==5'h1A && ~port_wr_n) sdcs <= cpu_o[0];
-- if (addrbus[4:0]==5'h1B && ~port_wr_n) begin
-- if (sdclk) sddata <= {sddata[5:0],SD_DAT};
-- sdcmd <= cpu_o[7];
-- sdclk <= 1'b0;
-- end
-- if (cpu_rd) sdclk <= 1'b1;
-- end
--end
SD_O <= SD_DATA & SD_MISO;
SD_SCK <= SD_CLK_R;
process(CLK)
begin
if RESET = '0' then
SD_CS <= '1';
SD_MOSI <= '1';
SD_CLK_R <= '0';
elsif rising_edge(CLK) then
if IO_WR = '0' and CPU_A(7 downto 0) = X"F0" then
SD_CS <= not CPU_DO(0);
elsif IO_WR = '0' and CPU_A(7 downto 0) = X"F1" then
if SD_CLK_R = '1' then
SD_DATA <= SD_DATA(5 downto 0) & SD_MISO;
end if;
SD_MOSI <= CPU_DO(7);
SD_CLK_R <= '0';
end if;
if IO_RD = '0' or MEM_RD = '0' then
SD_CLK_R <= '1';
end if;
end if;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: car_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY car_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE car_synth_ARCH OF car_synth IS
COMPONENT car_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: car_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity retorno_reg is
generic(
WIDTH : integer := 10
);
port(
swe : in vl_logic;
reset : in vl_logic;
d : in vl_logic_vector;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of WIDTH : constant is 1;
end retorno_reg;
|
--!
--! \file test_coop.vhd
--!
--! Simulation testbench thread for cooperative multithreading
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 23.04.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 23.04.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_coop is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_coop;
architecture Behavioral of test_coop is
-- OS synchronization state machine states
type state_t is (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07");
constant decode : decode_t := (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
-- resources used by thread
constant C_SEM_YIELD : std_logic_vector(0 to 31) := X"00000000";
constant C_SEM_DELAY : std_logic_vector(0 to 31) := X"00000001";
constant C_SEM_LOCK : std_logic_vector(0 to 31) := X"00000002";
constant C_MUTEX : std_logic_vector(0 to 31) := X"00000003";
constant C_DELAY : std_logic_vector(0 to 31) := X"0000007F"; -- delay for 128 ticks
signal state : state_t := STATE_CHECK;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_CHECK;
variable resume_state_enc : reconos_state_enc_t := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_CHECK;
next_state := STATE_CHECK;
resume_state_enc := (others => '0');
done := false;
success := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
next_state := decode(to_integer(unsigned(resume_state_enc)));
else
next_state := STATE_YIELD;
end if;
end if;
-- test thread_yield()
when STATE_YIELD =>
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_thread_yield(o_osif, i_osif, encode(STATE_POST_YIELD));
next_state := STATE_POST_YIELD;
when STATE_POST_YIELD =>
reconos_sem_post(o_osif, i_osif, C_SEM_YIELD);
next_state := STATE_DELAY;
-- test single-cycle blocking yielding call
when STATE_DELAY =>
reconos_thread_delay(o_osif, i_osif, C_DELAY); -- delay via OS
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_POST_DELAY));
next_state := STATE_POST_DELAY;
when STATE_POST_DELAY =>
reconos_sem_post(o_osif, i_osif, C_SEM_DELAY);
next_state := STATE_LOCK;
-- test multi-cycle blocking yielding call
when STATE_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX);
-- on multi-cycle calls, saved_state_enc must be set to the _current_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_LOCK));
if done then
if success then
next_state := STATE_POST_LOCK;
else
next_state := STATE_EXIT;
end if;
end if;
when STATE_POST_LOCK =>
reconos_sem_post(o_osif, i_osif, C_SEM_LOCK);
next_state := STATE_EXIT;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00417.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00417: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00417: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00417: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00417: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00417
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00417(ARCH00417)
-- ENT00417_Test_Bench(ARCH00417_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00417 is
end ENT00417 ;
--
--
architecture ARCH00417 of ENT00417 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00417.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00417" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00417" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00417" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00417" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00417" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f2.f2 <=
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2.f2 after 5 ns
when 3,
--
c_st_rec3_1.f2.f2 after 100 ns
when 4,
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1.f2.f2 after 40 ns when 6 ;
--
end ARCH00417 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00417_Test_Bench is
end ENT00417_Test_Bench ;
--
--
architecture ARCH00417_Test_Bench of ENT00417_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00417 ( ARCH00417 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00417_Test_Bench ;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
fault_out: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- East
signal E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in : std_logic;
-- West
signal W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in : std_logic;
-- South
signal S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in : std_logic;
-- Local
signal L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_South_Req_L,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_East_Req_N,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel : std_logic;
-- East
signal E_err_state_IDLE_xbar,
E_err_state_not_IDLE_xbar,
E_err_state_IDLE_RTS_FF_in,
E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
E_err_RTS_FF_not_DCTS_state_state_in,
E_err_not_RTS_FF_state_in_next_state,
E_err_RTS_FF_DCTS_state_in_next_state,
E_err_not_DCTS_Grants,
E_err_DCTS_not_RTS_FF_Grants,
E_err_DCTS_RTS_FF_IDLE_Grants,
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
E_err_Requests_next_state_IDLE,
E_err_IDLE_Req_L,
E_err_Local_Req_L,
E_err_North_Req_N,
E_err_IDLE_Req_N,
E_err_Local_Req_N,
E_err_South_Req_L,
E_err_West_Req_L,
E_err_South_Req_N,
E_err_East_Req_L,
E_err_West_Req_N,
E_err_East_Req_N,
E_err_next_state_onehot,
E_err_state_in_onehot,
E_err_state_north_xbar_sel,
E_err_state_east_xbar_sel,
E_err_state_west_xbar_sel,
E_err_state_south_xbar_sel : std_logic;
-- West
signal W_err_state_IDLE_xbar,
W_err_state_not_IDLE_xbar,
W_err_state_IDLE_RTS_FF_in,
W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
W_err_RTS_FF_not_DCTS_state_state_in,
W_err_not_RTS_FF_state_in_next_state,
W_err_RTS_FF_DCTS_state_in_next_state,
W_err_not_DCTS_Grants,
W_err_DCTS_not_RTS_FF_Grants,
W_err_DCTS_RTS_FF_IDLE_Grants,
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
W_err_Requests_next_state_IDLE,
W_err_IDLE_Req_L,
W_err_Local_Req_L,
W_err_North_Req_N,
W_err_IDLE_Req_N,
W_err_Local_Req_N,
W_err_South_Req_L,
W_err_West_Req_L,
W_err_South_Req_N,
W_err_East_Req_L,
W_err_West_Req_N,
W_err_East_Req_N,
W_err_next_state_onehot,
W_err_state_in_onehot,
W_err_state_north_xbar_sel,
W_err_state_east_xbar_sel,
W_err_state_west_xbar_sel,
W_err_state_south_xbar_sel : std_logic;
-- South
signal S_err_state_IDLE_xbar,
S_err_state_not_IDLE_xbar,
S_err_state_IDLE_RTS_FF_in,
S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
S_err_RTS_FF_not_DCTS_state_state_in,
S_err_not_RTS_FF_state_in_next_state,
S_err_RTS_FF_DCTS_state_in_next_state,
S_err_not_DCTS_Grants,
S_err_DCTS_not_RTS_FF_Grants,
S_err_DCTS_RTS_FF_IDLE_Grants,
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
S_err_Requests_next_state_IDLE,
S_err_IDLE_Req_L,
S_err_Local_Req_L,
S_err_North_Req_N,
S_err_IDLE_Req_N,
S_err_Local_Req_N,
S_err_South_Req_L,
S_err_West_Req_L,
S_err_South_Req_N,
S_err_East_Req_L,
S_err_West_Req_N,
S_err_East_Req_N,
S_err_next_state_onehot,
S_err_state_in_onehot,
S_err_state_north_xbar_sel,
S_err_state_east_xbar_sel,
S_err_state_west_xbar_sel,
S_err_state_south_xbar_sel : std_logic;
-- Local
signal L_err_state_IDLE_xbar,
L_err_state_not_IDLE_xbar,
L_err_state_IDLE_RTS_FF_in,
L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
L_err_RTS_FF_not_DCTS_state_state_in,
L_err_not_RTS_FF_state_in_next_state,
L_err_RTS_FF_DCTS_state_in_next_state,
L_err_not_DCTS_Grants,
L_err_DCTS_not_RTS_FF_Grants,
L_err_DCTS_RTS_FF_IDLE_Grants,
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
L_err_Requests_next_state_IDLE,
L_err_IDLE_Req_L,
L_err_Local_Req_L,
L_err_North_Req_N,
L_err_IDLE_Req_N,
L_err_Local_Req_N,
L_err_South_Req_L,
L_err_West_Req_L,
L_err_South_Req_N,
L_err_East_Req_L,
L_err_West_Req_N,
L_err_East_Req_N,
L_err_next_state_onehot,
L_err_state_in_onehot,
L_err_state_north_xbar_sel,
L_err_state_east_xbar_sel,
L_err_state_west_xbar_sel,
L_err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_write_en,
N_err_not_CTS_in,
N_err_read_en_mismatch : std_logic;
-- East
signal E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_write_en,
E_err_not_CTS_in,
E_err_read_en_mismatch : std_logic;
-- West
signal W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_write_en,
W_err_not_CTS_in,
W_err_read_en_mismatch : std_logic;
-- South
signal S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_write_en,
S_err_not_CTS_in,
S_err_read_en_mismatch : std_logic;
-- Local
signal L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_write_en,
L_err_not_CTS_in,
L_err_read_en_mismatch : std_logic;
-- Error Signals for each module (ORed combination of checker outputs)
signal N_LBDR_checkers_output,
E_LBDR_checkers_output,
W_LBDR_checkers_output,
S_LBDR_checkers_output,
L_LBDR_checkers_output: std_logic;
signal N_Arbiter_checkers_output,
E_Arbiter_checkers_output,
W_Arbiter_checkers_output,
S_Arbiter_checkers_output,
L_Arbiter_checkers_output: std_logic;
signal N_FIFO_control_part_checkers_output,
E_FIFO_control_part_checkers_output,
W_FIFO_control_part_checkers_output,
S_FIFO_control_part_checkers_output,
L_FIFO_control_part_checkers_output: std_logic;
begin
-- OR of checker outputs for each module (corresponding to each direction)
-- This is used for feeding the checker outputs to shift registers (later)
-- LBDR
N_LBDR_checkers_output <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in;
E_LBDR_checkers_output <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in;
W_LBDR_checkers_output <= W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_header_not_empty_Req_N_in or
W_err_header_not_empty_Req_E_in or
W_err_header_not_empty_Req_W_in or
W_err_header_not_empty_Req_S_in;
S_LBDR_checkers_output <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in;
L_LBDR_checkers_output <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in;
-- Arbiter
N_Arbiter_checkers_output <= N_err_state_IDLE_xbar or
N_err_state_not_IDLE_xbar or
N_err_state_IDLE_RTS_FF_in or
N_err_state_not_IDLE_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
N_err_RTS_FF_not_DCTS_state_state_in or
N_err_not_RTS_FF_state_in_next_state or
N_err_RTS_FF_DCTS_state_in_next_state or
N_err_not_DCTS_Grants or
N_err_DCTS_not_RTS_FF_Grants or
N_err_DCTS_RTS_FF_IDLE_Grants or
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
N_err_Requests_next_state_IDLE or
N_err_IDLE_Req_L or
N_err_Local_Req_L or
N_err_North_Req_N or
N_err_IDLE_Req_N or
N_err_Local_Req_N or
N_err_South_Req_L or
N_err_West_Req_L or
N_err_South_Req_N or
N_err_East_Req_L or
N_err_West_Req_N or
N_err_East_Req_N or
N_err_next_state_onehot or
N_err_state_in_onehot or
N_err_state_north_xbar_sel or
N_err_state_east_xbar_sel or
N_err_state_west_xbar_sel or
N_err_state_south_xbar_sel;
E_Arbiter_checkers_output <= E_err_state_IDLE_xbar or
E_err_state_not_IDLE_xbar or
E_err_state_IDLE_RTS_FF_in or
E_err_state_not_IDLE_RTS_FF_RTS_FF_in or
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
E_err_RTS_FF_not_DCTS_state_state_in or
E_err_not_RTS_FF_state_in_next_state or
E_err_RTS_FF_DCTS_state_in_next_state or
E_err_not_DCTS_Grants or
E_err_DCTS_not_RTS_FF_Grants or
E_err_DCTS_RTS_FF_IDLE_Grants or
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
E_err_Requests_next_state_IDLE or
E_err_IDLE_Req_L or
E_err_Local_Req_L or
E_err_North_Req_N or
E_err_IDLE_Req_N or
E_err_Local_Req_N or
E_err_South_Req_L or
E_err_West_Req_L or
E_err_South_Req_N or
E_err_East_Req_L or
E_err_West_Req_N or
E_err_East_Req_N or
E_err_next_state_onehot or
E_err_state_in_onehot or
E_err_state_north_xbar_sel or
E_err_state_east_xbar_sel or
E_err_state_west_xbar_sel or
E_err_state_south_xbar_sel;
W_Arbiter_checkers_output <= W_err_state_IDLE_xbar or
W_err_state_not_IDLE_xbar or
W_err_state_IDLE_RTS_FF_in or
W_err_state_not_IDLE_RTS_FF_RTS_FF_in or
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
W_err_RTS_FF_not_DCTS_state_state_in or
W_err_not_RTS_FF_state_in_next_state or
W_err_RTS_FF_DCTS_state_in_next_state or
W_err_not_DCTS_Grants or
W_err_DCTS_not_RTS_FF_Grants or
W_err_DCTS_RTS_FF_IDLE_Grants or
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
W_err_Requests_next_state_IDLE or
W_err_IDLE_Req_L or
W_err_Local_Req_L or
W_err_North_Req_N or
W_err_IDLE_Req_N or
W_err_Local_Req_N or
W_err_South_Req_L or
W_err_West_Req_L or
W_err_South_Req_N or
W_err_East_Req_L or
W_err_West_Req_N or
W_err_East_Req_N or
W_err_next_state_onehot or
W_err_state_in_onehot or
W_err_state_north_xbar_sel or
W_err_state_east_xbar_sel or
W_err_state_west_xbar_sel or
W_err_state_south_xbar_sel;
S_Arbiter_checkers_output <= S_err_state_IDLE_xbar or
S_err_state_not_IDLE_xbar or
S_err_state_IDLE_RTS_FF_in or
S_err_state_not_IDLE_RTS_FF_RTS_FF_in or
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
S_err_RTS_FF_not_DCTS_state_state_in or
S_err_not_RTS_FF_state_in_next_state or
S_err_RTS_FF_DCTS_state_in_next_state or
S_err_not_DCTS_Grants or
S_err_DCTS_not_RTS_FF_Grants or
S_err_DCTS_RTS_FF_IDLE_Grants or
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
S_err_Requests_next_state_IDLE or
S_err_IDLE_Req_L or
S_err_Local_Req_L or
S_err_North_Req_N or
S_err_IDLE_Req_N or
S_err_Local_Req_N or
S_err_South_Req_L or
S_err_West_Req_L or
S_err_South_Req_N or
S_err_East_Req_L or
S_err_West_Req_N or
S_err_East_Req_N or
S_err_next_state_onehot or
S_err_state_in_onehot or
S_err_state_north_xbar_sel or
S_err_state_east_xbar_sel or
S_err_state_west_xbar_sel or
S_err_state_south_xbar_sel;
L_Arbiter_checkers_output <= L_err_state_IDLE_xbar or
L_err_state_not_IDLE_xbar or
L_err_state_IDLE_RTS_FF_in or
L_err_state_not_IDLE_RTS_FF_RTS_FF_in or
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
L_err_RTS_FF_not_DCTS_state_state_in or
L_err_not_RTS_FF_state_in_next_state or
L_err_RTS_FF_DCTS_state_in_next_state or
L_err_not_DCTS_Grants or
L_err_DCTS_not_RTS_FF_Grants or
L_err_DCTS_RTS_FF_IDLE_Grants or
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
L_err_Requests_next_state_IDLE or
L_err_IDLE_Req_L or
L_err_Local_Req_L or
L_err_North_Req_N or
L_err_IDLE_Req_N or
L_err_Local_Req_N or
L_err_South_Req_L or
L_err_West_Req_L or
L_err_South_Req_N or
L_err_East_Req_L or
L_err_West_Req_N or
L_err_East_Req_N or
L_err_next_state_onehot or
L_err_state_in_onehot or
L_err_state_north_xbar_sel or
L_err_state_east_xbar_sel or
L_err_state_west_xbar_sel or
L_err_state_south_xbar_sel;
-- FIFO Control Part
N_FIFO_control_part_checkers_output <= N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_CTS_in or
N_err_read_en_mismatch;
E_FIFO_control_part_checkers_output <= E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_CTS_in or
E_err_read_en_mismatch;
W_FIFO_control_part_checkers_output <= W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_write_en or
W_err_not_CTS_in or
W_err_read_en_mismatch;
S_FIFO_control_part_checkers_output <= S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_write_en or
S_err_not_CTS_in or
S_err_read_en_mismatch;
L_FIFO_control_part_checkers_output <= L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or
L_err_not_CTS_in or
L_err_read_en_mismatch;
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_N, DRTS =>DRTS_N, fault_out => fault_out_N);
PC_E: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_E, DRTS =>DRTS_E, fault_out => fault_out_E);
PC_W: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_W, DRTS =>DRTS_W, fault_out => fault_out_W);
PC_S: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_S, DRTS =>DRTS_S, fault_out => fault_out_S);
PC_L: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_L, DRTS =>DRTS_L, fault_out => fault_out_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_read_en_mismatch => N_err_read_en_mismatch
);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E,
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_CTS_in => E_err_not_CTS_in,
err_read_en_mismatch => E_err_read_en_mismatch
);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W,
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_CTS_in => W_err_not_CTS_in,
err_read_en_mismatch => W_err_read_en_mismatch
);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S,
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_CTS_in => S_err_not_CTS_in,
err_read_en_mismatch => S_err_read_en_mismatch
);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L,
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_CTS_in => L_err_not_CTS_in,
err_read_en_mismatch => L_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in
);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_n_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in
);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in
);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N,
err_state_IDLE_xbar => N_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => N_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => N_err_IDLE_Req_L ,
err_Local_Req_L => N_err_Local_Req_L ,
err_North_Req_N => N_err_North_Req_N ,
err_IDLE_Req_N => N_err_IDLE_Req_N ,
err_Local_Req_N => N_err_Local_Req_N ,
err_South_Req_L => N_err_South_Req_L ,
err_West_Req_L => N_err_West_Req_L ,
err_South_Req_N => N_err_South_Req_N ,
err_East_Req_L => N_err_East_Req_L ,
err_West_Req_N => N_err_West_Req_N ,
err_East_Req_N => N_err_East_Req_N ,
err_next_state_onehot => N_err_next_state_onehot ,
err_state_in_onehot => N_err_state_in_onehot ,
err_state_north_xbar_sel => N_err_state_north_xbar_sel ,
err_state_east_xbar_sel => N_err_state_east_xbar_sel ,
err_state_west_xbar_sel => N_err_state_west_xbar_sel ,
err_state_south_xbar_sel => N_err_state_south_xbar_sel
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E,
err_state_IDLE_xbar => E_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => E_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => E_err_IDLE_Req_L ,
err_Local_Req_L => E_err_Local_Req_L ,
err_North_Req_N => E_err_North_Req_N ,
err_IDLE_Req_N => E_err_IDLE_Req_N ,
err_Local_Req_N => E_err_Local_Req_N ,
err_South_Req_L => E_err_South_Req_L ,
err_West_Req_L => E_err_West_Req_L ,
err_South_Req_N => E_err_South_Req_N ,
err_East_Req_L => E_err_East_Req_L ,
err_West_Req_N => E_err_West_Req_N ,
err_East_Req_N => E_err_East_Req_N ,
err_next_state_onehot => E_err_next_state_onehot ,
err_state_in_onehot => E_err_state_in_onehot ,
err_state_north_xbar_sel => E_err_state_north_xbar_sel ,
err_state_east_xbar_sel => E_err_state_east_xbar_sel ,
err_state_west_xbar_sel => E_err_state_west_xbar_sel ,
err_state_south_xbar_sel => E_err_state_south_xbar_sel
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W,
err_state_IDLE_xbar => W_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => W_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => W_err_IDLE_Req_L ,
err_Local_Req_L => W_err_Local_Req_L ,
err_North_Req_N => W_err_North_Req_N ,
err_IDLE_Req_N => W_err_IDLE_Req_N ,
err_Local_Req_N => W_err_Local_Req_N ,
err_South_Req_L => W_err_South_Req_L ,
err_West_Req_L => W_err_West_Req_L ,
err_South_Req_N => W_err_South_Req_N ,
err_East_Req_L => W_err_East_Req_L ,
err_West_Req_N => W_err_West_Req_N ,
err_East_Req_N => W_err_East_Req_N ,
err_next_state_onehot => W_err_next_state_onehot ,
err_state_in_onehot => W_err_state_in_onehot ,
err_state_north_xbar_sel => W_err_state_north_xbar_sel ,
err_state_east_xbar_sel => W_err_state_east_xbar_sel ,
err_state_west_xbar_sel => W_err_state_west_xbar_sel ,
err_state_south_xbar_sel => W_err_state_south_xbar_sel
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S,
err_state_IDLE_xbar => S_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => S_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => S_err_IDLE_Req_L ,
err_Local_Req_L => S_err_Local_Req_L ,
err_North_Req_N => S_err_North_Req_N ,
err_IDLE_Req_N => S_err_IDLE_Req_N ,
err_Local_Req_N => S_err_Local_Req_N ,
err_South_Req_L => S_err_South_Req_L ,
err_West_Req_L => S_err_West_Req_L ,
err_South_Req_N => S_err_South_Req_N ,
err_East_Req_L => S_err_East_Req_L ,
err_West_Req_N => S_err_West_Req_N ,
err_East_Req_N => S_err_East_Req_N ,
err_next_state_onehot => S_err_next_state_onehot ,
err_state_in_onehot => S_err_state_in_onehot ,
err_state_north_xbar_sel => S_err_state_north_xbar_sel ,
err_state_east_xbar_sel => S_err_state_east_xbar_sel ,
err_state_west_xbar_sel => S_err_state_west_xbar_sel ,
err_state_south_xbar_sel => S_err_state_south_xbar_sel
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L,
err_state_IDLE_xbar => L_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => L_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => L_err_IDLE_Req_L ,
err_Local_Req_L => L_err_Local_Req_L ,
err_North_Req_N => L_err_North_Req_N ,
err_IDLE_Req_N => L_err_IDLE_Req_N ,
err_Local_Req_N => L_err_Local_Req_N ,
err_South_Req_L => L_err_South_Req_L ,
err_West_Req_L => L_err_West_Req_L ,
err_South_Req_N => L_err_South_Req_N ,
err_East_Req_L => L_err_East_Req_L ,
err_West_Req_N => L_err_West_Req_N ,
err_East_Req_N => L_err_East_Req_N ,
err_next_state_onehot => L_err_next_state_onehot ,
err_state_in_onehot => L_err_state_in_onehot ,
err_state_north_xbar_sel => L_err_state_north_xbar_sel ,
err_state_east_xbar_sel => L_err_state_east_xbar_sel ,
err_state_west_xbar_sel => L_err_state_west_xbar_sel ,
err_state_south_xbar_sel => L_err_state_south_xbar_sel
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:02:56 09/23/2015
-- Design Name:
-- Module Name: lcd_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_display is
Port ( clk : in STD_LOGIC;
data: in STD_LOGIC_VECTOR(7 downto 0);
wr: in STD_LOGIC;
lcd_rw : out STD_LOGIC;
lcd_rs : out STD_LOGIC;
lcd_en : out STD_LOGIC;
lcd_data : out STD_LOGIC_VECTOR(3 downto 0)
);
end lcd_display;
architecture Behavioral of lcd_display is
component counter is
GENERIC (
Nbits: integer := 32;
Nmax: integer := 9
);
Port ( clk : in STD_LOGIC;
reset_counter : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (Nbits-1 downto 0));
end component;
constant t_start_to_init0: integer := 750000; -- 15ms
constant t_init0_to_init1: integer := 950000; -- 19ms
constant t_init1_to_init2: integer := 1050000; -- 21ms
constant t_init2_to_init3: integer := 1150000; -- 23ms
constant t_init3_to_set : integer := 1155000; -- 23,1ms
constant t_set_to_entry : integer := 1160000; -- 23,2ms
constant t_entry_to_on : integer := 1165000; -- 23,3ms
constant t_on_to_clear : integer := 1170000; -- 23,4ms
constant t_clear_to_ready: integer := 1270000; -- 25,4ms
type T_etat is (start, init0, init1, init2, init3, set, entry, state_on, clear, ready, setaddress, writeaddress, writedata);
signal next_state, state_reg : T_etat;
begin
data <= "10000001";
state_reg_process: process(clk)
begin
if rising_edge(clk) then
if state_reg /= ready then
state_reg <= start;
reset_counter <= '1';
reset_counter <= '0';
case Q is
when t_start_to_init0 =>
state_reg <= init0;
D <= (7 downto 4 => x"3");
when t_init0_to_init1 =>
state_reg <= init1;
D <= (7 downto 4 => x"3");
when t_init1_to_init2 =>
state_reg <= init2;
D <= (7 downto 4 => x"3");
when t_init2_to_init3 =>
state_reg <= init3;
D <= (7 downto 4 => x"2");
when t_init3_to_set =>
state_reg <= set;
D <= (7 downto 4 => x"2");
D <= (7 downto 4 => x"8");
when t_set_to_entry =>
state_reg <= entry;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"6");
when t_entry_to_on =>
state_reg <= state_on;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"C");
when t_on_to_clear =>
state_reg <= clear;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"1");
when t_clear_to_ready =>
state_reg <= ready;
state_reg <= next_state;
end case;
end if;
end if;
end process state_reg_process;
next_state_process: process(state_reg)
begin
next_state <= state_reg;
case state_reg is
when clear =>
reset_counter <= '1';
reset_counter <= '0';
if Q="100000" then -- 2ms
next_state <= ready;
D(7 downto 4) <= x"0";
D(7 downto 4) <= x"1";
end if;
when ready =>
if wr='1' and data=x"C" then
next_state <= clear;
else if wr='1' and data/=x"D" and data/=x"A" and data/=x"C" then
next_state <= writedata;
end if;
when writedata =>
LCD_DATA <= data(3 downto 0);
LCD_EN <= '1';
reset_counter <= '1';
reset_counter <= '0';
case Q is
when "50" => -- 1µs
LCD_EN <= '0';
LCD_DATA <= data(7 downto 4);
LCD_EN <= '1';
when "100" => -- 1+1µs
LCD_EN <= '0';
when "2100" => -- 40+1+1µs
next_state <= ready;
end case;
end case;
end process next_state_process
end architecture Behavioral;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_stbs_set_nodre.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hw_acc
-- Version: 1.00.a
-- Description: Example Axi Streaming core (VHDL).
-- Date: Mon Sep 15 15:41:21 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_AXIS_TDATA : Data in
-- S_AXIS_TLAST : Optional data in qualifier
-- S_AXIS_TVALID : Data in is valid
-- M_AXIS_TVALID : Data out is valid
-- M_AXIS_TDATA : Data Out
-- M_AXIS_TLAST : Optional data out qualifier
-- M_AXIS_TREADY : Connected slave device is ready to accept data out
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity myip_v1_0 is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
end myip_v1_0;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY hw_acc
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY hw_acc to implement your coprocessor
architecture EXAMPLE of myip_v1_0 is
-- Total number of input data.
constant KEY_LENGTH : natural := 4;
constant PIPELINE_LENGTH : natural := 69;
type STATE_TYPE is (IDLE, READ_KEY, EXPAND_KEY, STALL, DECRYPT);
signal state : STATE_TYPE;
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to KEY_LENGTH - 1;
component AES128_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY_TO_DECRYPT : out STD_LOGIC;
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal ENABLE : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
signal READY_TO_DECRYPT : STD_LOGIC := '0';
signal decrypt_cnt : natural range 0 to PIPELINE_LENGTH - 1;
signal stall_cycles : natural range 0 to 2 := 2;
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's hw_acc.c file
RESET <= not ARESETN; --AXIS reset is active low
M_AXIS_TLAST <= '0'; --Unused
aes: AES128_V1 port map( CLK => ACLK,
RESET => RESET,
ENABLE => ENABLE,
READY_TO_DECRYPT => READY_TO_DECRYPT,
WORD_IN => S_AXIS_TDATA,
WORD_OUT => M_AXIS_TDATA);
--Pro: The pipeline will not be corrupted if a clock cycle is skipped since it is active only when read and write are available.
--Con: The pipeline must be manually flushed.
ENABLE <= '0' when (state = IDLE) else
'1' when (state = EXPAND_KEY or state = STALL) else
S_AXIS_TVALID;
S_AXIS_TREADY <= '1' when (state = READ_KEY or state = DECRYPT) else
'0';
The_SW_accelerator : process (ACLK) is
begin -- process The_SW_accelerator
M_AXIS_TVALID <= '0'; --Default case: output data is not valid
if ACLK'event and ACLK = '1' then -- Rising clock edge
if ARESETN = '0' then -- Synchronous reset (active low)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= IDLE;
nr_of_reads <= KEY_LENGTH - 1;
else
case state is
when IDLE =>
if (S_AXIS_TVALID = '1') then --Begin reading key
state <= READ_KEY;
nr_of_reads <= KEY_LENGTH - 1;
end if;
when READ_KEY => --Read the 4 words that comprise the key
if (S_AXIS_TVALID = '1') then
if (nr_of_reads = 0) then
state <= EXPAND_KEY;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when EXPAND_KEY => --Cycle until key expansion is done.
if (READY_TO_DECRYPT = '1') then
state <= STALL;
stall_cycles <= 2;
end if;
when STALL => --Wait for one block cycle.
if (stall_cycles = 0) then
state <= DECRYPT;
decrypt_cnt <= PIPELINE_LENGTH - 1;
else
stall_cycles <= stall_cycles - 1;
end if;
when DECRYPT =>
if (S_AXIS_TVALID = '1') then --Output is only valid if something was pushed.
if (decrypt_cnt = 0) then --The first decrypted word has exited the pipeline and everything following should be valid data.
M_AXIS_TVALID <= '1'; --The 70th rising edge AFTER the key was input marks the first valid output.
-- This signal is asserted at the 69th rising edge, to be read one cycle after.
else
decrypt_cnt <= decrypt_cnt - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2015, Olof Kraigher olof.kraigher@gmail.com
library ieee;
use ieee.std_logic_1164.all;
package axi_lite_pkg is
procedure axi_lite_read(
constant address : in std_logic_vector;
variable result : inout std_logic_vector;
signal aclk : in std_logic;
signal arready : in std_logic;
signal arvalid : out std_logic;
signal araddr : out std_logic_vector;
signal rready : out std_logic;
signal rvalid : in std_logic;
signal rdata : in std_logic_vector;
signal rresp : in std_logic_vector);
procedure axi_lite_write(
constant address : in std_logic_vector;
constant data : in std_logic_vector;
constant stb : in std_logic_vector;
signal aclk : in std_logic;
signal awready : in std_logic;
signal awvalid : out std_logic;
signal awaddr : out std_logic_vector;
signal wready : in std_logic;
signal wvalid : out std_logic;
signal wdata : out std_logic_vector;
signal wstb : out std_logic_vector;
signal bvalid : in std_logic;
signal bready : out std_logic;
signal bresp : in std_logic_vector);
end package;
package body axi_lite_pkg is
procedure axi_lite_read(
constant address : in std_logic_vector;
variable result : inout std_logic_vector;
signal aclk : in std_logic;
signal arready : in std_logic;
signal arvalid : out std_logic;
signal araddr : out std_logic_vector;
signal rready : out std_logic;
signal rvalid : in std_logic;
signal rdata : in std_logic_vector;
signal rresp : in std_logic_vector) is
begin
araddr <= address;
arvalid <= '1';
wait until (arvalid and arready) = '1' and rising_edge(aclk);
arvalid <= '0';
rready <= '1';
wait until (rvalid and rready) = '1' and rising_edge(aclk);
rready <= '0';
result := rdata;
assert rresp = "00" report "Got non-OKAY rresp";
end;
procedure axi_lite_write(
constant address : in std_logic_vector;
constant data : in std_logic_vector;
constant stb : in std_logic_vector;
signal aclk : in std_logic;
signal awready : in std_logic;
signal awvalid : out std_logic;
signal awaddr : out std_logic_vector;
signal wready : in std_logic;
signal wvalid : out std_logic;
signal wdata : out std_logic_vector;
signal wstb : out std_logic_vector;
signal bvalid : in std_logic;
signal bready : out std_logic;
signal bresp : in std_logic_vector) is
variable w_done, aw_done : boolean := false;
begin
awaddr <= address;
wdata <= data;
wstb <= (wstb'range => '1');
wvalid <= '1';
awvalid <= '1';
while not (w_done and aw_done) loop
wait until ((awvalid and awready) = '1' or (wvalid and wready) = '1') and rising_edge(aclk);
if (awvalid and awready) = '1' then
awvalid <= '0';
aw_done := true;
end if;
if (wvalid and wready) = '1' then
wvalid <= '0';
w_done := true;
end if;
end loop;
bready <= '1';
wait until (bvalid and bready) = '1' and rising_edge(aclk);
bready <= '0';
assert bresp = "00" report "Got non-OKAY bresp";
end;
end package body;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_With_mem_v4
-- Module Name: McEliece_QD-Goppa_Decrypt_With_mem_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements a McEliece decryption algorithm for binary Goppa codes with
-- all necessary memories.
-- This circuit only supplies the necessary memories for mceliece_qd_goppa_decrypt_v4.
-- Because of how mceliece_qd_goppa_decrypt_v4 circuit handles the memories, it
-- is possible to implement efficiently for values of
-- number_of_polynomial_evaluator_syndrome_pipelines which are not power of 2.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 1 or greater, but only power of 2.
--
-- log2_number_of_polynomial_evaluator_syndrome_pipelines :
--
-- This is the log2 of the number_of_polynomial_evaluator_syndrome_pipelines.
-- This is ceil(log2(number_of_polynomial_evaluator_syndrome_pipelines))
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_v4_with_mem Rev 1.0
-- register_nbits Rev 1.0
-- synth_ram Rev 1.0
-- synth_double_ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mceliece_qd_goppa_decrypt_v4_with_mem is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 16;
log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
polynomial_evaluator_syndrome_pipeline_size : integer := 3;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 2048;
size_codeword : integer := 11;
number_of_errors : integer := 27;
size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 16;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 3;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load_address_mem : in STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_sel_mem : in STD_LOGIC_VECTOR(1 downto 0);
load_write_value_mem : in STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_write_enable_mem : in STD_LOGIC;
load_read_value_mem : out STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC
);
end mceliece_qd_goppa_decrypt_v4_with_mem;
architecture Behavioral of mceliece_qd_goppa_decrypt_v4_with_mem is
component register_nbits
Generic (
size : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component synth_ram
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component synth_double_ram
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component mceliece_qd_goppa_decrypt_v4
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_s : out STD_LOGIC;
write_enable_new_value_v : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end component;
signal value_h : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal address_value_h : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_L : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_codeword : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_error : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_s : STD_LOGIC;
signal write_enable_new_value_v : STD_LOGIC;
signal write_enable_new_value_sigma : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_new_value_error : STD_LOGIC;
signal write_enable_new_value_sigma_evaluated : STD_LOGIC;
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal mem_L_data_in : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_L_rw : STD_LOGIC;
signal mem_L_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_L_data_out : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_data_in : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_rw : STD_LOGIC;
signal mem_h_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_data_out : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_rw : STD_LOGIC;
signal mem_codeword_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_in_a : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_in_b : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_rw_a : STD_LOGIC;
signal mem_sigma_evaluated_rw_b : STD_LOGIC;
signal mem_sigma_evaluated_address_a : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_address_b : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_out_a : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_out_b : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_rw : STD_LOGIC;
signal mem_message_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_rw : STD_LOGIC;
signal mem_error_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_syndrome_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_rw_a : STD_LOGIC;
signal mem_syndrome_rw_b : STD_LOGIC;
signal mem_syndrome_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_syndrome_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_syndrome_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_rw_a : STD_LOGIC;
signal mem_F_rw_b : STD_LOGIC;
signal mem_F_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_F_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_F_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_rw_a : STD_LOGIC;
signal mem_B_rw_b : STD_LOGIC;
signal mem_B_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_B_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_B_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_rw_a : STD_LOGIC;
signal mem_sigma_rw_b : STD_LOGIC;
signal mem_sigma_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_sigma_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_sigma_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rst_q : STD_LOGIC;
signal reg_load_address_mem_q : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_load_sel_mem_q : STD_LOGIC_VECTOR(1 downto 0);
signal reg_load_write_value_mem_q : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_load_write_enable_mem_q : STD_LOGIC;
signal reg_load_read_value_mem_d : STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_syndrome_generation_finalized_d : STD_LOGIC;
signal reg_key_equation_finalized_d : STD_LOGIC;
signal reg_decryption_finalized_d : STD_LOGIC;
begin
reg_rst : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => rst,
clk => clk,
ce => '1',
q(0) => reg_rst_q
);
reg_load_address_mem : register_nbits
Generic Map(
size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => load_address_mem,
clk => clk,
ce => '1',
q => reg_load_address_mem_q
);
reg_load_sel_mem : register_nbits
Generic Map(
size => 2
)
Port Map(
d => load_sel_mem,
clk => clk,
ce => '1',
q => reg_load_sel_mem_q
);
reg_load_write_value_mem : register_nbits
Generic Map(
size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => load_write_value_mem,
clk => clk,
ce => '1',
q => reg_load_write_value_mem_q
);
reg_load_write_enable_mem : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => load_write_enable_mem,
clk => clk,
ce => '1',
q(0) => reg_load_write_enable_mem_q
);
reg_load_read_value_mem : register_nbits
Generic Map(
size => 2*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => reg_load_read_value_mem_d,
clk => clk,
ce => '1',
q => load_read_value_mem
);
reg_syndrome_generation_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_syndrome_generation_finalized_d,
clk => clk,
ce => '1',
q(0) => syndrome_generation_finalized
);
reg_key_equation_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_key_equation_finalized_d,
clk => clk,
ce => '1',
q(0) => key_equation_finalized
);
reg_decryption_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_decryption_finalized_d,
clk => clk,
ce => '1',
q(0) => decryption_finalized
);
mceliece : mceliece_qd_goppa_decrypt_v4
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => reg_rst_q,
value_h => value_h,
value_L => value_L,
value_syndrome => value_syndrome,
value_codeword => value_codeword,
value_s => value_s,
value_v => value_v,
value_sigma => value_sigma,
value_sigma_evaluated => value_sigma_evaluated,
syndrome_generation_finalized => reg_syndrome_generation_finalized_d,
key_equation_finalized => reg_key_equation_finalized_d,
decryption_finalized => reg_decryption_finalized_d,
address_value_h => address_value_h,
address_value_L => address_value_L,
address_value_syndrome => address_value_syndrome,
address_value_codeword => address_value_codeword,
address_value_s => address_value_s,
address_value_v => address_value_v,
address_value_sigma => address_value_sigma,
address_value_sigma_evaluated => address_value_sigma_evaluated,
new_value_syndrome => new_value_syndrome,
new_value_s => new_value_s,
new_value_v => new_value_v,
new_value_sigma => new_value_sigma,
new_value_message => new_value_message,
new_value_error => new_value_error,
new_value_sigma_evaluated => new_value_sigma_evaluated,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_s => write_enable_new_value_s,
write_enable_new_value_v => write_enable_new_value_v,
write_enable_new_value_sigma => write_enable_new_value_sigma,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_new_value_error => write_enable_new_value_error,
write_enable_new_value_sigma_evaluated => write_enable_new_value_sigma_evaluated,
address_new_value_syndrome => address_new_value_syndrome,
address_new_value_s => address_new_value_s,
address_new_value_v => address_new_value_v,
address_new_value_sigma => address_new_value_sigma,
address_new_value_message => address_new_value_message,
address_new_value_error => address_new_value_error,
address_new_value_sigma_evaluated => address_new_value_sigma_evaluated
);
mem_L : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_L_data_in,
rw => mem_L_rw,
clk => clk,
address => mem_L_address,
data_out => mem_L_data_out
);
mem_h : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_h_data_in,
rw => mem_h_rw,
clk => clk,
address => mem_h_address,
data_out => mem_h_data_out
);
mem_codeword : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_codeword_data_in,
rw => mem_codeword_rw,
clk => clk,
address => mem_codeword_address,
data_out => mem_codeword_data_out
);
mem_sigma_evaluated : synth_double_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in_a => mem_sigma_evaluated_data_in_a,
data_in_b => mem_sigma_evaluated_data_in_b,
rw_a => mem_sigma_evaluated_rw_a,
rw_b => mem_sigma_evaluated_rw_b,
clk => clk,
address_a => mem_sigma_evaluated_address_a,
address_b => mem_sigma_evaluated_address_b,
data_out_a => mem_sigma_evaluated_data_out_a,
data_out_b => mem_sigma_evaluated_data_out_b
);
mem_message : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_message_data_in,
rw => mem_message_rw,
clk => clk,
address => mem_message_address,
data_out => mem_message_data_out
);
mem_error : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_error_data_in,
rw => mem_error_rw,
clk => clk,
address => mem_error_address,
data_out => mem_error_data_out
);
mem_syndrome : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_syndrome_data_in_a,
data_in_b => mem_syndrome_data_in_b,
rw_a => mem_syndrome_rw_a,
rw_b => mem_syndrome_rw_b,
clk => clk,
address_a => mem_syndrome_address_a,
address_b => mem_syndrome_address_b,
data_out_a => mem_syndrome_data_out_a,
data_out_b => mem_syndrome_data_out_b
);
mem_F : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_F_data_in_a,
data_in_b => mem_F_data_in_b,
rw_a => mem_F_rw_a,
rw_b => mem_F_rw_b,
clk => clk,
address_a => mem_F_address_a,
address_b => mem_F_address_b,
data_out_a => mem_F_data_out_a,
data_out_b => mem_F_data_out_b
);
mem_B : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_B_data_in_a,
data_in_b => mem_B_data_in_b,
rw_a => mem_B_rw_a,
rw_b => mem_B_rw_b,
clk => clk,
address_a => mem_B_address_a,
address_b => mem_B_address_b,
data_out_a => mem_B_data_out_a,
data_out_b => mem_B_data_out_b
);
mem_sigma : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_sigma_data_in_a,
data_in_b => mem_sigma_data_in_b,
rw_a => mem_sigma_rw_a,
rw_b => mem_sigma_rw_b,
clk => clk,
address_a => mem_sigma_address_a,
address_b => mem_sigma_address_b,
data_out_a => mem_sigma_data_out_a,
data_out_b => mem_sigma_data_out_b
);
value_h <= mem_h_data_out;
value_L <= mem_L_data_out;
value_codeword <= mem_codeword_data_out;
value_syndrome <= mem_syndrome_data_out_a;
value_s <= mem_F_data_out_a;
value_v <= mem_B_data_out_a;
value_sigma <= mem_sigma_data_out_a;
value_sigma_evaluated <= mem_sigma_evaluated_data_out_a;
mem_L_data_in <= reg_load_write_value_mem_q;
mem_L_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "00") else
'0';
mem_L_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "00") else
address_value_L((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_h_data_in <= reg_load_write_value_mem_q;
mem_h_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "01") else
'0';
mem_h_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "01") else
address_value_h((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_codeword_data_in <= reg_load_write_value_mem_q((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
mem_codeword_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "10") else
'0';
mem_codeword_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "10") else
address_value_codeword((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_sigma_evaluated_data_in_a <= (others => '0');
mem_sigma_evaluated_data_in_b <= new_value_sigma_evaluated;
mem_sigma_evaluated_rw_a <= '0';
mem_sigma_evaluated_rw_b <= write_enable_new_value_sigma_evaluated;
mem_sigma_evaluated_address_a <= address_value_sigma_evaluated((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_sigma_evaluated_address_b <= address_new_value_sigma_evaluated((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_message_data_in <= new_value_message;
mem_message_rw <= '0' when reg_rst_q = '1' else
write_enable_new_value_message;
mem_message_address <= reg_load_address_mem_q when reg_rst_q = '1' else
address_new_value_message((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_error_data_in <= new_value_error;
mem_error_rw <= '0' when reg_rst_q = '1' else
write_enable_new_value_error;
mem_error_address <= reg_load_address_mem_q when reg_rst_q = '1' else
address_new_value_error((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_syndrome_data_in_a <= (others => '0');
mem_syndrome_data_in_b <= new_value_syndrome;
mem_syndrome_rw_a <= '0';
mem_syndrome_rw_b <= write_enable_new_value_syndrome;
mem_syndrome_address_a <= address_value_syndrome;
mem_syndrome_address_b <= address_new_value_syndrome;
mem_F_data_in_a <= (others => '0');
mem_F_data_in_b <= new_value_s;
mem_F_rw_a <= '0';
mem_F_rw_b <= write_enable_new_value_s;
mem_F_address_a <= address_value_s;
mem_F_address_b <= address_new_value_s;
mem_B_data_in_a <= (others => '0');
mem_B_data_in_b <= new_value_v;
mem_B_rw_a <= '0';
mem_B_rw_b <= write_enable_new_value_v;
mem_B_address_a <= address_value_v;
mem_B_address_b <= address_new_value_v;
mem_sigma_data_in_a <= (others => '0');
mem_sigma_data_in_b <= new_value_sigma;
mem_sigma_rw_a <= '0';
mem_sigma_rw_b <= write_enable_new_value_sigma;
mem_sigma_address_a <= address_value_sigma;
mem_sigma_address_b <= address_new_value_sigma;
reg_load_read_value_mem_d <= mem_error_data_out & mem_message_data_out;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (clk : std_logic);
end entity issue;
architecture beh of issue is
begin
--psl default clock is rising_edge (clk);
--psl assert (always (true or true));
end architecture;
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Thu Nov 19 17:38:29 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
reset : in STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component design_1;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal cellular_ram_dq_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
begin
cellular_ram_dq_iobuf_0: component IOBUF
port map (
I => cellular_ram_dq_o_0(0),
IO => cellular_ram_dq_io(0),
O => cellular_ram_dq_i_0(0),
T => cellular_ram_dq_t_0(0)
);
cellular_ram_dq_iobuf_1: component IOBUF
port map (
I => cellular_ram_dq_o_1(1),
IO => cellular_ram_dq_io(1),
O => cellular_ram_dq_i_1(1),
T => cellular_ram_dq_t_1(1)
);
cellular_ram_dq_iobuf_10: component IOBUF
port map (
I => cellular_ram_dq_o_10(10),
IO => cellular_ram_dq_io(10),
O => cellular_ram_dq_i_10(10),
T => cellular_ram_dq_t_10(10)
);
cellular_ram_dq_iobuf_11: component IOBUF
port map (
I => cellular_ram_dq_o_11(11),
IO => cellular_ram_dq_io(11),
O => cellular_ram_dq_i_11(11),
T => cellular_ram_dq_t_11(11)
);
cellular_ram_dq_iobuf_12: component IOBUF
port map (
I => cellular_ram_dq_o_12(12),
IO => cellular_ram_dq_io(12),
O => cellular_ram_dq_i_12(12),
T => cellular_ram_dq_t_12(12)
);
cellular_ram_dq_iobuf_13: component IOBUF
port map (
I => cellular_ram_dq_o_13(13),
IO => cellular_ram_dq_io(13),
O => cellular_ram_dq_i_13(13),
T => cellular_ram_dq_t_13(13)
);
cellular_ram_dq_iobuf_14: component IOBUF
port map (
I => cellular_ram_dq_o_14(14),
IO => cellular_ram_dq_io(14),
O => cellular_ram_dq_i_14(14),
T => cellular_ram_dq_t_14(14)
);
cellular_ram_dq_iobuf_15: component IOBUF
port map (
I => cellular_ram_dq_o_15(15),
IO => cellular_ram_dq_io(15),
O => cellular_ram_dq_i_15(15),
T => cellular_ram_dq_t_15(15)
);
cellular_ram_dq_iobuf_2: component IOBUF
port map (
I => cellular_ram_dq_o_2(2),
IO => cellular_ram_dq_io(2),
O => cellular_ram_dq_i_2(2),
T => cellular_ram_dq_t_2(2)
);
cellular_ram_dq_iobuf_3: component IOBUF
port map (
I => cellular_ram_dq_o_3(3),
IO => cellular_ram_dq_io(3),
O => cellular_ram_dq_i_3(3),
T => cellular_ram_dq_t_3(3)
);
cellular_ram_dq_iobuf_4: component IOBUF
port map (
I => cellular_ram_dq_o_4(4),
IO => cellular_ram_dq_io(4),
O => cellular_ram_dq_i_4(4),
T => cellular_ram_dq_t_4(4)
);
cellular_ram_dq_iobuf_5: component IOBUF
port map (
I => cellular_ram_dq_o_5(5),
IO => cellular_ram_dq_io(5),
O => cellular_ram_dq_i_5(5),
T => cellular_ram_dq_t_5(5)
);
cellular_ram_dq_iobuf_6: component IOBUF
port map (
I => cellular_ram_dq_o_6(6),
IO => cellular_ram_dq_io(6),
O => cellular_ram_dq_i_6(6),
T => cellular_ram_dq_t_6(6)
);
cellular_ram_dq_iobuf_7: component IOBUF
port map (
I => cellular_ram_dq_o_7(7),
IO => cellular_ram_dq_io(7),
O => cellular_ram_dq_i_7(7),
T => cellular_ram_dq_t_7(7)
);
cellular_ram_dq_iobuf_8: component IOBUF
port map (
I => cellular_ram_dq_o_8(8),
IO => cellular_ram_dq_io(8),
O => cellular_ram_dq_i_8(8),
T => cellular_ram_dq_t_8(8)
);
cellular_ram_dq_iobuf_9: component IOBUF
port map (
I => cellular_ram_dq_o_9(9),
IO => cellular_ram_dq_io(9),
O => cellular_ram_dq_i_9(9),
T => cellular_ram_dq_t_9(9)
);
design_1_i: component design_1
port map (
cellular_ram_addr(22 downto 0) => cellular_ram_addr(22 downto 0),
cellular_ram_adv_ldn => cellular_ram_adv_ldn,
cellular_ram_ben(1 downto 0) => cellular_ram_ben(1 downto 0),
cellular_ram_ce_n => cellular_ram_ce_n,
cellular_ram_cre => cellular_ram_cre,
cellular_ram_dq_i(15) => cellular_ram_dq_i_15(15),
cellular_ram_dq_i(14) => cellular_ram_dq_i_14(14),
cellular_ram_dq_i(13) => cellular_ram_dq_i_13(13),
cellular_ram_dq_i(12) => cellular_ram_dq_i_12(12),
cellular_ram_dq_i(11) => cellular_ram_dq_i_11(11),
cellular_ram_dq_i(10) => cellular_ram_dq_i_10(10),
cellular_ram_dq_i(9) => cellular_ram_dq_i_9(9),
cellular_ram_dq_i(8) => cellular_ram_dq_i_8(8),
cellular_ram_dq_i(7) => cellular_ram_dq_i_7(7),
cellular_ram_dq_i(6) => cellular_ram_dq_i_6(6),
cellular_ram_dq_i(5) => cellular_ram_dq_i_5(5),
cellular_ram_dq_i(4) => cellular_ram_dq_i_4(4),
cellular_ram_dq_i(3) => cellular_ram_dq_i_3(3),
cellular_ram_dq_i(2) => cellular_ram_dq_i_2(2),
cellular_ram_dq_i(1) => cellular_ram_dq_i_1(1),
cellular_ram_dq_i(0) => cellular_ram_dq_i_0(0),
cellular_ram_dq_o(15) => cellular_ram_dq_o_15(15),
cellular_ram_dq_o(14) => cellular_ram_dq_o_14(14),
cellular_ram_dq_o(13) => cellular_ram_dq_o_13(13),
cellular_ram_dq_o(12) => cellular_ram_dq_o_12(12),
cellular_ram_dq_o(11) => cellular_ram_dq_o_11(11),
cellular_ram_dq_o(10) => cellular_ram_dq_o_10(10),
cellular_ram_dq_o(9) => cellular_ram_dq_o_9(9),
cellular_ram_dq_o(8) => cellular_ram_dq_o_8(8),
cellular_ram_dq_o(7) => cellular_ram_dq_o_7(7),
cellular_ram_dq_o(6) => cellular_ram_dq_o_6(6),
cellular_ram_dq_o(5) => cellular_ram_dq_o_5(5),
cellular_ram_dq_o(4) => cellular_ram_dq_o_4(4),
cellular_ram_dq_o(3) => cellular_ram_dq_o_3(3),
cellular_ram_dq_o(2) => cellular_ram_dq_o_2(2),
cellular_ram_dq_o(1) => cellular_ram_dq_o_1(1),
cellular_ram_dq_o(0) => cellular_ram_dq_o_0(0),
cellular_ram_dq_t(15) => cellular_ram_dq_t_15(15),
cellular_ram_dq_t(14) => cellular_ram_dq_t_14(14),
cellular_ram_dq_t(13) => cellular_ram_dq_t_13(13),
cellular_ram_dq_t(12) => cellular_ram_dq_t_12(12),
cellular_ram_dq_t(11) => cellular_ram_dq_t_11(11),
cellular_ram_dq_t(10) => cellular_ram_dq_t_10(10),
cellular_ram_dq_t(9) => cellular_ram_dq_t_9(9),
cellular_ram_dq_t(8) => cellular_ram_dq_t_8(8),
cellular_ram_dq_t(7) => cellular_ram_dq_t_7(7),
cellular_ram_dq_t(6) => cellular_ram_dq_t_6(6),
cellular_ram_dq_t(5) => cellular_ram_dq_t_5(5),
cellular_ram_dq_t(4) => cellular_ram_dq_t_4(4),
cellular_ram_dq_t(3) => cellular_ram_dq_t_3(3),
cellular_ram_dq_t(2) => cellular_ram_dq_t_2(2),
cellular_ram_dq_t(1) => cellular_ram_dq_t_1(1),
cellular_ram_dq_t(0) => cellular_ram_dq_t_0(0),
cellular_ram_oen => cellular_ram_oen,
cellular_ram_wait => cellular_ram_wait,
cellular_ram_wen => cellular_ram_wen,
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_ref_clk => eth_ref_clk,
eth_rmii_crs_dv => eth_rmii_crs_dv,
eth_rmii_rx_er => eth_rmii_rx_er,
eth_rmii_rxd(1 downto 0) => eth_rmii_rxd(1 downto 0),
eth_rmii_tx_en => eth_rmii_tx_en,
eth_rmii_txd(1 downto 0) => eth_rmii_txd(1 downto 0),
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- I/D buses of the mblite
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
-- type dmem_in_type is record
-- dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
-- type imem_in_type is record
-- dat_i : std_logic_vector(CFG_dmem_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type imem_out_type is record
-- adr_o : std_logic_vector(CFG_dmem_SIZE - 1 downto 0);
-- ena_o : std_logic;
-- end record;
entity dm_simple is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000";
g_registered_out: boolean := false;
g_data_register : boolean := true;
g_mem_direct : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
disable : in std_logic := '0';
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_simple is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
-- constant c_tag_compare_width : natural := c_cachable_area_bits - c_cache_size_bits;
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
-- type t_tag_ram is record
--
-- end record;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill, reg);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => false, --true,
g_read_first_b => false, --true,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => false, --true,
g_read_first_b => false, --true,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, data_reg, disable)
begin
if g_registered_out then
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
else
dmem_o_comb.ena_i <= '1'; -- direct out, use this signal as enable output
end if;
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) and disable = '0' then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
if g_mem_direct then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end if;
if dmem_r.we_o='0' then -- was a read
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
when reg =>
dmem_o_comb.dat_i <= data_reg; -- ouch, 3rd input to 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end case;
end process;
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
r_comb: if not g_registered_out generate
dmem_o <= dmem_o_comb;
end generate;
r_reg: if g_registered_out generate
dmem_o <= dmem_o_reg;
end generate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
data_reg <= mem_i.dat_i; -- ouch, 32-bit register
dmem_r.ena_o <= '0';
if g_registered_out then
state <= idle;
elsif dmem_i.ena_o = '0' then
if g_data_register then
state <= reg;
else
report "No data register support, but it seems to be needed!"
severity error;
end if;
else
state <= idle;
end if;
end if;
when reg =>
if dmem_i.ena_o = '1' then
if d_miss = '1' then
state <= fill;
else
state <= idle;
end if;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdFilter
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
--
-- DepENDencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
ENTITY KbdFilter IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbdClk : IN STD_LOGIC;
kbdData : IN STD_LOGIC;
kbdClkF : OUT STD_LOGIC;
kbdDataF : OUT STD_LOGIC
);
END KbdFilter;
ARCHITECTURE Behavioral OF KbdFilter IS
CONSTANT FILTER_WIDTH : INTEGER := 4;
SIGNAL kbd_clkf_reg : std_logic_vector(FILTER_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL kbd_Dataf_reg : std_logic_vector(FILTER_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
BEGIN
FilterKbdClk:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
kbd_clkf_reg <= (OTHERS => '1');
kbdClkF <= '1';
ELSIF (clk = '1' and clk'Event) THEN
kbd_clkf_reg <= kbdClk & kbd_clkf_reg(FILTER_WIDTH-1 DOWNTO 1);
--clock
IF (kbd_clkf_reg = X"F") THEN
kbdClkF <= '1';
ELSIF (kbd_clkf_reg = X"0") THEN
kbdClkF <= '0';
END IF;
END IF;
END PROCESS;
FilterKbdData:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
kbd_dataf_reg <= (OTHERS => '1');
kbdDataF <= '1';
ELSIF (clk='1' and clk'Event) THEN
kbd_dataf_reg <= kbdData & kbd_dataf_reg(FILTER_WIDTH-1 DOWNTO 1);
--data
IF (kbd_dataf_reg = X"F") THEN
kbdDataF <= '1';
ELSIF (kbd_dataf_reg = X"0") THEN
kbdDataF <= '0';
END IF;
END IF;
END PROCESS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdFilter
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
--
-- DepENDencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
ENTITY KbdFilter IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbdClk : IN STD_LOGIC;
kbdData : IN STD_LOGIC;
kbdClkF : OUT STD_LOGIC;
kbdDataF : OUT STD_LOGIC
);
END KbdFilter;
ARCHITECTURE Behavioral OF KbdFilter IS
CONSTANT FILTER_WIDTH : INTEGER := 4;
SIGNAL kbd_clkf_reg : std_logic_vector(FILTER_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL kbd_Dataf_reg : std_logic_vector(FILTER_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
BEGIN
FilterKbdClk:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
kbd_clkf_reg <= (OTHERS => '1');
kbdClkF <= '1';
ELSIF (clk = '1' and clk'Event) THEN
kbd_clkf_reg <= kbdClk & kbd_clkf_reg(FILTER_WIDTH-1 DOWNTO 1);
--clock
IF (kbd_clkf_reg = X"F") THEN
kbdClkF <= '1';
ELSIF (kbd_clkf_reg = X"0") THEN
kbdClkF <= '0';
END IF;
END IF;
END PROCESS;
FilterKbdData:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
kbd_dataf_reg <= (OTHERS => '1');
kbdDataF <= '1';
ELSIF (clk='1' and clk'Event) THEN
kbd_dataf_reg <= kbdData & kbd_dataf_reg(FILTER_WIDTH-1 DOWNTO 1);
--data
IF (kbd_dataf_reg = X"F") THEN
kbdDataF <= '1';
ELSIF (kbd_dataf_reg = X"0") THEN
kbdDataF <= '0';
END IF;
END IF;
END PROCESS;
END Behavioral;
|
--------------------------------------------------------------
------------------------------------------------------------
-- Addsub.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Addsub_Unit is
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end entity Addsub_Unit;
architecture Behavior of Addsub_Unit is
begin
process(select_add_sub,a,b)
begin
case select_add_sub is
when '0'=>
result<=a+b;
when '1'=>
result<=a-b;
when others=>
result<=(others=>'Z');
end case;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Control_unit.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- dec3to8.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
when "001" => Y <= "01000000";
when "010" => Y <= "00100000";
when "011" => Y <= "00010000";
when "100" => Y <= "00001000";
when "101" => Y <= "00000100";
when "110" => Y <= "00000010";
when "111" => Y <= "00000001";
when others=> null;
end case;
else
Y <= "00000000";
end if;
end process;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- multiplexers.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplexers is
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end entity multiplexers;
architecture choice of multiplexers is
signal mid_choice:std_logic_vector(N+2-1 downto 0);
begin
mid_choice<=control_reg&control_GDi;--0~7|G|Din--
-- out_to_bus<= DataIn when control_GDi(0)='1'
-- else reg_G when control_GDi(1)='1'
-- else reg0 when control_reg(0)='1'
-- else reg1 when control_reg(1)='1'
-- ;--else (others=>'Z');
process(mid_choice,reg0,reg1,reg_G,DataIn)
begin
case mid_choice is
when "1000"=>
out_to_bus<=reg0;
when "0100"=>
out_to_bus<=reg1;
when "0010"=>
out_to_bus<=reg_G;
when others=>
--when "0001"=>
out_to_bus<=DataIn;
--when others=>
end case;
end process;
end architecture choice;
--------------------------------------------------------------
------------------------------------------------------------
-- regn.vhd
------------------------------------------------------------
--------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock = '1' Then
If Rin = '1' Then
Q <= R;
End If;
End If;
End Process;
End Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- upcount.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity upcount is
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end upcount;
architecture Behavior of upcount is
signal Count : STD_LOGIC_VECTOR(1 downto 0);
begin
process (Clock)
begin
if (Clock'EVENT and Clock = '1') then
if Clear = '1' then
Count <= "00";
else
Count <= Count + 1;
end if;
end if;
end process;
Q <= Count;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;
architecture Behavior of View is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
component regn --usual register
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
end component;
component upcount
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component Addsub_Unit
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end component;
component multiplexers
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end component;
component Control_unit
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
signal R0,R1,A,G:regwidth;
---------------------------------
--Control_unit output
---------------------------------
--IR control_unit
signal IRset: std_logic_vector(0 to 8);--instruction length =9 bits
signal IRin: std_logic;
--multiplexer
signal Riout: std_logic_vector(0 to 7);
signal Gout,DINout: std_logic;
--Register Data in
signal Rin: std_logic_vector(0 to 7);
signal Ain,Gin: std_logic;
--ALU control_unit
signal AddSub: std_logic;
--Counter state
signal Tstep_Q: std_logic_vector(1 downto 0);
signal Clear: std_logic;
--singular control signal
--signal Run,Resetn: std_logic;
--signal Done: std_logic;
-------------------------------------
signal ALU_result:std_logic_vector(15 downto 0);
begin
Tstep : upcount port map(Clear, Clock , Tstep_Q);
-- Din, RinControl,Clk,ROut
reg_0 : regn port map(BusWires, Rin(0), Clock, R0);
reg_1 : regn port map(BusWires, Rin(1), Clock, R1);
reg_A : regn port map(BusWires, Ain, Clock, A );
reg_G : regn port map(ALU_result, Gin, Clock, G );
reg_IR: regn generic map(9) port map(DIN(15 downto 7),IRin,Clock,IRset);
ALU_Unit:
Addsub_Unit port map(A, BusWires,AddSub, ALU_result);
--instantiate other registers and the adder/subtracter unit
Multiplexer_Unit:
multiplexers generic map(N=>2,n_multi=>16) port map(DIN,G,R0,R1,Riout(0 to 1) ,Gout&DINout,BusWires);
--define the bus
--Control_unit
--------------------
Control_unit_label:Control_unit port map(
IRset,--instruction length =9 bits
IRin,
--multiplexer
Riout,
Gout,DINout,
--Register Data in
Rin,
Ain,Gin,
--ALU control_unit
AddSub,
--Counter state
Tstep_Q,
Clear,
--singular control signal
Run,Resetn,
Done
);
--------------------
end architecture Behavior;
|
-------------------------------------------------------------------------------
--
-- Testbench for the
-- GCpad controller core
--
-- $Id: tb.vhd,v 1.4 2004-10-10 20:19:49 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
use work.gcpad_pack.all;
use work.gcpad_comp.gcpad_basic;
use work.gcpad_comp.gcpad_full;
architecture behav of tb is
-----------------------------------------------------------------------------
-- Some known commands for the GC controller
-----------------------------------------------------------------------------
constant cmd_get_id_c : std_logic_vector(7 downto 0) := "00000000";
constant cmd_poll_c : std_logic_vector(7 downto 0) := "01000000";
component gcpad_mod
generic (
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
pad_data_io : inout std_logic;
rx_data_i : in std_logic_vector(63 downto 0)
);
end component;
constant period_c : time := 100 ns;
constant reset_level_c : natural := 0;
constant clocks_per_1us_c : natural := 10;
signal clk_s : std_logic;
signal reset_s : std_logic;
-- signals for basic gcpad
signal stimuli_1_end_s : boolean;
signal pad_data_1_s : std_logic;
signal buttons_1_s : std_logic_vector(64 downto 0);
signal pad_request_1_s : std_logic;
signal pad_avail_1_s : std_logic;
signal pad_model_data_1_s : std_logic_vector(63 downto 0);
-- signals for full gcpad
signal stimuli_2_end_s : boolean;
signal pad_data_2_s : std_logic;
signal pad_request_2_s : std_logic;
signal pad_avail_2_s : std_logic;
signal pad_timeout_2_s : std_logic;
signal tx_size_2_s : std_logic_vector( 1 downto 0);
signal tx_command_2_s : std_logic_vector(23 downto 0);
signal rx_size_2_s : std_logic_vector( 3 downto 0);
signal rx_data_2_s : std_logic_vector(63 downto 0);
signal pad_model_data_2_s : std_logic_vector(63 downto 0);
begin
basic_b : gcpad_basic
generic map (
reset_level_g => reset_level_c,
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_1_s,
pad_avail_o => pad_avail_1_s,
pad_data_io => pad_data_1_s,
but_a_o => buttons_1_s(56),
but_b_o => buttons_1_s(57),
but_x_o => buttons_1_s(58),
but_y_o => buttons_1_s(59),
but_z_o => buttons_1_s(52),
but_start_o => buttons_1_s(60),
but_tl_o => buttons_1_s(54),
but_tr_o => buttons_1_s(53),
but_left_o => buttons_1_s(48),
but_right_o => buttons_1_s(49),
but_up_o => buttons_1_s(51),
but_down_o => buttons_1_s(50),
ana_joy_x_o => buttons_1_s(47 downto 40),
ana_joy_y_o => buttons_1_s(39 downto 32),
ana_c_x_o => buttons_1_s(31 downto 24),
ana_c_y_o => buttons_1_s(23 downto 16),
ana_l_o => buttons_1_s(15 downto 8),
ana_r_o => buttons_1_s( 7 downto 0)
);
buttons_1_s(64) <= '0';
buttons_1_s(63 downto 61) <= (others => '0');
buttons_1_s(55) <= '1';
full_b: gcpad_full
generic map (
reset_level_g => reset_level_c,
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_2_s,
pad_avail_o => pad_avail_2_s,
pad_timeout_o => pad_timeout_2_s,
tx_size_i => tx_size_2_s,
tx_command_i => tx_command_2_s,
rx_size_i => rx_size_2_s,
rx_data_o => rx_data_2_s,
pad_data_io => pad_data_2_s
);
pad_1 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_1_s,
rx_data_i => pad_model_data_1_s
);
-----------------------------------------------------------------------------
-- Process stimuli_pad_1
--
-- Executes test stimuli with Pad 1, the gcpad_basic flavour.
--
stimuli_pad_1: process
---------------------------------------------------------------------------
-- Procedure poll_pad
--
-- Requests the status of Pad 1 and checks the received data.
--
procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
pad_model_data_1_s <= packet;
-- send request;
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_1_s <= '0';
wait for 10 * 40 * period_c;
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
-- check result
for i in 0 to packet'high loop
assert packet(i) = buttons_1_s(i)
report "Button mismatch on Pad 1!"
severity error;
end loop;
end poll_pad;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad
--
-- Generates a timeout in gcpad_basic by disturbing the communication.
--
procedure timeout_gcpad is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- send request;
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_1_s <= '0';
wait for 2 * period_c;
-- disturb communication
pad_data_1_s <= 'X';
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
pad_data_1_s <= 'H';
wait for 10 * period_c;
end timeout_gcpad;
--
---------------------------------------------------------------------------
begin
stimuli_1_end_s <= false;
pad_data_1_s <= 'H';
pad_request_1_s <= '0';
pad_model_data_1_s <= (others => '0');
wait until reset_s = '1';
wait for period_c * 4;
timeout_gcpad;
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
wait for clocks_per_1us_c * 100 * period_c;
poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111");
poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010");
poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001");
wait for period_c * 2*40;
stimuli_1_end_s <= true;
wait;
end process stimuli_pad_1;
--
-----------------------------------------------------------------------------
pad_2 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_2_s,
rx_data_i => pad_model_data_2_s
);
-----------------------------------------------------------------------------
-- Process stimuli_pad_2
--
-- Executes test stimuli with Pad 2, the gcpad_full flavour.
--
stimuli_pad_2: process
---------------------------------------------------------------------------
-- Procedure issue_command
--
-- Sets the transmitter command for Pad 2 and starts the request.
--
procedure issue_command(cmd : in std_logic_vector(23 downto 0);
size : in std_logic_vector( 1 downto 0)) is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
tx_command_2_s <= cmd;
tx_size_2_s <= size;
-- send request;
pad_request_2_s <= '1';
wait for 1 * period_c;
pad_request_2_s <= '0';
end issue_command;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure poll_pad
--
-- Requests the status of Pad 2 and checks the received data.
--
procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- set up model answer
pad_model_data_2_s <= packet;
-- set expected number of bytes for gcpad_full
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_poll_c;
cmd_v(15 downto 0) := "0000001100000010";
issue_command(cmd => cmd_v,
size => "11");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '0'
report "Timout signalled on Pad 2 during status polling!"
severity error;
-- check result
for i in 0 to packet'high loop
assert packet(i) = rx_data_2_s(i)
report "Data mismatch on Pad 2!"
severity error;
end loop;
end poll_pad;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad_x
--
-- Generates a timeout in gcpad_full by disturbing the communication.
--
procedure timeout_gcpad_x is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
pad_model_data_2_s <= (others => '0');
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_poll_c;
cmd_v(15 downto 0) := "0000001100000010";
issue_command(cmd => cmd_v,
size => "11");
-- disturb communication
pad_data_2_s <= 'X';
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
pad_data_2_s <= 'H';
wait for 10 * period_c;
assert pad_timeout_2_s = '1'
report "No timeout indicated on Pad 2 when communication has been disturbed!"
severity error;
end timeout_gcpad_x;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad_short
--
-- Generates a timeout in gcpad_full by requesting too many bytes for
-- a "get id" command.
--
procedure timeout_gcpad_short is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- expect too many number of bytes
-- command is "get id", will yield 3 bytes, but 8 bytes are requested
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_get_id_c;
cmd_v(15 downto 0) := (others => '1');
issue_command(cmd => cmd_v,
size => "01");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '1'
report "No timout indicated on Pad 2 when too many bytes requested!"
severity error;
end timeout_gcpad_short;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure get_id
--
-- Requests the ID information from the GC controller model.
--
procedure get_id is
variable cmd_v : std_logic_vector(23 downto 0);
constant id_c : std_logic_vector(23 downto 0) := "000010010000000000000000";
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
rx_size_2_s <= "0011";
cmd_v(23 downto 16) := cmd_get_id_c;
cmd_v(15 downto 0) := (others => '1');
issue_command(cmd => cmd_v,
size => "01");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '0'
report "Timout signalled on Pad 2 during get id!"
severity error;
-- check result
for i in 0 to id_c'high loop
assert id_c(i) = rx_data_2_s(i)
report "ID mismatch on Pad 2!"
severity error;
end loop;
end get_id;
--
---------------------------------------------------------------------------
begin
stimuli_2_end_s <= false;
pad_data_2_s <= 'H';
pad_request_2_s <= '0';
tx_size_2_s <= (others => '0');
tx_command_2_s <= (others => '0');
rx_size_2_s <= (others => '0');
pad_model_data_2_s <= (others => '0');
wait until reset_s = '1';
wait for period_c * 4;
get_id;
timeout_gcpad_x;
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
wait for clocks_per_1us_c * 100 * period_c;
poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111");
timeout_gcpad_short;
poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010");
poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001");
wait for period_c * 2*40;
stimuli_2_end_s <= true;
wait;
end process stimuli_pad_2;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End of simulation detection
-----------------------------------------------------------------------------
eos: process (stimuli_1_end_s, stimuli_2_end_s)
begin
if stimuli_1_end_s and stimuli_2_end_s then
assert false
report "End of simulation reached."
severity failure;
end if;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/10/10 17:27:44 arniml
-- added second pad
-- introduced testbench model for GC controller
--
-- Revision 1.2 2004/10/09 17:05:59 arniml
-- delay assertion of request signal by real time (instead of delta cycles)
--
-- Revision 1.1 2004/10/07 21:24:06 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_CLKSYS <= I_CLK50; -- use 50 MHz clock
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
-- $Id: sys_tst_snhumanio_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_tb IS
END ENTITY;
ARCHITECTURE fifo_arch OF fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo_synth
fifo_synth_inst:fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 29
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY system_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END system_xlconstant_0_0;
ARCHITECTURE system_xlconstant_0_0_arch OF system_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1",
CONST_WIDTH => 1
)
PORT MAP (
dout => dout
);
END system_xlconstant_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY system_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END system_xlconstant_0_0;
ARCHITECTURE system_xlconstant_0_0_arch OF system_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1",
CONST_WIDTH => 1
)
PORT MAP (
dout => dout
);
END system_xlconstant_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY system_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END system_xlconstant_0_0;
ARCHITECTURE system_xlconstant_0_0_arch OF system_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1",
CONST_WIDTH => 1
)
PORT MAP (
dout => dout
);
END system_xlconstant_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY system_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END system_xlconstant_0_0;
ARCHITECTURE system_xlconstant_0_0_arch OF system_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1",
CONST_WIDTH => 1
)
PORT MAP (
dout => dout
);
END system_xlconstant_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when(rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when(rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity sl2 is
port(
a: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end entity;
architecture bh of sl2 is
begin
process(a)
begin
y <= a(29 downto 0) & "00";
end process;
end bh;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity sl2 is
port(
a: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end entity;
architecture bh of sl2 is
begin
process(a)
begin
y <= a(29 downto 0) & "00";
end process;
end bh;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity sl2 is
port(
a: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end entity;
architecture bh of sl2 is
begin
process(a)
begin
y <= a(29 downto 0) & "00";
end process;
end bh;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0_15;
USE axi_timer_v2_0_15.axi_timer;
ENTITY zqynq_lab_1_design_axi_timer_0_1 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END zqynq_lab_1_design_axi_timer_0_1;
ARCHITECTURE zqynq_lab_1_design_axi_timer_0_1_arch OF zqynq_lab_1_design_axi_timer_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "axi_timer,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_timer_0_1_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_timer_0_1_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END zqynq_lab_1_design_axi_timer_0_1_arch;
|
-- control signals for HF-RISCV
--
-- alu_op: alu_src1: mem_write: jump:
-- 0000 -> and 0 -> r[rs1] 00 -> no mem write 00 -> no jump
-- 0001 -> or 1 -> pc_last2 01 -> sb 01 -> don't care
-- 0010 -> xor 10 -> sh 10 -> jal
-- 0011 -> don't care alu_src2: 11 -> sw 11 -> jalr
-- 0100 -> add 000 -> imm_u
-- 0101 -> sub 001 -> imm_i mem_read: branch:
-- 0110 -> lui, jal, jalr 010 -> imm_s 00 -> no mem read 000 -> no branch
-- 0111 -> slt 011 -> pc 01 -> lb 001 -> beq
-- 1000 -> sltu 100 -> rs2 10 -> lh 010 -> bne
-- 1001 -> sll 101 -> r[rs2] 11 -> lw 011 -> blt
-- 1010 -> srl 110 -> don't care 100 -> bge
-- 1011 -> sra 111 -> don't care 101 -> bltu
-- 1100 -> mul 110 -> bgeu
-- 1101 -> mulh reg_write: sig_read: 111 -> system
-- 1110 -> mulhsu 0 -> no write 0 -> unsigned
-- 1111 -> mulhu 1 -> write register 1 -> signed
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port ( opcode: in std_logic_vector(6 downto 0);
funct3: in std_logic_vector(2 downto 0);
funct7: in std_logic_vector(6 downto 0);
reg_write: out std_logic;
alu_src1: out std_logic;
alu_src2: out std_logic_vector(2 downto 0);
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
sig_read: out std_logic
);
end control;
architecture arch_control of control is
begin
process(opcode, funct3, funct7)
begin
case opcode is -- load immediate / jumps
when "0110111" => -- LUI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0110";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0010111" => -- AUIPC
reg_write <= '1';
alu_src1 <= '1';
alu_src2 <= "000";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1101111" => -- JAL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "10";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100111" => -- JALR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "11";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100011" => -- branches
case funct3 is
when "000" => -- BEQ
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "001";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- BNE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "010";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- BLT
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "011";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" => -- BGE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "100";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- BLTU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "101";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- BGEU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "110";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0000011" => -- loads
case funct3 is
when "000" => -- LB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '1';
when "001" => -- LH
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '1';
when "010" => -- LW
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "11";
sig_read <= '1';
when "100" => -- LBU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '0';
when "101" => -- LHU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0100011" => -- stores
case funct3 is
when "000" => -- SB
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "01";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SH
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "10";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SW
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "11";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0010011" => -- imm computation
case funct3 is
when "000" => -- ADDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SLTI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "011" => -- SLTIU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- XORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- ORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- ANDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SLLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRAI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1011";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0110011" => -- computation
case funct3 is
when "000" =>
case funct7 is
when "0000000" => -- ADD
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SUB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0000001" => -- MUL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "001" =>
case funct7 is
when "0000001" => -- MULH
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1101";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "010" =>
case funct7 is
when "0000001" => -- MULHSU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1110";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLT
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "011" =>
case funct7 is
when "0000001" => -- MULHU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLTU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "100" => -- XOR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRA
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1011";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "110" => -- OR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- AND
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "1110011" => -- SYSTEM
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "111";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
end process;
end arch_control;
|
-- signextender whichs preserves the msb
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SignExtender IS
PORT (
se_in : IN STD_logic_vector(15 DOWNTO 0);
se_out : OUT STD_logic_vector(31 DOWNTO 0)
);
END SignExtender;
ARCHITECTURE Behavioral OF SignExtender IS
BEGIN
-- concat hex 0000 with se_in if msb is 0 else ...
se_out <= x"0000" & se_in WHEN se_in(15) = '0'
ELSE
x"FFFF" & se_in;
END Behavioral; |
-------------------------------------------------------------------------------
-- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- gen_sync_bram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
--
-- Description:
-- Code to infer asynchronous dual port bram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Async_FIFO_BRAM is
generic (
WordSize : integer := 8;
MemSize : integer := 16;
Protect : boolean := false
);
port (
Reset : in std_logic;
-- Clock region WrClk
WrClk : in std_logic;
WE : in std_logic;
DataIn : in std_logic_vector(WordSize-1 downto 0);
Full : out std_logic;
-- Clock region RdClk
RdClk : in std_logic;
RD : in std_logic;
DataOut : out std_logic_vector(WordSize-1 downto 0);
Exists : out std_logic
);
end entity Async_FIFO_BRAM;
architecture IMP of Async_FIFO_BRAM is
attribute ram_style : string;
function Bin2Gray(constant bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
gray(bin'high) := bin(bin'high);
for I in bin'high - 1 downto bin'low loop
gray(I) := bin(I + 1) xor bin(I);
end loop;
return gray;
end function Bin2Gray;
function Log2(x : integer) return integer is
variable i : integer := 0;
begin
-- coverage off
if x = 0 then return 0;
-- coverage on
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function Log2;
type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
signal ram_mem : ram_type;
attribute ram_style of ram_mem : signal is "block";
signal read_enable : std_logic;
signal write_enable : std_logic;
signal read_allow : std_logic;
signal write_allow : std_logic;
signal empty_allow : std_logic;
signal full_allow : std_logic;
signal full_i : std_logic;
signal empty : std_logic;
signal emptyg : std_logic;
signal fullg : std_logic;
signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
begin
-- Assign local signals from ports
read_enable <= RD;
write_enable <= WE;
-- Memory array
WritePort : process (WrClk)
begin
if (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
end if;
end if;
end process WritePort;
ReadPort : process (RdClk)
begin
if (RdClk'event and RdClk = '1') then
DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
end if;
end process ReadPort;
----------------------------------------------------------------
-- Allow flags determine whether FIFO control logic can --
-- operate. If read_enable is driven high, and the FIFO is --
-- not Empty, then Reads are allowed. Similarly, if the --
-- write_enable signal is high, and the FIFO is not Full, --
-- then Writes are allowed. --
----------------------------------------------------------------
read_allow <= (read_enable and not empty);
write_allow <= (write_enable and not full_i);
---------------------------------------------------------------
-- Empty flag is set on Reset (initial), or when gray --
-- code counters are equal, or when there is one word in --
-- the FIFO, and a Read operation is about to be performed. --
---------------------------------------------------------------
empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
EmptyFlag : process (RdClk, Reset)
begin
if (Reset = '1') then
empty <= '1';
elsif (RdClk'event and RdClk = '1') then
if (empty_allow = '1') then
empty <= emptyg;
end if;
end if;
end process EmptyFlag;
Exists <= not empty;
---------------------------------------------------------------
-- Full flag is set on Reset (initial, but it is cleared --
-- on the first valid write_clock edge after Reset is --
-- de-asserted), or when Gray-code counters are one away --
-- from being equal (the Write Gray-code address is equal --
-- to the Last Read Gray-code address), or when the Next --
-- Write Gray-code address is equal to the Last Read Gray- --
-- code address, and a Write operation is about to be --
-- performed. --
---------------------------------------------------------------
full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
FullFlag : process (WrClk, Reset)
begin
if (Reset = '1') then
full_i <= '1';
elsif (WrClk'event and WrClk = '1') then
if (full_allow = '1') then
full_i <= fullg;
end if;
end if;
end process FullFlag;
Full <= full_i;
----------------------------------------------------------------
-- Generation of Read address pointers. The primary one is --
-- binary (read_addr), and the Gray-code derivatives are --
-- generated via pipelining the binary-to-Gray-code result. --
-- The initial values are important, so they're in sequence. --
-- --
-- Grey-code addresses are used so that the registered --
-- Full and Empty flags are always clean, and never in an --
-- unknown state due to the asynchonous relationship of the --
-- Read and Write clocks. In the worst case scenario, Full --
-- and Empty would simply stay active one cycle longer, but --
-- it would not generate an error or give false values. --
----------------------------------------------------------------
read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
ReadAddrCnt : process (RdClk, Reset)
begin
if (Reset = '1') then
read_addr <= (others => '0');
elsif (RdClk'event and RdClk = '1') then
read_addr <= read_addr_next;
end if;
end process ReadAddrCnt;
ReadNextGray : process (RdClk, Reset)
begin
if (Reset = '1') then
read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
read_nextgray(read_nextgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_nextgray <= Bin2Gray(read_addr);
end if;
end if;
end process ReadNextGray;
ReadAddrGray : process (RdClk, Reset)
begin
if (Reset = '1') then
read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
read_addrgray(0) <= '1';
read_addrgray(read_addrgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_addrgray <= read_nextgray;
end if;
end if;
end process ReadAddrGray;
ReadLastGrey : process (RdClk, Reset)
begin
if (Reset = '1') then
read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
read_lastgray(0) <= '1';
read_lastgray(1) <= '1';
read_lastgray(read_lastgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_lastgray <= read_addrgray;
end if;
end if;
end process ReadLastGrey;
----------------------------------------------------------------
-- Generation of Write address pointers. Identical copy of --
-- read pointer generation above, except for names. --
----------------------------------------------------------------
WriteAddrCnt : process (WrClk, Reset)
begin
if (Reset = '1') then
write_addr <= (others => '0');
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_addr <= std_logic_vector(unsigned(write_addr) + 1);
end if;
end if;
end process WriteAddrCnt;
WriteNextGray : process (WrClk, Reset)
begin
if (Reset = '1') then
write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
write_nextgray(write_nextgray'high) <= '1';
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_nextgray <= Bin2Gray(write_addr);
end if;
end if;
end process WriteNextGray;
WriteAddrGray : process (WrClk, Reset)
begin
if (Reset = '1') then
write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
write_addrgray(0) <= '1';
write_addrgray(write_addrgray'high) <= '1';
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_addrgray <= write_nextgray;
end if;
end if;
end process WriteAddrGray;
----------------------------------------------------------------
-- The two conditions decoded with special carry logic are --
-- Empty and Full (gated versions). These are used to --
-- determine the next state of the Full/Empty flags. Carry --
-- logic is used for optimal speed. (The previous --
-- implementation of AlmostEmpty and AlmostFull have been --
-- wrapped into the corresponding carry chains for faster --
-- performance). --
-- --
-- When write_addrgray is equal to read_addrgray, the FIFO --
-- is Empty, and emptyg (combinatorial) is asserted. Or, --
-- when write_addrgray is equal to read_nextgray (1 word in --
-- the FIFO) then the FIFO potentially could be going Empty, --
-- so emptyg is asserted, and the Empty flip-flop enable is --
-- gated with empty_allow, which is conditioned with a valid --
-- read. --
-- --
-- Similarly, when read_lastgray is equal to write_addrgray, --
-- the FIFO is full (511 addresses). Or, when read_lastgray --
-- is equal to write_nextgray, then the FIFO potentially --
-- could be going Full, so fullg is asserted, and the Full --
-- flip-flop enable is gated with full_allow, which is --
-- conditioned with a valid write. --
-- --
-- Note: To have utilized the full address space (512) --
-- would have required extra logic to determine Full/Empty --
-- on equal addresses, and this would have slowed down the --
-- overall performance, which was the top priority. --
----------------------------------------------------------------
ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
begin
for I in 0 to Log2(MemSize)-1 loop
ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
(not (write_addrgray(I) xor read_nextgray(I)) and not empty);
end loop;
end process ECompare;
emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
begin
emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
end generate Gen_emuxcy;
emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
begin
for I in 0 to Log2(MemSize)-1 loop
fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
(not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
end loop;
end process FCompare;
fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
begin
fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
end generate Gen_fmuxcy;
fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
end architecture IMP;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_ENCODING : string := "MANCHESTER";
constant c_TX_CHANNELS : integer := 7;
constant c_RX_CHANNELS : integer := 7;
constant c_FE_TYPE : string := "FEI4";
constant c_RX_NUM_LANES : integer := 1;
constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(31,8);
constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(666,16);
constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(1,4);
end board_pkg;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity main is
Port ( functionfield : in STD_LOGIC_VECTOR (5 downto 0);
instr_op_main : in STD_LOGIC_VECTOR (5 downto 0);
reg_dst : out STD_LOGIC;
branch : out STD_LOGIC;
mem_read : out STD_LOGIC;
mem_to_reg : out STD_LOGIC;
alu_output : out STD_LOGIC_VECTOR (3 downto 0);
mem_write : out STD_LOGIC;
alu_src : out STD_LOGIC;
reg_write : out STD_LOGIC);
end main;
architecture Behavioral of main is
component control_unit is
port (
instr_op : in std_logic_vector(5 downto 0);
reg_dst : out std_logic;
branch : out std_logic;
mem_read : out std_logic;
mem_to_reg : out std_logic;
alu_op : out std_logic_vector(1 downto 0);
mem_write : out std_logic;
alu_src : out std_logic;
reg_write : out std_logic
);
end component;
component alu_control is
port (
alu_op : in std_logic_vector(1 downto 0);
instruction_5_0 : in std_logic_vector(5 downto 0);
alu_out : out std_logic_vector(3 downto 0)
);
end component;
signal temp_alu_op : std_logic_vector(1 downto 0) := (others => '0');
begin
C_UNIT : control_unit port map(
instr_op => instr_op_main,
reg_dst => reg_dst,
branch => branch,
mem_read => mem_read,
mem_to_reg => mem_to_reg,
alu_op => temp_alu_op,
mem_write => mem_write,
alu_src => alu_src,
reg_write => reg_write);
ALU_UNIT : alu_control port map(
alu_op => temp_alu_op,
instruction_5_0 => functionfield,
alu_out => alu_output);
end Behavioral;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
entity issue338b is
end entity;
architecture a of issue338b is
begin
main : process
procedure proc(s : string; variable value : out integer) is
begin
if s = "" then
value := 0;
else
value := 1;
end if;
end;
function func(s : string) return integer is
begin
if s = "" then
return 0;
end if;
return 1;
end;
constant s1 : string := "foobar";
constant s0 : string := "";
variable value : integer;
begin
assert func(s1) = 1;
assert func(s0) = 0;
proc(s1, value);
assert value = 1;
proc(s0, value);
assert value = 0;
wait;
end process;
end;
|
entity issue338b is
end entity;
architecture a of issue338b is
begin
main : process
procedure proc(s : string; variable value : out integer) is
begin
if s = "" then
value := 0;
else
value := 1;
end if;
end;
function func(s : string) return integer is
begin
if s = "" then
return 0;
end if;
return 1;
end;
constant s1 : string := "foobar";
constant s0 : string := "";
variable value : integer;
begin
assert func(s1) = 1;
assert func(s0) = 0;
proc(s1, value);
assert value = 1;
proc(s0, value);
assert value = 0;
wait;
end process;
end;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=3000ns
-->SIMSAVFILE=dspdiv.sav
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity bench_div is
end bench_div;
--=----------------------------------------------------------------------------
architecture archi_bench_div of bench_div is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_sig_width : integer := 16;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_num : std_logic_vector((2*c_sig_width - 1) downto 0);
signal s_den : std_logic_vector((c_sig_width - 1) downto 0);
signal s_q : std_logic_vector((c_sig_width - 1) downto 0);
signal s_r : std_logic_vector((2*c_sig_width - 3) downto 0);
begin -- archs_bench_div
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspdiv_1 : dspdiv
generic map (
sig_width => c_sig_width)
port map (
num => s_num,
den => s_den,
clk => s_clk,
q => s_q,
r => s_r);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_num <= x"00050000", x"05000000" after 21 ns, x"00050000" after 31 ns;
s_den <= x"0406", x"0400" after 11 ns, x"FBFA" after 41 ns, x"0400" after 51 ns;
-- s_num <= x"00050000",x"00050000" after 11 ns, x"FFFB0000" after 21 ns;
-- s_den <= x"0406",x"FC00" after 31 ns;
end archi_bench_div;
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=3000ns
-->SIMSAVFILE=dspdiv.sav
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity bench_div is
end bench_div;
--=----------------------------------------------------------------------------
architecture archi_bench_div of bench_div is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_sig_width : integer := 16;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_num : std_logic_vector((2*c_sig_width - 1) downto 0);
signal s_den : std_logic_vector((c_sig_width - 1) downto 0);
signal s_q : std_logic_vector((c_sig_width - 1) downto 0);
signal s_r : std_logic_vector((2*c_sig_width - 3) downto 0);
begin -- archs_bench_div
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspdiv_1 : dspdiv
generic map (
sig_width => c_sig_width)
port map (
num => s_num,
den => s_den,
clk => s_clk,
q => s_q,
r => s_r);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_num <= x"00050000", x"05000000" after 21 ns, x"00050000" after 31 ns;
s_den <= x"0406", x"0400" after 11 ns, x"FBFA" after 41 ns, x"0400" after 51 ns;
-- s_num <= x"00050000",x"00050000" after 11 ns, x"FFFB0000" after 21 ns;
-- s_den <= x"0406",x"FC00" after 31 ns;
end archi_bench_div;
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
rx => UART_RX,
do => RX_Data,
stb => RX_Strobe
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Transmitter for ultrasonic beacons
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Register description
--
-- offset | Meaning
-- -------+---------
-- 0x00 | Fractional Clock Divider MUL value
-- 0x01 | Fractional Clock Divider DIV value
-- 0x02 | Bit pattern 0
-- 0x03 | Bit pattern 1
-- 0x04 | Bit pattern 2
-- 0x05 | Bit pattern 3
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012, 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all; -- for half_bridge_type
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity uss_tx_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF# -- Base address at the internal data bus
);
port (
-- Ports to the ultrasonic transmitters
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
-- Output of the clock enable signal
clk_uss_enable_p : out std_logic;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end uss_tx_module;
-------------------------------------------------------------------------------
architecture behavioral of uss_tx_module is
-- types for states
-- none
-- record for internal states
-- none
-----------------------------------------------------------------------------
-- internal signals
-----------------------------------------------------------------------------
-- access to the internal register
constant REG_ADDR_BIT : natural := 3; -- 2**3 = 8 registers for mul and div value
constant BITPATTERN_WIDTH : positive := 64; -- Width of the bit pattern to send
signal reg_o : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal reg_i : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal clk_mul : std_logic_vector(15 downto 0);
signal clk_div : std_logic_vector(15 downto 0);
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
signal bitstream : std_logic;
signal clk_bit : std_logic;
signal modulation : std_logic_vector(2 downto 0); -- Modulation of the US carrier
signal clk_uss_enable : std_logic := '0';
signal clk_uss : std_logic := '0'; -- Clock signal with 50% duty cycle
signal clk_uss_n : std_logic;
signal uss_tx_high : std_logic; -- With deadtime, for H-bridges
signal uss_tx_low : std_logic; -- With deadtime, for H-bridges
begin -- behavioral
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- register for access to and from STM
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
reset => '0',
clk => clk
);
-- Serialise the bit pattern to a bit stream
serialiser : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-- Bit clock (2000 bps)
-- 50 MHz / 25000 = 2000
clock_divider : entity work.clock_divider
generic map (
DIV => 25000)
port map (
clk_out_p => clk_bit,
clk => clk);
-- clock generation of clk_uss_tx (carrier)
fractional_clock_divider_variable_1 : fractional_clock_divider_variable
generic map (
WIDTH => 16)
port map (
div => clk_div,
mul => clk_mul,
clk_out_p => clk_uss_enable,
clk => clk);
-- generate a signal with a 50% duty-cycle from the enable signal
process (clk, clk_uss_enable)
begin
if rising_edge(clk) then
if clk_uss_enable = '1' then
clk_uss <= not clk_uss;
end if;
end if;
end process;
-- generate clocks with deadtime
clk_uss_n <= not clk_uss;
-- output to the H-bridges
deadtime_on : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss_n,
out_p => uss_tx_low,
clk => clk);
deadtime_off : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss,
out_p => uss_tx_high,
clk => clk);
-----------------------------------------------------------------------------
-- Mapping of signals between components and module ports
-----------------------------------------------------------------------------
clk_mul <= reg_o(0);
clk_div <= reg_o(1);
pattern(15 downto 0) <= reg_o(2);
pattern(31 downto 16) <= reg_o(3);
pattern(47 downto 32) <= reg_o(4);
pattern(63 downto 48) <= reg_o(5);
-- enable readback of configurations
reg_i <= reg_o;
clk_uss_enable_p <= clk_uss_enable;
-----------------------------------------------------------------------------
-- Drive Ultrasonic transmitters
-----------------------------------------------------------------------------
modulation(0) <= bitstream;
modulation(1) <= bitstream;
modulation(2) <= bitstream;
uss_tx0_out_p.high <= uss_tx_high and modulation(0);
uss_tx1_out_p.high <= uss_tx_high and modulation(1);
uss_tx2_out_p.high <= uss_tx_high and modulation(2);
uss_tx0_out_p.low <= uss_tx_low and modulation(0);
uss_tx1_out_p.low <= uss_tx_low and modulation(1);
uss_tx2_out_p.low <= uss_tx_low and modulation(2);
end behavioral;
|
entity debug1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
architecture test of debug1 is
signal fRn2 : std_logic_vector(22 downto 0);
signal fR : std_logic_vector(23 downto 0);
signal round : std_logic;
begin
warn: fRn2 <= fR(23 downto 1) + ((22 downto 1 => '0') & round); -- rounding sqrt never changes exponents
control: process is
begin
wait for 1 ns;
report "simulation finished";
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bus_writer is
generic (
bus_length : natural;
bus_index : natural;
value : std_logic_vector(7 downto 0)
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end entity bus_writer;
architecture behavioural of bus_writer is
signal active_index : natural range bus_length-1 downto 0 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
if active_index = bus_index then
data <= value;
else
data <= (others => 'Z');
end if;
if active_index = bus_length - 1 then
active_index <= 0;
else
active_index <= active_index + 1;
end if;
end if;
end process;
end behavioural;
|
-- Generic size register made with sync latches
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_sync_register IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_sync_register;
ARCHITECTURE structural OF Generic_sync_register IS
COMPONENT SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END COMPONENT;
BEGIN
SYNC_REG_GENERATOR : for i in 0 to N-1 generate
SYNC_LATCH_I : SYNC_LATCH PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => DIN(i),
DOUT => DOUT(i));
end Generate;
END structural; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library DesignLab;
--use DesignLab.ALL;
entity Simulate_Your_CCL_Design is
end entity;
architecture sim of Simulate_Your_CCL_Design is
constant period: time := 10 ns;
signal clk: std_logic := '1';
signal rst: std_logic := '0';
COMPONENT A595
PORT(
--Put your custom external connections here
buttons : IN std_logic_vector(3 downto 0);
leds : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define your external connections here
signal buttons: std_logic_vector(3 downto 0) := "1010";
signal leds: std_logic_vector(3 downto 0);
begin
clk <= not clk after period/2;
-- Reset
process
begin
wait for 5 ns;
rst <= '1';
wait for 20 ns;
rst <= '0';
wait;
end process;
uut: A595 PORT MAP(
--Define your external connections here
buttons => buttons,
leds => leds
);
process
begin
wait until rst='1';
wait until rst='0';
wait until rising_edge(clk);
-- This is where you should start providing your stimulus to test your design.
-- Provide stimulus on the buttons
buttons <= "0000";
wait for 100 ns;
-- Check that the leds match
assert( leds = "0000");
-- Provide stimulus on the buttons
buttons <= "1111";
wait for 100 ns;
-- Check that the leds match
assert( leds = "1111");
wait for 200 ns;
report "Finsihed" severity failure;
end process;
end sim;
|
{{define "_entityFB"}}
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$specialIO := getSpecialIO $block .Blocks}}
entity {{$block.Name}} is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
{{if $block.EventInputs}}
--input events
{{range $index, $event := $block.EventInputs}}{{$event.Name}}_eI : in std_logic := '0';
{{end}}{{end}}
{{if $block.EventOutputs}}
--output events
{{range $index, $event := $block.EventOutputs}}{{$event.Name}}_eO : out std_logic;
{{end}}{{end}}
{{if $block.InputVars}}
--input variables
{{range $index, $var := $block.InputVars}}{{$var.Name}}_I : in {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.OutputVars}}
--output variables
{{range $index, $var := $block.OutputVars}}{{$var.Name}}_O : out {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.BasicFB}}{{if $specialIO.InternalVars}}
--special emitted internal vars for I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{else if $block.CompositeFB}}{{if $specialIO.InternalVars}}
--special emitted internal variables for child I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{end}}
--for done signal
done : out std_logic
);
end entity;
{{end}} |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_03 is
end entity test_bench_04_03;
library ch4_pkgs;
use ch4_pkgs.pk_04_02.all;
architecture test_byte_swap_behavior of test_bench_04_03 is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_byte_swap_behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_03 is
end entity test_bench_04_03;
library ch4_pkgs;
use ch4_pkgs.pk_04_02.all;
architecture test_byte_swap_behavior of test_bench_04_03 is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_byte_swap_behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_03 is
end entity test_bench_04_03;
library ch4_pkgs;
use ch4_pkgs.pk_04_02.all;
architecture test_byte_swap_behavior of test_bench_04_03 is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_byte_swap_behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity modem_controller is
end entity modem_controller;
----------------------------------------------------------------
architecture test of modem_controller is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity modem_controller is
end entity modem_controller;
----------------------------------------------------------------
architecture test of modem_controller is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity modem_controller is
end entity modem_controller;
----------------------------------------------------------------
architecture test of modem_controller is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:11:34 11/21/2013
-- Design Name:
-- Module Name: InstructionMem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionMem is
Port(
clk : in std_logic;
rst : in std_logic;
Address : in Int16;
Data : out Int16;
ramdata : INOUT std_logic_vector(15 downto 0);
ramaddr : OUT std_logic_vector(17 downto 0);
OE : OUT std_logic;
WE : OUT std_logic;
EN : OUT std_logic
);
end InstructionMem;
architecture Behavioral of InstructionMem is
signal flag: std_logic:= '0';
begin
process(rst, clk)
begin
if rst = '0' then
flag <= '0';
ramdata <= Int16_Z;
OE <= '1';
WE <= '1';
EN <= '1';
Data <= Int16_Zero;
ramaddr <= "00" & Int16_Zero;
elsif falling_edge(clk) then
case flag is
when '0' =>
EN <= '0';
OE <= '0';
WE <= '1';
ramaddr <= "00" & Address;
ramdata <= Int16_Z;
flag <= '1';
when '1' =>
data <= ramdata;
flag <= '0';
when others => flag <= '0';
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.1 2006/03/16 14:12:15 wig Exp $
-- $Date: 2006/03/16 14:12:15 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/03/16 14:12:15 wig
-- Added testcase for command line -conf add/overload
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: overloading my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG for inst_ba : ent_ba
-- __I_NO_CONFIG use configuration work.NO_CONFIG;
-- __I_NO_CONFIG end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity chram is
Port (
CLK : in std_logic;
CHRAM_A : in std_logic_vector(9 downto 0);
CHRAM_WR : in std_logic;
CHRAM_DI : in std_logic_vector(8 downto 0);
CHRAM_DO : out std_logic_vector(8 downto 0);
CHRAM_VA : in std_logic_vector(9 downto 0);
CHRAM_VD : out std_logic_vector(8 downto 0)
);
end chram;
architecture rtl of chram is
subtype word_t is std_logic_vector(8 downto 0);
type memory_t is array(0 to 1023) of word_t;
shared variable ram : memory_t := (
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000011", "001010000", "000101111", "001001101", "000101101", "000111000", "000110000", "000100000",
"000100000", "001110110", "000101110", "000100000", "000110010", "000101110", "000110010", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"011101111", "011100110", "011110000", "000100000", "000100000", "011101110", "011101001", "011101001",
"011110001", "011100110", "000100000", "000100000", "011101101", "011100111", "011110101", "000100000",
"000100000", "001000010", "001001001", "001001111", "001010011", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001010110", "001100101", "001110010", "000101110", "000100000", "000110001", "000101110", "000110010",
"000100000", "000101000", "001100011", "000101001", "000100000", "001001001", "001001001", "001001001",
"000100000", "000110001", "000111001", "000111000", "000111000", "000100000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111110", "001000100", "001001001", "001010010", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001001001", "001001110", "001000001", "001001100",
"001000101", "001001110", "001000100", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001000", "001000001", "001010011", "001000101", "001010010",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001001010", "001000001", "001001101", "001010000", "001000101", "001010010", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001001011", "001001100", "001000001", "001000100", "000110001", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001001101", "001000001", "001000110", "001001001", "001000001",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001010000", "001000001", "001000011", "001001101", "001000001", "001001110",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010000", "001001111", "001010000", "001001011", "001001111", "001010010", "001001110",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010011", "001001111", "001001011", "001001111", "000100000", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001010011", "001010100", "001000001", "001001100", "001001011",
"001000101", "001010010", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001011000", "001011001", "001011010", "001001111", "001001110", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001011010", "001010111", "000100000", "000100000", "000100000", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001000110", "001000001", "001001001", "001010010", "000100000", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001001111", "001001101", "001000010", "001000101",
"001010010", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001111", "001001100", "001001111", "001010010", "001000010",
"001000001", "001001100", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001000110", "001001001", "001010110", "001010100", "001000101", "001000101", "001001110",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010011", "001000001", "001001101", "001001111", "001010110", "001000001", "001010010", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001011000", "001000001", "001010010", "001010100", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000001", "001001110", "001010100", "001001111", "001001110", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010010", "001000001", "001001100", "001001100", "001011001", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010100", "001000101", "001010100", "001010010", "001001001", "001010011", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001000001", "001010010", "001010011", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000100000",
"000100000", "000100000", "001000100", "001000001", "001010100", "000100000", "000111010", "000100000",
"001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000100000", "000100000",
"000100000", "001010000", "001000011", "000110001", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101",
"001010011", "000110000", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000",
"000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011",
"000110001", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000", "000111010",
"000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000110100",
"000100000", "000100000", "001010010", "001000101", "001011010", "000100000", "000111010", "000100000",
"001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000110101", "000100000",
"000100000", "001010010", "001000101", "001011010", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101",
"001010011", "000111001", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000",
"000111010", "000100000", "001010000", "001000001", "001000111", "001000001", "001001110", "001001001",
"001001110", "001001001", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010011", "001010000", "001001111", "001010010", "001010100", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001000111", "001000001", "001001100", "001000001", "001011000", "001001001", "001000001", "001001110",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001010011", "001001111", "001001111", "000100000", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001001110", "001001001", "001001110", "001001010", "001000001", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001001011", "000110010", "000100000", "000100000", "000100000", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010100", "001010010", "001000101", "001000001", "001010011", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111110", "100000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000" );
begin
process(CLK)
begin
if rising_edge(CLK) then
if CHRAM_WR = '1' then
ram(to_integer(unsigned(CHRAM_A))) := CHRAM_DI;
else
CHRAM_DO <= ram(to_integer(unsigned(CHRAM_A)));
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
CHRAM_VD <= ram(to_integer(unsigned(CHRAM_VA)));
end if;
end process;
end rtl;
|
-- file: clk_base_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base_clk_wiz is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base_clk_wiz;
architecture xilinx of clk_base_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_raw_clk_base : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_base : std_logic;
signal clkfbout_buf_clk_base : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_250MHz_clk_base : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_raw_clk_base,
I => clk_raw);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 4.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_250MHz_clk_base,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_base,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_base,
I => clkfbout_clk_base);
clkout1_buf : BUFG
port map
(O => clk_250MHz,
I => clk_250MHz_clk_base);
end xilinx;
|
-- file: clk_base_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base_clk_wiz is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base_clk_wiz;
architecture xilinx of clk_base_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_raw_clk_base : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_base : std_logic;
signal clkfbout_buf_clk_base : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_250MHz_clk_base : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_raw_clk_base,
I => clk_raw);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 4.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_250MHz_clk_base,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_base,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_base,
I => clkfbout_clk_base);
clkout1_buf : BUFG
port map
(O => clk_250MHz,
I => clk_250MHz_clk_base);
end xilinx;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_bb_e -- bb instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end component;
-- ---------
component inst_vb_e -- verilog udc inst_bc2_i
-- No Generated Generics
-- Generated Generics for Entity inst_vb_e
-- End of Generated Generics for Entity inst_vb_e
-- No Generated Port
end component;
-- ---------
component inst_be_i -- no verilog udc here
-- No Generated Generics
-- Generated Generics for Entity inst_be_i
-- End of Generated Generics for Entity inst_be_i
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
udc: THIS GOES TO DECL of inst_b_i
begin
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_aa_ba <= p_mix_signal_aa_ba_gi; -- __I_I_BIT_PORT
p_mix_signal_bb_ab_go <= signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba_i
inst_ba_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => signal_aa_ba, -- signal test aa to ba
port_xa_o => open -- open signal to create port
);
-- End of Generated Instance Port Map for inst_ba_i
-- Generated Instance Port Map for inst_bb_i
inst_bb_i: inst_bb_e -- bb instance
port map (
port_bb_o => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_bb_i
-- Generated Instance Port Map for inst_bc1_i
inst_bc1_i: inst_vb_e -- verilog udc inst_bc2_i
;
-- End of Generated Instance Port Map for inst_bc1_i
udc: preinst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_bc2_i
inst_bc2_i: inst_vb_e -- verilog udc inst_bc2_i
;
-- End of Generated Instance Port Map for inst_bc2_i
udc: post_inst_udc for inst_bc2_i
udc: preinst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_be_i
inst_be_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_be_i
udc: post_inst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_bf_i
inst_bf_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_bf_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk_wa is
generic ( fc : real := 455.0e3; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequency
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk_wa;
----------------------------------------------------------------
architecture behavioral of bfsk_wa is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk_wa is
generic ( fc : real := 455.0e3; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequency
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk_wa;
----------------------------------------------------------------
architecture behavioral of bfsk_wa is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk_wa is
generic ( fc : real := 455.0e3; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequency
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk_wa;
----------------------------------------------------------------
architecture behavioral of bfsk_wa is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- $Id: sys_tst_rlink_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n3 - syn
-- Description: rlink tester design for nexys3
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-03-13 743 14.7 131013 xc6slx16-2 950 1380 70 504
-- 2014-12-20 614 14.7 131013 xc6slx16-2 917 1379 64 513 t 8.9
-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9
-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n3;
architecture syn of sys_tst_rlink_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"03"; -- nexys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
entity FIFO is
generic (
G_WIDTH : natural := 16
);
end entity;
architecture rtl of fifo is
signal w_data : std_logic_vector(g_width - 1 downto 0);
begin
output <= large_data(g_width - 1 downto 0);
end architecture rtl;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OZ3_Sys_Top is
port(clk : in std_logic;
rst : in std_logic);
end OZ3_Sys_Top;
architecture Behavioral of OZ3_Sys_Top is
component OZ3 is
Port ( main_clock : in STD_LOGIC;
reset : in STD_LOGIC;
input_pins : in STD_LOGIC_VECTOR(15 downto 0);
input_port : in STD_LOGIC_VECTOR(31 downto 0);
instruction_from_iROM : in STD_LOGIC_VECTOR(31 downto 0);
data_from_dRAM : in STD_LOGIC_VECTOR(31 downto 0);
output_pins : out STD_LOGIC_VECTOR(15 downto 0);
output_port : out STD_LOGIC_VECTOR(31 downto 0);
output_port_enable : out STD_LOGIC;
addr_to_iROM : out STD_LOGIC_VECTOR(22 downto 0);
data_to_dRAM : out STD_LOGIC_VECTOR(31 downto 0);
addr_to_dRAM : out STD_LOGIC_VECTOR(22 downto 0);
WR_to_dRAM : out STD_LOGIC);
end component;
component data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end component;
COMPONENT program_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal OZ3_ipins, OZ3_opins : std_logic_vector(15 downto 0);
signal OZ3_iport, OZ3_oport : std_logic_vector(31 downto 0);
signal OZ3_oport_we : std_logic;
signal prog_mem_addr : std_logic_vector(22 downto 0);
signal prog_mem_out : std_logic_vector(31 downto 0);
signal data_mem_addr : std_logic_vector(22 downto 0);
signal data_mem_real_addr : std_logic_vector(31 downto 0);
signal data_mem_out, data_mem_in : std_logic_vector(31 downto 0);
signal data_mem_we : std_logic;
begin
CPU : OZ3
port map(
main_clock => clk,
reset => rst,
input_pins => OZ3_ipins,
input_port => OZ3_iport,
instruction_from_iROM => prog_mem_out,
data_from_dRAM => data_mem_out,
output_pins => OZ3_opins,
output_port => OZ3_oport,
output_port_enable => OZ3_oport_we,
addr_to_iROM => prog_mem_addr,
data_to_dRAM => data_mem_in,
addr_to_dRAM => data_mem_addr,
WR_to_dRAM => data_mem_we
);
data_mem_real_addr <= "000000000" & data_mem_addr;
dmem : data_memory
port map(
clk => clk,
rst => rst,
address => data_mem_real_addr,
data_in => data_mem_in,
data_out => data_mem_out,
we => data_mem_we
);
pmem : program_memory
port map(
clka => clk,
addra => prog_mem_addr(8 downto 0),
douta => prog_mem_out
);
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul8_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul8_16;
ARCHITECTURE mul8_16_arch OF mul8_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul8_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul8_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul8_16_arch : ARCHITECTURE IS "mul8_16,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul8_16_arch: ARCHITECTURE IS "mul8_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=3,C_A_WIDTH=8,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=8,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul8_16_arch;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare16.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare16 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare16;
ARCHITECTURE SYN OF lpm_compare16 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "SIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clock_forwarder is
generic (
kArch : string := "artix7"
);
port (
aRst : in std_logic;
InClk : in std_logic;
iCE : in std_logic;
OutClk : out std_logic
);
end clock_forwarder;
architecture arch_imp of clock_forwarder is
begin
zynquplus: if kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus" generate
begin
ODDRE1_inst : ODDRE1
generic map (
IS_C_INVERTED => '0', -- Optional inversion for C
IS_D1_INVERTED => '0', -- Unsupported, do not use
IS_D2_INVERTED => '0', -- Unsupported, do not use
SRVAL => '0' -- Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1')
)
port map (
Q => OutClk, -- 1-bit output: Data output to IOB
C => InClk, -- 1-bit input: High-speed clock input
D1 => '1', -- 1-bit input: Parallel data input 1
D2 => '0', -- 1-bit input: Parallel data input 2
SR => aRst -- 1-bit input: Active High Async Reset
);
end generate zynquplus;
nonzynquplus: if not (kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus") generate
begin
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OutClk, -- 1-bit DDR output
C => InClk, -- 1-bit clock input
CE => iCE, -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => aRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate nonzynquplus;
end arch_imp;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:40:28 12/13/2009
-- Design Name:
-- Module Name:
-- Project Name: ciosspartan
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: rsa_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity test_rsa_512 is
end test_rsa_512;
architecture behavior of test_rsa_512 is
-- Component Declaration for the Unit Under Test (UUT)
component rsa_top
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector(15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal valid_in : std_logic := '0';
signal start_in : std_logic;
signal x : std_logic_vector(15 downto 0) := (others => '0');
signal y : std_logic_vector(15 downto 0) := (others => '0');
signal m : std_logic_vector(15 downto 0) := (others => '0');
signal r_c : std_logic_vector(15 downto 0) := (others => '0');
signal n_c : std_logic_vector(15 downto 0) := (others => '0');
signal bit_size : std_logic_vector(15 downto 0) := x"0200";
--Outputs
signal s : std_logic_vector(15 downto 0);
signal valid_out : std_logic;
-- Clock period definitions
constant clk_period : time := 1ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : rsa_top port map (
clk => clk,
reset => reset,
valid_in => valid_in,
start_in => start_in,
x => x,
y => y,
m => m,
r_c => r_c,
s => s,
valid_out => valid_out,
bit_size => bit_size
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
start_in <= '0';
valid_in <= '0';
-- hold reset state for 100ms.
reset <= '1';
wait for 10ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
--n_c and valid signal and the r_c constant are also required
--n_c <= x"738f";
m <= x"b491";
--Start_in to begin n_c calculation
start_in <= '1';
wait for clk_period;
start_in <= '0';
wait for clk_period*6;
--Start data flow
x <= x"f3ad";
y <= x"42b1";
m <= x"b491";
r_c <= x"f579";
valid_in <= '1';
wait for clk_period;
x <= x"8e40";
y <= x"1ad3";
m <= x"1417";
r_c <= x"6ee9";
wait for clk_period;
x <= x"6af9";
y <= x"a827";
m <= x"b498";
r_c <= x"972d";
wait for clk_period;
x <= x"4e63";
y <= x"0d64";
m <= x"e1b7";
r_c <= x"5052";
wait for clk_period;
x <= x"9600";
y <= x"3f76";
m <= x"e47c";
r_c <= x"1dca";
wait for clk_period;
x <= x"68f4";
y <= x"6670";
m <= x"b186";
r_c <= x"bc81";
wait for clk_period;
x <= x"5a12";
y <= x"5a1c";
m <= x"93f0";
r_c <= x"377e";
wait for clk_period;
x <= x"d62e";
y <= x"4844";
m <= x"b183";
r_c <= x"04ef";
wait for clk_period;
x <= x"8fc1";
y <= x"d5f2";
m <= x"f8f1";
r_c <= x"3a2a";
wait for clk_period;
x <= x"031d";
y <= x"b65a";
m <= x"eed1";
r_c <= x"291b";
wait for clk_period;
x <= x"f496";
y <= x"034f";
m <= x"0083";
r_c <= x"c159";
wait for clk_period;
x <= x"1268";
y <= x"9635";
m <= x"981c";
r_c <= x"9336";
wait for clk_period;
x <= x"2e5a";
y <= x"386e";
m <= x"6441";
r_c <= x"1bd0";
wait for clk_period;
x <= x"c1d6";
y <= x"fb73";
m <= x"fcd8";
r_c <= x"317d";
wait for clk_period;
x <= x"cd8f";
y <= x"5623";
m <= x"cbf0";
r_c <= x"64b4";
wait for clk_period;
x <= x"e4d2";
y <= x"9041";
m <= x"e3ca";
r_c <= x"8793";
wait for clk_period;
x <= x"36c6";
y <= x"99da";
m <= x"41d9";
r_c <= x"85f5";
wait for clk_period;
x <= x"df4a";
y <= x"cd68";
m <= x"b7a0";
r_c <= x"7c8d";
wait for clk_period;
x <= x"8e40";
y <= x"9a94";
m <= x"146e";
r_c <= x"64d9";
wait for clk_period;
x <= x"6af9";
y <= x"ccc8";
m <= x"4776";
r_c <= x"c7f6";
wait for clk_period;
x <= x"4e63";
y <= x"ed49";
m <= x"ec50";
r_c <= x"fba0";
wait for clk_period;
x <= x"9600";
y <= x"4d25";
m <= x"c07c";
r_c <= x"e3e0";
wait for clk_period;
x <= x"68f4";
y <= x"3b8e";
m <= x"e698";
r_c <= x"b567";
wait for clk_period;
x <= x"5a12";
y <= x"36d5";
m <= x"d85f";
r_c <= x"3172";
wait for clk_period;
x <= x"d62e";
y <= x"3a75";
m <= x"729c";
r_c <= x"111a";
wait for clk_period;
x <= x"8fc1";
y <= x"77a3";
m <= x"19b6";
r_c <= x"1971";
wait for clk_period;
x <= x"d2cd";
y <= x"367f";
m <= x"05d3";
r_c <= x"9f9b";
wait for clk_period;
x <= x"c6e4";
y <= x"68de";
m <= x"cacd";
r_c <= x"b574";
wait for clk_period;
x <= x"4a36";
y <= x"59a4";
m <= x"e16f";
r_c <= x"4a50";
wait for clk_period;
x <= x"f6df";
y <= x"9f89";
m <= x"f67b";
r_c <= x"6d56";
wait for clk_period;
x <= x"061c";
y <= x"ed71";
m <= x"7066";
r_c <= x"bdc6";
wait for clk_period;
x <= x"06c8";
y <= x"059f";
m <= x"08de";
r_c <= x"0400";
wait for clk_period;
valid_in <= '0';
--valid_in <='0';
wait for clk_period*200000;
--Now with the public key x"10001";
bit_size <= x"0011";
valid_in <= '1';
x <= x"f3ad";
y <= x"0001";
m <= x"b491";
r_c <= x"f579";
wait for clk_period;
x <= x"8e40";
y <= x"0001";
m <= x"1417";
r_c <= x"6ee9";
wait for clk_period;
x <= x"6af9";
y <= x"0000";
m <= x"b498";
r_c <= x"972d";
wait for clk_period;
x <= x"4e63";
m <= x"e1b7";
r_c <= x"5052";
wait for clk_period;
x <= x"9600";
m <= x"e47c";
r_c <= x"1dca";
wait for clk_period;
x <= x"68f4";
m <= x"b186";
r_c <= x"bc81";
wait for clk_period;
x <= x"5a12";
m <= x"93f0";
r_c <= x"377e";
wait for clk_period;
x <= x"d62e";
m <= x"b183";
r_c <= x"04ef";
wait for clk_period;
x <= x"8fc1";
m <= x"f8f1";
r_c <= x"3a2a";
wait for clk_period;
x <= x"031d";
m <= x"eed1";
r_c <= x"291b";
wait for clk_period;
x <= x"f496";
m <= x"0083";
r_c <= x"c159";
wait for clk_period;
x <= x"1268";
m <= x"981c";
r_c <= x"9336";
wait for clk_period;
x <= x"2e5a";
m <= x"6441";
r_c <= x"1bd0";
wait for clk_period;
x <= x"c1d6";
m <= x"fcd8";
r_c <= x"317d";
wait for clk_period;
x <= x"cd8f";
m <= x"cbf0";
r_c <= x"64b4";
wait for clk_period;
x <= x"e4d2";
m <= x"e3ca";
r_c <= x"8793";
wait for clk_period;
x <= x"36c6";
m <= x"41d9";
r_c <= x"85f5";
wait for clk_period;
x <= x"df4a";
m <= x"b7a0";
r_c <= x"7c8d";
wait for clk_period;
x <= x"8e40";
m <= x"146e";
r_c <= x"64d9";
wait for clk_period;
x <= x"6af9";
m <= x"4776";
r_c <= x"c7f6";
wait for clk_period;
x <= x"4e63";
m <= x"ec50";
r_c <= x"fba0";
wait for clk_period;
x <= x"9600";
m <= x"c07c";
r_c <= x"e3e0";
wait for clk_period;
x <= x"68f4";
m <= x"e698";
r_c <= x"b567";
wait for clk_period;
x <= x"5a12";
m <= x"d85f";
r_c <= x"3172";
wait for clk_period;
x <= x"d62e";
m <= x"729c";
r_c <= x"111a";
wait for clk_period;
x <= x"8fc1";
m <= x"19b6";
r_c <= x"1971";
wait for clk_period;
x <= x"d2cd";
m <= x"05d3";
r_c <= x"9f9b";
wait for clk_period;
x <= x"c6e4";
m <= x"cacd";
r_c <= x"b574";
wait for clk_period;
x <= x"4a36";
m <= x"e16f";
r_c <= x"4a50";
wait for clk_period;
x <= x"f6df";
m <= x"f67b";
r_c <= x"6d56";
wait for clk_period;
x <= x"061c";
m <= x"7066";
r_c <= x"bdc6";
wait for clk_period;
x <= x"06c8";
m <= x"08de";
r_c <= x"0400";
wait for clk_period;
valid_in <= '0';
wait;
end process;
end;
|
--
-- Copyright (c) ARMadeus Project 2011
--
-- Interface with the HMS Module ANYBUS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : anybus_interface.vhd
-- Created on : 12/05/2011
-- Author : Kevin JOLY joly.kevin25@gmail.com
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity anybus_interface is
generic (
ID : natural := 1;
wb_size : natural := 16
);
port (
-- Syscon signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone signals
wbs_add : in std_logic_vector (1 downto 0);
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic;
wbs_cycle : in std_logic;
wbs_write : in std_logic;
wbs_ack : out std_logic;
--hms anybus signals
anybus_interface_addr : out std_logic_vector(11 downto 0);
anybus_interface_data : inout std_logic_vector(7 downto 0);
anybus_interface_busy : in std_logic;
anybus_interface_oe : out std_logic;
anybus_interface_rw : out std_logic;
anybus_interface_ce : out std_logic
);
end entity anybus_interface;
architecture anybus_interface_arch of anybus_interface is
--State signal for anybus
type state_anybus_type is (init_anybus,start, read, end_read, write, end_write);
signal state_anybus : state_anybus_type := init_anybus;
--State signal for Wishbone Bus
type state_wb_type is (init_wb, read_register, write_register, transmission_error);
signal state_wb : state_wb_type := init_wb;
--Registers
--In the worst case, the interface will wait 7 clock cycles
signal CONTROL_REG : std_logic_vector(wb_size-1 downto 0) := x"0000";
signal ADDRESS_REG : std_logic_vector(wb_size-1 downto 0) := x"0000";
signal DATA_READ_REG : std_logic_vector(wb_size-1 downto 0) := x"0000";
signal DATA_WRITE_REG : std_logic_vector(wb_size-1 downto 0) := x"0000";
--Status signals
signal communication_error : std_logic := '0';
signal transmission : std_logic := '0';
signal reception : std_logic := '0';
signal com_in_progress : std_logic := '0';
signal wait_clock_cycles : integer range 0 to 7 := 7;
--write message signals
signal message_addr : std_logic_vector(11 downto 0);
signal message_data : std_logic_vector(7 downto 0);
begin
--FSM of the Wishbone interface
fsm_wb_interface : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
--Return to the waiting state
state_wb <= init_wb;
transmission <= '0';
reception <= '0';
communication_error <= '0';
ADDRESS_REG <= (others => '0');
DATA_WRITE_REG <= (others => '0');
wait_clock_cycles <= 7;
elsif rising_edge(gls_clk) then
case state_wb is
when init_wb =>
transmission <= '0';
reception <= '0';
if (wbs_strobe and wbs_write) = '1' then
state_wb <= write_register;
elsif (wbs_strobe = '1') and (wbs_write = '0') then
state_wb <= read_register;
end if;
when write_register =>
if wbs_strobe = '0' then
state_wb <= init_wb;
else
--ask for communication if a transmit is in progress or if the data is busy generate an error
if wbs_add(1 downto 0) = "01" then
if (wbs_writedata(1) or wbs_writedata(2)) = '1' and (not anybus_interface_busy or com_in_progress) = '1' then
state_wb <= transmission_error;
communication_error <= '1';
else
transmission <= wbs_writedata(1);
reception <= wbs_writedata(2);
end if;
wait_clock_cycles <= to_integer(unsigned(wbs_writedata(5 downto 3)));
elsif wbs_add(1 downto 0) = "10" then
ADDRESS_REG(11 downto 0) <= wbs_writedata(11 downto 0);
elsif wbs_add(1 downto 0) = "11" then
DATA_WRITE_REG(7 downto 0) <= wbs_writedata(7 downto 0);
end if;
end if;
when read_register =>
if wbs_add(1 downto 0) = "11" and com_in_progress = '1' then
communication_error <= '1';
state_wb <= transmission_error;
end if;
if wbs_strobe = '0' then
state_wb <= init_wb;
--Read in the CONTROL_REG will clear error flag
if wbs_add(1 downto 0) = "01" then
communication_error <= '0';
end if;
end if;
when transmission_error =>
if wbs_strobe = '0' then
state_wb <= init_wb;
end if;
end case;
end if;
end process fsm_wb_interface;
--FSM of the Anybus interface
fsm_anybus : process(gls_clk, gls_reset)
variable counter : integer range 0 to 7;
begin
if gls_reset = '1' then
--Return to the waiting state
state_anybus <= init_anybus;
counter := 0;
com_in_progress <= '0';
message_data <= (others => '0');
message_addr <= (others => '0');
DATA_READ_REG <= (others => '0');
elsif rising_edge(gls_clk) then
case state_anybus is
when init_anybus =>
counter := 0;
com_in_progress <= '0';
if (communication_error = '0' and (CONTROL_REG(1) or CONTROL_REG(2)) = '1') then
state_anybus <= start;
end if;
message_data <= DATA_WRITE_REG(7 downto 0);
message_addr <= ADDRESS_REG(11 downto 0);
when start =>
com_in_progress <= '1';
if CONTROL_REG(1) = '1' then
state_anybus <= write;
elsif CONTROL_REG(2) = '1' then
state_anybus <= read;
end if;
--Write
when write =>
if counter + 1 < wait_clock_cycles then
counter := counter + 1;
else
state_anybus <= end_write;
end if;
when end_write =>
state_anybus <= init_anybus;
--read
when read =>
if counter + 1 < wait_clock_cycles then
counter := counter + 1;
else
state_anybus <= end_read;
end if;
DATA_READ_REG(7 downto 0) <= anybus_interface_data;
when end_read =>
state_anybus <= init_anybus;
DATA_READ_REG(7 downto 0) <= anybus_interface_data;
when others =>
state_anybus <= init_anybus;
end case;
end if;
end process fsm_anybus;
--Anybus IO interface
anybus_interface_addr(10 downto 0) <= message_addr(10 downto 0);
anybus_interface_addr(11) <= '1';
anybus_interface_data <= message_data(7 downto 0) when state_anybus = write or state_anybus = end_write else
(others => 'Z');
anybus_interface_oe <= '0' when state_anybus = read or state_anybus = end_read else
'1';
anybus_interface_rw <= '0' when state_anybus = write else
'1';
anybus_interface_ce <= '1' when state_anybus = init_anybus or state_anybus = end_read else
'0';
--Wishbone interface
CONTROL_REG(0) <= communication_error;
CONTROL_REG(1) <= transmission;
CONTROL_REG(2) <= reception;
CONTROL_REG(5 downto 3) <= std_logic_vector(to_unsigned(wait_clock_cycles,3));
CONTROL_REG(15 downto 6) <= (others => '0');
wbs_readdata(wb_size-1 downto 0) <= std_logic_vector(to_unsigned(ID, wb_size)) when wbs_add = "00" else
CONTROL_REG when wbs_add = "01" else
ADDRESS_REG when wbs_add = "10" else
DATA_READ_REG when wbs_add = "11" and com_in_progress = '0' else
(others => '0');
wbs_ack <= '1' when state_wb = read_register or state_wb = write_register else
'0';
end architecture anybus_interface_arch;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_BIT.ALL;
library config;
use work.config.all;
entity ALU is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end ALU;
architecture Behavioral of ALU is
-- component declaration
component Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end component;
-- Signals and constants
constant all_bits_set : doubleword := (others => '1');
signal result: doubleword;
signal feedback: std_logic_vector(2 downto 0); -- (Error, Overflow, Zero)
signal mul_reg: std_logic_vector(127 downto 0);
signal mul_reg_plus: std_logic_vector(129 downto 0); -- Special case for MULSHU
signal add_word: doubleword;
-- Shift unit signals
signal s_shift_amt: std_logic_vector(5 downto 0);
signal s_shift_arg: doubleword;
signal s_shift_result: doubleword;
begin
-- Instantiation
myShifter : Shifter
port map(
clk => clk,
rst => rst,
ctrl => ctrl,
i_a1 => s_shift_arg, -- Operand 1
i_a2 => s_shift_amt, -- Shift bits number
result => s_shift_result
);
process(clk, rst)
-- variable shift_limit: natural;;
begin
-- shift_arg <= to_integer(unsigned(shamt));
feedback <= "000";
if(rising_edge(clk)) then
if('0' = halt) then
if('1' = rst) then
result <= (others => '0');
else
case ctrl is
-- Treat as 32-bit operands
when instr_SLL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
-- shift_limit := to_integer(unsigned(shamt));
-- result <= zero_word & rs1(31 - shift_limit downto 0) & zero_word(shift_limit-1 downto 0);
when instr_SRL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRA =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADD =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
when instr_ADDI =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_SUB =>
result <= std_logic_vector(signed(rs1) - signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_LUI =>
-- In brief: rd = sign_extend(rsimm20 << 12)
-- Load low 20 of immediate value shifted left 12
-- sign extend to fit 64 bit system
result(31 downto 0) <= rs2(19 downto 0) & "000000000000";
result(63 downto 32) <= (others => rs2(19));
when instr_AUIPC =>
-- TODO verify that PC can easily be passed in here as arg 1
-- In brief: rd = PC + (rs << 12)
-- Load 20 MSBs of low word with low 20 of immediate value
-- sign extend (rs << 12) to fit 64 bit
-- NOTE: Here, we use a "qualified expression" to hint at how the compiler should resolve
-- the ambiguity. We give a hint as to which overloaded function should be used,
-- in this case, the one that takes in a bit vector constant and a std_logic_vector
-- and returns a std_logic_vector.
--auipc_ext(31 downto 0) := std_logic_vector'(rs2(19 downto 0) & "000000000000");
result <= std_logic_vector(signed(rs1) + signed(std_logic_vector'(rs2(19 downto 0) & "000000000000")));
when instr_XOR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_XORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_OR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_ORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_AND =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_ANDI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_SLT =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTI =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTIU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLLW =>
-- Since these are word operations instead of double
-- word operations, only use the bottom 5 bits instead of 6
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADDW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_ADDIW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_SUBW =>
add_word <= std_logic_vector(signed(rs1) - signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_MUL =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= mul_reg(63 downto 0);
when instr_MULH =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= zero_word & mul_reg(63 downto 32);
when instr_MULHU =>
mul_reg <= std_logic_vector(unsigned(rs1) * unsigned(rs2));
result <= zero_word & mul_reg(63 downto 32);
--when instr_MULHSU =>
-- TODO - verify that this multiplier does not introduce problems on the schematic/layout
--mul_reg_plus <= std_logic_vector(signed(rs1(31) & rs1) * signed('0' & rs2));
--result <= zero_word & mul_reg_plus(63 downto 32);
--
-- Special Values for Divide by Zero and Division Overflow (per 2.2 spec)
-- Situation || Special Return Values for Each Instruction
-- <condition> <Dividend> <Divisor> || <DIVU> <REMU> <DIV> <REM>
-- Divide by 0 x 0 || All bits set x -1 x
-- Overflow -(2^64 -1) -1 || N/A N/A -(2^(64-1)) 0
--
when instr_DIV =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set only MSB
mul_reg <= (63 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) / signed(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_DIVU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) / unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_REM =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) rem signed(rs2));
end if;
result(31 downto 0) <= mul_reg(31 downto 0);
result(63 downto 32) <= (others => mul_reg(31));
when instr_REMU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) rem unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_MULW =>
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) * signed(rs2(31 downto 0)));
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set only MSB
mul_reg <= (31 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) / signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) / unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) rem signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) rem unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when others =>
-- Error condition: unknown control code
feedback(0) <= '1';
result <= (others => '0');
end case;
end if; -- Reset
end if; -- Halt
end if; -- Clock
end process;
error <= feedback(0); -- TODO feedback single bit for error conditions.
overflow <= feedback(1);-- TODO check here, remove from logic above
zero <= '1' when (0 = unsigned(result)) else '0';
rout <= result;
end Behavioral; |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_auto_pc_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end zynq_design_1_auto_pc_0;
architecture stub of zynq_design_1_auto_pc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:07 wig Exp $
-- $Date: 2004/08/18 10:47:07 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:07 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
;
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
;
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity selectresult is
port(
mem_result : in std_logic_vector(7 downto 0);
alu_result : in std_logic_vector(7 downto 0);
select_op : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0));
end selectresult;
architecture mixed of selectresult is
begin
process(select_op, mem_result, alu_result)
begin
case select_op is
when "10" =>
result_out <= mem_result;
when others =>
result_out <= alu_result;
end case;
end process;
end mixed;
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity datamux is
port(
alu_memdata:in std_logic_vector(7 downto 0);
intrhandler_data:in std_logic_vector(7 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(7 downto 0));
end datamux;
architecture mixed of datamux is
begin
process(alu_memdata, sel, intrhandler_data)
begin
case sel is
when '1' =>
data_out <= intrhandler_data;
when others =>
data_out <= alu_memdata;
end case;
end process;
end mixed;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity writemux is
port(
dec_wr:in std_logic_vector(3 downto 0);
intr_wr:in std_logic_vector(3 downto 0);
sel: in std_logic;
wr_out: out std_logic_vector(3 downto 0));
end writemux;
architecture mixed of writemux is
begin
process(dec_wr, intr_wr, sel)
begin
case sel is
when '1' =>
wr_out <= intr_wr;
when others =>
wr_out <= dec_wr;
end case;
end process;
end mixed;
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity readmux is
port(
dec_raddr1:in std_logic_vector(3 downto 0);
dec_raddr2:in std_logic_vector(3 downto 0);
intr_raddr1:in std_logic_vector(3 downto 0);
intr_raddr2:in std_logic_vector(3 downto 0);
sel: in std_logic;
out_raddr1: out std_logic_vector(3 downto 0);
out_raddr2: out std_logic_vector(3 downto 0));
end readmux;
architecture mixed of readmux is
begin
process(dec_raddr1, dec_raddr2, intr_raddr1, intr_raddr2, sel)
begin
case sel is
when '1' =>
out_raddr1 <= intr_raddr1;
out_raddr2 <= intr_raddr2;
when others =>
out_raddr1 <= dec_raddr1;
out_raddr2 <= dec_raddr2;
end case;
end process;
end mixed;
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity enable_mux is
port (
processor_en, sel : in std_logic;
en_out : out std_logic
);
end entity;
architecture behav of enable_mux is
begin
process(processor_en, sel)
begin
case sel is
when '1' =>
en_out <= '1';
when others =>
en_out <= processor_en;
end case;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1936.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01936ent IS
END c07s02b01x00p01n04i01936ent;
ARCHITECTURE c07s02b01x00p01n04i01936arch OF c07s02b01x00p01n04i01936ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x xor y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01936 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01936arch;
|
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