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-- whole_design.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Integrates ledblinker and freq_controller.
library ieee;
use ieee.std_logic_1164.all;
entity whole_design is
generic(RSTDEF: std_logic := '0'); -- reset button is low active
port(rst: in std_logic; -- reset, RESTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
led: out std_logic; -- LED status, active high
freq: out std_logic_vector(2 downto 0)); -- blinking frequency, 000 = stop, 111 = fast
end whole_design;
architecture behavioral of whole_design is
component ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
freq: in std_logic_vector(2 downto 0); -- blinking frequency, 000 = stop, 111 = fast
led: out std_logic); -- LED status, active high
end component;
component freq_controller is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
freq: out std_logic_vector(2 downto 0)); -- frequency, 000 = stop, 111 = fast
end component;
-- signal to connect freq, ledblinker and freq_controller
signal freq_tmp: std_logic_vector(2 downto 0) := (others => '0');
begin
-- connect freq_tmp to out port freq
freq <= freq_tmp;
-- connect freq of ledblinker to freq_tmp (read)
lblink: ledblinker
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
freq => freq_tmp,
led => led);
-- connect freq of freq_controlelr to freq_tmp (write)
fcontr : freq_controller
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
btn0 => btn0,
btn1 => btn1,
freq => freq_tmp);
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_ctrl is
generic (
Nangle : natural := 16
);
port (
clock : in std_logic;
write_rst_i: in std_logic;
read_rst_i : in std_logic;
sw_x_pos, sw_x_neg: in std_logic;
sw_y_pos, sw_y_neg: in std_logic;
sw_z_pos, sw_z_neg: in std_logic;
delta_angle: in std_logic_vector(Nangle-1 downto 0);
alfa, beta, gama: out std_logic_vector(Nangle-1 downto 0);
clear_reset, clear_enable: out std_logic;
clear_stop: in std_logic;
read_start: out std_logic;
read_stop: in std_logic;
read_reset_out, write_reset_out: out std_logic;
vga_start, vga_stop: in std_logic
);
end;
architecture global_ctrl_arq of global_ctrl is
type t_estado is (IDLE, CLEARING, READING, REFRESHING);
signal estado : t_estado := IDLE;
type t_subestado is (WAITING, REFRESHING);
signal refresh_subestado : t_subestado := WAITING;
signal ctrl_alfa, ctrl_beta, ctrl_gama : std_logic_vector(1 downto 0) := (others => '0');
signal alfa_aux, beta_aux, gama_aux: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal delta_alfa, delta_beta, delta_gama: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal minus_delta_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal button_down : std_logic := '0';
begin
button_down <= (sw_x_pos or sw_x_neg or
sw_y_pos or sw_y_neg or
sw_z_pos or sw_z_neg or
write_rst_i or read_rst_i);
--button_down <= ( (sw_x_pos XOR sw_x_neg) OR (sw_y_pos XOR sw_y_neg) OR (sw_z_pos XOR sw_z_neg)
-- OR write_rst_i OR read_rst_i );
clear_enable <= '1' when (estado = CLEARING) else '0';
read_reset_out <= '1' when (estado = CLEARING) else '0';
read_start <= '1' when (estado = READING) else '0';
write_reset_out <= write_rst_i;
process(clock, button_down)
begin
if rising_edge(clock) then
case estado is
when IDLE =>
refresh_subestado <= WAITING;
if button_down = '1' then
estado <= CLEARING;
clear_reset <= '0';
end if;
-- Borro la memoria de video
when CLEARING =>
if clear_stop = '1' then
clear_reset <= '1';
estado <= READING;
end if;
-- Leo los nuevos datos
when READING =>
clear_reset <= '0';
if read_stop = '1' then
estado <= REFRESHING;
end if;
-- Espero a que refresque la pantalla con los nuevos datos leídos
when REFRESHING =>
clear_reset <= '0';
case refresh_subestado is
when WAITING =>
if vga_start = '1' then
refresh_subestado <= REFRESHING;
-- else refresh_subestado <= WAITING;
end if;
when REFRESHING =>
if vga_stop = '1' then
estado <= IDLE;
refresh_subestado <= WAITING;
-- else
-- refresh_subestado <= REFRESHING;
end if;
end case;
end case;
end if;
end process;
-- Ángulos
-- Ctrl +/- (selector del mux)
ctrl_alfa <= sw_x_pos & sw_x_neg;
ctrl_beta <= sw_y_pos & sw_y_neg;
ctrl_gama <= sw_z_pos & sw_z_neg;
-- Menos delta (-delta)
minus_delta_angle <= std_logic_vector(unsigned(not delta_angle) + 1);
-- Mux
delta_alfa <= delta_angle when ctrl_alfa = "10" else
minus_delta_angle when ctrl_alfa = "01" else
(others => '0');
delta_beta <= delta_angle when ctrl_beta = "10" else
minus_delta_angle when ctrl_beta = "01" else
(others => '0');
delta_gama <= delta_angle when ctrl_gama = "10" else
minus_delta_angle when ctrl_gama = "01" else
(others => '0');
alfa <= alfa_aux;
beta <= beta_aux;
gama <= gama_aux;
-- Acumulador de ángulos
process(clock, estado)
begin
if rising_edge(clock) then
if estado = IDLE then
alfa_aux <= std_logic_vector( unsigned(alfa_aux) + unsigned(delta_alfa) );
beta_aux <= std_logic_vector( unsigned(beta_aux) + unsigned(delta_beta) );
gama_aux <= std_logic_vector( unsigned(gama_aux) + unsigned(delta_gama) );
end if;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
-- #############################################################################
-- DE0_Nano_SoC_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.0
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_top_level is
port(
-- ADC
-- ADC_CONVST : out std_logic;
-- ADC_SCK : out std_logic;
-- ADC_SDI : out std_logic;
-- ADC_SDO : in std_logic;
-- ARDUINO
-- ARDUINO_IO : inout std_logic_vector(15 downto 0);
-- ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
-- FPGA_CLK2_50 : in std_logic;
-- FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
-- SW : in std_logic_vector(3 downto 0);
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_top_level;
architecture rtl of DE0_Nano_SoC_top_level is
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0);
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0);
hps_0_ddr_mem_ck : out std_logic;
hps_0_ddr_mem_ck_n : out std_logic;
hps_0_ddr_mem_cke : out std_logic;
hps_0_ddr_mem_cs_n : out std_logic;
hps_0_ddr_mem_ras_n : out std_logic;
hps_0_ddr_mem_cas_n : out std_logic;
hps_0_ddr_mem_we_n : out std_logic;
hps_0_ddr_mem_reset_n : out std_logic;
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_odt : out std_logic;
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0);
hps_0_ddr_oct_rzqin : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
hps_fpga_leds_external_connection_export : out std_logic_vector(3 downto 0);
nios_leds_external_connection_export : out std_logic_vector(3 downto 0);
reset_reset_n : in std_logic := 'X'
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => FPGA_CLK1_50,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_fpga_leds_external_connection_export => LED(7 downto 4),
nios_leds_external_connection_export => LED(3 downto 0),
reset_reset_n => KEY_N(0)
);
end;
|
-- $Id: tbd_rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_sp1c - syn
-- Description: Wrapper for rlink_core plus rlink_serport with an interface
-- compatible to the rlink_core only module.
-- NOTE: this implementation is a hack, should be redone
-- using configurations.
--
-- Dependencies: tbu_rlink_sp1c [UUT]
-- serport_uart_tx
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
-- simlib/simclkcnt
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-28 588 4.0 use new rlink v4 iface and 4 bit STAT
-- 2011-12-23 444 3.2 use simclkcnt instead of simbus global
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_;
-- 2010-12-24 347 3.0.2 rename: CP_*->RL->*
-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again
-- 2010-04-03 274 2.2 add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport;
-- use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.comlib.all;
use work.serportlib.all;
use work.simlib.all;
use work.simbus.all;
entity tbd_rlink_sp1c is -- rlink_sp1c tb design
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_sp1c;
architecture syn of tbd_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !!
signal RRI_RXSD : slbit := '0';
signal RRI_TXSD : slbit := '0';
signal RTS_N : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
signal CLK_CYCLE : integer := 0;
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
begin
TBU : tbu_rlink_sp1c
port map (
CLK => CLK,
CE_INT => CE_INT,
CE_USEC => CE_USEC,
CE_MSEC => '1',
RESET => RESET,
RXSD => RRI_RXSD,
TXSD => RRI_TXSD,
CTS_N => '0',
RTS_N => RTS_N,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UARTRX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RRI_TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => open,
RXACT => RXACT
);
UARTTX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => RRI_RXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
TXRXACT <= RXACT or TXBUSY;
B2CD : byte2cdata -- byte stream -> 9bit comma,data
port map (
CLK => CLK,
RESET => RESET,
DI => RXDATA,
ENA => RXVAL,
ERR => '0',
BUSY => open,
DO => RL_DO,
VAL => RL_VAL,
HOLD => RL_HOLD
);
CD2B : cdata2byte -- 9bit comma,data -> byte stream
port map (
CLK => CLK,
RESET => RESET,
ESCXON => '0',
ESCFILL => '0',
DI => RL_DI,
ENA => RL_ENA,
BUSY => RL_BUSY,
DO => TXDATA,
VAL => TXENA,
HOLD => TXBUSY
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
variable ncycle : integer := 0;
begin
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, CLK_CYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
write(oline, RTS_N, right, 1);
write(oline, string'(" after "));
write(oline, ncycle, right, 5);
write(oline, string'(" cycles"));
writeline(output, oline);
rts_last := RTS_N;
ncycle := 0;
end if;
ncycle := ncycle + 1;
end loop;
end process proc_moni;
end syn;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 15;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
contact_in_ce0 :in STD_LOGIC;
contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
database_in_ce0 :in STD_LOGIC;
database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
matched_out_address0 :in STD_LOGIC_VECTOR(12 downto 0);
matched_out_ce0 :in STD_LOGIC;
matched_out_we0 :in STD_LOGIC;
matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0);
matched_finished :in STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
database_size_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0000 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x0004 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x0008 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x000c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0010 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x0014 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x4000 : Data signal of matched_finished
-- bit 31~0 - matched_finished[31:0] (Read)
-- 0x4004 : reserved
-- 0x4008 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x400c : reserved
-- 0x4010 : Data signal of database_size_out
-- bit 31~0 - database_size_out[31:0] (Read)
-- 0x4014 : reserved
-- 0x4018 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x401c : reserved
-- 0x0040 ~
-- 0x007f : Memory 'contact_in' (64 * 8b)
-- Word n : bit [ 7: 0] - contact_in[4n]
-- bit [15: 8] - contact_in[4n+1]
-- bit [23:16] - contact_in[4n+2]
-- bit [31:24] - contact_in[4n+3]
-- 0x0080 ~
-- 0x00bf : Memory 'database_in' (64 * 8b)
-- Word n : bit [ 7: 0] - database_in[4n]
-- bit [15: 8] - database_in[4n+1]
-- bit [23:16] - database_in[4n+2]
-- bit [31:24] - database_in[4n+3]
-- 0x2000 ~
-- 0x3fff : Memory 'matched_out' (7500 * 1b)
-- Word n : bit [ 0: 0] - matched_out[4n]
-- bit [ 8: 8] - matched_out[4n+1]
-- bit [16:16] - matched_out[4n+2]
-- bit [24:24] - matched_out[4n+3]
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0000#;
constant ADDR_GIE : INTEGER := 16#0004#;
constant ADDR_IER : INTEGER := 16#0008#;
constant ADDR_ISR : INTEGER := 16#000c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#0010#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#0014#;
constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#4000#;
constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#4004#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#4008#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#400c#;
constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#4010#;
constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#4014#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#4018#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#401c#;
constant ADDR_CONTACT_IN_BASE : INTEGER := 16#0040#;
constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#007f#;
constant ADDR_DATABASE_IN_BASE : INTEGER := 16#0080#;
constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#00bf#;
constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#2000#;
constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3fff#;
constant ADDR_BITS : INTEGER := 15;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
-- memory signals
signal int_contact_in_address0 : UNSIGNED(3 downto 0);
signal int_contact_in_ce0 : STD_LOGIC;
signal int_contact_in_we0 : STD_LOGIC;
signal int_contact_in_be0 : UNSIGNED(3 downto 0);
signal int_contact_in_d0 : UNSIGNED(31 downto 0);
signal int_contact_in_q0 : UNSIGNED(31 downto 0);
signal int_contact_in_address1 : UNSIGNED(3 downto 0);
signal int_contact_in_ce1 : STD_LOGIC;
signal int_contact_in_we1 : STD_LOGIC;
signal int_contact_in_be1 : UNSIGNED(3 downto 0);
signal int_contact_in_d1 : UNSIGNED(31 downto 0);
signal int_contact_in_q1 : UNSIGNED(31 downto 0);
signal int_contact_in_read : STD_LOGIC;
signal int_contact_in_write : STD_LOGIC;
signal int_contact_in_shift : UNSIGNED(1 downto 0);
signal int_database_in_address0 : UNSIGNED(3 downto 0);
signal int_database_in_ce0 : STD_LOGIC;
signal int_database_in_we0 : STD_LOGIC;
signal int_database_in_be0 : UNSIGNED(3 downto 0);
signal int_database_in_d0 : UNSIGNED(31 downto 0);
signal int_database_in_q0 : UNSIGNED(31 downto 0);
signal int_database_in_address1 : UNSIGNED(3 downto 0);
signal int_database_in_ce1 : STD_LOGIC;
signal int_database_in_we1 : STD_LOGIC;
signal int_database_in_be1 : UNSIGNED(3 downto 0);
signal int_database_in_d1 : UNSIGNED(31 downto 0);
signal int_database_in_q1 : UNSIGNED(31 downto 0);
signal int_database_in_read : STD_LOGIC;
signal int_database_in_write : STD_LOGIC;
signal int_database_in_shift : UNSIGNED(1 downto 0);
signal int_matched_out_address0 : UNSIGNED(10 downto 0);
signal int_matched_out_ce0 : STD_LOGIC;
signal int_matched_out_we0 : STD_LOGIC;
signal int_matched_out_be0 : UNSIGNED(3 downto 0);
signal int_matched_out_d0 : UNSIGNED(31 downto 0);
signal int_matched_out_q0 : UNSIGNED(31 downto 0);
signal int_matched_out_address1 : UNSIGNED(10 downto 0);
signal int_matched_out_ce1 : STD_LOGIC;
signal int_matched_out_we1 : STD_LOGIC;
signal int_matched_out_be1 : UNSIGNED(3 downto 0);
signal int_matched_out_d1 : UNSIGNED(31 downto 0);
signal int_matched_out_q1 : UNSIGNED(31 downto 0);
signal int_matched_out_read : STD_LOGIC;
signal int_matched_out_write : STD_LOGIC;
signal int_matched_out_shift : UNSIGNED(1 downto 0);
component contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component contact_discovery_AXILiteS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_contact_in
int_contact_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_contact_in_address0,
ce0 => int_contact_in_ce0,
we0 => int_contact_in_we0,
be0 => int_contact_in_be0,
d0 => int_contact_in_d0,
q0 => int_contact_in_q0,
clk1 => ACLK,
address1 => int_contact_in_address1,
ce1 => int_contact_in_ce1,
we1 => int_contact_in_we1,
be1 => int_contact_in_be1,
d1 => int_contact_in_d1,
q1 => int_contact_in_q1);
-- int_database_in
int_database_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_database_in_address0,
ce0 => int_database_in_ce0,
we0 => int_database_in_we0,
be0 => int_database_in_be0,
d0 => int_database_in_d0,
q0 => int_database_in_q0,
clk1 => ACLK,
address1 => int_database_in_address1,
ce1 => int_database_in_ce1,
we1 => int_database_in_we1,
be1 => int_database_in_be1,
d1 => int_database_in_d1,
q1 => int_database_in_q1);
-- int_matched_out
int_matched_out : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 1875,
AWIDTH => log2(1875))
port map (
clk0 => ACLK,
address0 => int_matched_out_address0,
ce0 => int_matched_out_ce0,
we0 => int_matched_out_we0,
be0 => int_matched_out_be0,
d0 => int_matched_out_d0,
q0 => int_matched_out_q0,
clk1 => ACLK,
address1 => int_matched_out_address1,
ce1 => int_matched_out_ce1,
we1 => int_matched_out_we1,
be1 => int_matched_out_be1,
d1 => int_matched_out_d1,
q1 => int_matched_out_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_MATCHED_FINISHED_DATA_0 =>
rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_DATABASE_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
elsif (int_contact_in_read = '1') then
rdata_data <= int_contact_in_q1;
elsif (int_database_in_read = '1') then
rdata_data <= int_database_in_q1;
elsif (int_matched_out_read = '1') then
rdata_data <= int_matched_out_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_finished <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_matched_finished <= UNSIGNED(matched_finished); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_database_size_out <= UNSIGNED(database_size_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
-- contact_in
int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0);
int_contact_in_ce0 <= contact_in_ce0;
int_contact_in_we0 <= '0';
int_contact_in_be0 <= (others => '0');
int_contact_in_d0 <= (others => '0');
contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0));
int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0';
int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0';
int_contact_in_be1 <= UNSIGNED(WSTRB);
int_contact_in_d1 <= UNSIGNED(WDATA);
-- database_in
int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0);
int_database_in_ce0 <= database_in_ce0;
int_database_in_we0 <= '0';
int_database_in_be0 <= (others => '0');
int_database_in_d0 <= (others => '0');
database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0));
int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0';
int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0';
int_database_in_be1 <= UNSIGNED(WSTRB);
int_database_in_d1 <= UNSIGNED(WDATA);
-- matched_out
int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(10 downto 0);
int_matched_out_ce0 <= matched_out_ce0;
int_matched_out_we0 <= matched_out_we0;
int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0))));
int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8));
int_matched_out_address1 <= raddr(12 downto 2) when ar_hs = '1' else waddr(12 downto 2);
int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0';
int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0';
int_matched_out_be1 <= UNSIGNED(WSTRB);
int_matched_out_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_read <= '1';
else
int_contact_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_write <= '1';
elsif (WVALID = '1') then
int_contact_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (contact_in_ce0 = '1') then
int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then
int_database_in_read <= '1';
else
int_database_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then
int_database_in_write <= '1';
elsif (WVALID = '1') then
int_database_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (database_in_ce0 = '1') then
int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_read <= '1';
else
int_matched_out_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_write <= '1';
elsif (WVALID = '1') then
int_matched_out_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (matched_out_ce0 = '1') then
int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity contact_discovery_AXILiteS_s_axi_ram;
architecture behave of contact_discovery_AXILiteS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 15;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
contact_in_ce0 :in STD_LOGIC;
contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
database_in_ce0 :in STD_LOGIC;
database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
matched_out_address0 :in STD_LOGIC_VECTOR(12 downto 0);
matched_out_ce0 :in STD_LOGIC;
matched_out_we0 :in STD_LOGIC;
matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0);
matched_finished :in STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
database_size_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0000 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x0004 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x0008 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x000c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0010 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x0014 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x4000 : Data signal of matched_finished
-- bit 31~0 - matched_finished[31:0] (Read)
-- 0x4004 : reserved
-- 0x4008 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x400c : reserved
-- 0x4010 : Data signal of database_size_out
-- bit 31~0 - database_size_out[31:0] (Read)
-- 0x4014 : reserved
-- 0x4018 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x401c : reserved
-- 0x0040 ~
-- 0x007f : Memory 'contact_in' (64 * 8b)
-- Word n : bit [ 7: 0] - contact_in[4n]
-- bit [15: 8] - contact_in[4n+1]
-- bit [23:16] - contact_in[4n+2]
-- bit [31:24] - contact_in[4n+3]
-- 0x0080 ~
-- 0x00bf : Memory 'database_in' (64 * 8b)
-- Word n : bit [ 7: 0] - database_in[4n]
-- bit [15: 8] - database_in[4n+1]
-- bit [23:16] - database_in[4n+2]
-- bit [31:24] - database_in[4n+3]
-- 0x2000 ~
-- 0x3fff : Memory 'matched_out' (7500 * 1b)
-- Word n : bit [ 0: 0] - matched_out[4n]
-- bit [ 8: 8] - matched_out[4n+1]
-- bit [16:16] - matched_out[4n+2]
-- bit [24:24] - matched_out[4n+3]
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0000#;
constant ADDR_GIE : INTEGER := 16#0004#;
constant ADDR_IER : INTEGER := 16#0008#;
constant ADDR_ISR : INTEGER := 16#000c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#0010#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#0014#;
constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#4000#;
constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#4004#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#4008#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#400c#;
constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#4010#;
constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#4014#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#4018#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#401c#;
constant ADDR_CONTACT_IN_BASE : INTEGER := 16#0040#;
constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#007f#;
constant ADDR_DATABASE_IN_BASE : INTEGER := 16#0080#;
constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#00bf#;
constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#2000#;
constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3fff#;
constant ADDR_BITS : INTEGER := 15;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
-- memory signals
signal int_contact_in_address0 : UNSIGNED(3 downto 0);
signal int_contact_in_ce0 : STD_LOGIC;
signal int_contact_in_we0 : STD_LOGIC;
signal int_contact_in_be0 : UNSIGNED(3 downto 0);
signal int_contact_in_d0 : UNSIGNED(31 downto 0);
signal int_contact_in_q0 : UNSIGNED(31 downto 0);
signal int_contact_in_address1 : UNSIGNED(3 downto 0);
signal int_contact_in_ce1 : STD_LOGIC;
signal int_contact_in_we1 : STD_LOGIC;
signal int_contact_in_be1 : UNSIGNED(3 downto 0);
signal int_contact_in_d1 : UNSIGNED(31 downto 0);
signal int_contact_in_q1 : UNSIGNED(31 downto 0);
signal int_contact_in_read : STD_LOGIC;
signal int_contact_in_write : STD_LOGIC;
signal int_contact_in_shift : UNSIGNED(1 downto 0);
signal int_database_in_address0 : UNSIGNED(3 downto 0);
signal int_database_in_ce0 : STD_LOGIC;
signal int_database_in_we0 : STD_LOGIC;
signal int_database_in_be0 : UNSIGNED(3 downto 0);
signal int_database_in_d0 : UNSIGNED(31 downto 0);
signal int_database_in_q0 : UNSIGNED(31 downto 0);
signal int_database_in_address1 : UNSIGNED(3 downto 0);
signal int_database_in_ce1 : STD_LOGIC;
signal int_database_in_we1 : STD_LOGIC;
signal int_database_in_be1 : UNSIGNED(3 downto 0);
signal int_database_in_d1 : UNSIGNED(31 downto 0);
signal int_database_in_q1 : UNSIGNED(31 downto 0);
signal int_database_in_read : STD_LOGIC;
signal int_database_in_write : STD_LOGIC;
signal int_database_in_shift : UNSIGNED(1 downto 0);
signal int_matched_out_address0 : UNSIGNED(10 downto 0);
signal int_matched_out_ce0 : STD_LOGIC;
signal int_matched_out_we0 : STD_LOGIC;
signal int_matched_out_be0 : UNSIGNED(3 downto 0);
signal int_matched_out_d0 : UNSIGNED(31 downto 0);
signal int_matched_out_q0 : UNSIGNED(31 downto 0);
signal int_matched_out_address1 : UNSIGNED(10 downto 0);
signal int_matched_out_ce1 : STD_LOGIC;
signal int_matched_out_we1 : STD_LOGIC;
signal int_matched_out_be1 : UNSIGNED(3 downto 0);
signal int_matched_out_d1 : UNSIGNED(31 downto 0);
signal int_matched_out_q1 : UNSIGNED(31 downto 0);
signal int_matched_out_read : STD_LOGIC;
signal int_matched_out_write : STD_LOGIC;
signal int_matched_out_shift : UNSIGNED(1 downto 0);
component contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component contact_discovery_AXILiteS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_contact_in
int_contact_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_contact_in_address0,
ce0 => int_contact_in_ce0,
we0 => int_contact_in_we0,
be0 => int_contact_in_be0,
d0 => int_contact_in_d0,
q0 => int_contact_in_q0,
clk1 => ACLK,
address1 => int_contact_in_address1,
ce1 => int_contact_in_ce1,
we1 => int_contact_in_we1,
be1 => int_contact_in_be1,
d1 => int_contact_in_d1,
q1 => int_contact_in_q1);
-- int_database_in
int_database_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_database_in_address0,
ce0 => int_database_in_ce0,
we0 => int_database_in_we0,
be0 => int_database_in_be0,
d0 => int_database_in_d0,
q0 => int_database_in_q0,
clk1 => ACLK,
address1 => int_database_in_address1,
ce1 => int_database_in_ce1,
we1 => int_database_in_we1,
be1 => int_database_in_be1,
d1 => int_database_in_d1,
q1 => int_database_in_q1);
-- int_matched_out
int_matched_out : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 1875,
AWIDTH => log2(1875))
port map (
clk0 => ACLK,
address0 => int_matched_out_address0,
ce0 => int_matched_out_ce0,
we0 => int_matched_out_we0,
be0 => int_matched_out_be0,
d0 => int_matched_out_d0,
q0 => int_matched_out_q0,
clk1 => ACLK,
address1 => int_matched_out_address1,
ce1 => int_matched_out_ce1,
we1 => int_matched_out_we1,
be1 => int_matched_out_be1,
d1 => int_matched_out_d1,
q1 => int_matched_out_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_MATCHED_FINISHED_DATA_0 =>
rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_DATABASE_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
elsif (int_contact_in_read = '1') then
rdata_data <= int_contact_in_q1;
elsif (int_database_in_read = '1') then
rdata_data <= int_database_in_q1;
elsif (int_matched_out_read = '1') then
rdata_data <= int_matched_out_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_finished <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_matched_finished <= UNSIGNED(matched_finished); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_database_size_out <= UNSIGNED(database_size_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
-- contact_in
int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0);
int_contact_in_ce0 <= contact_in_ce0;
int_contact_in_we0 <= '0';
int_contact_in_be0 <= (others => '0');
int_contact_in_d0 <= (others => '0');
contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0));
int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0';
int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0';
int_contact_in_be1 <= UNSIGNED(WSTRB);
int_contact_in_d1 <= UNSIGNED(WDATA);
-- database_in
int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0);
int_database_in_ce0 <= database_in_ce0;
int_database_in_we0 <= '0';
int_database_in_be0 <= (others => '0');
int_database_in_d0 <= (others => '0');
database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0));
int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0';
int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0';
int_database_in_be1 <= UNSIGNED(WSTRB);
int_database_in_d1 <= UNSIGNED(WDATA);
-- matched_out
int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(10 downto 0);
int_matched_out_ce0 <= matched_out_ce0;
int_matched_out_we0 <= matched_out_we0;
int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0))));
int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8));
int_matched_out_address1 <= raddr(12 downto 2) when ar_hs = '1' else waddr(12 downto 2);
int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0';
int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0';
int_matched_out_be1 <= UNSIGNED(WSTRB);
int_matched_out_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_read <= '1';
else
int_contact_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_write <= '1';
elsif (WVALID = '1') then
int_contact_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (contact_in_ce0 = '1') then
int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then
int_database_in_read <= '1';
else
int_database_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then
int_database_in_write <= '1';
elsif (WVALID = '1') then
int_database_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (database_in_ce0 = '1') then
int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_read <= '1';
else
int_matched_out_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_write <= '1';
elsif (WVALID = '1') then
int_matched_out_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (matched_out_ce0 = '1') then
int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity contact_discovery_AXILiteS_s_axi_ram;
architecture behave of contact_discovery_AXILiteS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 15;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
contact_in_ce0 :in STD_LOGIC;
contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
database_in_ce0 :in STD_LOGIC;
database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
matched_out_address0 :in STD_LOGIC_VECTOR(12 downto 0);
matched_out_ce0 :in STD_LOGIC;
matched_out_we0 :in STD_LOGIC;
matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0);
matched_finished :in STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
database_size_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0000 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x0004 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x0008 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x000c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0010 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x0014 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x4000 : Data signal of matched_finished
-- bit 31~0 - matched_finished[31:0] (Read)
-- 0x4004 : reserved
-- 0x4008 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x400c : reserved
-- 0x4010 : Data signal of database_size_out
-- bit 31~0 - database_size_out[31:0] (Read)
-- 0x4014 : reserved
-- 0x4018 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x401c : reserved
-- 0x0040 ~
-- 0x007f : Memory 'contact_in' (64 * 8b)
-- Word n : bit [ 7: 0] - contact_in[4n]
-- bit [15: 8] - contact_in[4n+1]
-- bit [23:16] - contact_in[4n+2]
-- bit [31:24] - contact_in[4n+3]
-- 0x0080 ~
-- 0x00bf : Memory 'database_in' (64 * 8b)
-- Word n : bit [ 7: 0] - database_in[4n]
-- bit [15: 8] - database_in[4n+1]
-- bit [23:16] - database_in[4n+2]
-- bit [31:24] - database_in[4n+3]
-- 0x2000 ~
-- 0x3fff : Memory 'matched_out' (7500 * 1b)
-- Word n : bit [ 0: 0] - matched_out[4n]
-- bit [ 8: 8] - matched_out[4n+1]
-- bit [16:16] - matched_out[4n+2]
-- bit [24:24] - matched_out[4n+3]
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0000#;
constant ADDR_GIE : INTEGER := 16#0004#;
constant ADDR_IER : INTEGER := 16#0008#;
constant ADDR_ISR : INTEGER := 16#000c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#0010#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#0014#;
constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#4000#;
constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#4004#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#4008#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#400c#;
constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#4010#;
constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#4014#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#4018#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#401c#;
constant ADDR_CONTACT_IN_BASE : INTEGER := 16#0040#;
constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#007f#;
constant ADDR_DATABASE_IN_BASE : INTEGER := 16#0080#;
constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#00bf#;
constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#2000#;
constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3fff#;
constant ADDR_BITS : INTEGER := 15;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
-- memory signals
signal int_contact_in_address0 : UNSIGNED(3 downto 0);
signal int_contact_in_ce0 : STD_LOGIC;
signal int_contact_in_we0 : STD_LOGIC;
signal int_contact_in_be0 : UNSIGNED(3 downto 0);
signal int_contact_in_d0 : UNSIGNED(31 downto 0);
signal int_contact_in_q0 : UNSIGNED(31 downto 0);
signal int_contact_in_address1 : UNSIGNED(3 downto 0);
signal int_contact_in_ce1 : STD_LOGIC;
signal int_contact_in_we1 : STD_LOGIC;
signal int_contact_in_be1 : UNSIGNED(3 downto 0);
signal int_contact_in_d1 : UNSIGNED(31 downto 0);
signal int_contact_in_q1 : UNSIGNED(31 downto 0);
signal int_contact_in_read : STD_LOGIC;
signal int_contact_in_write : STD_LOGIC;
signal int_contact_in_shift : UNSIGNED(1 downto 0);
signal int_database_in_address0 : UNSIGNED(3 downto 0);
signal int_database_in_ce0 : STD_LOGIC;
signal int_database_in_we0 : STD_LOGIC;
signal int_database_in_be0 : UNSIGNED(3 downto 0);
signal int_database_in_d0 : UNSIGNED(31 downto 0);
signal int_database_in_q0 : UNSIGNED(31 downto 0);
signal int_database_in_address1 : UNSIGNED(3 downto 0);
signal int_database_in_ce1 : STD_LOGIC;
signal int_database_in_we1 : STD_LOGIC;
signal int_database_in_be1 : UNSIGNED(3 downto 0);
signal int_database_in_d1 : UNSIGNED(31 downto 0);
signal int_database_in_q1 : UNSIGNED(31 downto 0);
signal int_database_in_read : STD_LOGIC;
signal int_database_in_write : STD_LOGIC;
signal int_database_in_shift : UNSIGNED(1 downto 0);
signal int_matched_out_address0 : UNSIGNED(10 downto 0);
signal int_matched_out_ce0 : STD_LOGIC;
signal int_matched_out_we0 : STD_LOGIC;
signal int_matched_out_be0 : UNSIGNED(3 downto 0);
signal int_matched_out_d0 : UNSIGNED(31 downto 0);
signal int_matched_out_q0 : UNSIGNED(31 downto 0);
signal int_matched_out_address1 : UNSIGNED(10 downto 0);
signal int_matched_out_ce1 : STD_LOGIC;
signal int_matched_out_we1 : STD_LOGIC;
signal int_matched_out_be1 : UNSIGNED(3 downto 0);
signal int_matched_out_d1 : UNSIGNED(31 downto 0);
signal int_matched_out_q1 : UNSIGNED(31 downto 0);
signal int_matched_out_read : STD_LOGIC;
signal int_matched_out_write : STD_LOGIC;
signal int_matched_out_shift : UNSIGNED(1 downto 0);
component contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component contact_discovery_AXILiteS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_contact_in
int_contact_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_contact_in_address0,
ce0 => int_contact_in_ce0,
we0 => int_contact_in_we0,
be0 => int_contact_in_be0,
d0 => int_contact_in_d0,
q0 => int_contact_in_q0,
clk1 => ACLK,
address1 => int_contact_in_address1,
ce1 => int_contact_in_ce1,
we1 => int_contact_in_we1,
be1 => int_contact_in_be1,
d1 => int_contact_in_d1,
q1 => int_contact_in_q1);
-- int_database_in
int_database_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_database_in_address0,
ce0 => int_database_in_ce0,
we0 => int_database_in_we0,
be0 => int_database_in_be0,
d0 => int_database_in_d0,
q0 => int_database_in_q0,
clk1 => ACLK,
address1 => int_database_in_address1,
ce1 => int_database_in_ce1,
we1 => int_database_in_we1,
be1 => int_database_in_be1,
d1 => int_database_in_d1,
q1 => int_database_in_q1);
-- int_matched_out
int_matched_out : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 1875,
AWIDTH => log2(1875))
port map (
clk0 => ACLK,
address0 => int_matched_out_address0,
ce0 => int_matched_out_ce0,
we0 => int_matched_out_we0,
be0 => int_matched_out_be0,
d0 => int_matched_out_d0,
q0 => int_matched_out_q0,
clk1 => ACLK,
address1 => int_matched_out_address1,
ce1 => int_matched_out_ce1,
we1 => int_matched_out_we1,
be1 => int_matched_out_be1,
d1 => int_matched_out_d1,
q1 => int_matched_out_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_MATCHED_FINISHED_DATA_0 =>
rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_DATABASE_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
elsif (int_contact_in_read = '1') then
rdata_data <= int_contact_in_q1;
elsif (int_database_in_read = '1') then
rdata_data <= int_database_in_q1;
elsif (int_matched_out_read = '1') then
rdata_data <= int_matched_out_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_finished <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_matched_finished <= UNSIGNED(matched_finished); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_database_size_out <= UNSIGNED(database_size_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
-- contact_in
int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0);
int_contact_in_ce0 <= contact_in_ce0;
int_contact_in_we0 <= '0';
int_contact_in_be0 <= (others => '0');
int_contact_in_d0 <= (others => '0');
contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0));
int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0';
int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0';
int_contact_in_be1 <= UNSIGNED(WSTRB);
int_contact_in_d1 <= UNSIGNED(WDATA);
-- database_in
int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0);
int_database_in_ce0 <= database_in_ce0;
int_database_in_we0 <= '0';
int_database_in_be0 <= (others => '0');
int_database_in_d0 <= (others => '0');
database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0));
int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0';
int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0';
int_database_in_be1 <= UNSIGNED(WSTRB);
int_database_in_d1 <= UNSIGNED(WDATA);
-- matched_out
int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(10 downto 0);
int_matched_out_ce0 <= matched_out_ce0;
int_matched_out_we0 <= matched_out_we0;
int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0))));
int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8));
int_matched_out_address1 <= raddr(12 downto 2) when ar_hs = '1' else waddr(12 downto 2);
int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0';
int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0';
int_matched_out_be1 <= UNSIGNED(WSTRB);
int_matched_out_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_read <= '1';
else
int_contact_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_write <= '1';
elsif (WVALID = '1') then
int_contact_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (contact_in_ce0 = '1') then
int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then
int_database_in_read <= '1';
else
int_database_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then
int_database_in_write <= '1';
elsif (WVALID = '1') then
int_database_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (database_in_ce0 = '1') then
int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_read <= '1';
else
int_matched_out_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_write <= '1';
elsif (WVALID = '1') then
int_matched_out_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (matched_out_ce0 = '1') then
int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity contact_discovery_AXILiteS_s_axi_ram;
architecture behave of contact_discovery_AXILiteS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: optimized down-counter to control timings for low speed signals
--
-- Description:
-- ------------------------------------
-- This down-counter can be configured with a TIMING_TABLE (a ROM), from which
-- the initial counter value is loaded. The table index can be selected by
-- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM
-- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.my_config.all;
use PoC.utils.all;
entity io_TimingCounter is
generic (
TIMING_TABLE : T_NATVEC -- timing table
);
port (
Clock : in STD_LOGIC; -- clock
Enable : in STD_LOGIC; -- enable counter
Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot
Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); --
Timeout : out STD_LOGIC -- timing reached
);
end;
architecture rtl of io_TimingCounter is
function transform(vec : T_NATVEC) return T_INTVEC is
variable Result : T_INTVEC(vec'range);
begin
assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE;
for i in vec'range loop
Result(I) := vec(I) - 1;
assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE;
end loop;
return Result;
end;
constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE);
constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2);
constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1);
signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Load = '1') then
Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length);
elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then
Counter_s <= Counter_s - 1;
end if;
end if;
end process;
timeout <= Counter_s(Counter_s'high);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: optimized down-counter to control timings for low speed signals
--
-- Description:
-- ------------------------------------
-- This down-counter can be configured with a TIMING_TABLE (a ROM), from which
-- the initial counter value is loaded. The table index can be selected by
-- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM
-- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.my_config.all;
use PoC.utils.all;
entity io_TimingCounter is
generic (
TIMING_TABLE : T_NATVEC -- timing table
);
port (
Clock : in STD_LOGIC; -- clock
Enable : in STD_LOGIC; -- enable counter
Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot
Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); --
Timeout : out STD_LOGIC -- timing reached
);
end;
architecture rtl of io_TimingCounter is
function transform(vec : T_NATVEC) return T_INTVEC is
variable Result : T_INTVEC(vec'range);
begin
assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE;
for i in vec'range loop
Result(I) := vec(I) - 1;
assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE;
end loop;
return Result;
end;
constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE);
constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2);
constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1);
signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Load = '1') then
Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length);
elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then
Counter_s <= Counter_s - 1;
end if;
end if;
end process;
timeout <= Counter_s(Counter_s'high);
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.3 2004/08/18 10:47:07 wig Exp $
-- $Date: 2004/08/18 10:47:07 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:07 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- $Id: ioleds_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c - syn
-- Description: io activity leds for rlink+serport_1clk combo
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 17.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-21 649 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.serportlib.all;
entity ioleds_sp1c is -- io activity leds for rlink_sp1c
port (
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c;
architecture syn of ioleds_sp1c is
begin
-- currently very minimal implementation
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
end syn;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
----------------------------------------------------------
-- Parameterized multiplier --
----------------------------------------------------------
entity parameterized_multiplier_2 is
generic
(
bits : integer := 0
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits+3 downto 0);
--outputs
S : out std_logic_vector((2*bits)+3 downto 0) := (others=>'0')
);
end parameterized_multiplier_2;
----------------------------------------------------------
-- Parameterized adder --
----------------------------------------------------------
architecture parameterized_multiplier_arch_2 of parameterized_multiplier_2 is
-- COMPONENT declaration
component mul_man_multiplier_2 is
port
(
clk : IN std_logic;
a : IN std_logic_VECTOR(bits-1 downto 0);
b : IN std_logic_VECTOR(bits+3 downto 0);
ce : IN std_logic;
sclr : IN std_logic;
p : OUT std_logic_VECTOR(2*bits+3 downto 0)
);
end component;
-- SIGNALS
signal enable : std_logic;
begin
enable <= not STALL;
MAN_MUL : mul_man_multiplier_2
port map
(
clk => CLK,
ce => enable,
sclr => RESET,
a => A,
b => B,
p => S
);
end parameterized_multiplier_arch_2; -- end of architecture
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p07n01i01148ent IS
END c06s05b00x00p07n01i01148ent;
ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS
type A is array (10 downto 1) of integer;
BEGIN
TESTING: PROCESS
variable var : A := (66,66,others=>66);
BEGIN
wait for 5 ns;
assert NOT( var(1 downto 1) = 66 )
report "***PASSED TEST: c06s05b00x00p07n01i01148"
severity NOTE;
assert ( var(1 downto 1) = 66 )
report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p07n01i01148arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p07n01i01148ent IS
END c06s05b00x00p07n01i01148ent;
ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS
type A is array (10 downto 1) of integer;
BEGIN
TESTING: PROCESS
variable var : A := (66,66,others=>66);
BEGIN
wait for 5 ns;
assert NOT( var(1 downto 1) = 66 )
report "***PASSED TEST: c06s05b00x00p07n01i01148"
severity NOTE;
assert ( var(1 downto 1) = 66 )
report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p07n01i01148arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p07n01i01148ent IS
END c06s05b00x00p07n01i01148ent;
ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS
type A is array (10 downto 1) of integer;
BEGIN
TESTING: PROCESS
variable var : A := (66,66,others=>66);
BEGIN
wait for 5 ns;
assert NOT( var(1 downto 1) = 66 )
report "***PASSED TEST: c06s05b00x00p07n01i01148"
severity NOTE;
assert ( var(1 downto 1) = 66 )
report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p07n01i01148arch;
|
-- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of an entity passed
-- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00646
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00646(ARCH00646)
-- ENT00646_Test_Bench(ARCH00646_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646 is
port ( G1 : in integer := 0 ;
signal G2, G3, G4 : in integer := 3 ) ;
end ENT00646 ;
--
architecture ARCH00646 of ENT00646 is
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
wait ;
end process ;
L1 :
block
port ( BG1 : in integer := 0 ;
signal BG2, BG3, BG4 : in integer := 3 ) ;
port map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00646 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646_Test_Bench is
end ENT00646_Test_Bench ;
architecture ARCH00646_Test_Bench of ENT00646_Test_Bench is
begin
L1:
block
component UUT
port ( CG1 : in integer ;
signal CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00646 ( ARCH00646 )
port map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
signal S1 : integer := 1 ;
signal S2 : integer := 2 ;
signal S4 : integer := 4 ;
begin
CIS1 : UUT
port map ( S1, S2, S4 );
end block L1 ;
end ARCH00646_Test_Bench ;
--
|
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- flt_pkg.vhd
-- This package contains functions that specify various characteristics about
-- floating-point entities.
-- This example has been configured based on latencies of Stratix 3 cores used
-- in the *_flt entities.
library ieee;
use ieee.std_logic_1164.all;
package flt_pkg is
function add_flt_latency(core_name : string) return natural;
function mult_flt_latency(core_name : string) return natural;
end flt_pkg;
package body flt_pkg is
function add_flt_latency(core_name : string) return natural is
begin
if (core_name = "stratix3_latency") then
return 7;
elsif (core_name = "stratix3_area" or core_name = "stratix3_speed") then
return 14;
elsif (core_name = "stratix5_latency") then
return 7;
elsif (core_name = "stratix5_area" or core_name = "stratix5_speed") then
return 14;
elsif (core_name = "virtex7_latency") then
return 8;
elsif (core_name = "virtex7_speed") then
return 11;
end if;
assert(false) report "Error: No add_flt latency specified for architecture " & '"' & core_name & '"' & " in flt_pkg.vhd" severity error;
return 0;
end function;
function mult_flt_latency(core_name : string) return natural is
begin
if (core_name = "area") then
return 5;
elsif (core_name = "speed") then
return 11;
end if;
assert(false) report "Error: No latency specified for mult_flt architecture " & '"' & core_name & '"' & " in flt_pkg.vhd" severity error;
return 0;
end function;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of cachemem is
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant DSNOOPFAST : boolean := (dsnoop = 2) or (dsnoop = 6);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+---+--------+-----+-------+
-- | LRR | LOCK_BIT |PAR| MMUCTX | TAG | VALID |
-- +-----+----------+---+--------+-----+-------+
-- [opt] [ opt ] [ ] [ opt ] [ ]
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + ICLOCK_BIT + MMUCTX_BITS
;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + DCLOCK_BIT + MMUCTX_BITS
;
constant IDWIDTH : natural := 32
;
constant DDWIDTH : natural := 32
;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant DTLRR_BIT_POS : natural := DTWIDTH-DLRR_BIT; -- if DTLRR_BIT=0 discard (pos DTWIDTH)
constant DTLOCK_BIT_POS : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT); -- if DTCLOCK_BIT=0 but DTLRR_BIT=1 lrr will overwrite
constant DTMMU_VEC_U : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT
)-1;
constant DTMMU_VEC_D : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT+
MMUCTX_BITS);
constant ITLRR_BIT_POS : natural := ITWIDTH-ILRR_BIT; -- if DLRR_BIT=0 discard (pos DTWIDTH)
constant ITLOCK_BIT_POS : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT); -- if DCLOCK_BIT=0 but DLRR_BIT=1 lrr will overwrite
constant ITMMU_VEC_U : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT
)-1;
constant ITMMU_VEC_D : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT+
MMUCTX_BITS);
constant DPTAG_RAM_BITS : integer := DPTAG_BITS
;
constant DTAG_RAM_BITS : integer := DTAG_BITS
;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype dddatain_vector is std_logic_vector(DDWIDTH-1 downto 0);
type dddatain_type is array (0 to MAXSETS-1) of dddatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdatainx : itdatain_type;
signal itdatain_cmp : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatainx : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatain_cmp : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr3 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatainx : dtdatain_type;
signal dtdatain_cmp : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : dddatain_type;
signal dddatainx : dddatain_type;
signal dddatain_cmp : dddatain_type;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(clk, crami, dtdataout2, dtdataout3
)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : dddatain_type;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)(DTMMU_VEC_U downto DTMMU_VEC_D) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTLOCK_BIT_POS) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
if drepl = lrr then
vdtdatain(i)(DTLRR_BIT_POS) := crami.dcramin.tag(i)(CTAG_LRRPOS);
end if;
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (crami.dcramin.flush = '1') then
vdtdatain(i) := (others => '0');
vdtdatain(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to DSETS-1 loop
vdtdatain2(i) := (others => '0');
vdddatain(i)(31 downto 0) := crami.dcramin.data(i);
vdtdatain2(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain2(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain2(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end loop;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
if DSNOOPSEP and (crami.dcramin.flush = '1') then
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"F3";
vdtdatain3(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain3(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)(ITMMU_VEC_U downto ITMMU_VEC_D) := crami.icramin.ctx;
end if;
vitdatain(i)(ITLOCK_BIT_POS) := crami.icramin.tag(i)(CTAG_LOCKPOS);
if irepl = lrr then
vitdatain(i)(ITLRR_BIT_POS) := crami.icramin.tag(i)(CTAG_LRRPOS);
end if;
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW)
& crami.icramin.tag(i)(ilinesize-1 downto 0);
if (crami.icramin.flush = '1') then
vitdatain(i) := (others => '0');
vitdatain(i)(ITAG_BITS-1 downto ITAG_BITS-8) := X"FF";
vitdatain(i)(ITAG_BITS-9 downto ITAG_BITS-10) := conv_std_logic_vector(i,2);
vitdatain(i)(ITAG_BITS-11 downto ITAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
-- pragma translate_off
itdatainx <= vitdatain; iddatainx <= viddatain;
dtdatainx <= vdtdatain; dddatainx <= vdddatain;
-- pragma translate_on
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dddatain <= vdddatain;
dtdatain3 <= vdtdatain3;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
dtaddr3 <= crami.dcramin.faddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH, testen)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i), crami.dcramin.tdiag);
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH, testen)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i), crami.dcramin.ddiag);
itdataout(i)(ITWIDTH) <= '0';
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32, testen)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write, crami.dcramin.ddiag);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH, testen)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i), crami.dcramin.tdiag);
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if not DSNOOPSEP generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
end generate;
end generate;
-- virtual address snoop case
mdt1 : if DSNOOPSEP generate
slow : if not DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout(i)(DTWIDTH-1 downto dlinesize-1), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout2(i)(DTWIDTH-1 downto dlinesize-1), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS) port map (
clk, dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i), crami.dcramin.sdiag);
end generate;
end generate;
fast : if DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_2p
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, 0, 1, testen) port map (
clk, dtenable(i), dtaddr, dtdataout(i)(DTWIDTH-1 downto dlinesize-1),
sclk, dtwrite2(i), dtaddr3, dtdatain(i)(DTWIDTH-1 downto dlinesize-1), crami.dcramin.tdiag);
dtags1 : syncram_2p
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, 0, 1, testen) port map (
sclk, dtenable2(i), dtaddr2, dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
clk, dtwrite3(i), dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), crami.dcramin.sdiag);
end generate;
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH, testen)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i), crami.dcramin.ddiag);
dtdataout(i)(DTWIDTH) <= '0';
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0)(31 downto 0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1)(31 downto 0);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32, testen)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write, crami.dcramin.ddiag);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITLRR_BIT_POS);
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITLOCK_BIT_POS);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)(ITMMU_VEC_U downto ITMMU_VEC_D);
end generate;
noictx : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
cramo.icramo.ctx(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
-- cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= (others => dtdataout(i)(dlinesize-1));
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTLRR_BIT_POS);
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTLOCK_BIT_POS);
dctx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)(DTMMU_VEC_U downto DTMMU_VEC_D);
end generate;
nodctx : if mmuen = 0 generate
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
stagv : if DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
stagp : if not DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
end ;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.1 2004/04/06 10:50:40 wig Exp $
-- $Date: 2004/04/06 10:50:40 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:40 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_e_e
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zqynq_lab_1_design_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zqynq_lab_1_design_axi_gpio_0_1;
ARCHITECTURE zqynq_lab_1_design_axi_gpio_0_1_arch OF zqynq_lab_1_design_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zqynq_lab_1_design_axi_gpio_0_1_arch;
|
-- Copyright (c) 2016-2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------------
-- Title : AXI interface for AlmaIF wrapper
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : tta-accel-rtl.vhdl
-- Author : Viitanen Timo (Tampere University) <timo.2.viitanen@tut.fi>
-- Company :
-- Created : 2016-01-27
-- Last update: 2017-03-27
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-01-27 1.0 viitanet Created
-- 2016-11-18 1.1 tervoa Added full AXI4 interface
-- 2017-03-27 1.2 tervoa Change to axislave interface
-- 2017-04-25 1.3 tervoa Merge entity and architecture, use generics
-- instead of consts from packages
-- 2017-06-01 1.4 tervoa Convert to memory buses with handshaking
-- 2018-07-30 1.5 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.tce_util.all;
entity tta_accel is
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
axi_offset_g : integer := 0;
full_debugger_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_awid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector (8-1 downto 0);
s_axi_awsize : in std_logic_vector (3-1 downto 0);
s_axi_awburst : in std_logic_vector (2-1 downto 0);
s_axi_bid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector (8-1 downto 0);
s_axi_arsize : in std_logic_vector (3-1 downto 0);
s_axi_arburst : in std_logic_vector (2-1 downto 0);
s_axi_rid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_rlast : out std_logic;
-- AXI4-Lite Master for global mem
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(dmem_data_width_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(dmem_data_width_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(dmem_data_width_g-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(0 downto 0);
core_dmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(core_count_g*dmem_addr_width_g-1
downto 0);
core_dmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_astrb_in : in std_logic_vector((dmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_dmem_adata_in : in std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
core_dmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_a_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_b_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(core_count_g*pmem_addr_width_g-1
downto 0);
core_pmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_astrb_in : in std_logic_vector((pmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_pmem_adata_in : in std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
core_pmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_a_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_b_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
-- Debug ports
core_db_tta_nreset : out std_logic_vector(core_count_g-1 downto 0);
core_db_lockrq : out std_logic_vector(core_count_g-1 downto 0);
core_db_pc : in std_logic_vector(core_count_g*imem_addr_width_g-1
downto 0);
core_db_lockcnt : in std_logic_vector(core_count_g*64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(core_count_g*64-1 downto 0)
);
end entity tta_accel;
architecture rtl of tta_accel is
constant dataw_c : integer := 32;
constant ctrl_addr_width_c : integer := 8;
constant dbg_core_sel_width_c : integer := bit_width(core_count_g);
constant imem_byte_sel_width_c : integer := bit_width(imem_data_width_g/8);
constant dmem_byte_sel_width_c : integer := bit_width(dmem_data_width_g/8);
constant pmem_byte_sel_width_c : integer := bit_width(pmem_data_width_g/8);
constant pmem_offset_c : integer := axi_offset_g + 2**(axi_addr_width_g-2)*3;
constant enable_dmem : boolean := dmem_data_width_g > 0;
constant enable_pmem : boolean := pmem_data_width_g > 0;
-- AXI slave memory bus
signal axi_avalid : std_logic;
signal axi_aready : std_logic;
signal axi_aaddr : std_logic_vector(axi_addr_width_g-2-1 downto 0);
signal axi_awren : std_logic;
signal axi_astrb : std_logic_vector(dataw_c/8-1 downto 0);
signal axi_adata : std_logic_vector(dataw_c-1 downto 0);
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal axi_rdata : std_logic_vector(dataw_c-1 downto 0);
signal dmem_avalid : std_logic;
signal dmem_aready : std_logic;
signal dmem_rvalid : std_logic;
signal dmem_rready : std_logic;
signal dmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_avalid : std_logic;
signal ctrl_aready : std_logic;
signal ctrl_rvalid : std_logic;
signal ctrl_rready : std_logic;
signal ctrl_rdata : std_logic_vector(core_count_g*dataw_c-1 downto 0);
signal pmem_avalid : std_logic;
signal pmem_aready : std_logic;
signal pmem_rvalid : std_logic;
signal pmem_rready : std_logic;
signal pmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal imem_avalid : std_logic;
signal imem_aready : std_logic;
signal imem_rvalid : std_logic;
signal imem_rready : std_logic;
signal imem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal core_busy : std_logic_vector(core_count_g-1 downto 0);
signal tta_sync_nreset : std_logic_vector(core_count_g-1 downto 0);
signal ctrl_en : std_logic;
signal ctrl_data : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_core_sel : std_logic_vector(bit_width(core_count_g)-1 downto 0);
signal mc_arb_pmem_avalid : std_logic;
signal mc_arb_pmem_aready : std_logic;
signal mc_arb_pmem_aaddr : std_logic_vector(pmem_addr_width_g-1 downto 0);
signal mc_arb_pmem_awren : std_logic;
signal mc_arb_pmem_astrb : std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
signal mc_arb_pmem_adata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal mc_arb_pmem_rvalid : std_logic;
signal mc_arb_pmem_rready : std_logic;
signal mc_arb_pmem_rdata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal axi_imem_avalid_out : std_logic;
signal axi_imem_aready_in : std_logic;
signal axi_imem_aaddr_out : std_logic_vector(imem_addr_width_g-1 downto 0);
signal axi_imem_awren_out : std_logic;
signal axi_imem_astrb_out : std_logic_vector((imem_data_width_g+7)/8-1 downto 0);
signal axi_imem_adata_out : std_logic_vector(imem_data_width_g-1 downto 0);
signal axi_imem_rvalid_in : std_logic;
signal axi_imem_rready_out : std_logic;
signal axi_imem_rdata_in : std_logic_vector(imem_data_width_g-1 downto 0);
signal tta_aready : std_logic_vector(core_count_g-1 downto 0);
signal tta_rvalid : std_logic_vector(core_count_g-1 downto 0);
signal aql_read_idx, aql_write_idx : std_logic_vector(64-1 downto 0);
signal aql_read_idx_clear : std_logic_vector(0 downto 0);
signal core_db_pc_start : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_instr : std_logic_vector(core_count_g*imem_data_width_g-1 downto 0);
signal core_db_pc_next : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_bustraces : std_logic_vector(core_count_g*32*bus_count_g-1 downto 0);
begin
-----------------------------------------------------------------------------
-- AXI Controller
-----------------------------------------------------------------------------
tta_axislave_1 : entity work.tta_axislave
generic map (
axi_addrw_g => axi_addr_width_g,
axi_idw_g => axi_id_width_g,
axi_dataw_g => dataw_c,
sync_reset_g => sync_reset_g
)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
avalid_out => axi_avalid,
aready_in => axi_aready,
aaddr_out => axi_aaddr,
awren_out => axi_awren,
astrb_out => axi_astrb,
adata_out => axi_adata,
rvalid_in => axi_rvalid,
rready_out => axi_rready,
rdata_in => axi_rdata
);
bus_splitter : entity work.membus_splitter
generic map (
core_count_g => core_count_g,
axi_addr_width_g => axi_addr_width_g,
axi_data_width_g => dataw_c,
ctrl_addr_width_g => ctrl_addr_width_c,
imem_addr_width_g => imem_addr_width_g + imem_byte_sel_width_c,
dmem_addr_width_g => dmem_addr_width_g + dmem_byte_sel_width_c,
pmem_addr_width_g => pmem_addr_width_g + pmem_byte_sel_width_c
) port map (
-- AXI slave
avalid_in => axi_avalid,
aready_out => axi_aready,
aaddr_in => axi_aaddr,
rvalid_out => axi_rvalid,
rready_in => axi_rready,
rdata_out => axi_rdata,
-- Control signals to arbiters
dmem_avalid_out => dmem_avalid,
dmem_aready_in => dmem_aready,
dmem_rvalid_in => dmem_rvalid,
dmem_rready_out => dmem_rready,
dmem_rdata_in => dmem_rdata,
pmem_avalid_out => pmem_avalid,
pmem_aready_in => pmem_aready,
pmem_rvalid_in => pmem_rvalid,
pmem_rready_out => pmem_rready,
pmem_rdata_in => pmem_rdata,
imem_avalid_out => imem_avalid,
imem_aready_in => imem_aready,
imem_rvalid_in => imem_rvalid,
imem_rready_out => imem_rready,
imem_rdata_in => imem_rdata,
-- Signals to debugger(s)
ctrl_avalid_out => ctrl_avalid,
ctrl_aready_in => ctrl_aready,
ctrl_rvalid_in => ctrl_rvalid,
ctrl_rready_out => ctrl_rready,
ctrl_rdata_in => ctrl_rdata,
ctrl_core_sel_out => ctrl_core_sel
);
------------------------------------------------------------------------------
-- Debugger
------------------------------------------------------------------------------
minidebug : entity work.minidebugger
generic map (
data_width_g => 32,
axi_addr_width_g => axi_addr_width_g,
core_count_g => core_count_g,
core_id_width_g => dbg_core_sel_width_c,
imem_data_width_g => imem_data_width_g,
imem_addr_width_g => imem_addr_width_g,
dmem_data_width_g => dmem_data_width_g,
dmem_addr_width_g => dmem_addr_width_g,
pmem_data_width_g => pmem_data_width_g,
pmem_addr_width_g => local_mem_addrw_g
) port map (
clk => clk,
rstx => rstx,
avalid_in => ctrl_avalid,
aready_out => ctrl_aready,
aaddr_in => axi_aaddr,
awren_in => axi_awren,
astrb_in => axi_astrb,
adata_in => axi_adata,
rvalid_out => ctrl_rvalid,
rready_in => ctrl_rready,
rdata_out => ctrl_rdata(dataw_c-1 downto 0),
core_sel_in => ctrl_core_sel,
tta_locked_in => core_busy,
tta_lockrq_out => core_db_lockrq,
tta_nreset_out => core_db_tta_nreset,
tta_pc_in => core_db_pc,
tta_lockcnt_in => core_db_lockcnt,
tta_cyclecnt_in => core_db_cyclecnt,
tta_read_idx_in => aql_read_idx,
tta_read_idx_clear_out => aql_read_idx_clear,
tta_write_idx_out => aql_write_idx
);
rdata_broadcast : for I in 1 to core_count_g-1 generate
ctrl_rdata((I+1)*dataw_c-1 downto I*dataw_c)
<= ctrl_rdata(dataw_c-1 downto 0);
end generate rdata_broadcast;
aql_read_idx <= aql_read_idx_in;
aql_read_idx_clear_out <= aql_read_idx_clear;
------------------------------------------------------------------------------
-- Memory arbitration between IO and TTA
------------------------------------------------------------------------------
mc_arbiters : if core_count_g > 1 generate
gen_dmem_arbiter : if enable_dmem generate
mc_arbiter_dmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_dmem_avalid_in,
tta_aready_out => core_dmem_aready_out,
tta_aaddr_in => core_dmem_aaddr_in,
tta_awren_in => core_dmem_awren_in,
tta_astrb_in => core_dmem_astrb_in,
tta_adata_in => core_dmem_adata_in,
tta_rvalid_out => core_dmem_rvalid_out,
tta_rready_in => core_dmem_rready_in,
tta_rdata_out => core_dmem_rdata_out,
-- Bus to memory
mem_avalid_out => data_a_avalid_out(0),
mem_aready_in => data_a_aready_in(0),
mem_aaddr_out => data_a_aaddr_out,
mem_awren_out => data_a_awren_out(0),
mem_astrb_out => data_a_astrb_out,
mem_adata_out => data_a_adata_out,
mem_rvalid_in => data_a_rvalid_in(0),
mem_rready_out => data_a_rready_out(0),
mem_rdata_in => data_a_rdata_in
);
end generate;
gen_pmem_arbiter : if enable_pmem generate
mc_arbiter_pmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => pmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_pmem_avalid_in,
tta_aready_out => core_pmem_aready_out,
tta_aaddr_in => core_pmem_aaddr_in,
tta_awren_in => core_pmem_awren_in,
tta_astrb_in => core_pmem_astrb_in,
tta_adata_in => core_pmem_adata_in,
tta_rvalid_out => core_pmem_rvalid_out,
tta_rready_in => core_pmem_rready_in,
tta_rdata_out => core_pmem_rdata_out,
-- Bus to memory
mem_avalid_out => mc_arb_pmem_avalid,
mem_aready_in => mc_arb_pmem_aready,
mem_aaddr_out => mc_arb_pmem_aaddr,
mem_awren_out => mc_arb_pmem_awren,
mem_astrb_out => mc_arb_pmem_astrb,
mem_adata_out => mc_arb_pmem_adata,
mem_rvalid_in => mc_arb_pmem_rvalid,
mem_rready_out => mc_arb_pmem_rready,
mem_rdata_in => mc_arb_pmem_rdata
);
end generate;
end generate;
no_mc_arbiters : if core_count_g <= 1 generate
data_a_avalid_out <= core_dmem_avalid_in;
core_dmem_aready_out <= data_a_aready_in;
data_a_aaddr_out <= core_dmem_aaddr_in;
data_a_awren_out <= core_dmem_awren_in;
data_a_astrb_out <= core_dmem_astrb_in;
data_a_adata_out <= core_dmem_adata_in;
core_dmem_rvalid_out <= data_a_rvalid_in;
data_a_rready_out <= core_dmem_rready_in;
core_dmem_rdata_out <= data_a_rdata_in;
mc_arb_pmem_avalid <= core_pmem_avalid_in(0);
core_pmem_aready_out(0) <= mc_arb_pmem_aready;
mc_arb_pmem_aaddr <= core_pmem_aaddr_in;
mc_arb_pmem_awren <= core_pmem_awren_in(0);
mc_arb_pmem_astrb <= core_pmem_astrb_in;
mc_arb_pmem_adata <= core_pmem_adata_in;
core_pmem_rvalid_out(0) <= mc_arb_pmem_rvalid;
mc_arb_pmem_rready <= core_pmem_rready_in(0);
core_pmem_rdata_out <= mc_arb_pmem_rdata;
end generate;
gen_decoder : if axi_offset_g /= 0 generate
decoder_pmem : entity work.almaif_decoder
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_addrw_g => 32,
mem_offset_g => pmem_offset_c,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
-- Bus from arbiter
arb_avalid_in => mc_arb_pmem_avalid,
arb_aready_out => mc_arb_pmem_aready,
arb_aaddr_in => mc_arb_pmem_aaddr,
arb_awren_in => mc_arb_pmem_awren,
arb_astrb_in => mc_arb_pmem_astrb,
arb_adata_in => mc_arb_pmem_adata,
--
arb_rvalid_out => mc_arb_pmem_rvalid,
arb_rready_in => mc_arb_pmem_rready,
arb_rdata_out => mc_arb_pmem_rdata,
-- Bus to local memory
mem_avalid_out => param_a_avalid_out(0),
mem_aready_in => param_a_aready_in(0),
mem_aaddr_out => param_a_aaddr_out,
mem_awren_out => param_a_awren_out(0),
mem_astrb_out => param_a_astrb_out,
mem_adata_out => param_a_adata_out,
--
mem_rvalid_in => param_a_rvalid_in(0),
mem_rready_out => param_a_rready_out(0),
mem_rdata_in => param_a_rdata_in,
-- AXI lite master
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awprot => m_axi_awprot,
--
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
--
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
--
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
--
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
m_axi_rdata => m_axi_rdata
);
end generate;
no_decoder : if axi_offset_g = 0 generate
param_a_avalid_out(0) <= mc_arb_pmem_avalid;
mc_arb_pmem_aready <= param_a_aready_in(0);
param_a_aaddr_out <= mc_arb_pmem_aaddr;
param_a_awren_out(0) <= mc_arb_pmem_awren;
param_a_astrb_out <= mc_arb_pmem_astrb;
param_a_adata_out <= mc_arb_pmem_adata;
mc_arb_pmem_rvalid <= param_a_rvalid_in(0);
param_a_rready_out(0) <= mc_arb_pmem_rready;
mc_arb_pmem_rdata <= param_a_rdata_in;
end generate;
gen_dmem_expander : if enable_dmem generate
dmem_expander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => dmem_avalid,
axi_aready_out => dmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => dmem_rvalid,
axi_rready_in => dmem_rready,
axi_rdata_out => dmem_rdata,
-- Bus to memory
mem_avalid_out => data_b_avalid_out(0),
mem_aready_in => data_b_aready_in(0),
mem_aaddr_out => data_b_aaddr_out,
mem_awren_out => data_b_awren_out(0),
mem_astrb_out => data_b_astrb_out,
mem_adata_out => data_b_adata_out,
mem_rvalid_in => data_b_rvalid_in(0),
mem_rready_out => data_b_rready_out(0),
mem_rdata_in => data_b_rdata_in
);
end generate;
no_dmem_expander : if not enable_dmem generate
dmem_aready <= '1';
dmem_rvalid <= '1';
dmem_rdata <= (others => '0');
end generate;
gen_pmem_expander : if enable_pmem generate
pmem_epander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => pmem_avalid,
axi_aready_out => pmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => pmem_rvalid,
axi_rready_in => pmem_rready,
axi_rdata_out => pmem_rdata,
-- Bus to memory
mem_avalid_out => param_b_avalid_out(0),
mem_aready_in => param_b_aready_in(0),
mem_aaddr_out => param_b_aaddr_out,
mem_awren_out => param_b_awren_out(0),
mem_astrb_out => param_b_astrb_out,
mem_adata_out => param_b_adata_out,
mem_rvalid_in => param_b_rvalid_in(0),
mem_rready_out => param_b_rready_out(0),
mem_rdata_in => param_b_rdata_in
);
end generate;
no_pmem_expander : if not enable_pmem generate
pmem_aready <= '1';
pmem_rvalid <= '1';
pmem_rdata <= (others => '0');
end generate;
end architecture rtl;
|
-- Copyright (c) 2016-2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------------
-- Title : AXI interface for AlmaIF wrapper
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : tta-accel-rtl.vhdl
-- Author : Viitanen Timo (Tampere University) <timo.2.viitanen@tut.fi>
-- Company :
-- Created : 2016-01-27
-- Last update: 2017-03-27
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-01-27 1.0 viitanet Created
-- 2016-11-18 1.1 tervoa Added full AXI4 interface
-- 2017-03-27 1.2 tervoa Change to axislave interface
-- 2017-04-25 1.3 tervoa Merge entity and architecture, use generics
-- instead of consts from packages
-- 2017-06-01 1.4 tervoa Convert to memory buses with handshaking
-- 2018-07-30 1.5 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.tce_util.all;
entity tta_accel is
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
axi_offset_g : integer := 0;
full_debugger_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_awid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector (8-1 downto 0);
s_axi_awsize : in std_logic_vector (3-1 downto 0);
s_axi_awburst : in std_logic_vector (2-1 downto 0);
s_axi_bid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector (8-1 downto 0);
s_axi_arsize : in std_logic_vector (3-1 downto 0);
s_axi_arburst : in std_logic_vector (2-1 downto 0);
s_axi_rid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_rlast : out std_logic;
-- AXI4-Lite Master for global mem
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(dmem_data_width_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(dmem_data_width_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(dmem_data_width_g-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(0 downto 0);
core_dmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(core_count_g*dmem_addr_width_g-1
downto 0);
core_dmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_astrb_in : in std_logic_vector((dmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_dmem_adata_in : in std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
core_dmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_a_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_b_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(core_count_g*pmem_addr_width_g-1
downto 0);
core_pmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_astrb_in : in std_logic_vector((pmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_pmem_adata_in : in std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
core_pmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_a_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_b_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
-- Debug ports
core_db_tta_nreset : out std_logic_vector(core_count_g-1 downto 0);
core_db_lockrq : out std_logic_vector(core_count_g-1 downto 0);
core_db_pc : in std_logic_vector(core_count_g*imem_addr_width_g-1
downto 0);
core_db_lockcnt : in std_logic_vector(core_count_g*64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(core_count_g*64-1 downto 0)
);
end entity tta_accel;
architecture rtl of tta_accel is
constant dataw_c : integer := 32;
constant ctrl_addr_width_c : integer := 8;
constant dbg_core_sel_width_c : integer := bit_width(core_count_g);
constant imem_byte_sel_width_c : integer := bit_width(imem_data_width_g/8);
constant dmem_byte_sel_width_c : integer := bit_width(dmem_data_width_g/8);
constant pmem_byte_sel_width_c : integer := bit_width(pmem_data_width_g/8);
constant pmem_offset_c : integer := axi_offset_g + 2**(axi_addr_width_g-2)*3;
constant enable_dmem : boolean := dmem_data_width_g > 0;
constant enable_pmem : boolean := pmem_data_width_g > 0;
-- AXI slave memory bus
signal axi_avalid : std_logic;
signal axi_aready : std_logic;
signal axi_aaddr : std_logic_vector(axi_addr_width_g-2-1 downto 0);
signal axi_awren : std_logic;
signal axi_astrb : std_logic_vector(dataw_c/8-1 downto 0);
signal axi_adata : std_logic_vector(dataw_c-1 downto 0);
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal axi_rdata : std_logic_vector(dataw_c-1 downto 0);
signal dmem_avalid : std_logic;
signal dmem_aready : std_logic;
signal dmem_rvalid : std_logic;
signal dmem_rready : std_logic;
signal dmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_avalid : std_logic;
signal ctrl_aready : std_logic;
signal ctrl_rvalid : std_logic;
signal ctrl_rready : std_logic;
signal ctrl_rdata : std_logic_vector(core_count_g*dataw_c-1 downto 0);
signal pmem_avalid : std_logic;
signal pmem_aready : std_logic;
signal pmem_rvalid : std_logic;
signal pmem_rready : std_logic;
signal pmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal imem_avalid : std_logic;
signal imem_aready : std_logic;
signal imem_rvalid : std_logic;
signal imem_rready : std_logic;
signal imem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal core_busy : std_logic_vector(core_count_g-1 downto 0);
signal tta_sync_nreset : std_logic_vector(core_count_g-1 downto 0);
signal ctrl_en : std_logic;
signal ctrl_data : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_core_sel : std_logic_vector(bit_width(core_count_g)-1 downto 0);
signal mc_arb_pmem_avalid : std_logic;
signal mc_arb_pmem_aready : std_logic;
signal mc_arb_pmem_aaddr : std_logic_vector(pmem_addr_width_g-1 downto 0);
signal mc_arb_pmem_awren : std_logic;
signal mc_arb_pmem_astrb : std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
signal mc_arb_pmem_adata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal mc_arb_pmem_rvalid : std_logic;
signal mc_arb_pmem_rready : std_logic;
signal mc_arb_pmem_rdata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal axi_imem_avalid_out : std_logic;
signal axi_imem_aready_in : std_logic;
signal axi_imem_aaddr_out : std_logic_vector(imem_addr_width_g-1 downto 0);
signal axi_imem_awren_out : std_logic;
signal axi_imem_astrb_out : std_logic_vector((imem_data_width_g+7)/8-1 downto 0);
signal axi_imem_adata_out : std_logic_vector(imem_data_width_g-1 downto 0);
signal axi_imem_rvalid_in : std_logic;
signal axi_imem_rready_out : std_logic;
signal axi_imem_rdata_in : std_logic_vector(imem_data_width_g-1 downto 0);
signal tta_aready : std_logic_vector(core_count_g-1 downto 0);
signal tta_rvalid : std_logic_vector(core_count_g-1 downto 0);
signal aql_read_idx, aql_write_idx : std_logic_vector(64-1 downto 0);
signal aql_read_idx_clear : std_logic_vector(0 downto 0);
signal core_db_pc_start : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_instr : std_logic_vector(core_count_g*imem_data_width_g-1 downto 0);
signal core_db_pc_next : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_bustraces : std_logic_vector(core_count_g*32*bus_count_g-1 downto 0);
begin
-----------------------------------------------------------------------------
-- AXI Controller
-----------------------------------------------------------------------------
tta_axislave_1 : entity work.tta_axislave
generic map (
axi_addrw_g => axi_addr_width_g,
axi_idw_g => axi_id_width_g,
axi_dataw_g => dataw_c,
sync_reset_g => sync_reset_g
)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
avalid_out => axi_avalid,
aready_in => axi_aready,
aaddr_out => axi_aaddr,
awren_out => axi_awren,
astrb_out => axi_astrb,
adata_out => axi_adata,
rvalid_in => axi_rvalid,
rready_out => axi_rready,
rdata_in => axi_rdata
);
bus_splitter : entity work.membus_splitter
generic map (
core_count_g => core_count_g,
axi_addr_width_g => axi_addr_width_g,
axi_data_width_g => dataw_c,
ctrl_addr_width_g => ctrl_addr_width_c,
imem_addr_width_g => imem_addr_width_g + imem_byte_sel_width_c,
dmem_addr_width_g => dmem_addr_width_g + dmem_byte_sel_width_c,
pmem_addr_width_g => pmem_addr_width_g + pmem_byte_sel_width_c
) port map (
-- AXI slave
avalid_in => axi_avalid,
aready_out => axi_aready,
aaddr_in => axi_aaddr,
rvalid_out => axi_rvalid,
rready_in => axi_rready,
rdata_out => axi_rdata,
-- Control signals to arbiters
dmem_avalid_out => dmem_avalid,
dmem_aready_in => dmem_aready,
dmem_rvalid_in => dmem_rvalid,
dmem_rready_out => dmem_rready,
dmem_rdata_in => dmem_rdata,
pmem_avalid_out => pmem_avalid,
pmem_aready_in => pmem_aready,
pmem_rvalid_in => pmem_rvalid,
pmem_rready_out => pmem_rready,
pmem_rdata_in => pmem_rdata,
imem_avalid_out => imem_avalid,
imem_aready_in => imem_aready,
imem_rvalid_in => imem_rvalid,
imem_rready_out => imem_rready,
imem_rdata_in => imem_rdata,
-- Signals to debugger(s)
ctrl_avalid_out => ctrl_avalid,
ctrl_aready_in => ctrl_aready,
ctrl_rvalid_in => ctrl_rvalid,
ctrl_rready_out => ctrl_rready,
ctrl_rdata_in => ctrl_rdata,
ctrl_core_sel_out => ctrl_core_sel
);
------------------------------------------------------------------------------
-- Debugger
------------------------------------------------------------------------------
minidebug : entity work.minidebugger
generic map (
data_width_g => 32,
axi_addr_width_g => axi_addr_width_g,
core_count_g => core_count_g,
core_id_width_g => dbg_core_sel_width_c,
imem_data_width_g => imem_data_width_g,
imem_addr_width_g => imem_addr_width_g,
dmem_data_width_g => dmem_data_width_g,
dmem_addr_width_g => dmem_addr_width_g,
pmem_data_width_g => pmem_data_width_g,
pmem_addr_width_g => local_mem_addrw_g
) port map (
clk => clk,
rstx => rstx,
avalid_in => ctrl_avalid,
aready_out => ctrl_aready,
aaddr_in => axi_aaddr,
awren_in => axi_awren,
astrb_in => axi_astrb,
adata_in => axi_adata,
rvalid_out => ctrl_rvalid,
rready_in => ctrl_rready,
rdata_out => ctrl_rdata(dataw_c-1 downto 0),
core_sel_in => ctrl_core_sel,
tta_locked_in => core_busy,
tta_lockrq_out => core_db_lockrq,
tta_nreset_out => core_db_tta_nreset,
tta_pc_in => core_db_pc,
tta_lockcnt_in => core_db_lockcnt,
tta_cyclecnt_in => core_db_cyclecnt,
tta_read_idx_in => aql_read_idx,
tta_read_idx_clear_out => aql_read_idx_clear,
tta_write_idx_out => aql_write_idx
);
rdata_broadcast : for I in 1 to core_count_g-1 generate
ctrl_rdata((I+1)*dataw_c-1 downto I*dataw_c)
<= ctrl_rdata(dataw_c-1 downto 0);
end generate rdata_broadcast;
aql_read_idx <= aql_read_idx_in;
aql_read_idx_clear_out <= aql_read_idx_clear;
------------------------------------------------------------------------------
-- Memory arbitration between IO and TTA
------------------------------------------------------------------------------
mc_arbiters : if core_count_g > 1 generate
gen_dmem_arbiter : if enable_dmem generate
mc_arbiter_dmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_dmem_avalid_in,
tta_aready_out => core_dmem_aready_out,
tta_aaddr_in => core_dmem_aaddr_in,
tta_awren_in => core_dmem_awren_in,
tta_astrb_in => core_dmem_astrb_in,
tta_adata_in => core_dmem_adata_in,
tta_rvalid_out => core_dmem_rvalid_out,
tta_rready_in => core_dmem_rready_in,
tta_rdata_out => core_dmem_rdata_out,
-- Bus to memory
mem_avalid_out => data_a_avalid_out(0),
mem_aready_in => data_a_aready_in(0),
mem_aaddr_out => data_a_aaddr_out,
mem_awren_out => data_a_awren_out(0),
mem_astrb_out => data_a_astrb_out,
mem_adata_out => data_a_adata_out,
mem_rvalid_in => data_a_rvalid_in(0),
mem_rready_out => data_a_rready_out(0),
mem_rdata_in => data_a_rdata_in
);
end generate;
gen_pmem_arbiter : if enable_pmem generate
mc_arbiter_pmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => pmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_pmem_avalid_in,
tta_aready_out => core_pmem_aready_out,
tta_aaddr_in => core_pmem_aaddr_in,
tta_awren_in => core_pmem_awren_in,
tta_astrb_in => core_pmem_astrb_in,
tta_adata_in => core_pmem_adata_in,
tta_rvalid_out => core_pmem_rvalid_out,
tta_rready_in => core_pmem_rready_in,
tta_rdata_out => core_pmem_rdata_out,
-- Bus to memory
mem_avalid_out => mc_arb_pmem_avalid,
mem_aready_in => mc_arb_pmem_aready,
mem_aaddr_out => mc_arb_pmem_aaddr,
mem_awren_out => mc_arb_pmem_awren,
mem_astrb_out => mc_arb_pmem_astrb,
mem_adata_out => mc_arb_pmem_adata,
mem_rvalid_in => mc_arb_pmem_rvalid,
mem_rready_out => mc_arb_pmem_rready,
mem_rdata_in => mc_arb_pmem_rdata
);
end generate;
end generate;
no_mc_arbiters : if core_count_g <= 1 generate
data_a_avalid_out <= core_dmem_avalid_in;
core_dmem_aready_out <= data_a_aready_in;
data_a_aaddr_out <= core_dmem_aaddr_in;
data_a_awren_out <= core_dmem_awren_in;
data_a_astrb_out <= core_dmem_astrb_in;
data_a_adata_out <= core_dmem_adata_in;
core_dmem_rvalid_out <= data_a_rvalid_in;
data_a_rready_out <= core_dmem_rready_in;
core_dmem_rdata_out <= data_a_rdata_in;
mc_arb_pmem_avalid <= core_pmem_avalid_in(0);
core_pmem_aready_out(0) <= mc_arb_pmem_aready;
mc_arb_pmem_aaddr <= core_pmem_aaddr_in;
mc_arb_pmem_awren <= core_pmem_awren_in(0);
mc_arb_pmem_astrb <= core_pmem_astrb_in;
mc_arb_pmem_adata <= core_pmem_adata_in;
core_pmem_rvalid_out(0) <= mc_arb_pmem_rvalid;
mc_arb_pmem_rready <= core_pmem_rready_in(0);
core_pmem_rdata_out <= mc_arb_pmem_rdata;
end generate;
gen_decoder : if axi_offset_g /= 0 generate
decoder_pmem : entity work.almaif_decoder
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_addrw_g => 32,
mem_offset_g => pmem_offset_c,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
-- Bus from arbiter
arb_avalid_in => mc_arb_pmem_avalid,
arb_aready_out => mc_arb_pmem_aready,
arb_aaddr_in => mc_arb_pmem_aaddr,
arb_awren_in => mc_arb_pmem_awren,
arb_astrb_in => mc_arb_pmem_astrb,
arb_adata_in => mc_arb_pmem_adata,
--
arb_rvalid_out => mc_arb_pmem_rvalid,
arb_rready_in => mc_arb_pmem_rready,
arb_rdata_out => mc_arb_pmem_rdata,
-- Bus to local memory
mem_avalid_out => param_a_avalid_out(0),
mem_aready_in => param_a_aready_in(0),
mem_aaddr_out => param_a_aaddr_out,
mem_awren_out => param_a_awren_out(0),
mem_astrb_out => param_a_astrb_out,
mem_adata_out => param_a_adata_out,
--
mem_rvalid_in => param_a_rvalid_in(0),
mem_rready_out => param_a_rready_out(0),
mem_rdata_in => param_a_rdata_in,
-- AXI lite master
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awprot => m_axi_awprot,
--
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
--
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
--
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
--
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
m_axi_rdata => m_axi_rdata
);
end generate;
no_decoder : if axi_offset_g = 0 generate
param_a_avalid_out(0) <= mc_arb_pmem_avalid;
mc_arb_pmem_aready <= param_a_aready_in(0);
param_a_aaddr_out <= mc_arb_pmem_aaddr;
param_a_awren_out(0) <= mc_arb_pmem_awren;
param_a_astrb_out <= mc_arb_pmem_astrb;
param_a_adata_out <= mc_arb_pmem_adata;
mc_arb_pmem_rvalid <= param_a_rvalid_in(0);
param_a_rready_out(0) <= mc_arb_pmem_rready;
mc_arb_pmem_rdata <= param_a_rdata_in;
end generate;
gen_dmem_expander : if enable_dmem generate
dmem_expander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => dmem_avalid,
axi_aready_out => dmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => dmem_rvalid,
axi_rready_in => dmem_rready,
axi_rdata_out => dmem_rdata,
-- Bus to memory
mem_avalid_out => data_b_avalid_out(0),
mem_aready_in => data_b_aready_in(0),
mem_aaddr_out => data_b_aaddr_out,
mem_awren_out => data_b_awren_out(0),
mem_astrb_out => data_b_astrb_out,
mem_adata_out => data_b_adata_out,
mem_rvalid_in => data_b_rvalid_in(0),
mem_rready_out => data_b_rready_out(0),
mem_rdata_in => data_b_rdata_in
);
end generate;
no_dmem_expander : if not enable_dmem generate
dmem_aready <= '1';
dmem_rvalid <= '1';
dmem_rdata <= (others => '0');
end generate;
gen_pmem_expander : if enable_pmem generate
pmem_epander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => pmem_avalid,
axi_aready_out => pmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => pmem_rvalid,
axi_rready_in => pmem_rready,
axi_rdata_out => pmem_rdata,
-- Bus to memory
mem_avalid_out => param_b_avalid_out(0),
mem_aready_in => param_b_aready_in(0),
mem_aaddr_out => param_b_aaddr_out,
mem_awren_out => param_b_awren_out(0),
mem_astrb_out => param_b_astrb_out,
mem_adata_out => param_b_adata_out,
mem_rvalid_in => param_b_rvalid_in(0),
mem_rready_out => param_b_rready_out(0),
mem_rdata_in => param_b_rdata_in
);
end generate;
no_pmem_expander : if not enable_pmem generate
pmem_aready <= '1';
pmem_rvalid <= '1';
pmem_rdata <= (others => '0');
end generate;
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_outputMem_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_outputMem_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:38:02 03/25/2015
-- Design Name:
-- Module Name: op_access - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity op_access is
Port( CLK : IN STD_LOGIC;
OPCODE_IN : IN STD_LOGIC_VECTOR (3 downto 0);
REG_A : IN STD_LOGIC_VECTOR (3 downto 0);
IMMEDIATE : IN STD_LOGIC_VECTOR (7 downto 0);
W_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
OP2_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
BANK_R_W : IN STD_LOGIC;
BANK_ENB : IN STD_LOGIC;
BANK_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
DEC_REG_ADDR : OUT STD_LOGIC_VECTOR (3 downto 0);
OPCODE_OUT : OUT STD_LOGIC_VECTOR (3 downto 0);
EX_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
EX_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
WB_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
WB_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_OUT : OUT STD_LOGIC_VECTOR (15 downto 0);
OP2_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
end op_access;
architecture Structural of op_access is
signal REG_BANK_A_OUT, REG_BANK_B_OUT, IMM_DATA, REG_A_IN, REG_B_IN, REG_B : STD_LOGIC_VECTOR (15 downto 0);
signal OPCODE_DEL_OUT, write_address, EX_FWD_ADDR_REG, WB_FWD_ADDR_REG : STD_LOGIC_VECTOR (3 downto 0);
signal DETECT_SEL1, DETECT_SEL2 : STD_LOGIC_VECTOR(1 downto 0);
begin
IMM_DATA <= x"00" & IMMEDIATE;
REG_B <= X"000" & IMMEDIATE(3 downto 0);
RegBank: entity work.register_bank
Port Map( CLK => CLK,
ADDR_A => REG_A,
ADDR_B => IMMEDIATE(7 downto 4),
W_ADDR => write_address,
R_W => BANK_R_W,
ENB => BANK_ENB,
DATA_IN => BANK_DATA,
REG_A => REG_BANK_A_OUT,
REG_B => REG_BANK_B_OUT);
OPCODE: entity work.Register_FE_4
Port Map( CLK => CLK,
D => OPCODE_IN,
ENB => '1',
Q => OPCODE_OUT);
REGA: entity work.Register_FE_4
Port Map( CLK => CLK,
D => REG_A,
ENB => '1',
Q => DEC_REG_ADDR);
-- OPCODEDEL: entity work.Register_FE_4
-- Port Map( CLK => CLK,
-- D => OPCODE_DEL_OUT,
-- ENB => '1',
-- Q => OPCODE_OUT);
FWD_DETECT1: entity work.Forwarding_unit
PORT MAP( OPA_REG => REG_A,
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP1_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL1);
OP1_MUX: entity work.MUX4to1
PORT MAP( SEL => DETECT_SEL1,
DATA_0 => REG_BANK_A_OUT,
DATA_1 => x"0000",
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_A_IN);
OP1: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_A_IN,
ENB => '1',
Q => OP1_OUT);
FWD_DETECT2: entity work.Forwarding_unit
PORT MAP( OPA_REG => IMMEDIATE(3 downto 0),
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP2_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL2);
OP2_MUX: entity work.mux4to1
Port Map( SEL => DETECT_SEL2,
DATA_0 => REG_BANK_B_OUT,
DATA_1 => IMM_DATA,
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_B_IN);
OP2: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_B_IN,
ENB => '1',
Q => OP2_OUT);
U5: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => W_ADDR,
Q => write_address);
U6: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => EX_FWD_ADDR,
Q => EX_FWD_ADDR_REG);
U7: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => WB_FWD_ADDR,
Q => WB_FWD_ADDR_REG);
end Structural;
|
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 2 3 6 8)
-- * data width: 8
--
-- Info : tools@easics.be
-- http://www.easics.com
--------------------------------------------------------------------------------
--
-- *********************************************************************
-- File : $RCSfile: pck_crc8_d8.vhd.rca $
-- Author : $Author: fec $
-- Author's Email : fec@cypress.com
-- Department : MPD_BE
-- Date : $Date: Thu Oct 8 18:40:45 2009 $
-- Revision : $Revision: 1.1 $
-- *********************************************************************
-- Modification History Summary
-- Date By Version Change Description
-- *********************************************************************
-- $Log: pck_crc8_d8.vhd.rca $
--
-- Revision: 1.1 Thu Oct 8 18:40:45 2009 fec
-- {CRC 8 polynome}
--
-- *********************************************************************
-- Description
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PCK_CRC8_D8 is
-- polynomial: (0 2 3 6 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC8_D8
(data: unsigned(7 downto 0);
crc: unsigned(7 downto 0))
return unsigned;
end PCK_CRC8_D8;
package body PCK_CRC8_D8 is
-- polynomial: (0 2 3 6 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC8_D8
(data: unsigned(7 downto 0);
crc: unsigned(7 downto 0))
return unsigned is
variable d: unsigned(7 downto 0);
variable c: unsigned(7 downto 0);
variable newcrc: unsigned(7 downto 0);
begin
d := data;
c := crc;
newcrc(0) := d(5) xor d(4) xor d(2) xor d(0) xor c(0) xor c(2) xor
c(4) xor c(5);
newcrc(1) := d(6) xor d(5) xor d(3) xor d(1) xor c(1) xor c(3) xor
c(5) xor c(6);
newcrc(2) := d(7) xor d(6) xor d(5) xor d(0) xor c(0) xor c(5) xor
c(6) xor c(7);
newcrc(3) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor
d(0) xor c(0) xor c(1) xor c(2) xor c(4) xor c(5) xor
c(6) xor c(7);
newcrc(4) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor
c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(7);
newcrc(5) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(2) xor
c(3) xor c(4) xor c(6) xor c(7);
newcrc(6) := d(7) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor
c(3) xor c(7);
newcrc(7) := d(4) xor d(3) xor d(1) xor c(1) xor c(3) xor c(4);
return newcrc;
end nextCRC8_D8;
end PCK_CRC8_D8;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n02i01386ent IS
END c08s05b00x00p03n02i01386ent;
ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
BEGIN
TESTING : PROCESS
variable radix : natural := 10;
variable v1 : natural;
type r_array_index_type is range 1 to 3;
type r_array_type is array (r_array_index_type) of natural;
variable r_array : r_array_type;
procedure set_radix ( constant radix : natural
) is
begin
TESTING.radix := radix; -- test selected name as target
end set_radix;
BEGIN
v1 := 8; --test simple name as target
assert v1 = 8
report "Simple name as target failed."
severity note ;
set_radix (v1);
assert radix = v1
report "Selected name as target failed."
severity note ;
r_array ( 3 to 3 ) := (3 => 10); -- test slice name as target
assert r_array ( 3 ) = 10
report "Slice name as target failed."
severity note ;
r_array ( 2 ) := 8; -- test indexed name as target
assert r_array ( 2 ) = 8
report "Indexed name as target failed."
severity note ;
assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8)
report "***PASSED TEST: c08s05b00x00p03n02i01386"
severity NOTE;
assert (v1=8 and r_array(3)=10 and r_array(2)=8)
report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n02i01386arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n02i01386ent IS
END c08s05b00x00p03n02i01386ent;
ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
BEGIN
TESTING : PROCESS
variable radix : natural := 10;
variable v1 : natural;
type r_array_index_type is range 1 to 3;
type r_array_type is array (r_array_index_type) of natural;
variable r_array : r_array_type;
procedure set_radix ( constant radix : natural
) is
begin
TESTING.radix := radix; -- test selected name as target
end set_radix;
BEGIN
v1 := 8; --test simple name as target
assert v1 = 8
report "Simple name as target failed."
severity note ;
set_radix (v1);
assert radix = v1
report "Selected name as target failed."
severity note ;
r_array ( 3 to 3 ) := (3 => 10); -- test slice name as target
assert r_array ( 3 ) = 10
report "Slice name as target failed."
severity note ;
r_array ( 2 ) := 8; -- test indexed name as target
assert r_array ( 2 ) = 8
report "Indexed name as target failed."
severity note ;
assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8)
report "***PASSED TEST: c08s05b00x00p03n02i01386"
severity NOTE;
assert (v1=8 and r_array(3)=10 and r_array(2)=8)
report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n02i01386arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n02i01386ent IS
END c08s05b00x00p03n02i01386ent;
ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
BEGIN
TESTING : PROCESS
variable radix : natural := 10;
variable v1 : natural;
type r_array_index_type is range 1 to 3;
type r_array_type is array (r_array_index_type) of natural;
variable r_array : r_array_type;
procedure set_radix ( constant radix : natural
) is
begin
TESTING.radix := radix; -- test selected name as target
end set_radix;
BEGIN
v1 := 8; --test simple name as target
assert v1 = 8
report "Simple name as target failed."
severity note ;
set_radix (v1);
assert radix = v1
report "Selected name as target failed."
severity note ;
r_array ( 3 to 3 ) := (3 => 10); -- test slice name as target
assert r_array ( 3 ) = 10
report "Slice name as target failed."
severity note ;
r_array ( 2 ) := 8; -- test indexed name as target
assert r_array ( 2 ) = 8
report "Indexed name as target failed."
severity note ;
assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8)
report "***PASSED TEST: c08s05b00x00p03n02i01386"
severity NOTE;
assert (v1=8 and r_array(3)=10 and r_array(2)=8)
report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n02i01386arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FC0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
|
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Component_Contatore is
Port (
enable_in : in STD_LOGIC ;
SEG : out STD_LOGIC_VECTOR(0 to 6);
N_out : out STD_LOGIC_VECTOR(3 downto 0);
enable_out : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR(3 downto 0);
CLK100M : in STD_LOGIC;
CLK_1K_O : out STD_LOGIC
);
end Component_Contatore;
architecture Behavioral of Component_Contatore is
signal N: UNSIGNED(3 downto 0);
signal NN: UNSIGNED(15 downto 0);
signal clk_1k: STD_LOGIC;
begin
CLK_1K_O <= clk_1k; --collego le varie scatole con i segnali
SEG(0)<='0' when N=0 or N=2 or N=3 or N>4 else '1';
SEG(1)<='0' when N=0 or N=1 or N=2 or N=3 or N=4 or N=7 or N=8 or N=9 else '1';
SEG(2)<='0' when N=0 or N=1 or N=3 or N=4 or N=5 or N=6 or N=7 or N=8 or N=9 else '1';
SEG(3)<='0' when N=0 or N=2 or N=3 or N=5 or N=6 or N=8 or N>9 else '1';
SEG(4)<='0' when N=0 or N=2 or N=6 or N=8 or N>9 else '1';
SEG(5)<='0' when N=0 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
SEG(6)<='0' when N=2 or N=3 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
AN <= "0000";
mod_freq:process(CLK100M)
begin
if rising_edge(CLK100M) then
if NN=49999 then
NN<=(others => '0');
clk_1k <= not clk_1k;
else
NN<=NN+1;
end if;
end if;
end process mod_freq;
contatore_1_cifra:process(clk_1k)
begin
if rising_edge(contatore_1_cifra) then
if(reset = '1') then
C <=(others => '0');
else
if(preset ='1') then
C<= C_preset;
else
if(enable_in='1')then
if(up_down='1')then
if C = 9 then
C <=(others=>'0');
else
C<=C+1;
end if;
else
if C=0 then
C <= "1001";
else
C<=C-1;
end if;
end if;
end if;
end process contatore_1_cifra;
enable_out <= '1' when(((C=9) and up_down='1') or (C=0 and up_down='0')) and else '0';
end Behavioral;
|
package numeric_std_perf is
procedure test_to_unsigned;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package body numeric_std_perf is
procedure test_to_unsigned is
constant WIDTH : integer := 8;
constant ITERS : integer := 1;
variable s : unsigned(WIDTH - 1 downto 0);
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s := to_unsigned(j, WIDTH);
end loop;
end loop;
end procedure;
end package body;
|
----------------------------------------------------------------------------------
--
-- 8-bit I/O port
-- Contains kludge for 6510/C64 I/O port behavior
-- (in a real C64 reset sets all DDR bits to input and pullup
-- resistors on the mainboard generate 1's)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
ioi : in std_logic_vector(7 downto 0);
ioo : out std_logic_vector(7 downto 0)
);
end ioport8bit;
architecture iop8_impl of ioport8bit is
signal data : std_logic_vector(7 downto 0);
signal ddr : std_logic_vector(7 downto 0); -- 0=in, 1=out
constant d_i : std_logic := '0';
constant d_o : std_logic := '1';
signal r0w1 : std_logic;
begin
r0w1 <= not r1w0;
read: process (a,data,ddr,ioi) is
variable pos : unsigned(2 downto 0);
begin
pos := "000";
case a is
when '1' => -- ioport
for pos in 7 downto 0 loop
if (ddr(pos) = d_o) then
dout(pos) <= data(pos);
else
dout(pos) <= ioi(pos);
end if;
end loop;
when others => -- ddr
dout <= ddr;
end case;
end process read;
write: process(clk,res0,ce,r0w1,a,din) is
begin
if (res0 = '1') then
-- kludge: Setting the first three bits to one
ddr <= "00101111";
data <= "00000111";
elsif (rising_edge(clk)) then
if (r0w1 = '1' and ce = '1') then
case a is
when '0' =>
ddr <= din;
when others =>
data <= din;
end case;
end if;
end if;
end process write;
iolines: process(data,ddr) is
variable pos : unsigned(2 downto 0);
begin
for pos in 7 downto 0 loop
if (ddr(pos) = '1') then
ioo(pos) <= data(pos);
else
ioo(pos) <= 'Z';
end if;
end loop;
end process iolines;
end iop8_impl;
|
----------------------------------------------------------------------------------
--
-- 8-bit I/O port
-- Contains kludge for 6510/C64 I/O port behavior
-- (in a real C64 reset sets all DDR bits to input and pullup
-- resistors on the mainboard generate 1's)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
ioi : in std_logic_vector(7 downto 0);
ioo : out std_logic_vector(7 downto 0)
);
end ioport8bit;
architecture iop8_impl of ioport8bit is
signal data : std_logic_vector(7 downto 0);
signal ddr : std_logic_vector(7 downto 0); -- 0=in, 1=out
constant d_i : std_logic := '0';
constant d_o : std_logic := '1';
signal r0w1 : std_logic;
begin
r0w1 <= not r1w0;
read: process (a,data,ddr,ioi) is
variable pos : unsigned(2 downto 0);
begin
pos := "000";
case a is
when '1' => -- ioport
for pos in 7 downto 0 loop
if (ddr(pos) = d_o) then
dout(pos) <= data(pos);
else
dout(pos) <= ioi(pos);
end if;
end loop;
when others => -- ddr
dout <= ddr;
end case;
end process read;
write: process(clk,res0,ce,r0w1,a,din) is
begin
if (res0 = '1') then
-- kludge: Setting the first three bits to one
ddr <= "00101111";
data <= "00000111";
elsif (rising_edge(clk)) then
if (r0w1 = '1' and ce = '1') then
case a is
when '0' =>
ddr <= din;
when others =>
data <= din;
end case;
end if;
end if;
end process write;
iolines: process(data,ddr) is
variable pos : unsigned(2 downto 0);
begin
for pos in 7 downto 0 loop
if (ddr(pos) = '1') then
ioo(pos) <= data(pos);
else
ioo(pos) <= 'Z';
end if;
end loop;
end process iolines;
end iop8_impl;
|
----------------------------------------------------------------------------------
--
-- 8-bit I/O port
-- Contains kludge for 6510/C64 I/O port behavior
-- (in a real C64 reset sets all DDR bits to input and pullup
-- resistors on the mainboard generate 1's)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
ioi : in std_logic_vector(7 downto 0);
ioo : out std_logic_vector(7 downto 0)
);
end ioport8bit;
architecture iop8_impl of ioport8bit is
signal data : std_logic_vector(7 downto 0);
signal ddr : std_logic_vector(7 downto 0); -- 0=in, 1=out
constant d_i : std_logic := '0';
constant d_o : std_logic := '1';
signal r0w1 : std_logic;
begin
r0w1 <= not r1w0;
read: process (a,data,ddr,ioi) is
variable pos : unsigned(2 downto 0);
begin
pos := "000";
case a is
when '1' => -- ioport
for pos in 7 downto 0 loop
if (ddr(pos) = d_o) then
dout(pos) <= data(pos);
else
dout(pos) <= ioi(pos);
end if;
end loop;
when others => -- ddr
dout <= ddr;
end case;
end process read;
write: process(clk,res0,ce,r0w1,a,din) is
begin
if (res0 = '1') then
-- kludge: Setting the first three bits to one
ddr <= "00101111";
data <= "00000111";
elsif (rising_edge(clk)) then
if (r0w1 = '1' and ce = '1') then
case a is
when '0' =>
ddr <= din;
when others =>
data <= din;
end case;
end if;
end if;
end process write;
iolines: process(data,ddr) is
variable pos : unsigned(2 downto 0);
begin
for pos in 7 downto 0 loop
if (ddr(pos) = '1') then
ioo(pos) <= data(pos);
else
ioo(pos) <= 'Z';
end if;
end loop;
end process iolines;
end iop8_impl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_k3_k4_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_shadow_k3_k4_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_k3_k4_rtl_conf / inst_shadow_k3_k4_e
--
configuration inst_shadow_k3_k4_rtl_conf of inst_shadow_k3_k4_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_k3_k4_rtl_conf;
--
-- End of Generated Configuration inst_shadow_k3_k4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--======================================================================
-- pdp11.vhd :: PDP-11 instruction-set compatible microprocessor
--======================================================================
--
-- The PDP-11 series was an extremely successful and influential
-- family of machines designed at Digital Equipment Corporation (DEC)
-- The first PDP-11 (/20) was designed in the early 1970's and the
-- PDP-11 family prospered for over two decades through the mid 1990s.
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity IP_PDP11 is
port (
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
R_W : out std_logic; -- 1==read 0==write
BYTE : out std_logic; -- Byte memory operation
SYNC : out std_logic; -- Opcode fetch status
IRQ0 : in std_logic; -- Interrupt (active-low)
IRQ1 : in std_logic; -- Interrupt (active-low)
IRQ2 : in std_logic; -- Interrupt (active-low)
IRQ3 : in std_logic; -- Interrupt (active-low)
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- system clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end IP_PDP11;
architecture BEHAVIORAL of IP_PDP11 is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
signal STATE : UCODE_STATE_TYPE;
signal NEXT_STATE : UCODE_STATE_TYPE;
signal C_OPCODE : CNT_OP_TYPE; -- count register micro-op
signal T_OPCODE : REG_OP_TYPE; -- temp register micro-op
signal S_OPCODE : REG_OP_TYPE; -- src operand micro-op
signal D_OPCODE : REG_OP_TYPE; -- dst operand micro-op
signal SA_OPCODE : REG_OP_TYPE; -- src address micro-op
signal DA_OPCODE : REG_OP_TYPE; -- dst address micro-op
signal ALU_OPCODE : ALU_OP_TYPE; -- ALU micro-op
signal SX_OPCODE : SX_OP_TYPE; -- Address micro-op
signal R0_OPCODE : PC_OP_TYPE; -- R0 micro-op
signal R1_OPCODE : PC_OP_TYPE; -- R1 micro-op
signal R2_OPCODE : PC_OP_TYPE; -- R2 micro-op
signal R3_OPCODE : PC_OP_TYPE; -- R3 micro-op
signal R4_OPCODE : PC_OP_TYPE; -- R4 micro-op
signal R5_OPCODE : PC_OP_TYPE; -- R5 micro-op
signal SP_OPCODE : REG_OP_TYPE; -- SP micro-op
signal PC_OPCODE : PC_OP_TYPE; -- PC micro-op
-- Internal busses
signal ABUS : std_logic_vector(15 downto 0); -- ALU operand A bus
signal BBUS : std_logic_vector(15 downto 0); -- ALU operand B bus
signal RBUS : std_logic_vector(15 downto 0); -- ALU result bus
signal SX : std_logic_vector(15 downto 0); -- Addr result bus
signal ADDR_OX : std_logic_vector(15 downto 0); -- Internal addr bus
signal DATA_OX : std_logic_vector(15 downto 0); -- Internal data bus
signal BYTE_DATA : std_logic_vector(15 downto 0); -- Byte_op data
signal ASEL : ASEL_TYPE;
signal BSEL : BSEL_TYPE;
-- Address Decoding
signal MACRO_OP : MACRO_OP_TYPE; -- macro opcode
signal BYTE_OP : std_logic;
signal BYTE_ALU : std_logic;
signal FORMAT_OP : std_logic_vector( 2 downto 0);
signal FORMAT : std_logic_vector( 2 downto 0);
signal SRC_MODE : std_logic_vector( 2 downto 0);
signal SRC_RSEL : std_logic_vector( 2 downto 0);
signal SRC_LOAD : std_logic;
signal DST_MODE : std_logic_vector( 2 downto 0);
signal DST_RSEL : std_logic_vector( 2 downto 0);
signal DST_LOAD : std_logic;
-- Architectural registers
signal R0 : std_logic_vector(15 downto 0); -- register 0
signal R1 : std_logic_vector(15 downto 0); -- register 1
signal R2 : std_logic_vector(15 downto 0); -- register 2
signal R3 : std_logic_vector(15 downto 0); -- register 3
signal R4 : std_logic_vector(15 downto 0); -- register 4
signal R5 : std_logic_vector(15 downto 0); -- register 5
signal SP : std_logic_vector(15 downto 0); -- stack pointer
signal PC : std_logic_vector(15 downto 0); -- program counter
signal PSW : std_logic_vector( 3 downto 0); -- status word
signal T : std_logic_vector(15 downto 0); -- temp register
signal SA : std_logic_vector(15 downto 0); -- src address
signal DA : std_logic_vector(15 downto 0); -- dst address
signal S : std_logic_vector(15 downto 0); -- src operand
signal D : std_logic_vector(15 downto 0); -- dst operand
signal SMUX : std_logic_vector(15 downto 0); -- src operand
signal DMUX : std_logic_vector(15 downto 0); -- dst operand
signal OPREG : std_logic_vector(15 downto 0); -- opcode reg
-- Status flag update
signal UPDATE_N : std_logic; -- update sign flag
signal UPDATE_Z : std_logic; -- update zero flag
signal UPDATE_V : std_logic; -- update overflow flag
signal UPDATE_C : std_logic; -- update carry flag
signal UPDATE_XC : std_logic; -- update aux carry flag
signal SET_N : std_logic; -- set N flag
signal SET_C : std_logic; -- set C flag
signal SET_V : std_logic; -- set V flag
signal SET_Z : std_logic; -- set Z flag
signal CLR_N : std_logic; -- clear N flag
signal CLR_C : std_logic; -- clear C flag
signal CLR_V : std_logic; -- clear V flag
signal CLR_Z : std_logic; -- clear Z flag
signal CCC_OP : std_logic; -- conditional clear
signal SCC_OP : std_logic; -- conditional set
-- Arithmetic Status
signal CARRY : std_logic; -- ALU carry-out
signal ZERO : std_logic; -- ALU Zero status
signal OVERFLOW : std_logic; -- ALU overflow
signal SIGNBIT : std_logic; -- ALU sign bit
signal XC : std_logic; -- ALU carry-out
-- Interrupt Status flip-flops
signal IRQ_FF : std_logic; -- IRQ flip-flop
signal CLR_IRQ : std_logic; -- clear IRQ flip-flop
signal IRQ_MASK : std_logic_vector( 3 downto 0);
signal IRQ_VEC : std_logic_vector( 3 downto 0);
-- Misc
signal MY_RESET : std_logic; -- active high reset
signal FETCH_FF : std_logic; -- fetch cycle flag
signal READING : std_logic; -- R/W status
signal CONDITION : std_logic; -- branch condition
signal INT_OK : std_logic; -- interrupt level OK
signal INIT_MPY : std_logic; -- for multiply
signal MPY_STEP : std_logic; -- for multiply
signal INIT_DIV : std_logic; -- for divide
signal DIV_STEP : std_logic; -- for divide
signal DIV_LAST : std_logic; -- for divide
signal DIV_OP : std_logic; -- for divide
signal SA_SBIT : std_logic; -- for divide
signal DIV_SBIT : std_logic; -- for divide
signal D_SBIT : std_logic; -- for divide
signal BYTE_FF : std_logic; -- byte flag
signal SET_BYTE_FF : std_logic; -- set byte flag
signal CLR_BYTE_FF : std_logic; -- clr byte flag
signal DEST_FF : std_logic; -- dest flag
signal SET_DEST_FF : std_logic; -- set dest flag
signal CLR_DEST_FF : std_logic; -- clr dest flag
signal C : std_logic_vector( 3 downto 0);
signal JSE : std_logic_vector( 6 downto 0);
signal BRANCH_OP : std_logic_vector( 3 downto 0);
--================================================================
-- Constant definition section
--================================================================
--================================================================
-- Component definition section
--================================================================
--==========================
-- instruction decoder
--==========================
component DECODE
port (
MACRO_OP : out MACRO_OP_TYPE; -- opcode
BYTE_OP : out std_logic; -- byte/word
FORMAT : out std_logic_vector( 2 downto 0); -- format
IR : in std_logic_vector(15 downto 0) -- inst reg
);
end component;
--==============================
-- 16-bit ALU
--==============================
component ALU
port (
COUT : out std_logic; -- carry out
ZERO : out std_logic; -- zero
OVFL : out std_logic; -- overflow
SIGN : out std_logic; -- sign
RBUS : out std_logic_vector(15 downto 0); -- result bus
A : in std_logic_vector(15 downto 0); -- operand A
B : in std_logic_vector(15 downto 0); -- operand B
OP : in ALU_OP_TYPE; -- micro op
BYTE_OP : in std_logic; -- byte op
DIV_OP : in std_logic; -- divide op
DIV_SBIT : in std_logic; -- divide sign bit
CIN : in std_logic -- carry in
);
end component;
--==============================
-- 16-bit Address Adder
--==============================
component ADDR
port (
SX : out std_logic_vector(15 downto 0); -- result bus
BX : in std_logic_vector(15 downto 0); -- operand bus
DISP : in std_logic_vector( 7 downto 0); -- displacement
OP : in SX_OP_TYPE -- micro op
);
end component;
--==============================
-- 4-bit Comparator
--==============================
component CMPR
port (
A_LE_B : out std_logic; -- A <= B
A : in std_logic_vector(3 downto 0); -- operand A
B : in std_logic_vector(3 downto 0) -- operand B
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
--================================================================
-- Start of the behavioral description
--================================================================
MY_RESET <= not RESET;
--================================================================
-- Microcode state machine
--================================================================
MICROCODE_STATE_MACHINE:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((FEN = '1') and (RDY = '1')) then
STATE <= NEXT_STATE;
-- reset state
if (MY_RESET = '1') then
STATE <= RST_1;
end if;
end if;
end if;
end process;
--================================================================
-- Signals for Debug
--================================================================
DBUG1 <= '1';
DBUG2 <= '1';
DBUG3 <= '1';
DBUG4 <= '1';
DBUG5 <= '1';
DBUG6 <= '1';
DBUG7 <= MY_RESET;
--================================================================
-- Register IRQ (active-low) inputs
--================================================================
INTERRUPT_STATUS_REGISTERS:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
-- Only set the IRQ flip-flop if the interrupt level
-- is less than or equal to the interrupt mask
if ((IRQ0 = '0') and (INT_OK = '1')) then
IRQ_FF <= '1';
end if;
if (CLR_IRQ = '1') then
IRQ_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
IRQ_FF <= '0';
IRQ_VEC <= (others => '0');
IRQ_MASK <= (others => '0');
end if;
end process;
--================================================================
-- Opcode Register
--================================================================
OPCODE_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (STATE = FETCH_OPCODE) then
OPREG <= DATA_IN;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
OPREG <= (others => '0');
end if;
end process;
--================================================================
-- Fetch cycle flag
--================================================================
FETCH_CYCLE_FLAG:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
FETCH_FF <= '0';
if (NEXT_STATE = FETCH_OPCODE) then
FETCH_FF <= '1';
end if;
end if;
end if;
end process;
--================================================================
-- byte flag
--================================================================
BYTE_FLAG:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (SET_BYTE_FF = '1') then
BYTE_FF <= '1';
end if;
if (CLR_BYTE_FF = '1') then
BYTE_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
BYTE_FF <= '0';
end if;
end process;
BYTE <= BYTE_FF;
--================================================================
-- dest flag
--================================================================
DEST_FLAG:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (SET_DEST_FF = '1') then
DEST_FF <= '1';
end if;
if (CLR_DEST_FF = '1') then
DEST_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
DEST_FF <= '0';
end if;
end process;
--================================================================
-- modify format to reuse code
--================================================================
MODIFY_FORMAT:
process(FORMAT_OP, DEST_FF)
begin
FORMAT <= FORMAT_OP;
-- force TWO_OPERAND to become ONE_OPERAND
if (DEST_FF = '1') then
FORMAT(0) <= '0';
end if;
end process;
SYNC <= FETCH_FF;
ADDR_OUT <= ADDR_OX;
BRANCH_OP <= OPREG(15) & OPREG(10 downto 8);
SRC_MODE <= OPREG(11 downto 9);
SRC_RSEL <= OPREG( 8 downto 6);
DST_MODE <= OPREG( 5 downto 3);
DST_RSEL <= OPREG( 2 downto 0);
--================================================================
-- Micro-operation and next-state generation
--================================================================
MICRO_OP_AND_NEXT_STATE_GENERATION:
process(MACRO_OP, FORMAT, STATE, PC, SP, SA, DA, T, XC, C, PSW,
SRC_MODE, SRC_RSEL, DST_MODE, DST_RSEL, RBUS, DMUX, SMUX,
SA_SBIT, D_SBIT, BYTE_OP, BYTE_FF, IRQ_FF, CONDITION,
SRC_LOAD, DST_LOAD)
begin
-- default micro-ops
R0_OPCODE <= HOLD;
R1_OPCODE <= HOLD;
R2_OPCODE <= HOLD;
R3_OPCODE <= HOLD;
R4_OPCODE <= HOLD;
R5_OPCODE <= HOLD;
SP_OPCODE <= HOLD;
PC_OPCODE <= HOLD;
SA_OPCODE <= HOLD;
DA_OPCODE <= HOLD;
S_OPCODE <= HOLD;
D_OPCODE <= HOLD;
C_OPCODE <= HOLD;
T_OPCODE <= HOLD;
ALU_OPCODE <= OP_INCA1;
SX_OPCODE <= OP_INC2;
-- default flag control
UPDATE_N <= '0'; -- update sign flag
UPDATE_Z <= '0'; -- update zero flag
UPDATE_V <= '0'; -- update overflow flag
UPDATE_C <= '0'; -- update carry flag
UPDATE_XC <= '0'; -- update carry flag
CLR_IRQ <= '0'; -- clear IRQ_FF
SET_N <= '0'; -- set N flag
SET_C <= '0'; -- set C flag
SET_V <= '0'; -- set V flag
SET_Z <= '0'; -- set Z flag
CLR_N <= '0'; -- clear N flag
CLR_C <= '0'; -- clear C flag
CLR_V <= '0'; -- clear V flag
CLR_Z <= '0'; -- clear Z flag
CCC_OP <= '0'; -- conditional clear
SCC_OP <= '0'; -- conditional set
BYTE_ALU <= '0'; -- ALU byte operation
NEXT_STATE <= FETCH_OPCODE;
DATA_OX <= RBUS;
ADDR_OX <= PC;
DST_LOAD <= '0';
SRC_LOAD <= '0';
READING <= '1';
ASEL <= SEL_PC;
BSEL <= SEL_D;
SET_BYTE_FF <= '0';
CLR_BYTE_FF <= '0';
SET_DEST_FF <= '0';
CLR_DEST_FF <= '0';
INIT_MPY <= '0';
INIT_DIV <= '0';
MPY_STEP <= '0';
DIV_STEP <= '0';
DIV_LAST <= '0';
DIV_SBIT <= D_SBIT;
case STATE is
--============================================
-- Reset startup sequence
--============================================
when RST_1 =>
-- Stay here until reset is de-bounced
NEXT_STATE <= FETCH_OPCODE;
when IRQ_1 =>
-- fix me !!!!
-- lot's of stuff missing here
ALU_OPCODE <= OP_TA;
T_OPCODE <= LOAD_FROM_ALU;
CLR_IRQ <= '1';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Fetch Opcode State
--============================================
when FETCH_OPCODE =>
if (IRQ_FF = '1') then
-- handle the interrupt
NEXT_STATE <= IRQ_1;
else
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= GOT_OPCODE;
end if;
CLR_BYTE_FF <= '1';
--============================================
-- Opcode register contains an opcode
--============================================
when GOT_OPCODE =>
if (BYTE_OP = '1') then
SET_BYTE_FF <= '1';
else
CLR_BYTE_FF <= '1';
end if;
case FORMAT is
--=================================
-- One operand Instruction Format
--=================================
when ONE_OPERAND =>
-- destination address mode calculations
case DST_MODE(2 downto 1) is
-- register
when "00" =>
-- check deferred bit
if (DST_MODE(0) = '0') then
-- load from register
D_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= DST_RI1;
end if;
-- post-increment
when "01" =>
ADDR_OX <= DMUX;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
DA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= DST_PI1;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_PI2;
end if;
-- pre-decrement
when "10" =>
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_DECA2;
if (BYTE_OP = '1') then
ALU_OPCODE <= OP_DECA1;
end if;
DST_LOAD <= '1';
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DST_PD1;
-- indexed ("11")
when others =>
-- get the next word
ADDR_OX <= PC;
D_OPCODE <= LOAD_FROM_MEM;
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= DST_X1;
end case;
--=======================================================
-- Two operands instruction Format
--=======================================================
when TWO_OPERAND =>
-- allow dest code reuse
SET_DEST_FF <= '1';
-- source address mode calculations
case SRC_MODE(2 downto 1) is
-- register
when "00" =>
if (SRC_MODE(0) = '0') then
-- load from register
S_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= GOT_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= SRC_RI1;
end if;
-- post-increment
when "01" =>
ADDR_OX <= SMUX;
-- check deferred bit
if (SRC_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
SA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= SRC_PI1;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_PI2;
end if;
-- pre-decrement
when "10" =>
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_DECA2;
if (BYTE_OP = '1') then
ALU_OPCODE <= OP_DECA1;
end if;
SRC_LOAD <= '1';
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= SRC_PD1;
-- indexed ("11")
when others =>
-- get the next word
ADDR_OX <= PC;
S_OPCODE <= LOAD_FROM_MEM;
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= SRC_X1;
end case;
--=================================
-- Branch Instruction Format
--=================================
when BRA_FORMAT =>
SX_OPCODE <= OP_REL;
if (CONDITION = '1') then
PC_OPCODE <= LOAD_FROM_SX;
end if;
NEXT_STATE <= FETCH_OPCODE;
--======================================
-- Floating Point Instruction Format
--======================================
when FLOAT =>
-- not implemented
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
--======================================
-- Implied-Operand Instruction Format
--======================================
when others =>
case MACRO_OP is
when MOP_HALT =>
-- halt processor
NEXT_STATE <= HALT_1;
when MOP_WAIT =>
-- wait for interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RESET =>
-- reset bus
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RTS =>
-- return from subroutine
-- load the PC from the link reg
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_TA;
PC_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= RTS_1;
-- special case when PC is link reg
if (DST_RSEL = "111") then
-- load the PC from the stack
ADDR_OX <= SP;
PC_OPCODE <= LOAD_FROM_MEM;
-- post-increment the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_INCA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= FETCH_OPCODE;
end if;
when MOP_RTI =>
-- return from interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RTT =>
-- return from interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_MARK =>
-- mark stack
NEXT_STATE <= FETCH_OPCODE;
when MOP_TRAP =>
-- SW trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_BPT =>
-- breakpoint trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_IOT =>
-- I/O trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_EMT =>
-- emulator trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEN =>
-- set N flag
SET_N <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEC =>
-- set C flag
SET_C <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEV =>
-- set V flag
SET_V <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEZ =>
-- set Z flag
SET_Z <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLN =>
-- clear N flag
CLR_N <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLC =>
-- clear C flag
CLR_C <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLV =>
-- clear V flag
CLR_V <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLZ =>
-- clear Z flag
CLR_Z <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CCC =>
-- clear condition codes
CCC_OP <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SCC =>
-- set condition codes
SCC_OP <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CSM =>
-- call supervisor mode
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPT =>
-- move from processor type
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPI =>
-- move from prev I-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPI =>
-- move to prev I-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPD =>
-- move to prev D-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPD =>
-- move to prev D-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPS =>
-- move to processor status
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPS =>
-- move from processor status
NEXT_STATE <= FETCH_OPCODE;
when others =>
-- unimplemented instruction
NEXT_STATE <= FETCH_OPCODE;
end case;
end case; -- end of instruction format case
--====================================================
-- We have the operands, now execute the instruction
--====================================================
when EXEC_OPCODE =>
CLR_DEST_FF <= '1';
BYTE_ALU <= BYTE_OP;
case MACRO_OP is
--=================================
-- Jump Instructions
--=================================
-- Jump
when MOP_JMP =>
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
-- Jump to Subroutine
when MOP_JSR =>
-- pre-decrement the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_DECA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= JSR_1;
--=================================
-- One-operand Instructions
--=================================
-- Test
when MOP_TST =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_TA;
D_OPCODE <= HOLD;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
NEXT_STATE <= FETCH_OPCODE;
-- Bit Test
when MOP_BIT =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_AND;
D_OPCODE <= HOLD;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
NEXT_STATE <= FETCH_OPCODE;
-- Clear
when MOP_CLR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ZERO;
D_OPCODE <= LOAD_FROM_ALU;
CLR_N <= '1'; -- clear sign flag
SET_Z <= '1'; -- set zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Sign Extend
when MOP_SXT =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ZERO;
-- check the sign bit
if (PSW(3) = '1') then
ALU_OPCODE <= OP_ONES;
end if;
D_OPCODE <= LOAD_FROM_ALU;
CLR_N <= '1'; -- clear sign flag
SET_Z <= '1'; -- set zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Ones Complement
when MOP_COM =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_INV;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
SET_C <= '1'; -- set carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Decrement by 1
when MOP_DEC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_DECA1;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Increment by 1
when MOP_INC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_INCA1;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Negate
when MOP_NEG =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_NEG;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Swap Bytes
when MOP_SWAB =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_SWP;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Rotate Right
when MOP_ROR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ROR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Rotate Left
when MOP_ROL =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ROL;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Shift Right
when MOP_ASR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ASR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Shift Left
when MOP_ASL =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ASL;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
--=================================
-- Two-operand Instructions
--=================================
-- Add
when MOP_ADD =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_ADD;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Add Carry
when MOP_ADC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ADC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Subtract
when MOP_SUB =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Subtract Carry
when MOP_SBC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_SBC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Compare
when MOP_CMP =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
NEXT_STATE <= FETCH_OPCODE;
-- Move
when MOP_MOV =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_TA;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Exclusive OR
when MOP_XOR =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_XOR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Bit Clear
when MOP_BIC =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_BIC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Bit Set
when MOP_BIS =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_OR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Multiply
when MOP_MUL =>
-- multiplicand is in D
-- multiplier is in S
-- accumulate product in T:SA
-- clear T and SA
-- load C with the MPY count
INIT_MPY <= '1';
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Divide
when MOP_DIV =>
-- the divisor is in S
-- the dividend is in D:T
-- the quotient will be in T
-- the remainder will be left in D
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
INIT_DIV <= '1';
UPDATE_XC <= '1'; -- update aux carry flag
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_1;
when others =>
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
end case; -- end of MACRO_OP case
--============================================
-- Complete destination register indirect
--============================================
when DST_RI1 =>
ADDR_OX <= DA;
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
--============================================
-- Complete source register indirect
--============================================
when SRC_RI1 =>
ADDR_OX <= SA;
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= GOT_OPCODE;
--============================================
-- Complete destination post increment
--============================================
when DST_PI1 =>
if (DST_RSEL = "111") then
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
else
-- post-increment the register
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_INCA2;
if (BYTE_FF = '1') then
ALU_OPCODE <= OP_INCA1;
end if;
DST_LOAD <= '1';
end if;
NEXT_STATE <= EXEC_OPCODE;
--============================================
-- Complete destination post indirect
--============================================
when DST_PI2 =>
ADDR_OX <= DA;
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_PI1;
--============================================
-- Complete source post increment
--============================================
when SRC_PI1 =>
if (SRC_RSEL = "111") then
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
else
-- post-increment the register
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_INCA2;
if (BYTE_FF = '1') then
ALU_OPCODE <= OP_INCA1;
end if;
SRC_LOAD <= '1';
end if;
NEXT_STATE <= GOT_OPCODE;
--============================================
-- Complete source post indirect
--============================================
when SRC_PI2 =>
ADDR_OX <= SA;
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_PI1;
--============================================
-- Complete destination pre decrement
--============================================
when DST_PD1 =>
ADDR_OX <= DA;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_RI1;
end if;
--============================================
-- Complete source pre decrement
--============================================
when SRC_PD1 =>
ADDR_OX <= SA;
-- check deferred bit
if (DST_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= GOT_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_RI1;
end if;
--============================================
-- Complete destination indexed address
--============================================
when DST_X1 =>
-- add D + R
ASEL <= SEL_D; -- D
BSEL <= SEL_DMUX; -- R
ALU_OPCODE <= OP_ADD;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DST_X2;
--============================================
-- Complete destination indexed address
--============================================
when DST_X2 =>
ADDR_OX <= DA;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_RI1;
end if;
--============================================
-- Complete source indexed address
--============================================
when SRC_X1 =>
-- add S + R
ASEL <= SEL_S; -- S
BSEL <= SEL_SMUX; -- R
ALU_OPCODE <= OP_ADD;
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= SRC_X2;
--============================================
-- Complete source indexed address
--============================================
when SRC_X2 =>
ADDR_OX <= SA;
-- check deferred bit
if (SRC_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_RI1;
end if;
--============================================
-- Store the result
--============================================
when STORE_D =>
-- store to the destination address
ADDR_OX <= DA;
ASEL <= SEL_D;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Halt the processor
-- requires reboot or operator console input
--============================================
when HALT_1 =>
PC_OPCODE <= HOLD;
NEXT_STATE <= HALT_1;
--============================================
-- Complete the JSR instruction
--============================================
when JSR_1 =>
-- store the source register
-- onto the stack
ADDR_OX <= SP;
READING <= '0';
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_TA;
NEXT_STATE <= JSR_2;
-- special case when PC is link reg
if (SRC_RSEL = "111") then
-- load the PC with the dest address
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
end if;
when JSR_2 =>
-- copy the PC to the source register
ASEL <= SEL_PC;
ALU_OPCODE <= OP_TA;
SRC_LOAD <= '1';
-- load the PC with the dest address
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the RTS instruction
--============================================
when RTS_1 =>
-- load the PC from the stack
ADDR_OX <= SP;
PC_OPCODE <= LOAD_FROM_MEM;
-- post-increment the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_INCA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the multiply instruction
--============================================
when MPY_1 =>
-- if the multiplier bit is a 1
-- then add the multiplicand to the product
-- and shift product and multiplier right
ASEL <= SEL_D;
BSEL <= SEL_T;
ALU_OPCODE <= OP_ADD;
MPY_STEP <= '1';
-- decrement the loop count
C_OPCODE <= DEC;
NEXT_STATE <= MPY_1;
-- Check if we are done
if (C = "0000") then
NEXT_STATE <= MPY_2;
end if;
when MPY_2 =>
-- store the upper product
ADDR_OX <= DA;
DATA_OX <= T;
READING <= '0';
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= MPY_3;
when MPY_3 =>
-- store the lower product
ADDR_OX <= DA;
ASEL <= SEL_SA;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the divide instruction
--============================================
when DIV_1 =>
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_2;
-- if D > S then abort
if (XC = '1') then
NEXT_STATE <= FETCH_OPCODE;
end if;
when DIV_2 =>
-- get the lower dividend
ADDR_OX <= DA;
T_OPCODE <= LOAD_FROM_MEM;
-- decrement DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_DECA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_3;
when DIV_3 =>
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
DIV_SBIT <= SA_SBIT;
BSEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_SUBA;
UPDATE_XC <= '1'; -- update aux carry flag
DIV_STEP <= '1';
C_OPCODE <= DEC;
NEXT_STATE <= DIV_3;
-- Check if we are done
if (C = "0000") then
NEXT_STATE <= DIV_4;
end if;
when DIV_4 =>
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
DIV_SBIT <= SA_SBIT;
BSEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_SUBA;
UPDATE_XC <= '1'; -- update aux carry flag
DIV_LAST <= '1';
C_OPCODE <= DEC;
NEXT_STATE <= DIV_5;
when DIV_5 =>
-- store the quotient
ADDR_OX <= DA;
DATA_OX <= T;
READING <= '0';
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_6;
when DIV_6 =>
-- store the remainder
ADDR_OX <= DA;
ASEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
ASEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--=========================================
-- Unimplemented Opcodes
--=========================================
when others =>
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
end case; -- end of STATE case
--=============================================
-- Load Source register
--=============================================
if (SRC_LOAD = '1') then
-- select register to load
case SRC_RSEL is
when "000" =>
R0_OPCODE <= LOAD_FROM_ALU;
when "001" =>
R1_OPCODE <= LOAD_FROM_ALU;
when "010" =>
R2_OPCODE <= LOAD_FROM_ALU;
when "011" =>
R3_OPCODE <= LOAD_FROM_ALU;
when "100" =>
R4_OPCODE <= LOAD_FROM_ALU;
when "101" =>
R5_OPCODE <= LOAD_FROM_ALU;
when "110" =>
SP_OPCODE <= LOAD_FROM_ALU;
when "111" =>
PC_OPCODE <= LOAD_FROM_ALU;
when others =>
end case;
end if;
--=============================================
-- Load Destination register
--=============================================
if (DST_LOAD = '1') then
-- select register to load
case DST_RSEL is
when "000" =>
R0_OPCODE <= LOAD_FROM_ALU;
when "001" =>
R1_OPCODE <= LOAD_FROM_ALU;
when "010" =>
R2_OPCODE <= LOAD_FROM_ALU;
when "011" =>
R3_OPCODE <= LOAD_FROM_ALU;
when "100" =>
R4_OPCODE <= LOAD_FROM_ALU;
when "101" =>
R5_OPCODE <= LOAD_FROM_ALU;
when "110" =>
SP_OPCODE <= LOAD_FROM_ALU;
when "111" =>
PC_OPCODE <= LOAD_FROM_ALU;
when others =>
end case;
end if;
end process;
--================================================
-- Destination register select
--================================================
DEST_REG_SELECT:
process(DST_RSEL, R0, R1, R2, R3, R4, R5, SP, PC)
begin
case DST_RSEL is
when "000" =>
DMUX <= R0;
when "001" =>
DMUX <= R1;
when "010" =>
DMUX <= R2;
when "011" =>
DMUX <= R3;
when "100" =>
DMUX <= R4;
when "101" =>
DMUX <= R5;
when "110" =>
DMUX <= SP;
when others =>
DMUX <= PC;
end case;
end process;
--================================================
-- Source register select
--================================================
SRC_RSEL_SELECT:
process(SRC_RSEL, R0, R1, R2, R3, R4, R5, SP, PC)
begin
case SRC_RSEL is
when "000" =>
SMUX <= R0;
when "001" =>
SMUX <= R1;
when "010" =>
SMUX <= R2;
when "011" =>
SMUX <= R3;
when "100" =>
SMUX <= R4;
when "101" =>
SMUX <= R5;
when "110" =>
SMUX <= SP;
when others =>
SMUX <= PC;
end case;
end process;
--============================================
-- Branch Condition Select
--============================================
BRANCH_CONDITION_SELECT:
process(BRANCH_OP, PSW)
begin
CONDITION <= '0';
case BRANCH_OP is
when "0001" =>
-- BR :: Unconditional
CONDITION <= '1';
when "0010" =>
-- BNE :: Not Equal
-- Zero = 0
CONDITION <= not PSW(2);
when "0011" =>
-- BEQ :: Equal
-- Zero = 1
CONDITION <= PSW(2);
when "0100" =>
-- BGE :: Greater Than of Equal
-- (Sign xor Overflow) = 0
CONDITION <= not (PSW(3) xor PSW(1));
when "0101" =>
-- BLT :: Less Than
-- (Sign xor Overflow) = 1
CONDITION <= PSW(3) xor PSW(1);
when "0110" =>
-- BGT :: Greater Than
-- (zero and (Sign xor Overflow)) = 0
CONDITION <= not(PSW(2) or (PSW(3) xor PSW(1)));
when "0111" =>
-- BLE :: Less Than or Equal
-- (zero and (Sign xor Overflow)) = 1
CONDITION <= PSW(2) or (PSW(3) xor PSW(1));
when "1000" =>
-- BPL :: Plus
-- Sign = 0
CONDITION <= not PSW(3);
when "1001" =>
-- BMI :: Minus
-- Sign = 1
CONDITION <= PSW(3);
when "1010" =>
-- BHI :: Higher
-- (Carry or Zero) = 0
CONDITION <= not(PSW(2) or PSW(0));
when "1011" =>
-- BLOS :: Lower or same
-- (Carry or Zero) = 1
CONDITION <= PSW(2) or PSW(0);
when "1100" =>
-- BVC :: Overflow Clear
-- Overflow = 0
CONDITION <= not PSW(1);
when "1101" =>
-- BVS :: Overflow Set
-- Overflow = 1
CONDITION <= PSW(1);
when "1110" =>
-- BCC :: Carry clear
-- Carry = 0
CONDITION <= not PSW(0);
when "1111" =>
-- BCS :: Carry set
-- Carry = 1
CONDITION <= PSW(0);
when others =>
-- Never
CONDITION <= '0';
end case;
end process;
--==================================================
-- A Mux
--==================================================
AMUX:
process(ASEL, SA, DA, S, D, DMUX, SMUX, PSW, SP, PC)
begin
case ASEL is
when SEL_SA =>
ABUS <= SA;
when SEL_DA =>
ABUS <= DA;
when SEL_S =>
ABUS <= S;
when SEL_D =>
ABUS <= D;
when SEL_DMUX =>
ABUS <= DMUX;
when SEL_SMUX =>
ABUS <= SMUX;
when SEL_PSW =>
ABUS <= "000000000000" & PSW;
when SEL_SP =>
ABUS <= SP;
when others =>
ABUS <= PC;
end case;
end process;
JSE <= (others => OPREG(7));
--=========================================================
-- B Mux
--=========================================================
BMUX:
process(BSEL, SA, DMUX, SMUX, T, D)
begin
case BSEL is
when SEL_SA =>
BBUS <= SA;
when SEL_DMUX =>
BBUS <= DMUX;
when SEL_SMUX =>
BBUS <= SMUX;
when SEL_T =>
BBUS <= T;
when others =>
BBUS <= D;
end case;
end process;
--=============================================
-- Byte input data (swap memory data byte)
--=============================================
MEM_BYTE_DATA_IN:
process (ADDR_OX(0), DATA_IN)
begin
BYTE_DATA <= "00000000" & DATA_IN(7 downto 0);
if (ADDR_OX(0) = '1') then
BYTE_DATA <= "00000000" & DATA_IN(15 downto 8);
end if;
end process;
--=============================================
-- Byte output data (swap memory data byte)
--=============================================
MEM_BYTE_DATA_OUT:
process (BYTE_OP, ADDR_OX(0), DATA_OX)
begin
DATA_OUT <= DATA_OX;
if ((BYTE_OP = '1') and (ADDR_OX(0) = '1')) then
DATA_OUT(15 downto 8) <= DATA_OX(7 downto 0);
end if;
end process;
--=======================================================
-- External RAM Write Enable
--=======================================================
R_W <= READING;
--=================================================
-- Processor Status Register
--=================================================
PSW_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
--===== Sign ========
if (UPDATE_N = '1') then
PSW(3) <= RBUS(15);
end if;
if (SET_N = '1') then
PSW(3) <= '1';
end if;
if (CLR_N = '1') then
PSW(3) <= '0';
end if;
if (CCC_OP = '1') then
PSW(3) <= PSW(3) and not OPREG(3);
end if;
if (SCC_OP = '1') then
PSW(3) <= PSW(3) or OPREG(3);
end if;
--===== Zero ========
if (UPDATE_Z = '1') then
PSW(2) <= ZERO;
end if;
if (SET_Z = '1') then
PSW(2) <= '1';
end if;
if (CLR_Z = '1') then
PSW(2) <= '0';
end if;
if (CCC_OP = '1') then
PSW(2) <= PSW(2) and not OPREG(2);
end if;
if (SCC_OP = '1') then
PSW(2) <= PSW(2) or OPREG(2);
end if;
--===== Overflow ========
if (UPDATE_V = '1') then
PSW(1) <= OVERFLOW;
end if;
if (SET_V = '1') then
PSW(1) <= '1';
end if;
if (CLR_V = '1') then
PSW(1) <= '0';
end if;
if (CCC_OP = '1') then
PSW(1) <= PSW(1) and not OPREG(1);
end if;
if (SCC_OP = '1') then
PSW(1) <= PSW(1) or OPREG(1);
end if;
--===== Carry ========
if (UPDATE_C = '1') then
PSW(0) <= CARRY;
end if;
if (SET_C = '1') then
PSW(0) <= '1';
end if;
if (CLR_C = '1') then
PSW(0) <= '0';
end if;
if (CCC_OP = '1') then
PSW(0) <= PSW(0) and not OPREG(0);
end if;
if (SCC_OP = '1') then
PSW(0) <= PSW(0) or OPREG(0);
end if;
--===== Aux Carry ========
if (UPDATE_XC = '1') then
XC <= CARRY;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
PSW <= (others => '0');
XC <= '0';
end if;
end process;
--=======================
-- Register R0
--=======================
REGISTER_R0:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R0_OPCODE is
when LOAD_FROM_ALU =>
R0 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R0 <= (others => '0');
end if;
end process;
--=======================
-- Register R1
--=======================
REGISTER_R1:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R1_OPCODE is
when LOAD_FROM_ALU =>
R1 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R1 <= (others => '0');
end if;
end process;
--=======================
-- Register R2
--=======================
REGISTER_R2:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R2_OPCODE is
when LOAD_FROM_ALU =>
R2 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R2 <= (others => '0');
end if;
end process;
--=======================
-- Register R3
--=======================
REGISTER_R3:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R3_OPCODE is
when LOAD_FROM_ALU =>
R3 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R3 <= (others => '0');
end if;
end process;
--=======================
-- Register R4
--=======================
REGISTER_R4:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R4_OPCODE is
when LOAD_FROM_ALU =>
R4 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R4 <= (others => '0');
end if;
end process;
--=======================
-- Register R5
--=======================
REGISTER_R5:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R5_OPCODE is
when LOAD_FROM_ALU =>
R5 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R5 <= (others => '0');
end if;
end process;
--=======================
-- Stack Pointer
--=======================
STACK_POINTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case SP_OPCODE is
when LOAD_FROM_ALU =>
SP <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
SP <= (others => '0');
end if;
end process;
--=======================
-- Program Counter
--=======================
PROGRAM_COUNTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case PC_OPCODE is
when LOAD_FROM_SX =>
PC <= SX;
when LOAD_FROM_ALU =>
PC <= RBUS;
when LOAD_FROM_MEM =>
PC <= DATA_IN;
when LOAD_FROM_DA =>
PC <= DA;
when others =>
-- hold
end case;
PC(0) <= '0'; -- PC is always even !!
end if;
end if;
-- reset state
if (MY_RESET = '1') then
PC <= (others => '0');
end if;
end process;
--===================================
-- Source operand Register
--===================================
S_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case S_OPCODE is
when LOAD_FROM_ALU =>
S <= RBUS;
when LOAD_FROM_REG =>
S <= SMUX;
when LOAD_FROM_MEM =>
S <= DATA_IN;
if (BYTE_OP = '1') then
S <= BYTE_DATA;
end if;
when others =>
-- hold
end case;
-- MPY step (shift multipier)
if (MPY_STEP = '1') then
S <= '0' & S(15 downto 1);
end if;
end if;
end if;
end process;
--===================================
-- Destination operand Register
--===================================
D_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
D_SBIT <= '0';
case D_OPCODE is
when LOAD_FROM_ALU =>
D <= RBUS;
when LOAD_FROM_REG =>
D <= DMUX;
when LOAD_FROM_MEM =>
D <= DATA_IN;
if (BYTE_OP = '1') then
D <= BYTE_DATA;
end if;
when others =>
-- hold
end case;
-- DIV step shift
if (DIV_STEP = '1') then
if (XC = '1') then
-- subtract and shift
D <= SA(14 downto 0) & T(15);
D_SBIT <= SA(15);
else
-- shift
D <= D(14 downto 0) & T(15);
D_SBIT <= D(15);
end if;
end if;
-- last DIV step
if (DIV_LAST = '1') then
if (XC = '1') then
-- subtract with no shift
D <= SA;
end if;
end if;
end if;
end if;
end process;
--===================================
-- Source Address Register
--===================================
SA_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
SA_SBIT <= '0';
case SA_OPCODE is
when LOAD_FROM_ALU =>
SA <= RBUS;
when LOAD_FROM_REG =>
SA <= SMUX;
when LOAD_FROM_MEM =>
SA <= DATA_IN;
when others =>
-- hold
end case;
-- initialize to zero for MPY
if (INIT_MPY = '1') then
SA <= (others => '0');
end if;
-- MPY step (add and shift)
if (MPY_STEP = '1') then
if (S(0) = '1') then
-- add and shift
SA <= RBUS(0) & SA(15 downto 1);
else
-- shift
SA <= T(0) & SA(15 downto 1);
end if;
end if;
-- DIV step (sub and shift)
if (DIV_STEP = '1') then
SA <= RBUS(14 downto 0) & T(15);
SA_SBIT <= RBUS(15);
end if;
-- last DIV step (sub with no shift)
if (DIV_LAST = '1') then
SA <= RBUS(15 downto 0);
end if;
end if;
end if;
end process;
--===================================
-- Destination Address Register
--===================================
DA_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case DA_OPCODE is
when LOAD_FROM_ALU =>
DA <= RBUS;
when LOAD_FROM_REG =>
DA <= DMUX;
when LOAD_FROM_MEM =>
DA <= DATA_IN;
when others =>
-- hold
end case;
end if;
end if;
end process;
--===================================
-- Temporary Register
--===================================
T_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case T_OPCODE is
when LOAD_FROM_ALU =>
T <= RBUS;
when LOAD_FROM_MEM =>
T <= DATA_IN;
when others =>
-- hold
end case;
-- init to zero for MPY
if (INIT_MPY = '1') then
T <= (others => '0');
end if;
-- MPY step shift
if (MPY_STEP = '1') then
if (S(0) = '1') then
-- add and shift
T <= CARRY & RBUS(15 downto 1);
else
-- shift
T <= '0' & T(15 downto 1);
end if;
end if;
-- DIV step shift
if ((DIV_STEP = '1') or (DIV_LAST = '1')) then
T <= T(14 downto 0) & CARRY;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
T <= (others => '0');
end if;
end process;
--===================================
-- Count Register
--===================================
C_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case C_OPCODE is
when LOAD_COUNT =>
-- load count from opcode
C <= OPREG(7 downto 4);
when DEC =>
-- decrement
C <= C - 1;
when others =>
-- hold
end case;
-- initialize with MPY count
if (INIT_MPY = '1') then
C <= (others => '1');
end if;
-- initialize with DIV count
if (INIT_DIV = '1') then
C <= (others => '1');
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
C <= (others => '0');
end if;
end process;
DIV_OP <= DIV_STEP or DIV_LAST;
--===================================
-- Instantiate the ALU
--===================================
ALU1:
ALU port map (
COUT => CARRY,
ZERO => ZERO,
OVFL => OVERFLOW,
SIGN => SIGNBIT,
RBUS => RBUS,
A => ABUS,
B => BBUS,
OP => ALU_OPCODE,
BYTE_OP => BYTE_ALU,
DIV_OP => DIV_OP,
DIV_SBIT => DIV_SBIT,
CIN => PSW(0)
);
--===================================
-- Instantiate the Address adder
--===================================
ADDR1:
ADDR port map (
SX => SX,
BX => PC,
DISP => OPREG(7 downto 0),
OP => SX_OPCODE
);
--=========================================
-- Instantiate the instruction decoder
--=========================================
DECODER:
DECODE port map (
MACRO_OP => MACRO_OP,
BYTE_OP => BYTE_OP,
FORMAT => FORMAT_OP,
IR => OPREG
);
--================================================
-- Instantiate the interrupt priority comparator
--================================================
PRIORITY:
CMPR port map (
A_LE_B => INT_OK,
A => "0000",
B => "1111"
);
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
package boot_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 667;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body boot_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C0001";
ram_buffer(1) := X"279C8A60";
ram_buffer(2) := X"3C1D0000";
ram_buffer(3) := X"27BD0A98";
ram_buffer(4) := X"0C0001BC";
ram_buffer(5) := X"00000000";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
ram_buffer(10) := X"00000000";
ram_buffer(11) := X"00000000";
ram_buffer(12) := X"00000000";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"00000000";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C000194";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C050000";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A0000";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"00850019";
ram_buffer(89) := X"00001012";
ram_buffer(90) := X"00002010";
ram_buffer(91) := X"03E00008";
ram_buffer(92) := X"ACC40000";
ram_buffer(93) := X"0000000C";
ram_buffer(94) := X"03E00008";
ram_buffer(95) := X"00000000";
ram_buffer(96) := X"AC900000";
ram_buffer(97) := X"AC910004";
ram_buffer(98) := X"AC920008";
ram_buffer(99) := X"AC93000C";
ram_buffer(100) := X"AC940010";
ram_buffer(101) := X"AC950014";
ram_buffer(102) := X"AC960018";
ram_buffer(103) := X"AC97001C";
ram_buffer(104) := X"AC9E0020";
ram_buffer(105) := X"AC9C0024";
ram_buffer(106) := X"AC9D0028";
ram_buffer(107) := X"AC9F002C";
ram_buffer(108) := X"03E00008";
ram_buffer(109) := X"34020000";
ram_buffer(110) := X"8C900000";
ram_buffer(111) := X"8C910004";
ram_buffer(112) := X"8C920008";
ram_buffer(113) := X"8C93000C";
ram_buffer(114) := X"8C940010";
ram_buffer(115) := X"8C950014";
ram_buffer(116) := X"8C960018";
ram_buffer(117) := X"8C97001C";
ram_buffer(118) := X"8C9E0020";
ram_buffer(119) := X"8C9C0024";
ram_buffer(120) := X"8C9D0028";
ram_buffer(121) := X"8C9F002C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"34A20000";
ram_buffer(124) := X"27BDFFC0";
ram_buffer(125) := X"AFBF003C";
ram_buffer(126) := X"AFB70034";
ram_buffer(127) := X"AFB5002C";
ram_buffer(128) := X"AFB1001C";
ram_buffer(129) := X"AFB00018";
ram_buffer(130) := X"AFBE0038";
ram_buffer(131) := X"AFB60030";
ram_buffer(132) := X"AFB40028";
ram_buffer(133) := X"AFB30024";
ram_buffer(134) := X"AFB20020";
ram_buffer(135) := X"0C000109";
ram_buffer(136) := X"3C15F0F0";
ram_buffer(137) := X"3C100000";
ram_buffer(138) := X"24040001";
ram_buffer(139) := X"0C000186";
ram_buffer(140) := X"3C110000";
ram_buffer(141) := X"36B5F0F0";
ram_buffer(142) := X"24170003";
ram_buffer(143) := X"26100988";
ram_buffer(144) := X"26310354";
ram_buffer(145) := X"0C000177";
ram_buffer(146) := X"00000000";
ram_buffer(147) := X"1455FFFD";
ram_buffer(148) := X"00000000";
ram_buffer(149) := X"0C000149";
ram_buffer(150) := X"24040001";
ram_buffer(151) := X"0C000186";
ram_buffer(152) := X"24040002";
ram_buffer(153) := X"3C131000";
ram_buffer(154) := X"00009025";
ram_buffer(155) := X"3C141000";
ram_buffer(156) := X"241600E6";
ram_buffer(157) := X"0C000177";
ram_buffer(158) := X"00000000";
ram_buffer(159) := X"0C000153";
ram_buffer(160) := X"AFA20014";
ram_buffer(161) := X"0C000153";
ram_buffer(162) := X"AFA20010";
ram_buffer(163) := X"8FA30014";
ram_buffer(164) := X"8FA40010";
ram_buffer(165) := X"16C00002";
ram_buffer(166) := X"0076001B";
ram_buffer(167) := X"0007000D";
ram_buffer(168) := X"305E00FF";
ram_buffer(169) := X"308400FF";
ram_buffer(170) := X"00001010";
ram_buffer(171) := X"14820025";
ram_buffer(172) := X"00000000";
ram_buffer(173) := X"AE630000";
ram_buffer(174) := X"16570020";
ram_buffer(175) := X"26730004";
ram_buffer(176) := X"02802825";
ram_buffer(177) := X"24060010";
ram_buffer(178) := X"0C000211";
ram_buffer(179) := X"24040004";
ram_buffer(180) := X"0260A025";
ram_buffer(181) := X"00009025";
ram_buffer(182) := X"0C000149";
ram_buffer(183) := X"24040001";
ram_buffer(184) := X"24020002";
ram_buffer(185) := X"17C2FFE3";
ram_buffer(186) := X"24060010";
ram_buffer(187) := X"02802825";
ram_buffer(188) := X"0C000211";
ram_buffer(189) := X"24040004";
ram_buffer(190) := X"0C00013C";
ram_buffer(191) := X"00000000";
ram_buffer(192) := X"0C000186";
ram_buffer(193) := X"24040003";
ram_buffer(194) := X"2404000C";
ram_buffer(195) := X"0C000227";
ram_buffer(196) := X"AE110004";
ram_buffer(197) := X"2404000C";
ram_buffer(198) := X"0C000227";
ram_buffer(199) := X"AE110008";
ram_buffer(200) := X"0C000186";
ram_buffer(201) := X"24040004";
ram_buffer(202) := X"3C021000";
ram_buffer(203) := X"00400008";
ram_buffer(204) := X"00000000";
ram_buffer(205) := X"1000FFC3";
ram_buffer(206) := X"00000000";
ram_buffer(207) := X"1000FFE6";
ram_buffer(208) := X"26520001";
ram_buffer(209) := X"0C000149";
ram_buffer(210) := X"24040002";
ram_buffer(211) := X"1000FFE5";
ram_buffer(212) := X"24020002";
ram_buffer(213) := X"3C021000";
ram_buffer(214) := X"00400008";
ram_buffer(215) := X"00000000";
ram_buffer(216) := X"03E00008";
ram_buffer(217) := X"00000000";
ram_buffer(218) := X"27BDFFE0";
ram_buffer(219) := X"AFBF001C";
ram_buffer(220) := X"AFB10018";
ram_buffer(221) := X"AFB00014";
ram_buffer(222) := X"3C030000";
ram_buffer(223) := X"8C620CB0";
ram_buffer(224) := X"3C110000";
ram_buffer(225) := X"8C420004";
ram_buffer(226) := X"00608025";
ram_buffer(227) := X"26310CB4";
ram_buffer(228) := X"2C430008";
ram_buffer(229) := X"14600006";
ram_buffer(230) := X"00000000";
ram_buffer(231) := X"8FBF001C";
ram_buffer(232) := X"8FB10018";
ram_buffer(233) := X"8FB00014";
ram_buffer(234) := X"03E00008";
ram_buffer(235) := X"27BD0020";
ram_buffer(236) := X"000210C0";
ram_buffer(237) := X"02221021";
ram_buffer(238) := X"8C430000";
ram_buffer(239) := X"8C440004";
ram_buffer(240) := X"0060F809";
ram_buffer(241) := X"00000000";
ram_buffer(242) := X"8E020CB0";
ram_buffer(243) := X"00000000";
ram_buffer(244) := X"8C420004";
ram_buffer(245) := X"1000FFEF";
ram_buffer(246) := X"2C430008";
ram_buffer(247) := X"8F828018";
ram_buffer(248) := X"00000000";
ram_buffer(249) := X"8C440004";
ram_buffer(250) := X"8F828010";
ram_buffer(251) := X"8F83800C";
ram_buffer(252) := X"24420001";
ram_buffer(253) := X"304201FF";
ram_buffer(254) := X"10430008";
ram_buffer(255) := X"00000000";
ram_buffer(256) := X"8F838010";
ram_buffer(257) := X"3C050000";
ram_buffer(258) := X"24A50AB0";
ram_buffer(259) := X"308400FF";
ram_buffer(260) := X"00651821";
ram_buffer(261) := X"A0640000";
ram_buffer(262) := X"AF828010";
ram_buffer(263) := X"03E00008";
ram_buffer(264) := X"00000000";
ram_buffer(265) := X"3C022004";
ram_buffer(266) := X"AF828018";
ram_buffer(267) := X"3C022003";
ram_buffer(268) := X"AF828014";
ram_buffer(269) := X"3C030000";
ram_buffer(270) := X"3C022001";
ram_buffer(271) := X"AC620CB0";
ram_buffer(272) := X"3C040000";
ram_buffer(273) := X"3C020000";
ram_buffer(274) := X"24420CB4";
ram_buffer(275) := X"24840CF4";
ram_buffer(276) := X"24420008";
ram_buffer(277) := X"1444FFFE";
ram_buffer(278) := X"AC40FFF8";
ram_buffer(279) := X"3C020000";
ram_buffer(280) := X"24640CB0";
ram_buffer(281) := X"244203DC";
ram_buffer(282) := X"AC820014";
ram_buffer(283) := X"AC800018";
ram_buffer(284) := X"3C06F000";
ram_buffer(285) := X"8CC40004";
ram_buffer(286) := X"3C050000";
ram_buffer(287) := X"00041100";
ram_buffer(288) := X"00441021";
ram_buffer(289) := X"00021080";
ram_buffer(290) := X"3C040000";
ram_buffer(291) := X"248409A0";
ram_buffer(292) := X"24420004";
ram_buffer(293) := X"00821021";
ram_buffer(294) := X"24A50368";
ram_buffer(295) := X"AC450038";
ram_buffer(296) := X"AC40003C";
ram_buffer(297) := X"8C630CB0";
ram_buffer(298) := X"00000000";
ram_buffer(299) := X"8C620000";
ram_buffer(300) := X"00000000";
ram_buffer(301) := X"34420004";
ram_buffer(302) := X"AC620000";
ram_buffer(303) := X"8CC30004";
ram_buffer(304) := X"00000000";
ram_buffer(305) := X"00031100";
ram_buffer(306) := X"00431021";
ram_buffer(307) := X"00021080";
ram_buffer(308) := X"00441021";
ram_buffer(309) := X"8C430000";
ram_buffer(310) := X"24040001";
ram_buffer(311) := X"8C620000";
ram_buffer(312) := X"00000000";
ram_buffer(313) := X"34420080";
ram_buffer(314) := X"08000046";
ram_buffer(315) := X"AC620000";
ram_buffer(316) := X"27BDFFE8";
ram_buffer(317) := X"AFBF0014";
ram_buffer(318) := X"0C000046";
ram_buffer(319) := X"00002025";
ram_buffer(320) := X"3C020000";
ram_buffer(321) := X"8C430CB0";
ram_buffer(322) := X"8FBF0014";
ram_buffer(323) := X"8C620000";
ram_buffer(324) := X"2404FFFB";
ram_buffer(325) := X"00441024";
ram_buffer(326) := X"AC620000";
ram_buffer(327) := X"03E00008";
ram_buffer(328) := X"27BD0018";
ram_buffer(329) := X"8F838018";
ram_buffer(330) := X"00000000";
ram_buffer(331) := X"8C620000";
ram_buffer(332) := X"00000000";
ram_buffer(333) := X"30420002";
ram_buffer(334) := X"1040FFFC";
ram_buffer(335) := X"00000000";
ram_buffer(336) := X"AC640008";
ram_buffer(337) := X"03E00008";
ram_buffer(338) := X"00000000";
ram_buffer(339) := X"40046000";
ram_buffer(340) := X"40806000";
ram_buffer(341) := X"8F838010";
ram_buffer(342) := X"8F82800C";
ram_buffer(343) := X"00000000";
ram_buffer(344) := X"14620004";
ram_buffer(345) := X"00000000";
ram_buffer(346) := X"40846000";
ram_buffer(347) := X"1000FFF7";
ram_buffer(348) := X"00000000";
ram_buffer(349) := X"8F82800C";
ram_buffer(350) := X"3C030000";
ram_buffer(351) := X"24630AB0";
ram_buffer(352) := X"00431021";
ram_buffer(353) := X"90420000";
ram_buffer(354) := X"8F83800C";
ram_buffer(355) := X"304200FF";
ram_buffer(356) := X"24630001";
ram_buffer(357) := X"306301FF";
ram_buffer(358) := X"AF83800C";
ram_buffer(359) := X"40846000";
ram_buffer(360) := X"03E00008";
ram_buffer(361) := X"00000000";
ram_buffer(362) := X"27BDFFE8";
ram_buffer(363) := X"00803025";
ram_buffer(364) := X"24050004";
ram_buffer(365) := X"AFBF0014";
ram_buffer(366) := X"0C000149";
ram_buffer(367) := X"30C400FF";
ram_buffer(368) := X"24A5FFFF";
ram_buffer(369) := X"14A0FFFC";
ram_buffer(370) := X"00063202";
ram_buffer(371) := X"8FBF0014";
ram_buffer(372) := X"00000000";
ram_buffer(373) := X"03E00008";
ram_buffer(374) := X"27BD0018";
ram_buffer(375) := X"27BDFFE8";
ram_buffer(376) := X"00002825";
ram_buffer(377) := X"00003025";
ram_buffer(378) := X"AFBF0014";
ram_buffer(379) := X"24070020";
ram_buffer(380) := X"0C000153";
ram_buffer(381) := X"00000000";
ram_buffer(382) := X"00A21004";
ram_buffer(383) := X"24A50008";
ram_buffer(384) := X"14A7FFFB";
ram_buffer(385) := X"00C23025";
ram_buffer(386) := X"8FBF0014";
ram_buffer(387) := X"00C01025";
ram_buffer(388) := X"03E00008";
ram_buffer(389) := X"27BD0018";
ram_buffer(390) := X"8F828014";
ram_buffer(391) := X"00000000";
ram_buffer(392) := X"03E00008";
ram_buffer(393) := X"AC440008";
ram_buffer(394) := X"3C02F000";
ram_buffer(395) := X"8C420004";
ram_buffer(396) := X"3C030000";
ram_buffer(397) := X"24630994";
ram_buffer(398) := X"00021080";
ram_buffer(399) := X"00431021";
ram_buffer(400) := X"8C420000";
ram_buffer(401) := X"24030002";
ram_buffer(402) := X"03E00008";
ram_buffer(403) := X"AC430000";
ram_buffer(404) := X"27BDFFE0";
ram_buffer(405) := X"AFBF001C";
ram_buffer(406) := X"AFB20018";
ram_buffer(407) := X"AFB10014";
ram_buffer(408) := X"AFB00010";
ram_buffer(409) := X"3C02F000";
ram_buffer(410) := X"8C430004";
ram_buffer(411) := X"00000000";
ram_buffer(412) := X"00031100";
ram_buffer(413) := X"00431021";
ram_buffer(414) := X"00021080";
ram_buffer(415) := X"24520004";
ram_buffer(416) := X"3C110000";
ram_buffer(417) := X"263109A0";
ram_buffer(418) := X"02221021";
ram_buffer(419) := X"8C430000";
ram_buffer(420) := X"00408025";
ram_buffer(421) := X"8C630004";
ram_buffer(422) := X"00000000";
ram_buffer(423) := X"2C620008";
ram_buffer(424) := X"14400007";
ram_buffer(425) := X"00000000";
ram_buffer(426) := X"8FBF001C";
ram_buffer(427) := X"8FB20018";
ram_buffer(428) := X"8FB10014";
ram_buffer(429) := X"8FB00010";
ram_buffer(430) := X"03E00008";
ram_buffer(431) := X"27BD0020";
ram_buffer(432) := X"000318C0";
ram_buffer(433) := X"00721821";
ram_buffer(434) := X"02231821";
ram_buffer(435) := X"8C620000";
ram_buffer(436) := X"8C640004";
ram_buffer(437) := X"0040F809";
ram_buffer(438) := X"00000000";
ram_buffer(439) := X"8E020000";
ram_buffer(440) := X"00000000";
ram_buffer(441) := X"8C430004";
ram_buffer(442) := X"1000FFED";
ram_buffer(443) := X"2C620008";
ram_buffer(444) := X"27BDFFE0";
ram_buffer(445) := X"AFBF001C";
ram_buffer(446) := X"AFB20018";
ram_buffer(447) := X"AFB10014";
ram_buffer(448) := X"AFB00010";
ram_buffer(449) := X"3C05F000";
ram_buffer(450) := X"8CA20004";
ram_buffer(451) := X"00000000";
ram_buffer(452) := X"00021240";
ram_buffer(453) := X"244301E8";
ram_buffer(454) := X"3C020000";
ram_buffer(455) := X"24420CF4";
ram_buffer(456) := X"00431021";
ram_buffer(457) := X"0040E825";
ram_buffer(458) := X"8CB00004";
ram_buffer(459) := X"8CA70004";
ram_buffer(460) := X"00000000";
ram_buffer(461) := X"00072100";
ram_buffer(462) := X"8CA20004";
ram_buffer(463) := X"3C030000";
ram_buffer(464) := X"24630994";
ram_buffer(465) := X"00021080";
ram_buffer(466) := X"00431021";
ram_buffer(467) := X"3C03F002";
ram_buffer(468) := X"AC430000";
ram_buffer(469) := X"00871021";
ram_buffer(470) := X"3C030000";
ram_buffer(471) := X"00021080";
ram_buffer(472) := X"246309A0";
ram_buffer(473) := X"00432821";
ram_buffer(474) := X"24420004";
ram_buffer(475) := X"3C06F001";
ram_buffer(476) := X"00621021";
ram_buffer(477) := X"ACA60000";
ram_buffer(478) := X"24A60044";
ram_buffer(479) := X"00402825";
ram_buffer(480) := X"14C50014";
ram_buffer(481) := X"24A50008";
ram_buffer(482) := X"3C050000";
ram_buffer(483) := X"24A50628";
ram_buffer(484) := X"AC450000";
ram_buffer(485) := X"AC400004";
ram_buffer(486) := X"00872021";
ram_buffer(487) := X"00042080";
ram_buffer(488) := X"00641821";
ram_buffer(489) := X"8C620000";
ram_buffer(490) := X"24030001";
ram_buffer(491) := X"AC430000";
ram_buffer(492) := X"1600000C";
ram_buffer(493) := X"2782800C";
ram_buffer(494) := X"27838894";
ram_buffer(495) := X"14430007";
ram_buffer(496) := X"24420004";
ram_buffer(497) := X"0C00007C";
ram_buffer(498) := X"00000000";
ram_buffer(499) := X"1000FFFF";
ram_buffer(500) := X"00000000";
ram_buffer(501) := X"1000FFEA";
ram_buffer(502) := X"ACA0FFF8";
ram_buffer(503) := X"1000FFF7";
ram_buffer(504) := X"AC40FFFC";
ram_buffer(505) := X"0C000227";
ram_buffer(506) := X"2404000C";
ram_buffer(507) := X"00101080";
ram_buffer(508) := X"3C100000";
ram_buffer(509) := X"26100988";
ram_buffer(510) := X"02028021";
ram_buffer(511) := X"02008825";
ram_buffer(512) := X"2412FFFF";
ram_buffer(513) := X"24060004";
ram_buffer(514) := X"02002825";
ram_buffer(515) := X"0C000211";
ram_buffer(516) := X"00002025";
ram_buffer(517) := X"8E220000";
ram_buffer(518) := X"00000000";
ram_buffer(519) := X"1052FFFA";
ram_buffer(520) := X"24060004";
ram_buffer(521) := X"0C000237";
ram_buffer(522) := X"00000000";
ram_buffer(523) := X"8E220000";
ram_buffer(524) := X"00000000";
ram_buffer(525) := X"0040F809";
ram_buffer(526) := X"00000000";
ram_buffer(527) := X"1000FFE3";
ram_buffer(528) := X"00000000";
ram_buffer(529) := X"10C00013";
ram_buffer(530) := X"00C51821";
ram_buffer(531) := X"2406FFF0";
ram_buffer(532) := X"00661024";
ram_buffer(533) := X"0043182B";
ram_buffer(534) := X"00031900";
ram_buffer(535) := X"24420010";
ram_buffer(536) := X"00A62824";
ram_buffer(537) := X"00431821";
ram_buffer(538) := X"40076000";
ram_buffer(539) := X"40806000";
ram_buffer(540) := X"10A30007";
ram_buffer(541) := X"2484FF00";
ram_buffer(542) := X"00A61024";
ram_buffer(543) := X"AC820000";
ram_buffer(544) := X"AC400000";
ram_buffer(545) := X"24A50010";
ram_buffer(546) := X"14A3FFFC";
ram_buffer(547) := X"00A61024";
ram_buffer(548) := X"40876000";
ram_buffer(549) := X"03E00008";
ram_buffer(550) := X"00000000";
ram_buffer(551) := X"40066000";
ram_buffer(552) := X"40806000";
ram_buffer(553) := X"00001025";
ram_buffer(554) := X"2483FF00";
ram_buffer(555) := X"24050200";
ram_buffer(556) := X"AC620000";
ram_buffer(557) := X"AC400000";
ram_buffer(558) := X"34440200";
ram_buffer(559) := X"AC640000";
ram_buffer(560) := X"AC800000";
ram_buffer(561) := X"24420010";
ram_buffer(562) := X"1445FFF9";
ram_buffer(563) := X"00000000";
ram_buffer(564) := X"40866000";
ram_buffer(565) := X"03E00008";
ram_buffer(566) := X"00000000";
ram_buffer(567) := X"40066000";
ram_buffer(568) := X"40806000";
ram_buffer(569) := X"00000000";
ram_buffer(570) := X"40076000";
ram_buffer(571) := X"40806000";
ram_buffer(572) := X"00001025";
ram_buffer(573) := X"2403FF0C";
ram_buffer(574) := X"24050200";
ram_buffer(575) := X"AC620000";
ram_buffer(576) := X"AC400000";
ram_buffer(577) := X"34440200";
ram_buffer(578) := X"AC640000";
ram_buffer(579) := X"AC800000";
ram_buffer(580) := X"24420010";
ram_buffer(581) := X"1445FFF9";
ram_buffer(582) := X"00000000";
ram_buffer(583) := X"40876000";
ram_buffer(584) := X"00000000";
ram_buffer(585) := X"40076000";
ram_buffer(586) := X"40806000";
ram_buffer(587) := X"00001025";
ram_buffer(588) := X"2403FF08";
ram_buffer(589) := X"24050200";
ram_buffer(590) := X"AC620000";
ram_buffer(591) := X"AC400000";
ram_buffer(592) := X"34440200";
ram_buffer(593) := X"AC640000";
ram_buffer(594) := X"AC800000";
ram_buffer(595) := X"24420010";
ram_buffer(596) := X"1445FFF9";
ram_buffer(597) := X"00000000";
ram_buffer(598) := X"40876000";
ram_buffer(599) := X"00000000";
ram_buffer(600) := X"40866000";
ram_buffer(601) := X"03E00008";
ram_buffer(602) := X"00000000";
ram_buffer(603) := X"00000000";
ram_buffer(604) := X"00000100";
ram_buffer(605) := X"01010001";
ram_buffer(606) := X"00000000";
ram_buffer(607) := X"00000000";
ram_buffer(608) := X"00000000";
ram_buffer(609) := X"00000000";
ram_buffer(610) := X"FFFFFFFF";
ram_buffer(611) := X"FFFFFFFF";
ram_buffer(612) := X"FFFFFFFF";
ram_buffer(613) := X"FFFFFFFF";
ram_buffer(614) := X"FFFFFFFF";
ram_buffer(615) := X"FFFFFFFF";
ram_buffer(616) := X"FFFFFFFF";
ram_buffer(617) := X"00000000";
ram_buffer(618) := X"00000000";
ram_buffer(619) := X"00000000";
ram_buffer(620) := X"00000000";
ram_buffer(621) := X"00000000";
ram_buffer(622) := X"00000000";
ram_buffer(623) := X"00000000";
ram_buffer(624) := X"00000000";
ram_buffer(625) := X"00000000";
ram_buffer(626) := X"00000000";
ram_buffer(627) := X"00000000";
ram_buffer(628) := X"00000000";
ram_buffer(629) := X"00000000";
ram_buffer(630) := X"00000000";
ram_buffer(631) := X"00000000";
ram_buffer(632) := X"00000000";
ram_buffer(633) := X"FFFFFFFF";
ram_buffer(634) := X"00000000";
ram_buffer(635) := X"00000000";
ram_buffer(636) := X"00000000";
ram_buffer(637) := X"00000000";
ram_buffer(638) := X"00000000";
ram_buffer(639) := X"00000000";
ram_buffer(640) := X"00000000";
ram_buffer(641) := X"00000000";
ram_buffer(642) := X"00000000";
ram_buffer(643) := X"00000000";
ram_buffer(644) := X"00000000";
ram_buffer(645) := X"00000000";
ram_buffer(646) := X"00000000";
ram_buffer(647) := X"00000000";
ram_buffer(648) := X"00000000";
ram_buffer(649) := X"00000000";
ram_buffer(650) := X"FFFFFFFF";
ram_buffer(651) := X"00000000";
ram_buffer(652) := X"00000000";
ram_buffer(653) := X"00000000";
ram_buffer(654) := X"00000000";
ram_buffer(655) := X"00000000";
ram_buffer(656) := X"00000000";
ram_buffer(657) := X"00000000";
ram_buffer(658) := X"00000000";
ram_buffer(659) := X"00000000";
ram_buffer(660) := X"00000000";
ram_buffer(661) := X"00000000";
ram_buffer(662) := X"00000000";
ram_buffer(663) := X"00000000";
ram_buffer(664) := X"00000000";
ram_buffer(665) := X"00000000";
ram_buffer(666) := X"00000000";
return ram_buffer;
end;
end;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (
-- prelimenary RAM initialization
0 => std_logic_vector(to_unsigned(16#00_FF#, DW)),
1 => std_logic_vector(to_unsigned(16#FF_01#, DW)),
2 => std_logic_vector(to_unsigned(16#7F_FF#, DW)),
3 => std_logic_vector(to_unsigned(16#7F_FE#, DW)),
others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.wr_enb = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (
-- prelimenary RAM initialization
0 => std_logic_vector(to_unsigned(16#00_FF#, DW)),
1 => std_logic_vector(to_unsigned(16#FF_01#, DW)),
2 => std_logic_vector(to_unsigned(16#7F_FF#, DW)),
3 => std_logic_vector(to_unsigned(16#7F_FE#, DW)),
others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.wr_enb = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (
-- prelimenary RAM initialization
0 => std_logic_vector(to_unsigned(16#00_FF#, DW)),
1 => std_logic_vector(to_unsigned(16#FF_01#, DW)),
2 => std_logic_vector(to_unsigned(16#7F_FF#, DW)),
3 => std_logic_vector(to_unsigned(16#7F_FE#, DW)),
others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.wr_enb = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/zqynq_lab_1_design_xbar_1_stub.vhdl
-- Design : zqynq_lab_1_design_xbar_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zqynq_lab_1_design_xbar_1 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end zqynq_lab_1_design_xbar_1;
architecture stub of zqynq_lab_1_design_xbar_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
begin
end;
|
------------------------------------------------------------------------------
-- Testbench for gmux.vhd
--
-- Project :
-- File : tb_gmux.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/15
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_GMux is
end tb_GMux;
architecture arch of tb_GMux is
constant NINP : integer := 8; -- 8:1 MUX
constant NSEL : integer := log2(NINP);
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6,
sel7);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(NSEL-1 downto 0);
signal InpxD : std_logic_vector(NINP*WIDTH-1 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal In4xD : std_logic_vector(WIDTH-1 downto 0);
signal In5xD : std_logic_vector(WIDTH-1 downto 0);
signal In6xD : std_logic_vector(WIDTH-1 downto 0);
signal In7xD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
component GMux
generic (
NINP : integer;
WIDTH : integer);
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InxDI : in std_logic_vector(NINP*WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : GMux
generic map (
NINP => NINP,
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
InxDI => InpxD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- input encoding
----------------------------------------------------------------------------
InpxD <= In7xD & In6xD & In5xD & In4xD & In3xD & In2xD & In1xD & In0xD;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
In1xD <= std_logic_vector(to_unsigned(1, WIDTH));
In2xD <= std_logic_vector(to_unsigned(2, WIDTH));
In3xD <= std_logic_vector(to_unsigned(3, WIDTH));
In4xD <= std_logic_vector(to_unsigned(4, WIDTH));
In5xD <= std_logic_vector(to_unsigned(5, WIDTH));
In6xD <= std_logic_vector(to_unsigned(6, WIDTH));
In7xD <= std_logic_vector(to_unsigned(7, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= std_logic_vector(to_unsigned(2, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= std_logic_vector(to_unsigned(3, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= std_logic_vector(to_unsigned(4, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= std_logic_vector(to_unsigned(5, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= std_logic_vector(to_unsigned(6, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= std_logic_vector(to_unsigned(7, NSEL));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
tbStatus <= sel1; -- sel1, vary input
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(31, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(32, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Sumador32bits_tb IS
END Sumador32bits_tb;
ARCHITECTURE behavior OF Sumador32bits_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bits PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
Oper1<="11110000000000000000000000000000";
Oper2<="00000000000000000000000000000100";
wait for 20 ns;
Oper1<="01110000000000000000000000000111";
Oper2<="10000000000000000000000000000101";
wait for 20 ns;
Oper1<="11111111110000101100000011000111";
Oper2<="11100000100011111111111000001111";
wait for 20 ns;
Oper1<="00000000000000000000000011000111";
Oper2<="00000000111100001111000011111111";
wait;
end process;
END;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eo7ztsvbgSYd1KGoylhOwWqcRC93ADsrF+RmXvAplO96rIXnjhzPYctzz+XAywaHSS1JGbblhi+C
CG/Xmr+Viw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VlDPvUjcTGR2bEjy3deiDqszXoduUt60+OFMFcjqa1auPc/2MBM/VWcMZU5YwD+sO6r7Cd2u8kzB
4QzmPkP7uO2zWeFpoq3C/41rplxKCcFvwXJzvHREIG1OnzYb/dPblCiS/+mn2VjAfB8xizQ6Nln/
0idL8DQKgMDcgl63gN8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Z5qUsXx9HJ3+prwOOiNYDTXnWkUAAahQNFkO/c02x1krdZ8WgOiYfdeKqnKAkYdW38T4bPzkQYXm
F9HRN7bup10M5O1nlm6pdyO+0sV6xeX4w+FYkNPaAEVwqHpj07WIEw/ue/EVXX5K2OIBRGh7/H4Q
P/1YmzkwpjoeaA309HPiLuhPj85iLqCcbqI65h/qN7AP0Cw8sPurVTI8asvfzZDURNFtxWWTqSWs
YDduGBX794GzpN6yKoOLlO9m+TqdchGrFtksq+MOHi3FXTk2bB8DuQ1tOwwGC7UV86QeCPa73FUc
osm7ZSxOiAN+kOHPLWKEtbJpRWeajTSUJalVHg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JcY1431frN/YbCQwZBS/ob/VuFxPcfZ9uCReqISX0nCqqpT4EXoXqqwJIy7mLfBpRuS8cBqIBklC
tHbwET69cUCSrkNm3K2/VMAOETKn/w+gzpzjBa3bSHor6jb9uEop3HqOLwiHUEycKwPcaK4IwTM1
mhUqYCQiEK4l0ddH7X4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U3FcEEjLh+ZVARgnFFqe0XZvyPgHip1ElX0vFmo09sq5rJT8+Qdr6xmVCCdsO7nwNQJfKuguSXwX
/iIz3TqU6Tn6yp5h5s9bP804Hk7RRSIidG4CeLzAMXaQ1e5OKAvfM6Zml/A25FdPg/TILkDmwRzv
W7RcVNcdHyRxomufsKZpSr+gVGgB3pmhiINQkpdVB8mx+GhfIqJiGsWlih0hZgR/9shgCikO1MO3
gpbzl6FJmydQlmczjFxBz+oTkQysHKMv8vTZuzxpp1/VDL/Ulr3zYq0oXVLMvwfYA7tAI2khu1nS
uTO//C2snIFFgujZl1JszXkeiMUpQns6O/rXUg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12064)
`protect data_block
pjbi/xQCQxX7daUuB4RG2FXtx+lQjp4/6p0yL2fYmN9pvPur+5XNjtIVjfvScGV2f336OVsgjNWz
j0ql5sY4U3xJRBjTnUuOVVMGIh1a+fXN1Ddh4pamOJd2bC5pEAhq98q1r9LqDZYggrWyDd/kHs+3
1ghs0oHAld1TYip9gk0AJgjfpianf7bA3C2YQOOc0hfr9wJgbqxgZ1ce0G0EjOnC06u34C0UrfRI
eGG5408R5HLykJKTRZikQherv6QL0X1fSrwz0AE3wBvX0AkCKybuoWt/lTRmZx1Ht62Q6HfQkzJL
019avqfnB4YVyUyJhQDd/HiKzM5DHYJtpVSVDj5U2wBqcuzgU4l7S80+x/ejnTkB4IEtCcRc3sKI
bPSScw25RVnK7VjLj53FUT9l/IUE8o2y+lJ/N/JCrDQI3kiMllUxUgh3mKoqkLQQNh0b0u3I4cgl
MHYC0LWu4SwYVlJT9akWmI/Y10n9hoqDOOT6jpMVQ6RjqVjaBOiTWv3M0iG8W6u4r58Jv3P/gJlL
MUxyTy1woIRnCg3weq4kx9uzHX2ZkBHXIT2ngQV5HQax1lLHGfrbipdGZVTQH6n1nrnvw1PwLUEu
XNDDNOAOKwBdPjsMChs9XQJlk7aSAT1nHR+x0rWpsGAM5Eld5Cm9wwv1HKm8Ac6vvdDciTi2I/bQ
zu+ph918RIGMlvixVe6/dZx9HNjBWoUOoUDN0BgAxGxeKPU9I2wfhRKmguCASnk7oR1k7QIGJ6JN
467dxoAWOSSAEmnIlAoBF7CkVTNRX2JVz3jPlEDUEUSrsczYZ/XgXWX9S26LreXIIGIixCBSpdLo
3a2y2VVcfQgD6s2u0Yl//fXwvtQ9Sxl6OYpYv0hIVIiconGn5KVCczTVUxG17wUWigel/431CXeE
yXnn1p+G17kP/1wQaD9mchKiOF3FNQlVHhmDqzA9Y4cnS1CmC8JKmOOPTcHLdysbxDunrDDkqf00
F04wnokYPbeCQDb0OcyNdJV+GIe5hRsRwH7gQWCMbhPsGS4ilJIyfJ7jSrGkp/GiHPiUhA3TiN6P
pojorK5aiLS8g5kvwepUXaijaKRFFxxxOv5R3MRHE0EbRAhqCf+Ndz6KnRnGd2iJTb+Mq0mC7c9U
ca92CnyFZ+FtAvGlEMzlRrt7WxukDMLtbYbKmEpNNoa/KnQrfJTawuaDaFM4X0RE4kwQPfSnVMKH
3VSQFDVA4hCbtx7IV4dZasQdApsZEtx6jk8wWk4JKpsUy5kblcBhpx6tmTlbDtwICYka6e/yVOCa
FbKJiz5SMR/A007kFbCxW8RhxdfgY+0e9Q8TBbT1DcY6CZEIFt2WRfQ1NSvBVbQ8KeMwQgl61+Sg
9LXY3le+lli0rlQc76+Rn7ZFIxDdTEP4CYlEpxDAm+Ux2xM7gTuVmcI/H+okaT420BT52gPNqdNH
XUbKD8X4FnZ18o/teMkkVZ/w909IaEbbo3kudfNQQmVgU9MPvFJ5cNBkpMcO8t/UsAUhH70sxRg3
p2IjBnWI17KDAgW0OLLuYcL3vEmOjJvl4qfVW9AkO51FHx7pFQFQLCglRB14R1ETTs4mA0px8w4J
TCswJPh5Ja9ynMZjlt3VJCRPlRJXRZl4Erzk80znCE27J2lyaXQhFBOJNT+uhYmUx4Ke2JLc7jc2
fehvqjbFhFb9aQTyaV7VJDmmx0I/KInFhHHIuXRbzjjNEk0LwC2fMex7GGxERuUn5La3lTj1Z29S
Pb2vyOeYkVcb+OPJ0bobxh3HA/MGJlIisCKBxD31Z011aaVClUJ6h3mRB0iSW1Z2dqWNjv2Uon/G
UYRdkngxuRahkZ0mJUZsE/7xqr6C3sJ+78fzSRi7bxzp5MLomD3WmiUPTvH+n4/dWffEfZdhrz9Q
tEeLHMogILdlX4oZspgmC/bVvV9BYvgL0Na7gji+9iBOaZGFGKG42iulzKPtdas6kzGSXebbSVGs
+Yw+aM+ziMv3F+0heTHnoxBJ7RziLZpSD1jIjOk6sz5seg5o1+/07oAyJWiFPX2lc+nKbgyFpunf
bZjmHetvSGZ+bdfVDapRNEx1uZCgPIdCtp2U0cIliu6+1mBDpiT/FuF3CBr2CoAqdqLiJ9PBI3/M
w7VtZAGIuBOuhF164rsmJBq2V/ybti+Ewekt0x1pn50X9GurGXshYuRsAmm0Xk3law/QkDtbS9KX
VkkVXcS34K62n7n2GGx2xnLJe7Jt5+0dZvnGdDoifjYvv+uKfdP2n81eAB6431xBtkK7ALGueWDy
OEPeDfpBeYiPyfFR6qOcXk+rMx8gn4HGEE+eopuB7Lb0kxwHhGP1cqLrZd/G/gbpVMpUCzYVcT2B
zcAklT+XAxdhKEIG2lSkVOO3v1qD0enSwyiz5JHlkTVB7Q9CLliE/7PZOlbtEkIZdPFM6y5JAZoN
3M7/IeajRZmkCPMluoQICkE+sJ1+INFmyW0mE/7Tc1FsILwJXEEsmiT2vWtI+ek8TtDJ/z1DTy/S
HziduGggEDk0VTozDIS7BEkyyiSDh4yal7mIwF2GecrUrX0Rg9VZOBQZ6nQohB+zR04Y2yb565o8
E2l4g6asBhaLqNyaaP2QfRqicC+Y7/kyf6zawHJ3AYLR0IGVSY19L0xA5vDTB1rN+9pzCRFNfvAS
dzWpRHn+Ys8YT0T5wVQ6iCqB1DgissHLt9zJjreutIizjXzqQuin61sStVrn3ur0wJwJTfYvxEb+
oZ+wMiVBJ5FhKQEc1tWrkZ6H6eHMK+PxMwN1pzSRIqHMuD0qJefiO0iuqJyGYztP7r/EnpkwILKS
lHu4VNVULPblOtVxIJlzd1pj3KIa7/3JVxGFknZ26i8pmIH5HDKfLA9v9gJMgLhPpXSuzXEPrJOv
m/jw3EYCYwc65Upn79Q5FCcvNkPEinuidVaEQs+aW6QpdC2VJOP3zeOCOBlY5qasPvphz3ACsbtX
LD66h3QjXhEZXI7JA+dQxlKwDiog0B2LvhQfSFh81sXdM7+H8jOlYjY9nWwoHvKvucaOdV02GJL4
Q8lO3yqO0EOTz+oaqbLlWvJftM6aFc4A4zIcoWlSyHDZcop+30XcdZCftAfqf9bnOWIn1ohQk6xZ
eFSMHIezs2sbnEs+8rrSTmldJzZiZ/i9UgC81Fr0dwALnErai2HoegnMSIREvb4+ys9YAhUO/4e1
DXanaeqlw0akC3VT2XQ4BIvmdNdHtDGc9k6VTG4VlgKkVVh4pU303Em2bh23w5DKISMX9Iigq4Bm
4dqnfDaaXV9yVHdFzkoHosXevYWxsZz+NALCM7CVU2JcgV8uINJq0XLRSjNT6mXilya4aGsZxn8i
jRG7di+fC2AZlhcVdzRP5v5ZP1kVVlDF1NIKIN+PxlBK3stGMZJCtaKKJ5I66YCMrqVjB/ZSDKxU
g8c+Ua3+cf89d2XGwpwukFjDt5xMKZmzr9xLsKhj99boLmIU812mTVVlNXALbtEjCFwC0UXRiiE6
yL9P4MeIRwIod05P+4YZR6SVrcIf1E++FdE28Y9xYrngfuFxJ3IZGYIGya0U/AGSZyUm0bq1U8C7
qGUXaM81dPWNUBn6wtQsh5igoyJbGDNE+Ja0P+nFd3jvu5kEexEYJgV0xmsPxgOreYUViPdgXnta
M/d7Y17lhS3SorhKx0X/cj11i7ee2Ersu/bbjlGlOT+LzL2IfaddvpVDFP5DxIlfhngqMeh49C7C
97sWhgEWL32b8qvFMSIiZGVKOvPKRn2nm3VvWE+ofeFXXNak1oYa8L1chBKTKL8kdh9Qr/d98vcT
Ibo0440U7hTT1CLXAMXWpNLRFx/TP0z0NBXT0ZOB58w8Z/wlwT4d6S/FsRY2JDrc6C2D5n6XuIRq
7BS4uw9S4av0Mq9yo856gVlqOd7JAZzAGXJHaRIta5t4t/53z/1h1GLQJQ+3ft3m5X7pA2/Mzxgw
oeGNazpUgnD0qtci5FX7tNPzI76v4o6RqszY/tN7vzbpGti8uts8WSnHoEmmHZ2vfHqpYiURpAGW
+vxp94l1lUYxVgz4fBPWwRPZQ8r1RddZTFXJ2H0eVHAm5qjiqUQA0NTRhtMllFuf5PY+/fvT9WOC
x6fSr/3bMYMz5LGpu7vGXhgFZfi/BD6DzZ/Wmi0vLGfbQCZiZBAlZfsvfHME/eXgdgHlTTs0qO43
kEjlHf/0sWzIXWEmpI0x/WqnfnLGatgiDQTbmcDxgIng2s7vI7FUhTqequ5vllmUssrbJa1kpMeY
D0mW8xtEAvWuDIVrcPjVHHuUTwwy8pcsuMUb9XIPzk/6agwwcmzpcWTw2XxQu/7fknb2RdLMffIV
ZThyI9AgdPiViHeiWHa5j8HLdU+ovZYIUengWLQTBLtUASPljXKHxOu2ZlDbyeHpzMrIYJFErCxJ
TUSBGp9wmTcf9kIdf3s1P6yf0x/U3t6wz6gIe3JWFxUbn0OJ+iG+4NokvAcGW9nczhnkTRm+86zT
ktZX7WG0IOvJ2y9qsrmvTn1/2LZ+Pi64RxJBlt5byfctA+gjd98455igwuuLW50axXWfHLywA7Wx
JYup90umZpiEazNbulMYkQHijTwzzwypL3UG2olW9Tz/P5ecGyEBRIYN+hpZCAQkjHImBtcNmjds
K0/oqKblQhYihXXymwhYwigATajOi4zfrqF8zGj0BAo1Pl5/SKWDUjkDPT7kvAOzFbySYXhMFgBW
/NzZpz+1XqzX3tjWF0CDtXCP+NulbxIN53I456WMzqPWO08xfGxVcm9X1GMvE5r91xneCqmZk/3s
5EL1emxKT4zeSft7ZCwCPZF5mZVRpL4Ev5QFKU7Q3sqqHYWF3YAUh+kDjfO16oGL9Mvq2Y7Rv3lE
EDY17JEtJvqdIdEpzi8rL5g+oPMAPocoF9KgnasoIkEfqPFeZcBQjTQYg2dg7Dol7KBdea5CW000
D2Ra2sq+ob69YMjhwGAFEFKmwlzxq/9lyjzykwVi+ZhChsZvIpF+13nTyBC+rUAJe0+lpoXwtB4B
OuWhQtghdJ0u4BVoBSb2rbJI9YknTwMSogFPWw4KzfcW1mPeMTpCaUD5aIcnyOOgNHRxgheX3lC4
r2Gjx1sZoc9sZvgAkRs/0CbsOSqrmpthIBbOfbdCYDp+imaQqU4/DKwWQJ3AuL1w41QDjP8S6DG/
xwccHuUhC1a4HLVMafGyfA3jepWUaID9wRFF1o3roLCyzT9u6vWJEd3+EVbK7lGxlAiWlwR35IRz
rIM+4l83i4N/HEtxvPCN9iPmrmXyWvOlGKx04nUyTNQsX7A+QpGddN4dgenH6g7dNfzjTGjqUyXC
KINx6MJjDaqbQMo0XU0uznYBn8woQXswfxCXuIjscrbnf+6PMKM4R6z77txzGHNFNdud+A87gnwy
BqNcUhnpdCcxyVPp+mTQVMyPznneOBfOZPcpT9wbQBu2gFf5psp9CGWp9EGNcMyTzLZ5rjFJL/iD
Phus6N6rLZeM/agKQeCM/b+iw51KMLbpUZZO/yCkINFNVb6/PjRrqcjJPWBWXlygCSt2RkMCXy2z
XnXA/pXtol1zQNBaAG60Q1zFNdnxSUNaIWpuTBvJNlCp9I6NmhVUcmf/np+JZp5GzEq0sI51MzGe
Xi3RHQ23+6zEbSNiDqZN0BktupaVZqauRkVWnSQQKzihKpiIEyrjOTGNgRDCFHhVILPI2qWP8GT4
agoGTeBxCnuyOuqF3+eVao0KHdTfi6QaT6i2MqkzNOlcMrOiFZ0SkF/vJvEj5XraLjz/Dig0wSlx
k6YHcEg8kawk4M2VYK4xm9+MEt+MaSxtZRAj6iiqDn2tNNq3f4HUManEWmfa1uxKBjR3fLebPYC4
PO0OEPczILvlbmjuywJwpavSmAi2GXksTYUq8JbM4Gv4uWYNrorBvUZe3zHhd3tmlvOnG0ehfmDX
UJlipWPvOUw10T7M3H1pc2hTwZyZoVT1iR8L+qmE6wjBZ8VvpX1ySQbc3liQq2I3psB6fF5hwlMq
7Vmz8cAphOx2ylE260y7DJngwAp6bIaNhFEDx3YY5XgrYs/BsVBi3STmmtLhpMTDr3c1bCPSoJGU
LEEFmpIYJZAhlNJlp+psb2pEcHum+SlfVkKQJQl5SDjfwE0wD4J3XXoTMitF3jn5Op/ZMcCJGaYS
ZolnaBMlvLOAJKBBabRBx0qLteO7wpMiRPkxoCR7IsX1Dx4tZAwVm8qq88lr+ifLlf7/T6V72ahX
SvZU8nuzSwdEcszi1mU1rHQ5EmMZPYp2/MuqlHlcpkiRps3PLs5XHP7NFgURiDTpXddwDpYrebxI
LqxITOgumDkGmgpCZuE+EtjeW6qnOL6b/nCzUou6IA/9rxmI3A4WMdQQMmjwpqAv+ODTPS0GPmvq
tPs2DE//02PzeHG4Ihi9Hhf93dspotbOqKOqI2xhquH+MrCtbBTnDMz8JwidHtNOKCtAYozSIcD2
nonCSjaTiN6pkxcTAtmOyJEb1OHmf+dXplKlzeuDXQubi52Tzjsv/qhrpUvV+22rfslbfwnD3PYL
sMrOSDRUNJOpQyajkdBpamjjQrErSnn9RGJaWTSZfQNDBTeyBaDAL+ysl8Y5pBsr4zUDL42cXMqD
31XBQ0fbQvhkCcTX3zjkdSg0Q4+1dTw3SXxptWm4LLbkOSxu5vqDHCQa8lkmwUjb/gHD1AZLnz51
kiIwFacQP3nCw/CzpZ9F+DA/sMF0KHCxLM9qyQnZKxeOrZyC7cbfM9nTwqhvix7iu5/iX0Hx9SLc
31I+e52KEUfnIRnTEk7heNZxSixrLF+Dth7crAn8fAyQVG1c93hUVk537WjulKhyEC7Dxn1QIdtg
Jn4ufESMehogvIEDzsP6xeCbb06nHShtze2C266EgBMvwXpbPWLuRtwSKXFHGbxyf3avnba/2jvz
H7OzcBFEEdH7tmp0Jt5LPMxZ6CiBfvkw5nald7ovW/XCaGaucYE1KsX6k6eHBu2Mfdp4kOLoAoCC
qHlbJgy2BCy7JPILNRL+kSwetc/gSL0mw14xGLxAQzUH7OI5jNOP1wtQVm6I4jR22IOmhh4mR/wT
daWabITu/4jCpVRVoP6tvCYqfAGFMLEEDUxNZnOrsqQ7HB3BoWdQSE0EbrVqkwRdEzWRAgrAN9bD
2UJkQUk1K9eKyH0mMF0+jUU0GUHGhSqDVvhjeTB591/CehGinNij+w2uW1XRiGE7W0MY5jBp46pj
95C+VkCtx6Y4gwrMxSzc4brzdAnG5Weo8js/HEu9lTc+ezPRL0SGFgYtrS7uqkf4GLLsa1YvBAy/
mC44Pc9ZvKpPEe/k0dKCRZplObHACL5KGi0jDfT+PnMvSDN8yCWqHOKJtg/vxBtLB/p9c1MJ3RIy
tTQH2QbHsOqiVemgZUaBgW+fTw+bS7qxMVz92ujdZUKqI+THhMud76uvcHLJIj5tfiuppa9ewWmQ
wPiq1EckuPSxrXophTmtOdIFQhsyf+bzND4QQyqxSllb8fpd4hMlCmbcz01Idc36HlDIj3G57OiJ
G+gS4NneiAxoLxaoIUl3AkI6d7qCj7ujfJiKdyQB3RMyODJovLN/Zz6Wbv/x7Cx5u4ARvuYcHgwb
uumm7pzTFOOxv3fqmwxj5U3199QB6lpRB9wBs/3NWGoftBFYWi6cDIc5cG2UEa2ET4HdqaKfWYUu
YBzaZoK+grgoxlTyznT17/5NZ/aaJZhGTM32bMpFcQO9h+4bmAUcLTCeCT6UBnNirR1X4uJvcKAv
fRxFFsaJYnnlRFqq0jU5gQaTb1s847c3M93CYWshdGJDEu5XvBVIQGwAq/xe3imuXOFdUl003UF8
49o/8P4M+bwIhyLQlQPqm0D1LwCrd49sLGROc+XBqwFkOZ6Fp4vMh8UwyyYsqqvbp3NOo50zszp+
HlxjMrvuMejDrwCw0306enbLRFt6WrXws27I+1wVzRVxkAuPuJ4+8d9tdmhSef3OdVmcm+PGdqPc
bWGwT8CaZey+bxdmLLHyhA8hdTuGmH7dXxvI7ajinCQzwEuEfc8Mg/R9JA73oPxJs5HLijZweKN4
i/C3EfGmbMPSZ1RMQgz2x31t2N+gxqQhLvKfS6obQGA8zTLZ49ZXtp9PX3Qlx22+zopa01nozVak
XLQvNuj9SuB+GF/H9ZXEanXLnHkgeJqjoEt9CqEOUGT6ZbF2imDbuAVmo3ilp0TNXP2cc6IlVFB1
TesByGLtJbzdt2X2Wmuw3DEJJjgqQVMu4DZGrJAhJ8X7INBEDq6mFaXo01sAVoAbcBFs5nDDSKBt
+xvqSbZZaD90E09Do1T0uZBPrS16ElIR4kRoqplA0pe9lMKIMeVo9FEjx5M85k7bklC3RPADaATU
ynSTStGCdCI1kU6Mdg8FPlzn6GT5THQhCEePhOf1RTtHBX8w1+HVY1iAtqqVDFcQvb4RRtbwxszF
5h9BVNOCVZAUPj8ZxyUKWMrd4Mb/Gq/6564Ojc4RQV6Ony9888Du7Ue2VwXSPb+NQtTbvAYh5ceE
8Xpedq/nJs4k+KT88qnXYT/UCL1Kz9n/6Ys6MNqwV3fD5H+sq7uT7wBWrnAZglQboskjMH2JXeXq
NreurugYF1kh4WYqg/8vCYr8rgeAy28ctWxLXwfnp0L0dGjR0TycCBHlLNK+tTexRw43L127/VHE
d+SkwSoNvALUcRTIzRabanJ8UwuZZxwmSGMt2On3DKgpA6T4tZ2qrcn38mZyX1+IcqhEDX1CNgAX
fKtgwxbGXCfIcK2MsNF4aOcH7lbDuc8eV45GJReTac+zgpfZ0s4d2ABp7HL4FHs6uJxSC8AFDisv
qTInW3QSDmc9olG1FDwdsTfyuPUFT3A73XznlFJdDbUK5LzGbwGg6o5Izw/I8auLULGvqF+sKohj
IdKubDOQuXAgu4SzkDFqbMkYwGfRdrMvusjwdI3r6iDROsXHptzRUYGqVYIxh4QnWu96w2naubAe
fK78aNCQz0YhNPXuaiUeSgbDgi9cEg/bWBEzOe7BdAzSbgDF7uazZRXC9xN0/EEnETXjzwhcZicf
Z6TCrngpIrORw502nb91t0k/9JEiJY+XHwawhtSf/Bx8a492Hmn76vlWi5vn/XiaZ6v73oFb3GYh
vUs70AgyXbro8yyKti1b8Om8kbibGxsGx6l7byg0bg4FEVJZ4AHv3+M2mfcOorZRDhJTZBSm9XZu
BBqqYRW/ctPab963iO/jIWY5G+rpi/EjxrnKGOsTOaTh2P9/9N5jc/zwdH98TftBnctZ5ox6eN6t
c0+I4K0rGMaImPx7Y37HTHq+eYUbIsIRki9t2W+sxRR9nTBQtd7FS4Zhz/cAOA++8y6/lGiEOiEc
Yd2a4BHvFYLhtX3SL3v+D4rTgv9yVtCnZHiR44QdyzlcF5A0yzPN3JWx2OnF5282akPzY+X/yhTp
NLP00hVYYurVwz57aP9W/F72XmuDbdBGPvcfKNUZCbrR2jVaZK1urCDfrnMZLkoqkv6Akq4bXJ9s
4LeGxVaRS3Qz4R4FWHD2/FEm+eK4+eHE/Xm6Aas8ypaqxqzC35cNrEDs6FqfYEPAl8NFpxtnKZOs
3mT6L/BJWqjJdz+ZA0OBGTQu76k2puvLlaTU7y7ldE0qk21kfSmzUdAtSnqwDZbwuSmfaVn7bS+6
tpsqb40LUNLaZl7SaIEUhYqUO7fixNH/dao3buP+NxnWBS3p9gCXEatzD0OTRJkvCgi8Pi1q+Sxe
JUyJkPfYlLHoyO5u2B5P4Espg036DiLFcYPxZS+uuA55YG/dIvIr3e06m5Qkb5njCttDA4bSnMyL
w/pEGdd1WYEQtX7EyD0zaiCwd+WSwRvbtmdy7v5USsXN3GTNSOfNTtozjNTJaqfhVbkN1tOV5tCk
wHDAI+mdbI5Q7bUipXX7r7tpNkiu221gGjFg8cBmaWS6cQw74zEs9Pn5czmjYU5OK6cnRvs+zGNA
aS5YRADde5Lw16RC8+20i5rnBc25mHO3hrXqvtuGVECy+Y+1/JvQu2l81YowjM2UA9Hmjq3ugPsy
33yj7Jw4LG8Tw3/lczBH8XMIoTXMdh299mvUAGyZqJwDlcrIem39MX6uPvRhTEIBGidMkJdmJY5f
2I7ugooAHMrJRRvW5OgZ3IpD8HrjR9qZPYaEcXQgi5Rz7n4h8FrtSg4FP5yF7baEjPAuGI/iF0Q9
ye0jlEnvFxvU7prDZBg7bed4yqg2W1SbnFrRd+7vrmjIauUYykfxVsV2h/DfYyczbB2zRagKvKU2
4JF/z8lm1XnUkANqQWhTJEd/U1EjNTTMRtiWPnUQr9jn0XMJxRq25fNKmrL03ZSIJS6Q3xH1e0C7
Ndes2uJTS3cIeX0m/6AeFrWPdm+fF4F641UR0GF8JsX87bIJFbwuzlKbdwiEQ94MaSmTN+Zs3xjE
TIdt5D2+KpPImW73E1Zx9djeamZbW5+LuvPiLdcNgPLb/n0xjO8pKyWWXWnfRB1Ina/tpSfK/JyH
woeoTVdBeKvUQl88XRFhsdb83VLflb0RGCqljUUYx4OK1dxbK0oycpL48B73XgVeJhzbRCFvu0xr
cfxbBd6dbOsdw6q2OcENv7IhD2juzpaUSZ9qUHNO0OGB3K6SEcwKuucF3Nkt+98JgBFvhtGKI1Sf
z8UYN4HedO+274fHQQGQJ6rs0nPg1UArE1UgP/sLW5l7hA37zIXSNw5auBR1g3bIER38tVgOlROz
N+N2BB/1/FX6jfxqHSplRRMMMUXS0vwwerjQiqteWCP3wLB1dZU4YlEY0EzxclcW7P4uMrTfWNTW
FYG2Hp6TFnbLcCcgXFiKW1krROfM4QyqN+iVF43TgGFDsF92gg62nL6P6pqTRmWRQzU57f5izONI
2ejulFapn4TjX0cylV6ILP81czGnMrHTVvMVyOSCK3gBQTtQ4b1bVOC6RBDbGBUmEc+gYpkqxXFZ
YWJedq3Zu3OaVLr8A3ZYko9QVm+kLvOeRAvULWEWoXmoyh+Tvn/P/U5yL05nZ2NPFjiiUtS36DxP
xWvXxBDa2bc8vRMh+Mg+9+nvwqg/2T92dB8YXyJ0FMLnmzIJxU3iybURGKycQvpMqhDDr9C9u99b
14IJPy2PofOwtiozb4FaLGFEbBS1IsVT6p9951eFQTfZR1wagKxsrOPbViMom24ywLjWv0Q/lB2r
eBxZtBaFSZi5zZWODNeiouO8TCUdVSStJxDE8+JxesCIQJvrW1HjrLyZdSdmq3PnlrNWCR3Z6UHG
LhUjKlFlyXJGyZykyY/YZcLyPHVYgHvPR5eOsoR0t52ftRzfZZtiJNuI7+8aCpT8SiuTXKFXwMxW
1TtfRgaalivz4gOKQXNIzyFg7MUziEsSIHvEuYqie4Il962Z+EhmlP+6RUbahOSAFQuQzg087eqv
A3wv+SizE+pJvS2UCoSPYOV7iE4Yzd6uXqK7QwLLeEvp4DMEvm21+brl5dLd/7GxJ9I/tfWKgsL1
RS2alwvidVvw0htDCoZIumObAroc7Kp3hYqD5/hBj8eHAWoTwY25tmvNfgA2yCnyBrgbyckKblV6
eWjH2AJjGoz4E6nOlFgUpNfsfy86aygJB7lhxOA093Y+onUFSm+VEu0BdLkGfwpRtJJl6gOJFg+p
X36/sEZlPgWQY4s0PP8YvU3lF8M+/FXmkMtQOgnLlLCR27hPns1ecYfhd9iwni1hG45/K1Gm6dkg
ffYU2Ej0b2LAaE8d3kB1gNKEypixePTlNGe8sMsK1sHOkbgF4Rfwmb5wU5ClG3jAo/uas5jm2D9y
zbqTB2i0QDFybsXJAK1OJefVghQ12vKH+S5Eew6kC7OPFqqNnM0+9byiADj7UEPuMAocZWF8LcLh
yqwG884vuSCPdoQCmQbhsTSAjxHdDhfFfByfdF0dccMewUq9RUqrkMUTGzdoGew81rKRk91JFQyi
X+8D3LcCzIQG89OR3moTRXuYVqlTAML7bcII4PeBCCwW4kom7nXcGE/mCNp1xbDPkn8lCZdjQR0P
4J9eEjwfvTe1U2MOVme7jQkDddwaWUW/WJyINWD3UBtjhq32jbSNoMkAosEC5NC3StARzqaC1fXt
tX8j3bOpELHDUEOTHLDkkeu0eVne0CG9iYU4SP0zLXS8IcBMdIN3iF8ECHReD845zAv5aunVOomj
eIT+L62ajJzX/4H1l1tiK3Ae4bDZQd9rWde2I7vIuJWYS9g19XAMe6oOmO6AzWAIOr/huw9QXJqX
Olte6VYYQnnsOvrHhJrYNCySs9Mis3Ub3FbotQaf02BWVOQXyTb2IKkA+yyCdQ1NB4RoJ+IDmxEe
t5Im3EMI6xjumpNNr6Ut6VAXhW0NAKToH+iq3SmKCQhWpym+vYIZOQAVcCEYtzdxqRGWwmUI/DsA
jnlOOGjCXB4VvoSPStKRd5atlro3tsmGdW4q+7jjhb5qWN0IShUG/6QoEQ+PRKh4EztEkSkuMqpD
kQYhZas1VA4dUkU/uxYtaUo9waOJn2jSjHdsbl/qvzDm3dtAeckMY3oB+WKMLka1Bpy0blstZqYP
sZE8puLgcAN9WnL6oBnP/agB9RCIsybJO9IMRUnbW0bRHyUBDFeExSWxu1mefP12wBUWcC1oq37f
u/QCYsUnxA8Wm8d5CnktIrpU/UpR6q4jFZ7scCRxtGN7x0QYVnqRdtgXmyAHiNNMdHKSF9Mh2xeD
wYTSoU2v+we7dPV+QgxyHo2np5140WuUB74W1xh7L0IvHZHyjdPOuLQSJr39ZnVqYol5UmJAxNun
Mrp3nzSxwtz6KyqoDupRWIeTXj+fwMNjK9Y+cuoNOm8bqH1ol+POPt+IYjpctd/5/Kp41vfUZN/Y
h6a05AVuezDpRWzeAYavNKY3LXlbplqhicoeUIV/sDTd516YN0F8iZA6EE0A6U/JJuhMPYuYA6GN
pB2ftXt+DwIjmNd726k5fNmxyjuMl/EhQgKEdIxZetcbE2TCFImVgsTQpSazV83OS+RiDQnqxtiX
DL4yyRzBYmZkqh3QBnYuzo8cNASgGBOEDHRWGYU7fSLCFDXxX3xtWis2w8pgrWTGjVh2lVuGS7lC
UbGqJagnwoI/8z+UZzmKx9BfaKtN1V9/0lIuoAU5CMtMMfJ1A9q3Fn0wqaCsqU+izBHgdTa1mDaa
68N4dHhTvw2CwP3bz2s/oGbtU3Sbsmqb3/ci6EFzfvmop5l3XhKEa0IPDsDJg74OqPW0dMMhV69u
OKwdSNHSH0PkeI0csIoa2MIgTtxxn5rwDFHju80Qfjj8lvY4PzzFeXWIKk4fBvEh1yCJqZj9GOXp
kwPIVoJ2sCkG460mtJvHKYd4jQmgocQpElFJWbvWaPH0tWUcjYPRTC87XjZs9wXTlKOgfQxKuAy2
+zuzAgPZrqKrpSlEolbcvs5n8cA5Iz0+Vzgly7NBaN1GmSk1EMo56hJGNAxBB12YQFyfca6OcFPN
gIfpwDKuARvtZs/n/bYuoy4UxVhsCi4FuwWZzivi+MbfF4qRiQgyBTNxNQShfCNmj3MqPgyWmazy
SXRTN2RLloD9D9KewneoXfsvGsxaQ42N6W7CedPAQLtCGHMw5kXdYF8xCTd+yLNrXJa9iracjLrR
ZO/FKrb/6pzV919N6+UWNvM4P9dl/FmSm3RYrahqR6zWWINwG8cSyAWQLzgMNEqHO/8IhjiHV1nG
9YFFBJKLi1Ed2f1y0P0dx47f+VTZrEqlAKYc5XWEB+T8Edy8SxzMifmqOk11fyYK4OUU3/MgaGv5
Pf6xpfKj+3ZYv/JorsW4HAEb3W937Gm2WEumFfVaKsn3F3bXAjT9rn7mUl5OfUyj/ZTZeXG0rjsp
6dmGnEGwsmakwlg8AtdUIRBltk+okiO1Fs5ResGHHsL0YuFM/gt7RcZ/G6UjhAzsdaUMhJte0qBR
AORr3NjsuPC4fpi41LGFXTCNcTtOUcFd8Yir3Dbeh3uZxcXeb/xM6gDyaPaFy4ISDUDXFxVr5Mzb
kNkJUbaEOHwJhByo6U+9XilL4fsudPZNaR9zJTxWhU9voblPYvLkJPuA3UXeEw69i0Mgd1NDOMg7
7DxZvO60S+t8ZtZLJ5T/wyBz57beXTZU6OC3DNOaWdwy03HrMyvWg21LPRa6UeMZ0tSmU7DW7qZ0
fuJ6GVpXx5bqK7tXpOQJi6RHO7hQN3wO4PUSLS3DUeu4X+lSlaQD9Bpb9yqfb5o+aqOsxsvsltZZ
5KVErm0vmS/eKezuR/JiGhb3Wf+JbJY82ODwcet1tD4Gle501OS6l+VI9FqPo018QOjZxjM7lfsE
XfP3cbvMSJqNOeVBPJnG+mM7Kwf3F6BAeGpXztrwCQ2IIBAArdArP2BH23KZEEIvqLI8T4UWdCE4
M9CBO7MJdDneqDYuw0ywZWNu2Xm849Lvpwcu0lDJebYjEi3yS7bG4GBX4JDoH2HuX0pbVhoNqHxb
xowkj6v14Vo/s5WctO5wukFnkz0EUXqrcsBBLUjAVQudIUCoqElRWNxGktB6rvJPncwtHcKBGoAu
Ea3NbYzr99OyKmcXGz4laj4dE6qW7lexcXt6977GobI3j0ef7ZK0yDfsKPFyNmw/b24az2Jphkgb
S5KLO+LPzB1ufjDdndx6xEHE375iPxiNtElQRI9e/GVeUomLxE+fGzUSAULCJoY9vPhmS5jz55Wu
Vb6LVVNuNB+KotHX7Upvpmxn9ADTe/xXKQ4gR2C4UIOT+d7gbb2zk6zUd34pepelgXBKhKxs10Rq
AlFSk4Pl4qTZT7Tx0N/zL1MUPp/V3l/Q2NtfZV8Lzors5g1/6w674IsNdIo4bHUq/NU6lWSSQ+mX
K84IFl8fO2p6q8UPpmRPuX+uvNa4LWB1P4tbksMi5FC+PtJZo+hzBnIQjePkHZysZ6MiqCyjpS1B
ufTHAe78JI65SHzVBNIIGgUfOjV2nwdkitoO1APEwYzVejTRaXJcRn2VnazfeGIg0e6rrmftLlF8
zEzZlNB88n8CPjZrq1MPlBveFn4y1hF7OeLTajucWEwhi6GzitvoG4/CnGeVEyVOmhfwepMaEf1w
ObdjzgwEH7Ydt+6/y8U3Ts8zX8MPrE80OrYf3y/wclUEYKrHBpF7czRLUYdnmeGYiO1kl8ypV5cr
OMpg7fSsx7LenfVpW+PqGAl1yQ3VD5HliVFxIbRhdRQMa+QgSEBvwnlsOsTEnL1RA2U2nF6QNql0
6h7lTZSGmMBANJDdRrcywQ3eUMhRfjLKBIwkFr8Y+ddYIGMUgwVnEjIzw4bjQwP4zcR6R3fTyiee
qDibs1YMcROke9VCSITC5IkHtWPIpifbkkQhby0N5qYz0bNOeRO8XziRoD0KrrLAqgiohcDBMtyz
ydneT6Ij/JInZty0WW2HZUQ2FlUDLzRx2IaNSt+TugawvINCwk9AuxWtiDVr5bQ9N6kt2E5fhTY7
TKawrn/+nXGAHsWoQsOQLKxWfJUJrCS9SzQhoJnsq4592W5/dahbEKv6/Vin4K2Y0owK66Cd0Grg
VHD8SIwUXTyr1fieE3XgdGcopVuhVfRVl00sc/0qTUYdUUUJudwaNCmY931aG0OntWcRNWW46Pha
02kUt21AziBSC1XHqDV3ITWkSbxHGFRnp0XuTu1CsHoTt82IZJIujrmxZ38zYwLgDReZnO/7EUjO
x4jBgr0vxNg1+xcHJeC4R5/CPeEFxrOBydkl3qnpAmwcLMtAoipfVvsUt05G1zXg3s3vuLjJBXuG
1eLCfjcV5ZDj+SyXvNBC9CgFmDesqBm841HRtTMhuD17pSU8PU/5/v3x2xYHuO4ZatfrNtE67HbH
ud/oUumjb9nqYxdv2MxznSo0FOgrBmKeqnazLS9uc3cGEiiiuJGPjTF3twU2OeaOi3kZ/PFBbBs/
ElN/U5ZV2+76a2XVRyYBU5XQ8ua6wD7gEy5tuD67quB9RnWXZ+2Ndmn565ELMjh1pWiKSNcvwwpT
m0lc/4mCQ70tSGggM5bIpoSmsBsym8ohRPp7vaOTCohJMpE/j9E4SY69InekWGP27QHigBbqNd/1
bAorjavV/8JUtCl4e3hON4rd393r8rs6wxFyXD/WLq88hQ7QNg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eo7ztsvbgSYd1KGoylhOwWqcRC93ADsrF+RmXvAplO96rIXnjhzPYctzz+XAywaHSS1JGbblhi+C
CG/Xmr+Viw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VlDPvUjcTGR2bEjy3deiDqszXoduUt60+OFMFcjqa1auPc/2MBM/VWcMZU5YwD+sO6r7Cd2u8kzB
4QzmPkP7uO2zWeFpoq3C/41rplxKCcFvwXJzvHREIG1OnzYb/dPblCiS/+mn2VjAfB8xizQ6Nln/
0idL8DQKgMDcgl63gN8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Z5qUsXx9HJ3+prwOOiNYDTXnWkUAAahQNFkO/c02x1krdZ8WgOiYfdeKqnKAkYdW38T4bPzkQYXm
F9HRN7bup10M5O1nlm6pdyO+0sV6xeX4w+FYkNPaAEVwqHpj07WIEw/ue/EVXX5K2OIBRGh7/H4Q
P/1YmzkwpjoeaA309HPiLuhPj85iLqCcbqI65h/qN7AP0Cw8sPurVTI8asvfzZDURNFtxWWTqSWs
YDduGBX794GzpN6yKoOLlO9m+TqdchGrFtksq+MOHi3FXTk2bB8DuQ1tOwwGC7UV86QeCPa73FUc
osm7ZSxOiAN+kOHPLWKEtbJpRWeajTSUJalVHg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JcY1431frN/YbCQwZBS/ob/VuFxPcfZ9uCReqISX0nCqqpT4EXoXqqwJIy7mLfBpRuS8cBqIBklC
tHbwET69cUCSrkNm3K2/VMAOETKn/w+gzpzjBa3bSHor6jb9uEop3HqOLwiHUEycKwPcaK4IwTM1
mhUqYCQiEK4l0ddH7X4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U3FcEEjLh+ZVARgnFFqe0XZvyPgHip1ElX0vFmo09sq5rJT8+Qdr6xmVCCdsO7nwNQJfKuguSXwX
/iIz3TqU6Tn6yp5h5s9bP804Hk7RRSIidG4CeLzAMXaQ1e5OKAvfM6Zml/A25FdPg/TILkDmwRzv
W7RcVNcdHyRxomufsKZpSr+gVGgB3pmhiINQkpdVB8mx+GhfIqJiGsWlih0hZgR/9shgCikO1MO3
gpbzl6FJmydQlmczjFxBz+oTkQysHKMv8vTZuzxpp1/VDL/Ulr3zYq0oXVLMvwfYA7tAI2khu1nS
uTO//C2snIFFgujZl1JszXkeiMUpQns6O/rXUg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12064)
`protect data_block
pjbi/xQCQxX7daUuB4RG2FXtx+lQjp4/6p0yL2fYmN9pvPur+5XNjtIVjfvScGV2f336OVsgjNWz
j0ql5sY4U3xJRBjTnUuOVVMGIh1a+fXN1Ddh4pamOJd2bC5pEAhq98q1r9LqDZYggrWyDd/kHs+3
1ghs0oHAld1TYip9gk0AJgjfpianf7bA3C2YQOOc0hfr9wJgbqxgZ1ce0G0EjOnC06u34C0UrfRI
eGG5408R5HLykJKTRZikQherv6QL0X1fSrwz0AE3wBvX0AkCKybuoWt/lTRmZx1Ht62Q6HfQkzJL
019avqfnB4YVyUyJhQDd/HiKzM5DHYJtpVSVDj5U2wBqcuzgU4l7S80+x/ejnTkB4IEtCcRc3sKI
bPSScw25RVnK7VjLj53FUT9l/IUE8o2y+lJ/N/JCrDQI3kiMllUxUgh3mKoqkLQQNh0b0u3I4cgl
MHYC0LWu4SwYVlJT9akWmI/Y10n9hoqDOOT6jpMVQ6RjqVjaBOiTWv3M0iG8W6u4r58Jv3P/gJlL
MUxyTy1woIRnCg3weq4kx9uzHX2ZkBHXIT2ngQV5HQax1lLHGfrbipdGZVTQH6n1nrnvw1PwLUEu
XNDDNOAOKwBdPjsMChs9XQJlk7aSAT1nHR+x0rWpsGAM5Eld5Cm9wwv1HKm8Ac6vvdDciTi2I/bQ
zu+ph918RIGMlvixVe6/dZx9HNjBWoUOoUDN0BgAxGxeKPU9I2wfhRKmguCASnk7oR1k7QIGJ6JN
467dxoAWOSSAEmnIlAoBF7CkVTNRX2JVz3jPlEDUEUSrsczYZ/XgXWX9S26LreXIIGIixCBSpdLo
3a2y2VVcfQgD6s2u0Yl//fXwvtQ9Sxl6OYpYv0hIVIiconGn5KVCczTVUxG17wUWigel/431CXeE
yXnn1p+G17kP/1wQaD9mchKiOF3FNQlVHhmDqzA9Y4cnS1CmC8JKmOOPTcHLdysbxDunrDDkqf00
F04wnokYPbeCQDb0OcyNdJV+GIe5hRsRwH7gQWCMbhPsGS4ilJIyfJ7jSrGkp/GiHPiUhA3TiN6P
pojorK5aiLS8g5kvwepUXaijaKRFFxxxOv5R3MRHE0EbRAhqCf+Ndz6KnRnGd2iJTb+Mq0mC7c9U
ca92CnyFZ+FtAvGlEMzlRrt7WxukDMLtbYbKmEpNNoa/KnQrfJTawuaDaFM4X0RE4kwQPfSnVMKH
3VSQFDVA4hCbtx7IV4dZasQdApsZEtx6jk8wWk4JKpsUy5kblcBhpx6tmTlbDtwICYka6e/yVOCa
FbKJiz5SMR/A007kFbCxW8RhxdfgY+0e9Q8TBbT1DcY6CZEIFt2WRfQ1NSvBVbQ8KeMwQgl61+Sg
9LXY3le+lli0rlQc76+Rn7ZFIxDdTEP4CYlEpxDAm+Ux2xM7gTuVmcI/H+okaT420BT52gPNqdNH
XUbKD8X4FnZ18o/teMkkVZ/w909IaEbbo3kudfNQQmVgU9MPvFJ5cNBkpMcO8t/UsAUhH70sxRg3
p2IjBnWI17KDAgW0OLLuYcL3vEmOjJvl4qfVW9AkO51FHx7pFQFQLCglRB14R1ETTs4mA0px8w4J
TCswJPh5Ja9ynMZjlt3VJCRPlRJXRZl4Erzk80znCE27J2lyaXQhFBOJNT+uhYmUx4Ke2JLc7jc2
fehvqjbFhFb9aQTyaV7VJDmmx0I/KInFhHHIuXRbzjjNEk0LwC2fMex7GGxERuUn5La3lTj1Z29S
Pb2vyOeYkVcb+OPJ0bobxh3HA/MGJlIisCKBxD31Z011aaVClUJ6h3mRB0iSW1Z2dqWNjv2Uon/G
UYRdkngxuRahkZ0mJUZsE/7xqr6C3sJ+78fzSRi7bxzp5MLomD3WmiUPTvH+n4/dWffEfZdhrz9Q
tEeLHMogILdlX4oZspgmC/bVvV9BYvgL0Na7gji+9iBOaZGFGKG42iulzKPtdas6kzGSXebbSVGs
+Yw+aM+ziMv3F+0heTHnoxBJ7RziLZpSD1jIjOk6sz5seg5o1+/07oAyJWiFPX2lc+nKbgyFpunf
bZjmHetvSGZ+bdfVDapRNEx1uZCgPIdCtp2U0cIliu6+1mBDpiT/FuF3CBr2CoAqdqLiJ9PBI3/M
w7VtZAGIuBOuhF164rsmJBq2V/ybti+Ewekt0x1pn50X9GurGXshYuRsAmm0Xk3law/QkDtbS9KX
VkkVXcS34K62n7n2GGx2xnLJe7Jt5+0dZvnGdDoifjYvv+uKfdP2n81eAB6431xBtkK7ALGueWDy
OEPeDfpBeYiPyfFR6qOcXk+rMx8gn4HGEE+eopuB7Lb0kxwHhGP1cqLrZd/G/gbpVMpUCzYVcT2B
zcAklT+XAxdhKEIG2lSkVOO3v1qD0enSwyiz5JHlkTVB7Q9CLliE/7PZOlbtEkIZdPFM6y5JAZoN
3M7/IeajRZmkCPMluoQICkE+sJ1+INFmyW0mE/7Tc1FsILwJXEEsmiT2vWtI+ek8TtDJ/z1DTy/S
HziduGggEDk0VTozDIS7BEkyyiSDh4yal7mIwF2GecrUrX0Rg9VZOBQZ6nQohB+zR04Y2yb565o8
E2l4g6asBhaLqNyaaP2QfRqicC+Y7/kyf6zawHJ3AYLR0IGVSY19L0xA5vDTB1rN+9pzCRFNfvAS
dzWpRHn+Ys8YT0T5wVQ6iCqB1DgissHLt9zJjreutIizjXzqQuin61sStVrn3ur0wJwJTfYvxEb+
oZ+wMiVBJ5FhKQEc1tWrkZ6H6eHMK+PxMwN1pzSRIqHMuD0qJefiO0iuqJyGYztP7r/EnpkwILKS
lHu4VNVULPblOtVxIJlzd1pj3KIa7/3JVxGFknZ26i8pmIH5HDKfLA9v9gJMgLhPpXSuzXEPrJOv
m/jw3EYCYwc65Upn79Q5FCcvNkPEinuidVaEQs+aW6QpdC2VJOP3zeOCOBlY5qasPvphz3ACsbtX
LD66h3QjXhEZXI7JA+dQxlKwDiog0B2LvhQfSFh81sXdM7+H8jOlYjY9nWwoHvKvucaOdV02GJL4
Q8lO3yqO0EOTz+oaqbLlWvJftM6aFc4A4zIcoWlSyHDZcop+30XcdZCftAfqf9bnOWIn1ohQk6xZ
eFSMHIezs2sbnEs+8rrSTmldJzZiZ/i9UgC81Fr0dwALnErai2HoegnMSIREvb4+ys9YAhUO/4e1
DXanaeqlw0akC3VT2XQ4BIvmdNdHtDGc9k6VTG4VlgKkVVh4pU303Em2bh23w5DKISMX9Iigq4Bm
4dqnfDaaXV9yVHdFzkoHosXevYWxsZz+NALCM7CVU2JcgV8uINJq0XLRSjNT6mXilya4aGsZxn8i
jRG7di+fC2AZlhcVdzRP5v5ZP1kVVlDF1NIKIN+PxlBK3stGMZJCtaKKJ5I66YCMrqVjB/ZSDKxU
g8c+Ua3+cf89d2XGwpwukFjDt5xMKZmzr9xLsKhj99boLmIU812mTVVlNXALbtEjCFwC0UXRiiE6
yL9P4MeIRwIod05P+4YZR6SVrcIf1E++FdE28Y9xYrngfuFxJ3IZGYIGya0U/AGSZyUm0bq1U8C7
qGUXaM81dPWNUBn6wtQsh5igoyJbGDNE+Ja0P+nFd3jvu5kEexEYJgV0xmsPxgOreYUViPdgXnta
M/d7Y17lhS3SorhKx0X/cj11i7ee2Ersu/bbjlGlOT+LzL2IfaddvpVDFP5DxIlfhngqMeh49C7C
97sWhgEWL32b8qvFMSIiZGVKOvPKRn2nm3VvWE+ofeFXXNak1oYa8L1chBKTKL8kdh9Qr/d98vcT
Ibo0440U7hTT1CLXAMXWpNLRFx/TP0z0NBXT0ZOB58w8Z/wlwT4d6S/FsRY2JDrc6C2D5n6XuIRq
7BS4uw9S4av0Mq9yo856gVlqOd7JAZzAGXJHaRIta5t4t/53z/1h1GLQJQ+3ft3m5X7pA2/Mzxgw
oeGNazpUgnD0qtci5FX7tNPzI76v4o6RqszY/tN7vzbpGti8uts8WSnHoEmmHZ2vfHqpYiURpAGW
+vxp94l1lUYxVgz4fBPWwRPZQ8r1RddZTFXJ2H0eVHAm5qjiqUQA0NTRhtMllFuf5PY+/fvT9WOC
x6fSr/3bMYMz5LGpu7vGXhgFZfi/BD6DzZ/Wmi0vLGfbQCZiZBAlZfsvfHME/eXgdgHlTTs0qO43
kEjlHf/0sWzIXWEmpI0x/WqnfnLGatgiDQTbmcDxgIng2s7vI7FUhTqequ5vllmUssrbJa1kpMeY
D0mW8xtEAvWuDIVrcPjVHHuUTwwy8pcsuMUb9XIPzk/6agwwcmzpcWTw2XxQu/7fknb2RdLMffIV
ZThyI9AgdPiViHeiWHa5j8HLdU+ovZYIUengWLQTBLtUASPljXKHxOu2ZlDbyeHpzMrIYJFErCxJ
TUSBGp9wmTcf9kIdf3s1P6yf0x/U3t6wz6gIe3JWFxUbn0OJ+iG+4NokvAcGW9nczhnkTRm+86zT
ktZX7WG0IOvJ2y9qsrmvTn1/2LZ+Pi64RxJBlt5byfctA+gjd98455igwuuLW50axXWfHLywA7Wx
JYup90umZpiEazNbulMYkQHijTwzzwypL3UG2olW9Tz/P5ecGyEBRIYN+hpZCAQkjHImBtcNmjds
K0/oqKblQhYihXXymwhYwigATajOi4zfrqF8zGj0BAo1Pl5/SKWDUjkDPT7kvAOzFbySYXhMFgBW
/NzZpz+1XqzX3tjWF0CDtXCP+NulbxIN53I456WMzqPWO08xfGxVcm9X1GMvE5r91xneCqmZk/3s
5EL1emxKT4zeSft7ZCwCPZF5mZVRpL4Ev5QFKU7Q3sqqHYWF3YAUh+kDjfO16oGL9Mvq2Y7Rv3lE
EDY17JEtJvqdIdEpzi8rL5g+oPMAPocoF9KgnasoIkEfqPFeZcBQjTQYg2dg7Dol7KBdea5CW000
D2Ra2sq+ob69YMjhwGAFEFKmwlzxq/9lyjzykwVi+ZhChsZvIpF+13nTyBC+rUAJe0+lpoXwtB4B
OuWhQtghdJ0u4BVoBSb2rbJI9YknTwMSogFPWw4KzfcW1mPeMTpCaUD5aIcnyOOgNHRxgheX3lC4
r2Gjx1sZoc9sZvgAkRs/0CbsOSqrmpthIBbOfbdCYDp+imaQqU4/DKwWQJ3AuL1w41QDjP8S6DG/
xwccHuUhC1a4HLVMafGyfA3jepWUaID9wRFF1o3roLCyzT9u6vWJEd3+EVbK7lGxlAiWlwR35IRz
rIM+4l83i4N/HEtxvPCN9iPmrmXyWvOlGKx04nUyTNQsX7A+QpGddN4dgenH6g7dNfzjTGjqUyXC
KINx6MJjDaqbQMo0XU0uznYBn8woQXswfxCXuIjscrbnf+6PMKM4R6z77txzGHNFNdud+A87gnwy
BqNcUhnpdCcxyVPp+mTQVMyPznneOBfOZPcpT9wbQBu2gFf5psp9CGWp9EGNcMyTzLZ5rjFJL/iD
Phus6N6rLZeM/agKQeCM/b+iw51KMLbpUZZO/yCkINFNVb6/PjRrqcjJPWBWXlygCSt2RkMCXy2z
XnXA/pXtol1zQNBaAG60Q1zFNdnxSUNaIWpuTBvJNlCp9I6NmhVUcmf/np+JZp5GzEq0sI51MzGe
Xi3RHQ23+6zEbSNiDqZN0BktupaVZqauRkVWnSQQKzihKpiIEyrjOTGNgRDCFHhVILPI2qWP8GT4
agoGTeBxCnuyOuqF3+eVao0KHdTfi6QaT6i2MqkzNOlcMrOiFZ0SkF/vJvEj5XraLjz/Dig0wSlx
k6YHcEg8kawk4M2VYK4xm9+MEt+MaSxtZRAj6iiqDn2tNNq3f4HUManEWmfa1uxKBjR3fLebPYC4
PO0OEPczILvlbmjuywJwpavSmAi2GXksTYUq8JbM4Gv4uWYNrorBvUZe3zHhd3tmlvOnG0ehfmDX
UJlipWPvOUw10T7M3H1pc2hTwZyZoVT1iR8L+qmE6wjBZ8VvpX1ySQbc3liQq2I3psB6fF5hwlMq
7Vmz8cAphOx2ylE260y7DJngwAp6bIaNhFEDx3YY5XgrYs/BsVBi3STmmtLhpMTDr3c1bCPSoJGU
LEEFmpIYJZAhlNJlp+psb2pEcHum+SlfVkKQJQl5SDjfwE0wD4J3XXoTMitF3jn5Op/ZMcCJGaYS
ZolnaBMlvLOAJKBBabRBx0qLteO7wpMiRPkxoCR7IsX1Dx4tZAwVm8qq88lr+ifLlf7/T6V72ahX
SvZU8nuzSwdEcszi1mU1rHQ5EmMZPYp2/MuqlHlcpkiRps3PLs5XHP7NFgURiDTpXddwDpYrebxI
LqxITOgumDkGmgpCZuE+EtjeW6qnOL6b/nCzUou6IA/9rxmI3A4WMdQQMmjwpqAv+ODTPS0GPmvq
tPs2DE//02PzeHG4Ihi9Hhf93dspotbOqKOqI2xhquH+MrCtbBTnDMz8JwidHtNOKCtAYozSIcD2
nonCSjaTiN6pkxcTAtmOyJEb1OHmf+dXplKlzeuDXQubi52Tzjsv/qhrpUvV+22rfslbfwnD3PYL
sMrOSDRUNJOpQyajkdBpamjjQrErSnn9RGJaWTSZfQNDBTeyBaDAL+ysl8Y5pBsr4zUDL42cXMqD
31XBQ0fbQvhkCcTX3zjkdSg0Q4+1dTw3SXxptWm4LLbkOSxu5vqDHCQa8lkmwUjb/gHD1AZLnz51
kiIwFacQP3nCw/CzpZ9F+DA/sMF0KHCxLM9qyQnZKxeOrZyC7cbfM9nTwqhvix7iu5/iX0Hx9SLc
31I+e52KEUfnIRnTEk7heNZxSixrLF+Dth7crAn8fAyQVG1c93hUVk537WjulKhyEC7Dxn1QIdtg
Jn4ufESMehogvIEDzsP6xeCbb06nHShtze2C266EgBMvwXpbPWLuRtwSKXFHGbxyf3avnba/2jvz
H7OzcBFEEdH7tmp0Jt5LPMxZ6CiBfvkw5nald7ovW/XCaGaucYE1KsX6k6eHBu2Mfdp4kOLoAoCC
qHlbJgy2BCy7JPILNRL+kSwetc/gSL0mw14xGLxAQzUH7OI5jNOP1wtQVm6I4jR22IOmhh4mR/wT
daWabITu/4jCpVRVoP6tvCYqfAGFMLEEDUxNZnOrsqQ7HB3BoWdQSE0EbrVqkwRdEzWRAgrAN9bD
2UJkQUk1K9eKyH0mMF0+jUU0GUHGhSqDVvhjeTB591/CehGinNij+w2uW1XRiGE7W0MY5jBp46pj
95C+VkCtx6Y4gwrMxSzc4brzdAnG5Weo8js/HEu9lTc+ezPRL0SGFgYtrS7uqkf4GLLsa1YvBAy/
mC44Pc9ZvKpPEe/k0dKCRZplObHACL5KGi0jDfT+PnMvSDN8yCWqHOKJtg/vxBtLB/p9c1MJ3RIy
tTQH2QbHsOqiVemgZUaBgW+fTw+bS7qxMVz92ujdZUKqI+THhMud76uvcHLJIj5tfiuppa9ewWmQ
wPiq1EckuPSxrXophTmtOdIFQhsyf+bzND4QQyqxSllb8fpd4hMlCmbcz01Idc36HlDIj3G57OiJ
G+gS4NneiAxoLxaoIUl3AkI6d7qCj7ujfJiKdyQB3RMyODJovLN/Zz6Wbv/x7Cx5u4ARvuYcHgwb
uumm7pzTFOOxv3fqmwxj5U3199QB6lpRB9wBs/3NWGoftBFYWi6cDIc5cG2UEa2ET4HdqaKfWYUu
YBzaZoK+grgoxlTyznT17/5NZ/aaJZhGTM32bMpFcQO9h+4bmAUcLTCeCT6UBnNirR1X4uJvcKAv
fRxFFsaJYnnlRFqq0jU5gQaTb1s847c3M93CYWshdGJDEu5XvBVIQGwAq/xe3imuXOFdUl003UF8
49o/8P4M+bwIhyLQlQPqm0D1LwCrd49sLGROc+XBqwFkOZ6Fp4vMh8UwyyYsqqvbp3NOo50zszp+
HlxjMrvuMejDrwCw0306enbLRFt6WrXws27I+1wVzRVxkAuPuJ4+8d9tdmhSef3OdVmcm+PGdqPc
bWGwT8CaZey+bxdmLLHyhA8hdTuGmH7dXxvI7ajinCQzwEuEfc8Mg/R9JA73oPxJs5HLijZweKN4
i/C3EfGmbMPSZ1RMQgz2x31t2N+gxqQhLvKfS6obQGA8zTLZ49ZXtp9PX3Qlx22+zopa01nozVak
XLQvNuj9SuB+GF/H9ZXEanXLnHkgeJqjoEt9CqEOUGT6ZbF2imDbuAVmo3ilp0TNXP2cc6IlVFB1
TesByGLtJbzdt2X2Wmuw3DEJJjgqQVMu4DZGrJAhJ8X7INBEDq6mFaXo01sAVoAbcBFs5nDDSKBt
+xvqSbZZaD90E09Do1T0uZBPrS16ElIR4kRoqplA0pe9lMKIMeVo9FEjx5M85k7bklC3RPADaATU
ynSTStGCdCI1kU6Mdg8FPlzn6GT5THQhCEePhOf1RTtHBX8w1+HVY1iAtqqVDFcQvb4RRtbwxszF
5h9BVNOCVZAUPj8ZxyUKWMrd4Mb/Gq/6564Ojc4RQV6Ony9888Du7Ue2VwXSPb+NQtTbvAYh5ceE
8Xpedq/nJs4k+KT88qnXYT/UCL1Kz9n/6Ys6MNqwV3fD5H+sq7uT7wBWrnAZglQboskjMH2JXeXq
NreurugYF1kh4WYqg/8vCYr8rgeAy28ctWxLXwfnp0L0dGjR0TycCBHlLNK+tTexRw43L127/VHE
d+SkwSoNvALUcRTIzRabanJ8UwuZZxwmSGMt2On3DKgpA6T4tZ2qrcn38mZyX1+IcqhEDX1CNgAX
fKtgwxbGXCfIcK2MsNF4aOcH7lbDuc8eV45GJReTac+zgpfZ0s4d2ABp7HL4FHs6uJxSC8AFDisv
qTInW3QSDmc9olG1FDwdsTfyuPUFT3A73XznlFJdDbUK5LzGbwGg6o5Izw/I8auLULGvqF+sKohj
IdKubDOQuXAgu4SzkDFqbMkYwGfRdrMvusjwdI3r6iDROsXHptzRUYGqVYIxh4QnWu96w2naubAe
fK78aNCQz0YhNPXuaiUeSgbDgi9cEg/bWBEzOe7BdAzSbgDF7uazZRXC9xN0/EEnETXjzwhcZicf
Z6TCrngpIrORw502nb91t0k/9JEiJY+XHwawhtSf/Bx8a492Hmn76vlWi5vn/XiaZ6v73oFb3GYh
vUs70AgyXbro8yyKti1b8Om8kbibGxsGx6l7byg0bg4FEVJZ4AHv3+M2mfcOorZRDhJTZBSm9XZu
BBqqYRW/ctPab963iO/jIWY5G+rpi/EjxrnKGOsTOaTh2P9/9N5jc/zwdH98TftBnctZ5ox6eN6t
c0+I4K0rGMaImPx7Y37HTHq+eYUbIsIRki9t2W+sxRR9nTBQtd7FS4Zhz/cAOA++8y6/lGiEOiEc
Yd2a4BHvFYLhtX3SL3v+D4rTgv9yVtCnZHiR44QdyzlcF5A0yzPN3JWx2OnF5282akPzY+X/yhTp
NLP00hVYYurVwz57aP9W/F72XmuDbdBGPvcfKNUZCbrR2jVaZK1urCDfrnMZLkoqkv6Akq4bXJ9s
4LeGxVaRS3Qz4R4FWHD2/FEm+eK4+eHE/Xm6Aas8ypaqxqzC35cNrEDs6FqfYEPAl8NFpxtnKZOs
3mT6L/BJWqjJdz+ZA0OBGTQu76k2puvLlaTU7y7ldE0qk21kfSmzUdAtSnqwDZbwuSmfaVn7bS+6
tpsqb40LUNLaZl7SaIEUhYqUO7fixNH/dao3buP+NxnWBS3p9gCXEatzD0OTRJkvCgi8Pi1q+Sxe
JUyJkPfYlLHoyO5u2B5P4Espg036DiLFcYPxZS+uuA55YG/dIvIr3e06m5Qkb5njCttDA4bSnMyL
w/pEGdd1WYEQtX7EyD0zaiCwd+WSwRvbtmdy7v5USsXN3GTNSOfNTtozjNTJaqfhVbkN1tOV5tCk
wHDAI+mdbI5Q7bUipXX7r7tpNkiu221gGjFg8cBmaWS6cQw74zEs9Pn5czmjYU5OK6cnRvs+zGNA
aS5YRADde5Lw16RC8+20i5rnBc25mHO3hrXqvtuGVECy+Y+1/JvQu2l81YowjM2UA9Hmjq3ugPsy
33yj7Jw4LG8Tw3/lczBH8XMIoTXMdh299mvUAGyZqJwDlcrIem39MX6uPvRhTEIBGidMkJdmJY5f
2I7ugooAHMrJRRvW5OgZ3IpD8HrjR9qZPYaEcXQgi5Rz7n4h8FrtSg4FP5yF7baEjPAuGI/iF0Q9
ye0jlEnvFxvU7prDZBg7bed4yqg2W1SbnFrRd+7vrmjIauUYykfxVsV2h/DfYyczbB2zRagKvKU2
4JF/z8lm1XnUkANqQWhTJEd/U1EjNTTMRtiWPnUQr9jn0XMJxRq25fNKmrL03ZSIJS6Q3xH1e0C7
Ndes2uJTS3cIeX0m/6AeFrWPdm+fF4F641UR0GF8JsX87bIJFbwuzlKbdwiEQ94MaSmTN+Zs3xjE
TIdt5D2+KpPImW73E1Zx9djeamZbW5+LuvPiLdcNgPLb/n0xjO8pKyWWXWnfRB1Ina/tpSfK/JyH
woeoTVdBeKvUQl88XRFhsdb83VLflb0RGCqljUUYx4OK1dxbK0oycpL48B73XgVeJhzbRCFvu0xr
cfxbBd6dbOsdw6q2OcENv7IhD2juzpaUSZ9qUHNO0OGB3K6SEcwKuucF3Nkt+98JgBFvhtGKI1Sf
z8UYN4HedO+274fHQQGQJ6rs0nPg1UArE1UgP/sLW5l7hA37zIXSNw5auBR1g3bIER38tVgOlROz
N+N2BB/1/FX6jfxqHSplRRMMMUXS0vwwerjQiqteWCP3wLB1dZU4YlEY0EzxclcW7P4uMrTfWNTW
FYG2Hp6TFnbLcCcgXFiKW1krROfM4QyqN+iVF43TgGFDsF92gg62nL6P6pqTRmWRQzU57f5izONI
2ejulFapn4TjX0cylV6ILP81czGnMrHTVvMVyOSCK3gBQTtQ4b1bVOC6RBDbGBUmEc+gYpkqxXFZ
YWJedq3Zu3OaVLr8A3ZYko9QVm+kLvOeRAvULWEWoXmoyh+Tvn/P/U5yL05nZ2NPFjiiUtS36DxP
xWvXxBDa2bc8vRMh+Mg+9+nvwqg/2T92dB8YXyJ0FMLnmzIJxU3iybURGKycQvpMqhDDr9C9u99b
14IJPy2PofOwtiozb4FaLGFEbBS1IsVT6p9951eFQTfZR1wagKxsrOPbViMom24ywLjWv0Q/lB2r
eBxZtBaFSZi5zZWODNeiouO8TCUdVSStJxDE8+JxesCIQJvrW1HjrLyZdSdmq3PnlrNWCR3Z6UHG
LhUjKlFlyXJGyZykyY/YZcLyPHVYgHvPR5eOsoR0t52ftRzfZZtiJNuI7+8aCpT8SiuTXKFXwMxW
1TtfRgaalivz4gOKQXNIzyFg7MUziEsSIHvEuYqie4Il962Z+EhmlP+6RUbahOSAFQuQzg087eqv
A3wv+SizE+pJvS2UCoSPYOV7iE4Yzd6uXqK7QwLLeEvp4DMEvm21+brl5dLd/7GxJ9I/tfWKgsL1
RS2alwvidVvw0htDCoZIumObAroc7Kp3hYqD5/hBj8eHAWoTwY25tmvNfgA2yCnyBrgbyckKblV6
eWjH2AJjGoz4E6nOlFgUpNfsfy86aygJB7lhxOA093Y+onUFSm+VEu0BdLkGfwpRtJJl6gOJFg+p
X36/sEZlPgWQY4s0PP8YvU3lF8M+/FXmkMtQOgnLlLCR27hPns1ecYfhd9iwni1hG45/K1Gm6dkg
ffYU2Ej0b2LAaE8d3kB1gNKEypixePTlNGe8sMsK1sHOkbgF4Rfwmb5wU5ClG3jAo/uas5jm2D9y
zbqTB2i0QDFybsXJAK1OJefVghQ12vKH+S5Eew6kC7OPFqqNnM0+9byiADj7UEPuMAocZWF8LcLh
yqwG884vuSCPdoQCmQbhsTSAjxHdDhfFfByfdF0dccMewUq9RUqrkMUTGzdoGew81rKRk91JFQyi
X+8D3LcCzIQG89OR3moTRXuYVqlTAML7bcII4PeBCCwW4kom7nXcGE/mCNp1xbDPkn8lCZdjQR0P
4J9eEjwfvTe1U2MOVme7jQkDddwaWUW/WJyINWD3UBtjhq32jbSNoMkAosEC5NC3StARzqaC1fXt
tX8j3bOpELHDUEOTHLDkkeu0eVne0CG9iYU4SP0zLXS8IcBMdIN3iF8ECHReD845zAv5aunVOomj
eIT+L62ajJzX/4H1l1tiK3Ae4bDZQd9rWde2I7vIuJWYS9g19XAMe6oOmO6AzWAIOr/huw9QXJqX
Olte6VYYQnnsOvrHhJrYNCySs9Mis3Ub3FbotQaf02BWVOQXyTb2IKkA+yyCdQ1NB4RoJ+IDmxEe
t5Im3EMI6xjumpNNr6Ut6VAXhW0NAKToH+iq3SmKCQhWpym+vYIZOQAVcCEYtzdxqRGWwmUI/DsA
jnlOOGjCXB4VvoSPStKRd5atlro3tsmGdW4q+7jjhb5qWN0IShUG/6QoEQ+PRKh4EztEkSkuMqpD
kQYhZas1VA4dUkU/uxYtaUo9waOJn2jSjHdsbl/qvzDm3dtAeckMY3oB+WKMLka1Bpy0blstZqYP
sZE8puLgcAN9WnL6oBnP/agB9RCIsybJO9IMRUnbW0bRHyUBDFeExSWxu1mefP12wBUWcC1oq37f
u/QCYsUnxA8Wm8d5CnktIrpU/UpR6q4jFZ7scCRxtGN7x0QYVnqRdtgXmyAHiNNMdHKSF9Mh2xeD
wYTSoU2v+we7dPV+QgxyHo2np5140WuUB74W1xh7L0IvHZHyjdPOuLQSJr39ZnVqYol5UmJAxNun
Mrp3nzSxwtz6KyqoDupRWIeTXj+fwMNjK9Y+cuoNOm8bqH1ol+POPt+IYjpctd/5/Kp41vfUZN/Y
h6a05AVuezDpRWzeAYavNKY3LXlbplqhicoeUIV/sDTd516YN0F8iZA6EE0A6U/JJuhMPYuYA6GN
pB2ftXt+DwIjmNd726k5fNmxyjuMl/EhQgKEdIxZetcbE2TCFImVgsTQpSazV83OS+RiDQnqxtiX
DL4yyRzBYmZkqh3QBnYuzo8cNASgGBOEDHRWGYU7fSLCFDXxX3xtWis2w8pgrWTGjVh2lVuGS7lC
UbGqJagnwoI/8z+UZzmKx9BfaKtN1V9/0lIuoAU5CMtMMfJ1A9q3Fn0wqaCsqU+izBHgdTa1mDaa
68N4dHhTvw2CwP3bz2s/oGbtU3Sbsmqb3/ci6EFzfvmop5l3XhKEa0IPDsDJg74OqPW0dMMhV69u
OKwdSNHSH0PkeI0csIoa2MIgTtxxn5rwDFHju80Qfjj8lvY4PzzFeXWIKk4fBvEh1yCJqZj9GOXp
kwPIVoJ2sCkG460mtJvHKYd4jQmgocQpElFJWbvWaPH0tWUcjYPRTC87XjZs9wXTlKOgfQxKuAy2
+zuzAgPZrqKrpSlEolbcvs5n8cA5Iz0+Vzgly7NBaN1GmSk1EMo56hJGNAxBB12YQFyfca6OcFPN
gIfpwDKuARvtZs/n/bYuoy4UxVhsCi4FuwWZzivi+MbfF4qRiQgyBTNxNQShfCNmj3MqPgyWmazy
SXRTN2RLloD9D9KewneoXfsvGsxaQ42N6W7CedPAQLtCGHMw5kXdYF8xCTd+yLNrXJa9iracjLrR
ZO/FKrb/6pzV919N6+UWNvM4P9dl/FmSm3RYrahqR6zWWINwG8cSyAWQLzgMNEqHO/8IhjiHV1nG
9YFFBJKLi1Ed2f1y0P0dx47f+VTZrEqlAKYc5XWEB+T8Edy8SxzMifmqOk11fyYK4OUU3/MgaGv5
Pf6xpfKj+3ZYv/JorsW4HAEb3W937Gm2WEumFfVaKsn3F3bXAjT9rn7mUl5OfUyj/ZTZeXG0rjsp
6dmGnEGwsmakwlg8AtdUIRBltk+okiO1Fs5ResGHHsL0YuFM/gt7RcZ/G6UjhAzsdaUMhJte0qBR
AORr3NjsuPC4fpi41LGFXTCNcTtOUcFd8Yir3Dbeh3uZxcXeb/xM6gDyaPaFy4ISDUDXFxVr5Mzb
kNkJUbaEOHwJhByo6U+9XilL4fsudPZNaR9zJTxWhU9voblPYvLkJPuA3UXeEw69i0Mgd1NDOMg7
7DxZvO60S+t8ZtZLJ5T/wyBz57beXTZU6OC3DNOaWdwy03HrMyvWg21LPRa6UeMZ0tSmU7DW7qZ0
fuJ6GVpXx5bqK7tXpOQJi6RHO7hQN3wO4PUSLS3DUeu4X+lSlaQD9Bpb9yqfb5o+aqOsxsvsltZZ
5KVErm0vmS/eKezuR/JiGhb3Wf+JbJY82ODwcet1tD4Gle501OS6l+VI9FqPo018QOjZxjM7lfsE
XfP3cbvMSJqNOeVBPJnG+mM7Kwf3F6BAeGpXztrwCQ2IIBAArdArP2BH23KZEEIvqLI8T4UWdCE4
M9CBO7MJdDneqDYuw0ywZWNu2Xm849Lvpwcu0lDJebYjEi3yS7bG4GBX4JDoH2HuX0pbVhoNqHxb
xowkj6v14Vo/s5WctO5wukFnkz0EUXqrcsBBLUjAVQudIUCoqElRWNxGktB6rvJPncwtHcKBGoAu
Ea3NbYzr99OyKmcXGz4laj4dE6qW7lexcXt6977GobI3j0ef7ZK0yDfsKPFyNmw/b24az2Jphkgb
S5KLO+LPzB1ufjDdndx6xEHE375iPxiNtElQRI9e/GVeUomLxE+fGzUSAULCJoY9vPhmS5jz55Wu
Vb6LVVNuNB+KotHX7Upvpmxn9ADTe/xXKQ4gR2C4UIOT+d7gbb2zk6zUd34pepelgXBKhKxs10Rq
AlFSk4Pl4qTZT7Tx0N/zL1MUPp/V3l/Q2NtfZV8Lzors5g1/6w674IsNdIo4bHUq/NU6lWSSQ+mX
K84IFl8fO2p6q8UPpmRPuX+uvNa4LWB1P4tbksMi5FC+PtJZo+hzBnIQjePkHZysZ6MiqCyjpS1B
ufTHAe78JI65SHzVBNIIGgUfOjV2nwdkitoO1APEwYzVejTRaXJcRn2VnazfeGIg0e6rrmftLlF8
zEzZlNB88n8CPjZrq1MPlBveFn4y1hF7OeLTajucWEwhi6GzitvoG4/CnGeVEyVOmhfwepMaEf1w
ObdjzgwEH7Ydt+6/y8U3Ts8zX8MPrE80OrYf3y/wclUEYKrHBpF7czRLUYdnmeGYiO1kl8ypV5cr
OMpg7fSsx7LenfVpW+PqGAl1yQ3VD5HliVFxIbRhdRQMa+QgSEBvwnlsOsTEnL1RA2U2nF6QNql0
6h7lTZSGmMBANJDdRrcywQ3eUMhRfjLKBIwkFr8Y+ddYIGMUgwVnEjIzw4bjQwP4zcR6R3fTyiee
qDibs1YMcROke9VCSITC5IkHtWPIpifbkkQhby0N5qYz0bNOeRO8XziRoD0KrrLAqgiohcDBMtyz
ydneT6Ij/JInZty0WW2HZUQ2FlUDLzRx2IaNSt+TugawvINCwk9AuxWtiDVr5bQ9N6kt2E5fhTY7
TKawrn/+nXGAHsWoQsOQLKxWfJUJrCS9SzQhoJnsq4592W5/dahbEKv6/Vin4K2Y0owK66Cd0Grg
VHD8SIwUXTyr1fieE3XgdGcopVuhVfRVl00sc/0qTUYdUUUJudwaNCmY931aG0OntWcRNWW46Pha
02kUt21AziBSC1XHqDV3ITWkSbxHGFRnp0XuTu1CsHoTt82IZJIujrmxZ38zYwLgDReZnO/7EUjO
x4jBgr0vxNg1+xcHJeC4R5/CPeEFxrOBydkl3qnpAmwcLMtAoipfVvsUt05G1zXg3s3vuLjJBXuG
1eLCfjcV5ZDj+SyXvNBC9CgFmDesqBm841HRtTMhuD17pSU8PU/5/v3x2xYHuO4ZatfrNtE67HbH
ud/oUumjb9nqYxdv2MxznSo0FOgrBmKeqnazLS9uc3cGEiiiuJGPjTF3twU2OeaOi3kZ/PFBbBs/
ElN/U5ZV2+76a2XVRyYBU5XQ8ua6wD7gEy5tuD67quB9RnWXZ+2Ndmn565ELMjh1pWiKSNcvwwpT
m0lc/4mCQ70tSGggM5bIpoSmsBsym8ohRPp7vaOTCohJMpE/j9E4SY69InekWGP27QHigBbqNd/1
bAorjavV/8JUtCl4e3hON4rd393r8rs6wxFyXD/WLq88hQ7QNg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eo7ztsvbgSYd1KGoylhOwWqcRC93ADsrF+RmXvAplO96rIXnjhzPYctzz+XAywaHSS1JGbblhi+C
CG/Xmr+Viw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VlDPvUjcTGR2bEjy3deiDqszXoduUt60+OFMFcjqa1auPc/2MBM/VWcMZU5YwD+sO6r7Cd2u8kzB
4QzmPkP7uO2zWeFpoq3C/41rplxKCcFvwXJzvHREIG1OnzYb/dPblCiS/+mn2VjAfB8xizQ6Nln/
0idL8DQKgMDcgl63gN8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Z5qUsXx9HJ3+prwOOiNYDTXnWkUAAahQNFkO/c02x1krdZ8WgOiYfdeKqnKAkYdW38T4bPzkQYXm
F9HRN7bup10M5O1nlm6pdyO+0sV6xeX4w+FYkNPaAEVwqHpj07WIEw/ue/EVXX5K2OIBRGh7/H4Q
P/1YmzkwpjoeaA309HPiLuhPj85iLqCcbqI65h/qN7AP0Cw8sPurVTI8asvfzZDURNFtxWWTqSWs
YDduGBX794GzpN6yKoOLlO9m+TqdchGrFtksq+MOHi3FXTk2bB8DuQ1tOwwGC7UV86QeCPa73FUc
osm7ZSxOiAN+kOHPLWKEtbJpRWeajTSUJalVHg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JcY1431frN/YbCQwZBS/ob/VuFxPcfZ9uCReqISX0nCqqpT4EXoXqqwJIy7mLfBpRuS8cBqIBklC
tHbwET69cUCSrkNm3K2/VMAOETKn/w+gzpzjBa3bSHor6jb9uEop3HqOLwiHUEycKwPcaK4IwTM1
mhUqYCQiEK4l0ddH7X4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U3FcEEjLh+ZVARgnFFqe0XZvyPgHip1ElX0vFmo09sq5rJT8+Qdr6xmVCCdsO7nwNQJfKuguSXwX
/iIz3TqU6Tn6yp5h5s9bP804Hk7RRSIidG4CeLzAMXaQ1e5OKAvfM6Zml/A25FdPg/TILkDmwRzv
W7RcVNcdHyRxomufsKZpSr+gVGgB3pmhiINQkpdVB8mx+GhfIqJiGsWlih0hZgR/9shgCikO1MO3
gpbzl6FJmydQlmczjFxBz+oTkQysHKMv8vTZuzxpp1/VDL/Ulr3zYq0oXVLMvwfYA7tAI2khu1nS
uTO//C2snIFFgujZl1JszXkeiMUpQns6O/rXUg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12064)
`protect data_block
pjbi/xQCQxX7daUuB4RG2FXtx+lQjp4/6p0yL2fYmN9pvPur+5XNjtIVjfvScGV2f336OVsgjNWz
j0ql5sY4U3xJRBjTnUuOVVMGIh1a+fXN1Ddh4pamOJd2bC5pEAhq98q1r9LqDZYggrWyDd/kHs+3
1ghs0oHAld1TYip9gk0AJgjfpianf7bA3C2YQOOc0hfr9wJgbqxgZ1ce0G0EjOnC06u34C0UrfRI
eGG5408R5HLykJKTRZikQherv6QL0X1fSrwz0AE3wBvX0AkCKybuoWt/lTRmZx1Ht62Q6HfQkzJL
019avqfnB4YVyUyJhQDd/HiKzM5DHYJtpVSVDj5U2wBqcuzgU4l7S80+x/ejnTkB4IEtCcRc3sKI
bPSScw25RVnK7VjLj53FUT9l/IUE8o2y+lJ/N/JCrDQI3kiMllUxUgh3mKoqkLQQNh0b0u3I4cgl
MHYC0LWu4SwYVlJT9akWmI/Y10n9hoqDOOT6jpMVQ6RjqVjaBOiTWv3M0iG8W6u4r58Jv3P/gJlL
MUxyTy1woIRnCg3weq4kx9uzHX2ZkBHXIT2ngQV5HQax1lLHGfrbipdGZVTQH6n1nrnvw1PwLUEu
XNDDNOAOKwBdPjsMChs9XQJlk7aSAT1nHR+x0rWpsGAM5Eld5Cm9wwv1HKm8Ac6vvdDciTi2I/bQ
zu+ph918RIGMlvixVe6/dZx9HNjBWoUOoUDN0BgAxGxeKPU9I2wfhRKmguCASnk7oR1k7QIGJ6JN
467dxoAWOSSAEmnIlAoBF7CkVTNRX2JVz3jPlEDUEUSrsczYZ/XgXWX9S26LreXIIGIixCBSpdLo
3a2y2VVcfQgD6s2u0Yl//fXwvtQ9Sxl6OYpYv0hIVIiconGn5KVCczTVUxG17wUWigel/431CXeE
yXnn1p+G17kP/1wQaD9mchKiOF3FNQlVHhmDqzA9Y4cnS1CmC8JKmOOPTcHLdysbxDunrDDkqf00
F04wnokYPbeCQDb0OcyNdJV+GIe5hRsRwH7gQWCMbhPsGS4ilJIyfJ7jSrGkp/GiHPiUhA3TiN6P
pojorK5aiLS8g5kvwepUXaijaKRFFxxxOv5R3MRHE0EbRAhqCf+Ndz6KnRnGd2iJTb+Mq0mC7c9U
ca92CnyFZ+FtAvGlEMzlRrt7WxukDMLtbYbKmEpNNoa/KnQrfJTawuaDaFM4X0RE4kwQPfSnVMKH
3VSQFDVA4hCbtx7IV4dZasQdApsZEtx6jk8wWk4JKpsUy5kblcBhpx6tmTlbDtwICYka6e/yVOCa
FbKJiz5SMR/A007kFbCxW8RhxdfgY+0e9Q8TBbT1DcY6CZEIFt2WRfQ1NSvBVbQ8KeMwQgl61+Sg
9LXY3le+lli0rlQc76+Rn7ZFIxDdTEP4CYlEpxDAm+Ux2xM7gTuVmcI/H+okaT420BT52gPNqdNH
XUbKD8X4FnZ18o/teMkkVZ/w909IaEbbo3kudfNQQmVgU9MPvFJ5cNBkpMcO8t/UsAUhH70sxRg3
p2IjBnWI17KDAgW0OLLuYcL3vEmOjJvl4qfVW9AkO51FHx7pFQFQLCglRB14R1ETTs4mA0px8w4J
TCswJPh5Ja9ynMZjlt3VJCRPlRJXRZl4Erzk80znCE27J2lyaXQhFBOJNT+uhYmUx4Ke2JLc7jc2
fehvqjbFhFb9aQTyaV7VJDmmx0I/KInFhHHIuXRbzjjNEk0LwC2fMex7GGxERuUn5La3lTj1Z29S
Pb2vyOeYkVcb+OPJ0bobxh3HA/MGJlIisCKBxD31Z011aaVClUJ6h3mRB0iSW1Z2dqWNjv2Uon/G
UYRdkngxuRahkZ0mJUZsE/7xqr6C3sJ+78fzSRi7bxzp5MLomD3WmiUPTvH+n4/dWffEfZdhrz9Q
tEeLHMogILdlX4oZspgmC/bVvV9BYvgL0Na7gji+9iBOaZGFGKG42iulzKPtdas6kzGSXebbSVGs
+Yw+aM+ziMv3F+0heTHnoxBJ7RziLZpSD1jIjOk6sz5seg5o1+/07oAyJWiFPX2lc+nKbgyFpunf
bZjmHetvSGZ+bdfVDapRNEx1uZCgPIdCtp2U0cIliu6+1mBDpiT/FuF3CBr2CoAqdqLiJ9PBI3/M
w7VtZAGIuBOuhF164rsmJBq2V/ybti+Ewekt0x1pn50X9GurGXshYuRsAmm0Xk3law/QkDtbS9KX
VkkVXcS34K62n7n2GGx2xnLJe7Jt5+0dZvnGdDoifjYvv+uKfdP2n81eAB6431xBtkK7ALGueWDy
OEPeDfpBeYiPyfFR6qOcXk+rMx8gn4HGEE+eopuB7Lb0kxwHhGP1cqLrZd/G/gbpVMpUCzYVcT2B
zcAklT+XAxdhKEIG2lSkVOO3v1qD0enSwyiz5JHlkTVB7Q9CLliE/7PZOlbtEkIZdPFM6y5JAZoN
3M7/IeajRZmkCPMluoQICkE+sJ1+INFmyW0mE/7Tc1FsILwJXEEsmiT2vWtI+ek8TtDJ/z1DTy/S
HziduGggEDk0VTozDIS7BEkyyiSDh4yal7mIwF2GecrUrX0Rg9VZOBQZ6nQohB+zR04Y2yb565o8
E2l4g6asBhaLqNyaaP2QfRqicC+Y7/kyf6zawHJ3AYLR0IGVSY19L0xA5vDTB1rN+9pzCRFNfvAS
dzWpRHn+Ys8YT0T5wVQ6iCqB1DgissHLt9zJjreutIizjXzqQuin61sStVrn3ur0wJwJTfYvxEb+
oZ+wMiVBJ5FhKQEc1tWrkZ6H6eHMK+PxMwN1pzSRIqHMuD0qJefiO0iuqJyGYztP7r/EnpkwILKS
lHu4VNVULPblOtVxIJlzd1pj3KIa7/3JVxGFknZ26i8pmIH5HDKfLA9v9gJMgLhPpXSuzXEPrJOv
m/jw3EYCYwc65Upn79Q5FCcvNkPEinuidVaEQs+aW6QpdC2VJOP3zeOCOBlY5qasPvphz3ACsbtX
LD66h3QjXhEZXI7JA+dQxlKwDiog0B2LvhQfSFh81sXdM7+H8jOlYjY9nWwoHvKvucaOdV02GJL4
Q8lO3yqO0EOTz+oaqbLlWvJftM6aFc4A4zIcoWlSyHDZcop+30XcdZCftAfqf9bnOWIn1ohQk6xZ
eFSMHIezs2sbnEs+8rrSTmldJzZiZ/i9UgC81Fr0dwALnErai2HoegnMSIREvb4+ys9YAhUO/4e1
DXanaeqlw0akC3VT2XQ4BIvmdNdHtDGc9k6VTG4VlgKkVVh4pU303Em2bh23w5DKISMX9Iigq4Bm
4dqnfDaaXV9yVHdFzkoHosXevYWxsZz+NALCM7CVU2JcgV8uINJq0XLRSjNT6mXilya4aGsZxn8i
jRG7di+fC2AZlhcVdzRP5v5ZP1kVVlDF1NIKIN+PxlBK3stGMZJCtaKKJ5I66YCMrqVjB/ZSDKxU
g8c+Ua3+cf89d2XGwpwukFjDt5xMKZmzr9xLsKhj99boLmIU812mTVVlNXALbtEjCFwC0UXRiiE6
yL9P4MeIRwIod05P+4YZR6SVrcIf1E++FdE28Y9xYrngfuFxJ3IZGYIGya0U/AGSZyUm0bq1U8C7
qGUXaM81dPWNUBn6wtQsh5igoyJbGDNE+Ja0P+nFd3jvu5kEexEYJgV0xmsPxgOreYUViPdgXnta
M/d7Y17lhS3SorhKx0X/cj11i7ee2Ersu/bbjlGlOT+LzL2IfaddvpVDFP5DxIlfhngqMeh49C7C
97sWhgEWL32b8qvFMSIiZGVKOvPKRn2nm3VvWE+ofeFXXNak1oYa8L1chBKTKL8kdh9Qr/d98vcT
Ibo0440U7hTT1CLXAMXWpNLRFx/TP0z0NBXT0ZOB58w8Z/wlwT4d6S/FsRY2JDrc6C2D5n6XuIRq
7BS4uw9S4av0Mq9yo856gVlqOd7JAZzAGXJHaRIta5t4t/53z/1h1GLQJQ+3ft3m5X7pA2/Mzxgw
oeGNazpUgnD0qtci5FX7tNPzI76v4o6RqszY/tN7vzbpGti8uts8WSnHoEmmHZ2vfHqpYiURpAGW
+vxp94l1lUYxVgz4fBPWwRPZQ8r1RddZTFXJ2H0eVHAm5qjiqUQA0NTRhtMllFuf5PY+/fvT9WOC
x6fSr/3bMYMz5LGpu7vGXhgFZfi/BD6DzZ/Wmi0vLGfbQCZiZBAlZfsvfHME/eXgdgHlTTs0qO43
kEjlHf/0sWzIXWEmpI0x/WqnfnLGatgiDQTbmcDxgIng2s7vI7FUhTqequ5vllmUssrbJa1kpMeY
D0mW8xtEAvWuDIVrcPjVHHuUTwwy8pcsuMUb9XIPzk/6agwwcmzpcWTw2XxQu/7fknb2RdLMffIV
ZThyI9AgdPiViHeiWHa5j8HLdU+ovZYIUengWLQTBLtUASPljXKHxOu2ZlDbyeHpzMrIYJFErCxJ
TUSBGp9wmTcf9kIdf3s1P6yf0x/U3t6wz6gIe3JWFxUbn0OJ+iG+4NokvAcGW9nczhnkTRm+86zT
ktZX7WG0IOvJ2y9qsrmvTn1/2LZ+Pi64RxJBlt5byfctA+gjd98455igwuuLW50axXWfHLywA7Wx
JYup90umZpiEazNbulMYkQHijTwzzwypL3UG2olW9Tz/P5ecGyEBRIYN+hpZCAQkjHImBtcNmjds
K0/oqKblQhYihXXymwhYwigATajOi4zfrqF8zGj0BAo1Pl5/SKWDUjkDPT7kvAOzFbySYXhMFgBW
/NzZpz+1XqzX3tjWF0CDtXCP+NulbxIN53I456WMzqPWO08xfGxVcm9X1GMvE5r91xneCqmZk/3s
5EL1emxKT4zeSft7ZCwCPZF5mZVRpL4Ev5QFKU7Q3sqqHYWF3YAUh+kDjfO16oGL9Mvq2Y7Rv3lE
EDY17JEtJvqdIdEpzi8rL5g+oPMAPocoF9KgnasoIkEfqPFeZcBQjTQYg2dg7Dol7KBdea5CW000
D2Ra2sq+ob69YMjhwGAFEFKmwlzxq/9lyjzykwVi+ZhChsZvIpF+13nTyBC+rUAJe0+lpoXwtB4B
OuWhQtghdJ0u4BVoBSb2rbJI9YknTwMSogFPWw4KzfcW1mPeMTpCaUD5aIcnyOOgNHRxgheX3lC4
r2Gjx1sZoc9sZvgAkRs/0CbsOSqrmpthIBbOfbdCYDp+imaQqU4/DKwWQJ3AuL1w41QDjP8S6DG/
xwccHuUhC1a4HLVMafGyfA3jepWUaID9wRFF1o3roLCyzT9u6vWJEd3+EVbK7lGxlAiWlwR35IRz
rIM+4l83i4N/HEtxvPCN9iPmrmXyWvOlGKx04nUyTNQsX7A+QpGddN4dgenH6g7dNfzjTGjqUyXC
KINx6MJjDaqbQMo0XU0uznYBn8woQXswfxCXuIjscrbnf+6PMKM4R6z77txzGHNFNdud+A87gnwy
BqNcUhnpdCcxyVPp+mTQVMyPznneOBfOZPcpT9wbQBu2gFf5psp9CGWp9EGNcMyTzLZ5rjFJL/iD
Phus6N6rLZeM/agKQeCM/b+iw51KMLbpUZZO/yCkINFNVb6/PjRrqcjJPWBWXlygCSt2RkMCXy2z
XnXA/pXtol1zQNBaAG60Q1zFNdnxSUNaIWpuTBvJNlCp9I6NmhVUcmf/np+JZp5GzEq0sI51MzGe
Xi3RHQ23+6zEbSNiDqZN0BktupaVZqauRkVWnSQQKzihKpiIEyrjOTGNgRDCFHhVILPI2qWP8GT4
agoGTeBxCnuyOuqF3+eVao0KHdTfi6QaT6i2MqkzNOlcMrOiFZ0SkF/vJvEj5XraLjz/Dig0wSlx
k6YHcEg8kawk4M2VYK4xm9+MEt+MaSxtZRAj6iiqDn2tNNq3f4HUManEWmfa1uxKBjR3fLebPYC4
PO0OEPczILvlbmjuywJwpavSmAi2GXksTYUq8JbM4Gv4uWYNrorBvUZe3zHhd3tmlvOnG0ehfmDX
UJlipWPvOUw10T7M3H1pc2hTwZyZoVT1iR8L+qmE6wjBZ8VvpX1ySQbc3liQq2I3psB6fF5hwlMq
7Vmz8cAphOx2ylE260y7DJngwAp6bIaNhFEDx3YY5XgrYs/BsVBi3STmmtLhpMTDr3c1bCPSoJGU
LEEFmpIYJZAhlNJlp+psb2pEcHum+SlfVkKQJQl5SDjfwE0wD4J3XXoTMitF3jn5Op/ZMcCJGaYS
ZolnaBMlvLOAJKBBabRBx0qLteO7wpMiRPkxoCR7IsX1Dx4tZAwVm8qq88lr+ifLlf7/T6V72ahX
SvZU8nuzSwdEcszi1mU1rHQ5EmMZPYp2/MuqlHlcpkiRps3PLs5XHP7NFgURiDTpXddwDpYrebxI
LqxITOgumDkGmgpCZuE+EtjeW6qnOL6b/nCzUou6IA/9rxmI3A4WMdQQMmjwpqAv+ODTPS0GPmvq
tPs2DE//02PzeHG4Ihi9Hhf93dspotbOqKOqI2xhquH+MrCtbBTnDMz8JwidHtNOKCtAYozSIcD2
nonCSjaTiN6pkxcTAtmOyJEb1OHmf+dXplKlzeuDXQubi52Tzjsv/qhrpUvV+22rfslbfwnD3PYL
sMrOSDRUNJOpQyajkdBpamjjQrErSnn9RGJaWTSZfQNDBTeyBaDAL+ysl8Y5pBsr4zUDL42cXMqD
31XBQ0fbQvhkCcTX3zjkdSg0Q4+1dTw3SXxptWm4LLbkOSxu5vqDHCQa8lkmwUjb/gHD1AZLnz51
kiIwFacQP3nCw/CzpZ9F+DA/sMF0KHCxLM9qyQnZKxeOrZyC7cbfM9nTwqhvix7iu5/iX0Hx9SLc
31I+e52KEUfnIRnTEk7heNZxSixrLF+Dth7crAn8fAyQVG1c93hUVk537WjulKhyEC7Dxn1QIdtg
Jn4ufESMehogvIEDzsP6xeCbb06nHShtze2C266EgBMvwXpbPWLuRtwSKXFHGbxyf3avnba/2jvz
H7OzcBFEEdH7tmp0Jt5LPMxZ6CiBfvkw5nald7ovW/XCaGaucYE1KsX6k6eHBu2Mfdp4kOLoAoCC
qHlbJgy2BCy7JPILNRL+kSwetc/gSL0mw14xGLxAQzUH7OI5jNOP1wtQVm6I4jR22IOmhh4mR/wT
daWabITu/4jCpVRVoP6tvCYqfAGFMLEEDUxNZnOrsqQ7HB3BoWdQSE0EbrVqkwRdEzWRAgrAN9bD
2UJkQUk1K9eKyH0mMF0+jUU0GUHGhSqDVvhjeTB591/CehGinNij+w2uW1XRiGE7W0MY5jBp46pj
95C+VkCtx6Y4gwrMxSzc4brzdAnG5Weo8js/HEu9lTc+ezPRL0SGFgYtrS7uqkf4GLLsa1YvBAy/
mC44Pc9ZvKpPEe/k0dKCRZplObHACL5KGi0jDfT+PnMvSDN8yCWqHOKJtg/vxBtLB/p9c1MJ3RIy
tTQH2QbHsOqiVemgZUaBgW+fTw+bS7qxMVz92ujdZUKqI+THhMud76uvcHLJIj5tfiuppa9ewWmQ
wPiq1EckuPSxrXophTmtOdIFQhsyf+bzND4QQyqxSllb8fpd4hMlCmbcz01Idc36HlDIj3G57OiJ
G+gS4NneiAxoLxaoIUl3AkI6d7qCj7ujfJiKdyQB3RMyODJovLN/Zz6Wbv/x7Cx5u4ARvuYcHgwb
uumm7pzTFOOxv3fqmwxj5U3199QB6lpRB9wBs/3NWGoftBFYWi6cDIc5cG2UEa2ET4HdqaKfWYUu
YBzaZoK+grgoxlTyznT17/5NZ/aaJZhGTM32bMpFcQO9h+4bmAUcLTCeCT6UBnNirR1X4uJvcKAv
fRxFFsaJYnnlRFqq0jU5gQaTb1s847c3M93CYWshdGJDEu5XvBVIQGwAq/xe3imuXOFdUl003UF8
49o/8P4M+bwIhyLQlQPqm0D1LwCrd49sLGROc+XBqwFkOZ6Fp4vMh8UwyyYsqqvbp3NOo50zszp+
HlxjMrvuMejDrwCw0306enbLRFt6WrXws27I+1wVzRVxkAuPuJ4+8d9tdmhSef3OdVmcm+PGdqPc
bWGwT8CaZey+bxdmLLHyhA8hdTuGmH7dXxvI7ajinCQzwEuEfc8Mg/R9JA73oPxJs5HLijZweKN4
i/C3EfGmbMPSZ1RMQgz2x31t2N+gxqQhLvKfS6obQGA8zTLZ49ZXtp9PX3Qlx22+zopa01nozVak
XLQvNuj9SuB+GF/H9ZXEanXLnHkgeJqjoEt9CqEOUGT6ZbF2imDbuAVmo3ilp0TNXP2cc6IlVFB1
TesByGLtJbzdt2X2Wmuw3DEJJjgqQVMu4DZGrJAhJ8X7INBEDq6mFaXo01sAVoAbcBFs5nDDSKBt
+xvqSbZZaD90E09Do1T0uZBPrS16ElIR4kRoqplA0pe9lMKIMeVo9FEjx5M85k7bklC3RPADaATU
ynSTStGCdCI1kU6Mdg8FPlzn6GT5THQhCEePhOf1RTtHBX8w1+HVY1iAtqqVDFcQvb4RRtbwxszF
5h9BVNOCVZAUPj8ZxyUKWMrd4Mb/Gq/6564Ojc4RQV6Ony9888Du7Ue2VwXSPb+NQtTbvAYh5ceE
8Xpedq/nJs4k+KT88qnXYT/UCL1Kz9n/6Ys6MNqwV3fD5H+sq7uT7wBWrnAZglQboskjMH2JXeXq
NreurugYF1kh4WYqg/8vCYr8rgeAy28ctWxLXwfnp0L0dGjR0TycCBHlLNK+tTexRw43L127/VHE
d+SkwSoNvALUcRTIzRabanJ8UwuZZxwmSGMt2On3DKgpA6T4tZ2qrcn38mZyX1+IcqhEDX1CNgAX
fKtgwxbGXCfIcK2MsNF4aOcH7lbDuc8eV45GJReTac+zgpfZ0s4d2ABp7HL4FHs6uJxSC8AFDisv
qTInW3QSDmc9olG1FDwdsTfyuPUFT3A73XznlFJdDbUK5LzGbwGg6o5Izw/I8auLULGvqF+sKohj
IdKubDOQuXAgu4SzkDFqbMkYwGfRdrMvusjwdI3r6iDROsXHptzRUYGqVYIxh4QnWu96w2naubAe
fK78aNCQz0YhNPXuaiUeSgbDgi9cEg/bWBEzOe7BdAzSbgDF7uazZRXC9xN0/EEnETXjzwhcZicf
Z6TCrngpIrORw502nb91t0k/9JEiJY+XHwawhtSf/Bx8a492Hmn76vlWi5vn/XiaZ6v73oFb3GYh
vUs70AgyXbro8yyKti1b8Om8kbibGxsGx6l7byg0bg4FEVJZ4AHv3+M2mfcOorZRDhJTZBSm9XZu
BBqqYRW/ctPab963iO/jIWY5G+rpi/EjxrnKGOsTOaTh2P9/9N5jc/zwdH98TftBnctZ5ox6eN6t
c0+I4K0rGMaImPx7Y37HTHq+eYUbIsIRki9t2W+sxRR9nTBQtd7FS4Zhz/cAOA++8y6/lGiEOiEc
Yd2a4BHvFYLhtX3SL3v+D4rTgv9yVtCnZHiR44QdyzlcF5A0yzPN3JWx2OnF5282akPzY+X/yhTp
NLP00hVYYurVwz57aP9W/F72XmuDbdBGPvcfKNUZCbrR2jVaZK1urCDfrnMZLkoqkv6Akq4bXJ9s
4LeGxVaRS3Qz4R4FWHD2/FEm+eK4+eHE/Xm6Aas8ypaqxqzC35cNrEDs6FqfYEPAl8NFpxtnKZOs
3mT6L/BJWqjJdz+ZA0OBGTQu76k2puvLlaTU7y7ldE0qk21kfSmzUdAtSnqwDZbwuSmfaVn7bS+6
tpsqb40LUNLaZl7SaIEUhYqUO7fixNH/dao3buP+NxnWBS3p9gCXEatzD0OTRJkvCgi8Pi1q+Sxe
JUyJkPfYlLHoyO5u2B5P4Espg036DiLFcYPxZS+uuA55YG/dIvIr3e06m5Qkb5njCttDA4bSnMyL
w/pEGdd1WYEQtX7EyD0zaiCwd+WSwRvbtmdy7v5USsXN3GTNSOfNTtozjNTJaqfhVbkN1tOV5tCk
wHDAI+mdbI5Q7bUipXX7r7tpNkiu221gGjFg8cBmaWS6cQw74zEs9Pn5czmjYU5OK6cnRvs+zGNA
aS5YRADde5Lw16RC8+20i5rnBc25mHO3hrXqvtuGVECy+Y+1/JvQu2l81YowjM2UA9Hmjq3ugPsy
33yj7Jw4LG8Tw3/lczBH8XMIoTXMdh299mvUAGyZqJwDlcrIem39MX6uPvRhTEIBGidMkJdmJY5f
2I7ugooAHMrJRRvW5OgZ3IpD8HrjR9qZPYaEcXQgi5Rz7n4h8FrtSg4FP5yF7baEjPAuGI/iF0Q9
ye0jlEnvFxvU7prDZBg7bed4yqg2W1SbnFrRd+7vrmjIauUYykfxVsV2h/DfYyczbB2zRagKvKU2
4JF/z8lm1XnUkANqQWhTJEd/U1EjNTTMRtiWPnUQr9jn0XMJxRq25fNKmrL03ZSIJS6Q3xH1e0C7
Ndes2uJTS3cIeX0m/6AeFrWPdm+fF4F641UR0GF8JsX87bIJFbwuzlKbdwiEQ94MaSmTN+Zs3xjE
TIdt5D2+KpPImW73E1Zx9djeamZbW5+LuvPiLdcNgPLb/n0xjO8pKyWWXWnfRB1Ina/tpSfK/JyH
woeoTVdBeKvUQl88XRFhsdb83VLflb0RGCqljUUYx4OK1dxbK0oycpL48B73XgVeJhzbRCFvu0xr
cfxbBd6dbOsdw6q2OcENv7IhD2juzpaUSZ9qUHNO0OGB3K6SEcwKuucF3Nkt+98JgBFvhtGKI1Sf
z8UYN4HedO+274fHQQGQJ6rs0nPg1UArE1UgP/sLW5l7hA37zIXSNw5auBR1g3bIER38tVgOlROz
N+N2BB/1/FX6jfxqHSplRRMMMUXS0vwwerjQiqteWCP3wLB1dZU4YlEY0EzxclcW7P4uMrTfWNTW
FYG2Hp6TFnbLcCcgXFiKW1krROfM4QyqN+iVF43TgGFDsF92gg62nL6P6pqTRmWRQzU57f5izONI
2ejulFapn4TjX0cylV6ILP81czGnMrHTVvMVyOSCK3gBQTtQ4b1bVOC6RBDbGBUmEc+gYpkqxXFZ
YWJedq3Zu3OaVLr8A3ZYko9QVm+kLvOeRAvULWEWoXmoyh+Tvn/P/U5yL05nZ2NPFjiiUtS36DxP
xWvXxBDa2bc8vRMh+Mg+9+nvwqg/2T92dB8YXyJ0FMLnmzIJxU3iybURGKycQvpMqhDDr9C9u99b
14IJPy2PofOwtiozb4FaLGFEbBS1IsVT6p9951eFQTfZR1wagKxsrOPbViMom24ywLjWv0Q/lB2r
eBxZtBaFSZi5zZWODNeiouO8TCUdVSStJxDE8+JxesCIQJvrW1HjrLyZdSdmq3PnlrNWCR3Z6UHG
LhUjKlFlyXJGyZykyY/YZcLyPHVYgHvPR5eOsoR0t52ftRzfZZtiJNuI7+8aCpT8SiuTXKFXwMxW
1TtfRgaalivz4gOKQXNIzyFg7MUziEsSIHvEuYqie4Il962Z+EhmlP+6RUbahOSAFQuQzg087eqv
A3wv+SizE+pJvS2UCoSPYOV7iE4Yzd6uXqK7QwLLeEvp4DMEvm21+brl5dLd/7GxJ9I/tfWKgsL1
RS2alwvidVvw0htDCoZIumObAroc7Kp3hYqD5/hBj8eHAWoTwY25tmvNfgA2yCnyBrgbyckKblV6
eWjH2AJjGoz4E6nOlFgUpNfsfy86aygJB7lhxOA093Y+onUFSm+VEu0BdLkGfwpRtJJl6gOJFg+p
X36/sEZlPgWQY4s0PP8YvU3lF8M+/FXmkMtQOgnLlLCR27hPns1ecYfhd9iwni1hG45/K1Gm6dkg
ffYU2Ej0b2LAaE8d3kB1gNKEypixePTlNGe8sMsK1sHOkbgF4Rfwmb5wU5ClG3jAo/uas5jm2D9y
zbqTB2i0QDFybsXJAK1OJefVghQ12vKH+S5Eew6kC7OPFqqNnM0+9byiADj7UEPuMAocZWF8LcLh
yqwG884vuSCPdoQCmQbhsTSAjxHdDhfFfByfdF0dccMewUq9RUqrkMUTGzdoGew81rKRk91JFQyi
X+8D3LcCzIQG89OR3moTRXuYVqlTAML7bcII4PeBCCwW4kom7nXcGE/mCNp1xbDPkn8lCZdjQR0P
4J9eEjwfvTe1U2MOVme7jQkDddwaWUW/WJyINWD3UBtjhq32jbSNoMkAosEC5NC3StARzqaC1fXt
tX8j3bOpELHDUEOTHLDkkeu0eVne0CG9iYU4SP0zLXS8IcBMdIN3iF8ECHReD845zAv5aunVOomj
eIT+L62ajJzX/4H1l1tiK3Ae4bDZQd9rWde2I7vIuJWYS9g19XAMe6oOmO6AzWAIOr/huw9QXJqX
Olte6VYYQnnsOvrHhJrYNCySs9Mis3Ub3FbotQaf02BWVOQXyTb2IKkA+yyCdQ1NB4RoJ+IDmxEe
t5Im3EMI6xjumpNNr6Ut6VAXhW0NAKToH+iq3SmKCQhWpym+vYIZOQAVcCEYtzdxqRGWwmUI/DsA
jnlOOGjCXB4VvoSPStKRd5atlro3tsmGdW4q+7jjhb5qWN0IShUG/6QoEQ+PRKh4EztEkSkuMqpD
kQYhZas1VA4dUkU/uxYtaUo9waOJn2jSjHdsbl/qvzDm3dtAeckMY3oB+WKMLka1Bpy0blstZqYP
sZE8puLgcAN9WnL6oBnP/agB9RCIsybJO9IMRUnbW0bRHyUBDFeExSWxu1mefP12wBUWcC1oq37f
u/QCYsUnxA8Wm8d5CnktIrpU/UpR6q4jFZ7scCRxtGN7x0QYVnqRdtgXmyAHiNNMdHKSF9Mh2xeD
wYTSoU2v+we7dPV+QgxyHo2np5140WuUB74W1xh7L0IvHZHyjdPOuLQSJr39ZnVqYol5UmJAxNun
Mrp3nzSxwtz6KyqoDupRWIeTXj+fwMNjK9Y+cuoNOm8bqH1ol+POPt+IYjpctd/5/Kp41vfUZN/Y
h6a05AVuezDpRWzeAYavNKY3LXlbplqhicoeUIV/sDTd516YN0F8iZA6EE0A6U/JJuhMPYuYA6GN
pB2ftXt+DwIjmNd726k5fNmxyjuMl/EhQgKEdIxZetcbE2TCFImVgsTQpSazV83OS+RiDQnqxtiX
DL4yyRzBYmZkqh3QBnYuzo8cNASgGBOEDHRWGYU7fSLCFDXxX3xtWis2w8pgrWTGjVh2lVuGS7lC
UbGqJagnwoI/8z+UZzmKx9BfaKtN1V9/0lIuoAU5CMtMMfJ1A9q3Fn0wqaCsqU+izBHgdTa1mDaa
68N4dHhTvw2CwP3bz2s/oGbtU3Sbsmqb3/ci6EFzfvmop5l3XhKEa0IPDsDJg74OqPW0dMMhV69u
OKwdSNHSH0PkeI0csIoa2MIgTtxxn5rwDFHju80Qfjj8lvY4PzzFeXWIKk4fBvEh1yCJqZj9GOXp
kwPIVoJ2sCkG460mtJvHKYd4jQmgocQpElFJWbvWaPH0tWUcjYPRTC87XjZs9wXTlKOgfQxKuAy2
+zuzAgPZrqKrpSlEolbcvs5n8cA5Iz0+Vzgly7NBaN1GmSk1EMo56hJGNAxBB12YQFyfca6OcFPN
gIfpwDKuARvtZs/n/bYuoy4UxVhsCi4FuwWZzivi+MbfF4qRiQgyBTNxNQShfCNmj3MqPgyWmazy
SXRTN2RLloD9D9KewneoXfsvGsxaQ42N6W7CedPAQLtCGHMw5kXdYF8xCTd+yLNrXJa9iracjLrR
ZO/FKrb/6pzV919N6+UWNvM4P9dl/FmSm3RYrahqR6zWWINwG8cSyAWQLzgMNEqHO/8IhjiHV1nG
9YFFBJKLi1Ed2f1y0P0dx47f+VTZrEqlAKYc5XWEB+T8Edy8SxzMifmqOk11fyYK4OUU3/MgaGv5
Pf6xpfKj+3ZYv/JorsW4HAEb3W937Gm2WEumFfVaKsn3F3bXAjT9rn7mUl5OfUyj/ZTZeXG0rjsp
6dmGnEGwsmakwlg8AtdUIRBltk+okiO1Fs5ResGHHsL0YuFM/gt7RcZ/G6UjhAzsdaUMhJte0qBR
AORr3NjsuPC4fpi41LGFXTCNcTtOUcFd8Yir3Dbeh3uZxcXeb/xM6gDyaPaFy4ISDUDXFxVr5Mzb
kNkJUbaEOHwJhByo6U+9XilL4fsudPZNaR9zJTxWhU9voblPYvLkJPuA3UXeEw69i0Mgd1NDOMg7
7DxZvO60S+t8ZtZLJ5T/wyBz57beXTZU6OC3DNOaWdwy03HrMyvWg21LPRa6UeMZ0tSmU7DW7qZ0
fuJ6GVpXx5bqK7tXpOQJi6RHO7hQN3wO4PUSLS3DUeu4X+lSlaQD9Bpb9yqfb5o+aqOsxsvsltZZ
5KVErm0vmS/eKezuR/JiGhb3Wf+JbJY82ODwcet1tD4Gle501OS6l+VI9FqPo018QOjZxjM7lfsE
XfP3cbvMSJqNOeVBPJnG+mM7Kwf3F6BAeGpXztrwCQ2IIBAArdArP2BH23KZEEIvqLI8T4UWdCE4
M9CBO7MJdDneqDYuw0ywZWNu2Xm849Lvpwcu0lDJebYjEi3yS7bG4GBX4JDoH2HuX0pbVhoNqHxb
xowkj6v14Vo/s5WctO5wukFnkz0EUXqrcsBBLUjAVQudIUCoqElRWNxGktB6rvJPncwtHcKBGoAu
Ea3NbYzr99OyKmcXGz4laj4dE6qW7lexcXt6977GobI3j0ef7ZK0yDfsKPFyNmw/b24az2Jphkgb
S5KLO+LPzB1ufjDdndx6xEHE375iPxiNtElQRI9e/GVeUomLxE+fGzUSAULCJoY9vPhmS5jz55Wu
Vb6LVVNuNB+KotHX7Upvpmxn9ADTe/xXKQ4gR2C4UIOT+d7gbb2zk6zUd34pepelgXBKhKxs10Rq
AlFSk4Pl4qTZT7Tx0N/zL1MUPp/V3l/Q2NtfZV8Lzors5g1/6w674IsNdIo4bHUq/NU6lWSSQ+mX
K84IFl8fO2p6q8UPpmRPuX+uvNa4LWB1P4tbksMi5FC+PtJZo+hzBnIQjePkHZysZ6MiqCyjpS1B
ufTHAe78JI65SHzVBNIIGgUfOjV2nwdkitoO1APEwYzVejTRaXJcRn2VnazfeGIg0e6rrmftLlF8
zEzZlNB88n8CPjZrq1MPlBveFn4y1hF7OeLTajucWEwhi6GzitvoG4/CnGeVEyVOmhfwepMaEf1w
ObdjzgwEH7Ydt+6/y8U3Ts8zX8MPrE80OrYf3y/wclUEYKrHBpF7czRLUYdnmeGYiO1kl8ypV5cr
OMpg7fSsx7LenfVpW+PqGAl1yQ3VD5HliVFxIbRhdRQMa+QgSEBvwnlsOsTEnL1RA2U2nF6QNql0
6h7lTZSGmMBANJDdRrcywQ3eUMhRfjLKBIwkFr8Y+ddYIGMUgwVnEjIzw4bjQwP4zcR6R3fTyiee
qDibs1YMcROke9VCSITC5IkHtWPIpifbkkQhby0N5qYz0bNOeRO8XziRoD0KrrLAqgiohcDBMtyz
ydneT6Ij/JInZty0WW2HZUQ2FlUDLzRx2IaNSt+TugawvINCwk9AuxWtiDVr5bQ9N6kt2E5fhTY7
TKawrn/+nXGAHsWoQsOQLKxWfJUJrCS9SzQhoJnsq4592W5/dahbEKv6/Vin4K2Y0owK66Cd0Grg
VHD8SIwUXTyr1fieE3XgdGcopVuhVfRVl00sc/0qTUYdUUUJudwaNCmY931aG0OntWcRNWW46Pha
02kUt21AziBSC1XHqDV3ITWkSbxHGFRnp0XuTu1CsHoTt82IZJIujrmxZ38zYwLgDReZnO/7EUjO
x4jBgr0vxNg1+xcHJeC4R5/CPeEFxrOBydkl3qnpAmwcLMtAoipfVvsUt05G1zXg3s3vuLjJBXuG
1eLCfjcV5ZDj+SyXvNBC9CgFmDesqBm841HRtTMhuD17pSU8PU/5/v3x2xYHuO4ZatfrNtE67HbH
ud/oUumjb9nqYxdv2MxznSo0FOgrBmKeqnazLS9uc3cGEiiiuJGPjTF3twU2OeaOi3kZ/PFBbBs/
ElN/U5ZV2+76a2XVRyYBU5XQ8ua6wD7gEy5tuD67quB9RnWXZ+2Ndmn565ELMjh1pWiKSNcvwwpT
m0lc/4mCQ70tSGggM5bIpoSmsBsym8ohRPp7vaOTCohJMpE/j9E4SY69InekWGP27QHigBbqNd/1
bAorjavV/8JUtCl4e3hON4rd393r8rs6wxFyXD/WLq88hQ7QNg==
`protect end_protected
|
--------------------------------------------------------------------------------
-- wpa2_main.vhd
-- Master file, starting at PBKDF2 and cascading down
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity wpa2_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
start_i : in std_ulogic;
ssid_dat_i : in ssid_data;
data_dat_i : in packet_data;
anonce_dat : in nonce_data;
cnonce_dat : in nonce_data;
amac_dat : in mac_data;
cmac_dat : in mac_data;
mk_initial : in mk_data;
mk_end : in mk_data;
mk_dat_o : out mk_data;
mk_valid_o : out std_ulogic;
wpa2_complete_o : out std_ulogic
);
end wpa2_main;
architecture RTL of wpa2_main is
-- Fixed input format for benchmarking
-- Generates sample passwords of ten ascii digits, 0-f
component gen_tenhex
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
start_i : in std_ulogic;
start_val_i : in mk_data;
end_val_i : in mk_data;
complete_o : out std_ulogic;
dat_mk_o : out mk_data
);
end component;
component pbkdf2_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
mk_i : in mk_data;
ssid_i : in ssid_data;
dat_o : out w_output;
valid_o : out std_ulogic
);
end component;
component wpa2_compare_test
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
mk_dat_i : in mk_data;
data_dat_i : in w_input;
pke_dat_i : in w_input;
mic_dat_i : in w_input;
pmk_dat_o : out pmk_data;
pmk_valid_o : out std_ulogic
);
end component;
signal w: w_input;
signal w_temp: w_input;
--signal mk_init_load: std_ulogic;
signal mk: mk_data;
signal pmk: pmk_data;
--signal i : integer range 0 to 4;
signal gen_complete: std_ulogic := '0';
signal comp_complete: std_ulogic := '0';
signal running: std_ulogic := '0';
signal load_gen: std_ulogic := '0';
signal start_gen: std_ulogic := '0';
signal pbkdf_valid : std_ulogic;
signal pbkdf_load : std_ulogic := '0';
signal pbkdf_mk : mk_data;
signal pbkdf_ssid : ssid_data;
signal pbkdf_dat : w_output;
begin
gen1: gen_tenhex port map (clk_i,rst_i,load_gen,start_gen,mk_initial,mk_end,gen_complete,mk);
pbkdf2: pbkdf2_main port map (clk_i,rst_i, pbkdf_load, pbkdf_mk, pbkdf_ssid, pbkdf_dat, pbkdf_valid);
comp1: wpa2_compare_test port map (clk_i,rst_i,mk,w,w,w,pmk,comp_complete);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
wpa2_complete_o <= '0';
running <= '0';
--mk_init_load <= '1';
else
if start_i = '1' then
running <= '1';
load_gen <= '1';
elsif load_gen = '1' then
load_gen <= '0';
start_gen <= '1';
else
start_gen <= '0';
end if;
--mk_init_load <= '0';
if gen_complete = '1' or comp_complete = '1' then
wpa2_complete_o <= '1';
running <= '0';
else
wpa2_complete_o <= '0';
end if;
end if;
end if;
end process;
mk_valid_o <= comp_complete;
end RTL; |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests for various subprogram features.
library ieee;
use ieee.std_logic_1164.all;
-- tests functions defined in packages
package subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector;
end subprogram_pkg;
package body subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector is
variable output_word : std_logic_vector(7 downto 0);
begin
for i in 7 downto 0 loop
output_word(i) := input_word(7 - i);
end loop;
return output_word;
end function;
end subprogram_pkg;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests for various subprogram features.
library ieee;
use ieee.std_logic_1164.all;
-- tests functions defined in packages
package subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector;
end subprogram_pkg;
package body subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector is
variable output_word : std_logic_vector(7 downto 0);
begin
for i in 7 downto 0 loop
output_word(i) := input_word(7 - i);
end loop;
return output_word;
end function;
end subprogram_pkg;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests for various subprogram features.
library ieee;
use ieee.std_logic_1164.all;
-- tests functions defined in packages
package subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector;
end subprogram_pkg;
package body subprogram_pkg is
function reverse(input_word : std_logic_vector(7 downto 0))
return std_logic_vector is
variable output_word : std_logic_vector(7 downto 0);
begin
for i in 7 downto 0 loop
output_word(i) := input_word(7 - i);
end loop;
return output_word;
end function;
end subprogram_pkg;
|
entity repro is
end repro;
architecture behav of repro is
signal a, i, r : bit;
begin
process (all)
begin
r <= a when i = '0' else not a;
end process;
process
begin
i <= '0';
a <= '1';
wait for 1 ns;
assert r = '1' severity failure;
i <= '0';
a <= '0';
wait for 1 ns;
assert r = '0' severity failure;
i <= '1';
a <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1624.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01624pkg is
return true; -- illegal in package spec
end c08s12b00x00p03n01i01624pkg;
ENTITY c08s12b00x00p03n01i01624ent IS
END c08s12b00x00p03n01i01624ent;
ARCHITECTURE c08s12b00x00p03n01i01624arch OF c08s12b00x00p03n01i01624ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01624 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1624.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01624pkg is
return true; -- illegal in package spec
end c08s12b00x00p03n01i01624pkg;
ENTITY c08s12b00x00p03n01i01624ent IS
END c08s12b00x00p03n01i01624ent;
ARCHITECTURE c08s12b00x00p03n01i01624arch OF c08s12b00x00p03n01i01624ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01624 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1624.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01624pkg is
return true; -- illegal in package spec
end c08s12b00x00p03n01i01624pkg;
ENTITY c08s12b00x00p03n01i01624ent IS
END c08s12b00x00p03n01i01624ent;
ARCHITECTURE c08s12b00x00p03n01i01624arch OF c08s12b00x00p03n01i01624ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01624 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01624arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
architecture rtl of madd_seq_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
overflow : std_ulogic;
end record;
signal c : comb_type;
type stage_type is record
overflow : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
end record;
constant stage_x : stage_type := (
overflow => 'X',
result => (others => 'X')
);
type pipe_type is array(latency-1 downto 0) of stage_type;
type reg_type is record
status : std_ulogic_vector(latency-1 downto 0);
pipe : pipe_type;
end record;
constant reg_x : reg_type := (
status => (others => 'X'),
pipe => (others => stage_x)
);
signal r, r_next : reg_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
c.overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
c.result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
status_latency_gt_1 : if latency > 1 generate
r_next.status(latency-1) <= (r.status(latency-1) or r.status(latency-2)) and not en;
status_latency_gt_2 : if latency > 2 generate
status_loop : for n in latency-2 downto 1 generate
r_next.status(n) <= r.status(n-1) and not en;
end generate;
end generate;
r_next.status(0) <= en;
end generate;
status_latency_eq_1 : if latency = 1 generate
r_next.status(0) <= r.status(0) or en;
end generate;
with en select
r_next.pipe(0) <= r.pipe(0) when '0',
(overflow => c.overflow,
result => c.result
) when '1',
stage_x when others;
pipe_loop : for n in latency-1 downto 1 generate
with en select
r_next.pipe(n) <= r.pipe(n-1) when '0',
stage_x when others;
end generate;
valid <= r.status(latency-1);
result <= r.pipe(latency-1).result;
overflow <= r.pipe(latency-1).overflow;
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Dilate_0_0_1080_1920_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_V_full_n : IN STD_LOGIC;
p_dst_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_Dilate_0_0_1080_1920_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_pp0_stg0_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st12_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_const_lv11_7FD : STD_LOGIC_VECTOR (10 downto 0) := "11111111101";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv12_FFC : STD_LOGIC_VECTOR (11 downto 0) := "111111111100";
constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv12_FFB : STD_LOGIC_VECTOR (11 downto 0) := "111111111011";
constant ap_const_lv12_FFA : STD_LOGIC_VECTOR (11 downto 0) := "111111111010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_24 : BOOLEAN;
signal p_025_0_i_i_reg_263 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_48 : BOOLEAN;
signal heightloop_fu_324_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal heightloop_reg_1240 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_fu_330_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_reg_1245 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_cast_fu_342_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_14_cast_reg_1250 : STD_LOGIC_VECTOR (11 downto 0);
signal p_neg226_i_i_cast_fu_350_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal p_neg226_i_i_cast_reg_1255 : STD_LOGIC_VECTOR (1 downto 0);
signal ref_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_reg_1261 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_cast_fu_362_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ref_cast_reg_1267 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_2_i_fu_366_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i_reg_1272 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i1_fu_376_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_2_i1_reg_1277 : STD_LOGIC_VECTOR (1 downto 0);
signal i_V_fu_391_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_1286 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_76 : BOOLEAN;
signal tmp_17_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_1291 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_1296 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_1301 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_104_reg_1306 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_105_fu_457_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_105_reg_1310 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_fu_473_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_reg_1316 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i1_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i1_reg_1322 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_110_reg_1327 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_111_fu_520_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_111_reg_1332 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_fu_524_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_reg_1337 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i2_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i2_reg_1344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_114_reg_1349 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_115_fu_567_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_115_reg_1354 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp8_fu_575_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_1359 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_116 : BOOLEAN;
signal sel_tmp3_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_reg_1364 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_602_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_1369 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_fu_607_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_reg_1374 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_2_t_fu_625_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_2_t_reg_1379 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_1387 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_135 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_1419 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_154 : BOOLEAN;
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal or_cond219_i_i_reg_1396 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_643_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond219_i_i_fu_665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_117_fu_676_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_117_reg_1400 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i_fu_698_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_1405 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_fu_703_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_reg_1409 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_120_reg_1414 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal col_assign_fu_734_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_reg_1427 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_reg_1427_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_addr_reg_1433 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_addr_reg_1439 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_addr_reg_1445 : STD_LOGIC_VECTOR (10 downto 0);
signal col_assign_1_fu_762_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_1_reg_1451 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_2_0_reg_1457 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_0_reg_1464 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_0_reg_1471 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_reg_1477 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_1_6_reg_1483 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_6_reg_1490 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_lo_reg_1496 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_reg_1501 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_fu_1033_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_reg_1506 : STD_LOGIC_VECTOR (0 downto 0);
signal src_kernel_win_0_val_0_1_lo_reg_1511 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_lo_reg_1517 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_reg_1523 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_lo_reg_1529 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_fu_1080_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_reg_1539 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_reg_1544 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_0_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce0 : STD_LOGIC;
signal k_buf_0_val_0_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce1 : STD_LOGIC;
signal k_buf_0_val_0_we1 : STD_LOGIC;
signal k_buf_0_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce0 : STD_LOGIC;
signal k_buf_0_val_1_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce1 : STD_LOGIC;
signal k_buf_0_val_1_we1 : STD_LOGIC;
signal k_buf_0_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce0 : STD_LOGIC;
signal k_buf_0_val_2_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce1 : STD_LOGIC;
signal k_buf_0_val_2_we1 : STD_LOGIC;
signal k_buf_0_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_012_0_i_i_reg_252 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st12_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_355 : BOOLEAN;
signal tmp_69_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal src_kernel_win_0_val_0_1_fu_106 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_0_fu_934_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_9_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_fu_110 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_3_fu_114 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_1_fu_118 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_fu_122 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_0_fu_946_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_11_fu_1006_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_fu_126 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_5_fu_130 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_2_fu_134 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_6_fu_138 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_1_fu_142 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_8_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_2_fu_146 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_6_fu_868_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_7_fu_150 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_4_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_0_fu_166 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_1_fu_170 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_2_fu_174 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_316_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_fu_320_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_fu_336_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_101_fu_346_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_102_fu_372_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_15_cast_cast_fu_382_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_y_fu_403_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_103_fu_415_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal icmp_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_i_i_fu_450_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i5_fu_461_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_106_fu_466_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_107_fu_470_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal y_1_fu_481_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_109_fu_487_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal y_1_1_fu_528_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_113_fu_534_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev1_fu_542_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_fu_571_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_s_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_80_fu_591_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_1_t_fu_597_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_81_fu_613_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_82_fu_619_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_116_fu_649_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal icmp2_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_cast_fu_634_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_x_fu_670_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_119_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rev2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_118_fu_680_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal p_assign_fu_739_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal p_assign_1_i_fu_745_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_121_fu_751_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp1_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal right_border_buf_0_val_1_2_3_fu_838_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_5_fu_860_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_1_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp9_fu_929_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp6_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_984_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_buf_0_val_0_0_2_fu_976_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_fu_998_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_2_fu_1021_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_1_fu_1055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_2_fu_1070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_1_fu_1095_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_2_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_0_val_0_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_0_address0,
ce0 => k_buf_0_val_0_ce0,
q0 => k_buf_0_val_0_q0,
address1 => k_buf_0_val_0_address1,
ce1 => k_buf_0_val_0_ce1,
we1 => k_buf_0_val_0_we1,
d1 => k_buf_0_val_0_d1);
k_buf_0_val_1_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_1_address0,
ce0 => k_buf_0_val_1_ce0,
q0 => k_buf_0_val_1_q0,
address1 => k_buf_0_val_1_address1,
ce1 => k_buf_0_val_1_ce1,
we1 => k_buf_0_val_1_we1,
d1 => k_buf_0_val_1_d1);
k_buf_0_val_2_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_2_address0,
ce0 => k_buf_0_val_2_ce0,
q0 => k_buf_0_val_2_q0,
address1 => k_buf_0_val_2_address1,
ce1 => k_buf_0_val_2_ce1,
we1 => k_buf_0_val_2_we1,
d1 => k_buf_0_val_2_d1);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_19_fu_638_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
if (not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2))) then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_012_0_i_i_reg_252 assign process. --
p_012_0_i_i_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_4)) then
p_012_0_i_i_reg_252 <= i_V_reg_1286;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
p_012_0_i_i_reg_252 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_025_0_i_i_reg_263 assign process. --
p_025_0_i_i_reg_263_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
p_025_0_i_i_reg_263 <= j_V_fu_643_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_025_0_i_i_reg_263 <= ap_const_lv11_0;
end if;
end if;
end process;
-- src_kernel_win_0_val_0_1_fu_106 assign process. --
src_kernel_win_0_val_0_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_0_1_fu_106 <= right_border_buf_0_val_2_0_reg_1457;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= col_buf_0_val_0_0_9_fu_989_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= src_kernel_win_0_val_0_0_fu_934_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_1_1_fu_122 assign process. --
src_kernel_win_0_val_1_1_fu_122_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_0_reg_1464;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_2_11_fu_1006_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= src_kernel_win_0_val_1_0_fu_946_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_2_1_fu_118 assign process. --
src_kernel_win_0_val_2_1_fu_118_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and not((col_assign_1_reg_1451 = ap_const_lv2_1)) and not((col_assign_1_reg_1451 = ap_const_lv2_0)))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_2_fu_174;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_0_fu_166;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_1_fu_170;
elsif (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1))))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_2_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_0_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_1_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 <= col_assign_1_reg_1451;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_1419_pp0_it1;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 <= src_kernel_win_0_val_0_1_6_reg_1483;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 <= src_kernel_win_0_val_0_1_lo_reg_1511;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 <= ap_reg_ppstg_tmp_120_reg_1414_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it2;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it3;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_i_reg_1405_pp0_it1;
src_kernel_win_0_val_0_1_6_reg_1483 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_6_reg_1490 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppstg_col_assign_reg_1427_pp0_it1 <= col_assign_reg_1427;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 <= or_cond219_i_i_reg_1396;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 <= or_cond2_reg_1419;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 <= tmp_120_reg_1414;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 <= tmp_19_reg_1387;
ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 <= tmp_29_reg_1423;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 <= tmp_i_reg_1405;
tmp_19_reg_1387 <= tmp_19_fu_638_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
brmerge_reg_1383 <= brmerge_fu_630_p2;
locy_2_t_reg_1379 <= locy_2_t_fu_625_p2;
sel_tmp3_reg_1364 <= sel_tmp3_fu_579_p2;
sel_tmp4_reg_1369 <= sel_tmp4_fu_602_p2;
sel_tmp7_reg_1374 <= sel_tmp7_fu_607_p2;
sel_tmp8_reg_1359 <= sel_tmp8_fu_575_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)) and (ap_const_lv1_0 = or_cond2_reg_1419) and (ap_const_lv1_0 = tmp_120_reg_1414) and (ap_const_lv1_0 = tmp_i_reg_1405))) then
col_assign_1_reg_1451 <= col_assign_1_fu_762_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)) and (ap_const_lv1_0 = tmp_29_fu_729_p2))) then
col_assign_reg_1427 <= col_assign_fu_734_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
col_buf_0_val_0_0_3_fu_114 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_2_fu_174 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1))) then
col_buf_0_val_0_0_5_fu_130 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_1_fu_170 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) then
col_buf_0_val_0_0_6_fu_138 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_0_fu_166 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
heightloop_reg_1240 <= heightloop_fu_324_p2;
p_neg226_i_i_cast_reg_1255 <= p_neg226_i_i_cast_fu_350_p2;
ref_cast_reg_1267(0) <= ref_cast_fu_362_p1(0);
ref_cast_reg_1267(1) <= ref_cast_fu_362_p1(1);
ref_cast_reg_1267(2) <= ref_cast_fu_362_p1(2);
ref_cast_reg_1267(3) <= ref_cast_fu_362_p1(3);
ref_cast_reg_1267(4) <= ref_cast_fu_362_p1(4);
ref_cast_reg_1267(5) <= ref_cast_fu_362_p1(5);
ref_cast_reg_1267(6) <= ref_cast_fu_362_p1(6);
ref_cast_reg_1267(7) <= ref_cast_fu_362_p1(7);
ref_cast_reg_1267(8) <= ref_cast_fu_362_p1(8);
ref_cast_reg_1267(9) <= ref_cast_fu_362_p1(9);
ref_cast_reg_1267(10) <= ref_cast_fu_362_p1(10);
ref_reg_1261 <= ref_fu_356_p2;
tmp_14_cast_reg_1250(0) <= tmp_14_cast_fu_342_p1(0);
tmp_14_cast_reg_1250(1) <= tmp_14_cast_fu_342_p1(1);
tmp_14_cast_reg_1250(2) <= tmp_14_cast_fu_342_p1(2);
tmp_14_cast_reg_1250(3) <= tmp_14_cast_fu_342_p1(3);
tmp_14_cast_reg_1250(4) <= tmp_14_cast_fu_342_p1(4);
tmp_14_cast_reg_1250(5) <= tmp_14_cast_fu_342_p1(5);
tmp_14_cast_reg_1250(6) <= tmp_14_cast_fu_342_p1(6);
tmp_14_cast_reg_1250(7) <= tmp_14_cast_fu_342_p1(7);
tmp_14_cast_reg_1250(8) <= tmp_14_cast_fu_342_p1(8);
tmp_14_cast_reg_1250(9) <= tmp_14_cast_fu_342_p1(9);
tmp_14_cast_reg_1250(10) <= tmp_14_cast_fu_342_p1(10);
tmp_2_i1_reg_1277 <= tmp_2_i1_fu_376_p2;
tmp_2_i_reg_1272 <= tmp_2_i_fu_366_p2;
widthloop_reg_1245 <= widthloop_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_1286 <= i_V_fu_391_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)))) then
k_buf_0_val_0_addr_reg_1433 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_addr_reg_1439 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_addr_reg_1445 <= tmp_69_fu_755_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond219_i_i_reg_1396 <= or_cond219_i_i_fu_665_p2;
or_cond_i_reg_1409 <= or_cond_i_fu_703_p2;
tmp_117_reg_1400 <= tmp_117_fu_676_p1;
tmp_120_reg_1414 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_i_reg_1405 <= tmp_i_fu_698_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond2_reg_1419 <= or_cond2_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
or_cond_i1_reg_1322 <= or_cond_i1_fu_506_p2;
or_cond_i2_reg_1344 <= or_cond_i2_fu_553_p2;
or_cond_reg_1301 <= or_cond_fu_436_p2;
tmp_104_reg_1306 <= ImagLoc_y_fu_403_p2(11 downto 11);
tmp_105_reg_1310 <= tmp_105_fu_457_p1;
tmp_108_reg_1316 <= tmp_108_fu_473_p3;
tmp_110_reg_1327 <= y_1_fu_481_p2(11 downto 11);
tmp_111_reg_1332 <= tmp_111_fu_520_p1;
tmp_112_reg_1337 <= tmp_112_fu_524_p1;
tmp_114_reg_1349 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_reg_1354 <= tmp_115_fu_567_p1;
tmp_17_reg_1291 <= tmp_17_fu_397_p2;
tmp_23_reg_1296 <= tmp_23_fu_409_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
right_border_buf_0_val_1_0_reg_1464 <= k_buf_0_val_1_q0;
right_border_buf_0_val_2_0_reg_1457 <= k_buf_0_val_0_q0;
src_kernel_win_0_val_2_0_reg_1471 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
right_border_buf_0_val_1_2_1_fu_142 <= right_border_buf_0_val_1_2_8_fu_877_p3;
right_border_buf_0_val_1_2_2_fu_146 <= right_border_buf_0_val_1_2_6_fu_868_p3;
right_border_buf_0_val_1_2_7_fu_150 <= right_border_buf_0_val_1_2_4_fu_851_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3)))) then
src_kernel_win_0_val_0_1_lo_reg_1511 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_lo_reg_1517 <= src_kernel_win_0_val_1_1_fu_122;
temp_0_i_i_i_057_i_i_1_1_1_reg_1523 <= temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it4)))) then
src_kernel_win_0_val_0_2_fu_110 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4)))) then
src_kernel_win_0_val_0_2_lo_reg_1529 <= src_kernel_win_0_val_0_2_fu_110;
temp_0_i_i_i_057_i_i_1_1_2_reg_1534 <= temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3;
tmp_128_2_reg_1539 <= tmp_128_2_fu_1080_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)))) then
src_kernel_win_0_val_1_2_fu_126 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2)))) then
src_kernel_win_0_val_1_2_lo_reg_1496 <= src_kernel_win_0_val_1_2_fu_126;
temp_0_i_i_i_057_i_i_1_0_2_reg_1501 <= temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3;
tmp_128_1_reg_1506 <= tmp_128_1_fu_1033_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
src_kernel_win_0_val_2_2_fu_134 <= src_kernel_win_0_val_2_1_fu_118;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1)))) then
temp_0_i_i_i_057_i_i_1_0_1_reg_1477 <= temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5)))) then
temp_0_i_i_i_057_i_i_1_2_1_reg_1544 <= temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)))) then
tmp_29_reg_1423 <= tmp_29_fu_729_p2;
end if;
end if;
end process;
tmp_14_cast_reg_1250(11) <= '0';
ref_cast_reg_1267(11) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_48, tmp_16_fu_386_p2, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_48)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((tmp_16_fu_386_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
when ap_ST_pp0_stg0_fsm_3 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4))))) then
ap_NS_fsm <= ap_ST_st12_fsm_4;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
end if;
when ap_ST_st12_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ImagLoc_x_fu_670_p2 <= std_logic_vector(unsigned(tmp_18_cast_fu_634_p1) + unsigned(ap_const_lv12_FFF));
ImagLoc_y_fu_403_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFC));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_116 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_135 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_154 assign process. --
ap_sig_bdd_154_assign_proc : process(p_src_data_stream_V_empty_n, brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)
begin
ap_sig_bdd_154 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(p_dst_data_stream_V_full_n, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)
begin
ap_sig_bdd_172 <= ((p_dst_data_stream_V_full_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)));
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_355 assign process. --
ap_sig_bdd_355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_48 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_76 assign process. --
ap_sig_bdd_76_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_3 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_3_assign_proc : process(ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_4 assign process. --
ap_sig_cseq_ST_st12_fsm_4_assign_proc : process(ap_sig_bdd_355)
begin
if (ap_sig_bdd_355) then
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24)
begin
if (ap_sig_bdd_24) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_76)
begin
if (ap_sig_bdd_76) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
brmerge_fu_630_p2 <= (tmp_23_reg_1296 or or_cond_reg_1301);
col_assign_1_fu_762_p2 <= std_logic_vector(unsigned(tmp_121_fu_751_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_assign_fu_734_p2 <= std_logic_vector(unsigned(tmp_118_fu_680_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_buf_0_val_0_0_2_fu_976_p3 <=
col_buf_0_val_0_0_5_fu_130 when (sel_tmp_fu_971_p2(0) = '1') else
col_buf_0_val_0_0_3_fu_114;
col_buf_0_val_0_0_9_fu_989_p3 <=
col_buf_0_val_0_0_6_fu_138 when (sel_tmp2_fu_984_p2(0) = '1') else
col_buf_0_val_0_0_2_fu_976_p3;
heightloop_fu_324_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_5));
i_V_fu_391_p2 <= std_logic_vector(unsigned(p_012_0_i_i_reg_252) + unsigned(ap_const_lv11_1));
icmp2_fu_659_p2 <= "0" when (tmp_116_fu_649_p4 = ap_const_lv10_0) else "1";
icmp_fu_425_p2 <= "1" when (signed(tmp_103_fu_415_p4) > signed(ap_const_lv11_0)) else "0";
j_V_fu_643_p2 <= std_logic_vector(unsigned(p_025_0_i_i_reg_263) + unsigned(ap_const_lv11_1));
k_buf_0_val_0_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_0_address1 <= k_buf_0_val_0_addr_reg_1433;
-- k_buf_0_val_0_ce0 assign process. --
k_buf_0_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce0 <= ap_const_logic_1;
else
k_buf_0_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_0_ce1 assign process. --
k_buf_0_val_0_ce1_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce1 <= ap_const_logic_1;
else
k_buf_0_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_0_d1 <= p_src_data_stream_V_dout;
-- k_buf_0_val_0_we1 assign process. --
k_buf_0_val_0_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))))) then
k_buf_0_val_0_we1 <= ap_const_logic_1;
else
k_buf_0_val_0_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_address1 <= k_buf_0_val_1_addr_reg_1439;
-- k_buf_0_val_1_ce0 assign process. --
k_buf_0_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_1_ce0 <= ap_const_logic_1;
else
k_buf_0_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_1_ce1 assign process. --
k_buf_0_val_1_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_ce1 <= ap_const_logic_1;
else
k_buf_0_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_d1 <= k_buf_0_val_0_q0;
-- k_buf_0_val_1_we1 assign process. --
k_buf_0_val_1_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_we1 <= ap_const_logic_1;
else
k_buf_0_val_1_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_address1 <= k_buf_0_val_2_addr_reg_1445;
-- k_buf_0_val_2_ce0 assign process. --
k_buf_0_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_2_ce0 <= ap_const_logic_1;
else
k_buf_0_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_2_ce1 assign process. --
k_buf_0_val_2_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_ce1 <= ap_const_logic_1;
else
k_buf_0_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_d1 <= k_buf_0_val_1_q0;
-- k_buf_0_val_2_we1 assign process. --
k_buf_0_val_2_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_we1 <= ap_const_logic_1;
else
k_buf_0_val_2_we1 <= ap_const_logic_0;
end if;
end process;
locy_1_t_fu_597_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_80_fu_591_p3));
locy_2_t_fu_625_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_82_fu_619_p3));
locy_fu_571_p2 <= std_logic_vector(unsigned(tmp_105_reg_1310) - unsigned(tmp_108_reg_1316));
or_cond219_i_i_fu_665_p2 <= (tmp_17_reg_1291 and icmp2_fu_659_p2);
or_cond2_fu_723_p2 <= (tmp_26_fu_717_p2 and tmp_i_fu_698_p2);
or_cond_fu_436_p2 <= (icmp_fu_425_p2 and tmp_25_fu_431_p2);
or_cond_i1_fu_506_p2 <= (tmp_i1_fu_501_p2 and rev_fu_495_p2);
or_cond_i2_fu_553_p2 <= (tmp_i2_fu_548_p2 and rev1_fu_542_p2);
or_cond_i_fu_703_p2 <= (tmp_i_fu_698_p2 and rev2_fu_692_p2);
p_assign_1_i_fu_745_p3 <=
tmp_117_reg_1400 when (or_cond_i_reg_1409(0) = '1') else
p_assign_fu_739_p3;
p_assign_fu_739_p3 <=
ap_const_lv11_0 when (tmp_120_reg_1414(0) = '1') else
tmp_2_i_reg_1272;
p_dst_data_stream_V_din <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 when (tmp_128_2_2_fu_1107_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_1_reg_1544;
-- p_dst_data_stream_V_write assign process. --
p_dst_data_stream_V_write_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_dst_data_stream_V_write <= ap_const_logic_1;
else
p_dst_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i_fu_450_p3 <=
ap_const_lv11_2 when (tmp_25_fu_431_p2(0) = '1') else
ref_reg_1261;
p_neg226_i_i_cast_fu_350_p2 <= (tmp_101_fu_346_p1 xor ap_const_lv2_3);
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
ref_cast_fu_362_p1 <= std_logic_vector(resize(unsigned(ref_fu_356_p2),12));
ref_fu_356_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_7FF));
rev1_fu_542_p2 <= (tmp_113_fu_534_p3 xor ap_const_lv1_1);
rev2_fu_692_p2 <= (tmp_119_fu_684_p3 xor ap_const_lv1_1);
rev_fu_495_p2 <= (tmp_109_fu_487_p3 xor ap_const_lv1_1);
right_border_buf_0_val_1_2_11_fu_1006_p3 <=
right_border_buf_0_val_1_2_1_fu_142 when (sel_tmp2_fu_984_p2(0) = '1') else
right_border_buf_0_val_1_2_fu_998_p3;
right_border_buf_0_val_1_2_3_fu_838_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp1_fu_833_p2(0) = '1') else
k_buf_0_val_1_q0;
right_border_buf_0_val_1_2_4_fu_851_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_3_fu_838_p3;
right_border_buf_0_val_1_2_5_fu_860_p3 <=
k_buf_0_val_1_q0 when (sel_tmp1_fu_833_p2(0) = '1') else
right_border_buf_0_val_1_2_2_fu_146;
right_border_buf_0_val_1_2_6_fu_868_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_5_fu_860_p3;
right_border_buf_0_val_1_2_8_fu_877_p3 <=
k_buf_0_val_1_q0 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_1_fu_142;
right_border_buf_0_val_1_2_fu_998_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp_fu_971_p2(0) = '1') else
right_border_buf_0_val_1_2_7_fu_150;
sel_tmp1_fu_833_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1) else "0";
sel_tmp2_fu_984_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0) else "0";
sel_tmp3_fu_579_p2 <= "1" when (locy_fu_571_p2 = ap_const_lv2_1) else "0";
sel_tmp4_fu_602_p2 <= "1" when (tmp_112_reg_1337 = tmp_80_fu_591_p3) else "0";
sel_tmp5_fu_846_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0) else "0";
sel_tmp6_fu_941_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp4_reg_1369(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp7_fu_607_p2 <= "1" when (locy_1_t_fu_597_p2 = ap_const_lv2_1) else "0";
sel_tmp8_fu_575_p2 <= "1" when (tmp_105_reg_1310 = tmp_108_reg_1316) else "0";
sel_tmp9_fu_929_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp8_reg_1359(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp_fu_971_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1) else "0";
src_kernel_win_0_val_0_0_fu_934_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp3_reg_1364(0) = '1') else
sel_tmp9_fu_929_p3;
src_kernel_win_0_val_1_0_fu_946_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp7_reg_1374(0) = '1') else
sel_tmp6_fu_941_p3;
temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_1_fu_904_p2(0) = '1') else
src_kernel_win_0_val_2_2_fu_134;
temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_2_fu_1021_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_1_reg_1477;
temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 <=
src_kernel_win_0_val_1_1_6_reg_1490 when (tmp_128_1_1_fu_1055_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3;
temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 <=
src_kernel_win_0_val_1_1_lo_reg_1517 when (tmp_128_1_2_fu_1070_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_1_reg_1523;
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 <=
src_kernel_win_0_val_1_2_lo_reg_1496 when (tmp_128_1_reg_1506(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_2_reg_1501;
temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 when (tmp_128_2_1_fu_1095_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3;
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 <=
src_kernel_win_0_val_0_2_lo_reg_1529 when (tmp_128_2_reg_1539(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_2_reg_1534;
tmp_100_fu_320_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_101_fu_346_p1 <= p_src_cols_V_read(2 - 1 downto 0);
tmp_102_fu_372_p1 <= p_src_rows_V_read(2 - 1 downto 0);
tmp_103_fu_415_p4 <= ImagLoc_y_fu_403_p2(11 downto 1);
tmp_105_fu_457_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_106_fu_466_p1 <= ImagLoc_y_fu_403_p2(2 - 1 downto 0);
tmp_107_fu_470_p1 <= ref_reg_1261(2 - 1 downto 0);
tmp_108_fu_473_p3 <=
tmp_106_fu_466_p1 when (tmp_i5_fu_461_p2(0) = '1') else
tmp_107_fu_470_p1;
tmp_109_fu_487_p3 <= y_1_fu_481_p2(11 downto 11);
tmp_111_fu_520_p1 <= y_1_fu_481_p2(2 - 1 downto 0);
tmp_112_fu_524_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_113_fu_534_p3 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_fu_567_p1 <= y_1_1_fu_528_p2(2 - 1 downto 0);
tmp_116_fu_649_p4 <= p_025_0_i_i_reg_263(10 downto 1);
tmp_117_fu_676_p1 <= ImagLoc_x_fu_670_p2(11 - 1 downto 0);
tmp_118_fu_680_p1 <= ImagLoc_x_fu_670_p2(2 - 1 downto 0);
tmp_119_fu_684_p3 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_121_fu_751_p1 <= p_assign_1_i_fu_745_p3(2 - 1 downto 0);
tmp_128_0_1_fu_904_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(src_kernel_win_0_val_2_2_fu_134)) else "0";
tmp_128_0_2_fu_1021_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(temp_0_i_i_i_057_i_i_1_0_1_reg_1477)) else "0";
tmp_128_1_1_fu_1055_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_6_reg_1490) > unsigned(temp_0_i_i_i_057_i_i_1_1_fu_1050_p3)) else "0";
tmp_128_1_2_fu_1070_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_lo_reg_1517) > unsigned(temp_0_i_i_i_057_i_i_1_1_1_reg_1523)) else "0";
tmp_128_1_fu_1033_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_2_fu_126) > unsigned(temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3)) else "0";
tmp_128_2_1_fu_1095_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5) > unsigned(temp_0_i_i_i_057_i_i_1_2_fu_1090_p3)) else "0";
tmp_128_2_2_fu_1107_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6) > unsigned(temp_0_i_i_i_057_i_i_1_2_1_reg_1544)) else "0";
tmp_128_2_fu_1080_p2 <= "1" when (unsigned(src_kernel_win_0_val_0_2_fu_110) > unsigned(temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3)) else "0";
tmp_14_cast_fu_342_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_336_p2),12));
tmp_14_fu_336_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FD));
tmp_15_cast_cast_fu_382_p1 <= std_logic_vector(resize(unsigned(p_012_0_i_i_reg_252),12));
tmp_16_fu_386_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) < unsigned(heightloop_reg_1240)) else "0";
tmp_17_fu_397_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) > unsigned(ap_const_lv11_4)) else "0";
tmp_18_cast_fu_634_p1 <= std_logic_vector(resize(unsigned(p_025_0_i_i_reg_263),12));
tmp_19_fu_638_p2 <= "1" when (unsigned(p_025_0_i_i_reg_263) < unsigned(widthloop_reg_1245)) else "0";
tmp_23_fu_409_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ap_const_lv12_FFF)) else "0";
tmp_25_fu_431_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ref_cast_reg_1267)) else "0";
tmp_26_fu_717_p2 <= "0" when (p_025_0_i_i_reg_263 = ap_const_lv11_0) else "1";
tmp_29_fu_729_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(tmp_14_cast_reg_1250)) else "0";
tmp_2_i1_fu_376_p2 <= std_logic_vector(unsigned(tmp_102_fu_372_p1) + unsigned(ap_const_lv2_3));
tmp_2_i_fu_366_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FF));
tmp_69_fu_755_p1 <= std_logic_vector(resize(unsigned(p_assign_1_i_fu_745_p3),64));
tmp_80_fu_591_p3 <=
tmp_111_reg_1332 when (or_cond_i1_reg_1322(0) = '1') else
tmp_s_fu_585_p3;
tmp_81_fu_613_p3 <=
ap_const_lv2_0 when (tmp_114_reg_1349(0) = '1') else
tmp_2_i1_reg_1277;
tmp_82_fu_619_p3 <=
tmp_115_reg_1354 when (or_cond_i2_reg_1344(0) = '1') else
tmp_81_fu_613_p3;
tmp_fu_316_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_i1_fu_501_p2 <= "1" when (signed(y_1_fu_481_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i2_fu_548_p2 <= "1" when (signed(y_1_1_fu_528_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i5_fu_461_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i_fu_698_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(p_src_cols_V_read)) else "0";
tmp_s_fu_585_p3 <=
ap_const_lv2_0 when (tmp_110_reg_1327(0) = '1') else
tmp_2_i1_reg_1277;
widthloop_fu_330_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_2));
y_1_1_fu_528_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFA));
y_1_fu_481_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFB));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Dilate_0_0_1080_1920_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_V_full_n : IN STD_LOGIC;
p_dst_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_Dilate_0_0_1080_1920_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_pp0_stg0_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st12_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_const_lv11_7FD : STD_LOGIC_VECTOR (10 downto 0) := "11111111101";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv12_FFC : STD_LOGIC_VECTOR (11 downto 0) := "111111111100";
constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv12_FFB : STD_LOGIC_VECTOR (11 downto 0) := "111111111011";
constant ap_const_lv12_FFA : STD_LOGIC_VECTOR (11 downto 0) := "111111111010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_24 : BOOLEAN;
signal p_025_0_i_i_reg_263 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_48 : BOOLEAN;
signal heightloop_fu_324_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal heightloop_reg_1240 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_fu_330_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_reg_1245 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_cast_fu_342_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_14_cast_reg_1250 : STD_LOGIC_VECTOR (11 downto 0);
signal p_neg226_i_i_cast_fu_350_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal p_neg226_i_i_cast_reg_1255 : STD_LOGIC_VECTOR (1 downto 0);
signal ref_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_reg_1261 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_cast_fu_362_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ref_cast_reg_1267 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_2_i_fu_366_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i_reg_1272 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i1_fu_376_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_2_i1_reg_1277 : STD_LOGIC_VECTOR (1 downto 0);
signal i_V_fu_391_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_1286 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_76 : BOOLEAN;
signal tmp_17_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_1291 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_1296 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_1301 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_104_reg_1306 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_105_fu_457_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_105_reg_1310 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_fu_473_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_reg_1316 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i1_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i1_reg_1322 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_110_reg_1327 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_111_fu_520_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_111_reg_1332 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_fu_524_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_reg_1337 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i2_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i2_reg_1344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_114_reg_1349 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_115_fu_567_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_115_reg_1354 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp8_fu_575_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_1359 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_116 : BOOLEAN;
signal sel_tmp3_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_reg_1364 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_602_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_1369 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_fu_607_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_reg_1374 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_2_t_fu_625_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_2_t_reg_1379 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_1387 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_135 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_1419 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_154 : BOOLEAN;
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal or_cond219_i_i_reg_1396 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_643_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond219_i_i_fu_665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_117_fu_676_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_117_reg_1400 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i_fu_698_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_1405 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_fu_703_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_reg_1409 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_120_reg_1414 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal col_assign_fu_734_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_reg_1427 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_reg_1427_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_addr_reg_1433 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_addr_reg_1439 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_addr_reg_1445 : STD_LOGIC_VECTOR (10 downto 0);
signal col_assign_1_fu_762_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_1_reg_1451 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_2_0_reg_1457 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_0_reg_1464 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_0_reg_1471 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_reg_1477 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_1_6_reg_1483 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_6_reg_1490 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_lo_reg_1496 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_reg_1501 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_fu_1033_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_reg_1506 : STD_LOGIC_VECTOR (0 downto 0);
signal src_kernel_win_0_val_0_1_lo_reg_1511 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_lo_reg_1517 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_reg_1523 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_lo_reg_1529 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_fu_1080_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_reg_1539 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_reg_1544 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_0_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce0 : STD_LOGIC;
signal k_buf_0_val_0_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce1 : STD_LOGIC;
signal k_buf_0_val_0_we1 : STD_LOGIC;
signal k_buf_0_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce0 : STD_LOGIC;
signal k_buf_0_val_1_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce1 : STD_LOGIC;
signal k_buf_0_val_1_we1 : STD_LOGIC;
signal k_buf_0_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce0 : STD_LOGIC;
signal k_buf_0_val_2_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce1 : STD_LOGIC;
signal k_buf_0_val_2_we1 : STD_LOGIC;
signal k_buf_0_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_012_0_i_i_reg_252 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st12_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_355 : BOOLEAN;
signal tmp_69_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal src_kernel_win_0_val_0_1_fu_106 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_0_fu_934_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_9_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_fu_110 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_3_fu_114 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_1_fu_118 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_fu_122 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_0_fu_946_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_11_fu_1006_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_fu_126 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_5_fu_130 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_2_fu_134 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_6_fu_138 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_1_fu_142 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_8_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_2_fu_146 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_6_fu_868_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_7_fu_150 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_4_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_0_fu_166 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_1_fu_170 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_2_fu_174 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_316_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_fu_320_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_fu_336_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_101_fu_346_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_102_fu_372_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_15_cast_cast_fu_382_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_y_fu_403_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_103_fu_415_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal icmp_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_i_i_fu_450_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i5_fu_461_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_106_fu_466_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_107_fu_470_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal y_1_fu_481_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_109_fu_487_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal y_1_1_fu_528_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_113_fu_534_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev1_fu_542_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_fu_571_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_s_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_80_fu_591_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_1_t_fu_597_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_81_fu_613_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_82_fu_619_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_116_fu_649_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal icmp2_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_cast_fu_634_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_x_fu_670_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_119_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rev2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_118_fu_680_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal p_assign_fu_739_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal p_assign_1_i_fu_745_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_121_fu_751_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp1_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal right_border_buf_0_val_1_2_3_fu_838_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_5_fu_860_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_1_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp9_fu_929_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp6_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_984_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_buf_0_val_0_0_2_fu_976_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_fu_998_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_2_fu_1021_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_1_fu_1055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_2_fu_1070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_1_fu_1095_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_2_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_0_val_0_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_0_address0,
ce0 => k_buf_0_val_0_ce0,
q0 => k_buf_0_val_0_q0,
address1 => k_buf_0_val_0_address1,
ce1 => k_buf_0_val_0_ce1,
we1 => k_buf_0_val_0_we1,
d1 => k_buf_0_val_0_d1);
k_buf_0_val_1_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_1_address0,
ce0 => k_buf_0_val_1_ce0,
q0 => k_buf_0_val_1_q0,
address1 => k_buf_0_val_1_address1,
ce1 => k_buf_0_val_1_ce1,
we1 => k_buf_0_val_1_we1,
d1 => k_buf_0_val_1_d1);
k_buf_0_val_2_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_2_address0,
ce0 => k_buf_0_val_2_ce0,
q0 => k_buf_0_val_2_q0,
address1 => k_buf_0_val_2_address1,
ce1 => k_buf_0_val_2_ce1,
we1 => k_buf_0_val_2_we1,
d1 => k_buf_0_val_2_d1);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_19_fu_638_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
if (not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2))) then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_012_0_i_i_reg_252 assign process. --
p_012_0_i_i_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_4)) then
p_012_0_i_i_reg_252 <= i_V_reg_1286;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
p_012_0_i_i_reg_252 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_025_0_i_i_reg_263 assign process. --
p_025_0_i_i_reg_263_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
p_025_0_i_i_reg_263 <= j_V_fu_643_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_025_0_i_i_reg_263 <= ap_const_lv11_0;
end if;
end if;
end process;
-- src_kernel_win_0_val_0_1_fu_106 assign process. --
src_kernel_win_0_val_0_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_0_1_fu_106 <= right_border_buf_0_val_2_0_reg_1457;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= col_buf_0_val_0_0_9_fu_989_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= src_kernel_win_0_val_0_0_fu_934_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_1_1_fu_122 assign process. --
src_kernel_win_0_val_1_1_fu_122_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_0_reg_1464;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_2_11_fu_1006_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= src_kernel_win_0_val_1_0_fu_946_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_2_1_fu_118 assign process. --
src_kernel_win_0_val_2_1_fu_118_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and not((col_assign_1_reg_1451 = ap_const_lv2_1)) and not((col_assign_1_reg_1451 = ap_const_lv2_0)))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_2_fu_174;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_0_fu_166;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_1_fu_170;
elsif (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1))))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_2_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_0_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_1_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 <= col_assign_1_reg_1451;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_1419_pp0_it1;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 <= src_kernel_win_0_val_0_1_6_reg_1483;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 <= src_kernel_win_0_val_0_1_lo_reg_1511;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 <= ap_reg_ppstg_tmp_120_reg_1414_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it2;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it3;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_i_reg_1405_pp0_it1;
src_kernel_win_0_val_0_1_6_reg_1483 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_6_reg_1490 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppstg_col_assign_reg_1427_pp0_it1 <= col_assign_reg_1427;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 <= or_cond219_i_i_reg_1396;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 <= or_cond2_reg_1419;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 <= tmp_120_reg_1414;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 <= tmp_19_reg_1387;
ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 <= tmp_29_reg_1423;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 <= tmp_i_reg_1405;
tmp_19_reg_1387 <= tmp_19_fu_638_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
brmerge_reg_1383 <= brmerge_fu_630_p2;
locy_2_t_reg_1379 <= locy_2_t_fu_625_p2;
sel_tmp3_reg_1364 <= sel_tmp3_fu_579_p2;
sel_tmp4_reg_1369 <= sel_tmp4_fu_602_p2;
sel_tmp7_reg_1374 <= sel_tmp7_fu_607_p2;
sel_tmp8_reg_1359 <= sel_tmp8_fu_575_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)) and (ap_const_lv1_0 = or_cond2_reg_1419) and (ap_const_lv1_0 = tmp_120_reg_1414) and (ap_const_lv1_0 = tmp_i_reg_1405))) then
col_assign_1_reg_1451 <= col_assign_1_fu_762_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)) and (ap_const_lv1_0 = tmp_29_fu_729_p2))) then
col_assign_reg_1427 <= col_assign_fu_734_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
col_buf_0_val_0_0_3_fu_114 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_2_fu_174 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1))) then
col_buf_0_val_0_0_5_fu_130 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_1_fu_170 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) then
col_buf_0_val_0_0_6_fu_138 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_0_fu_166 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
heightloop_reg_1240 <= heightloop_fu_324_p2;
p_neg226_i_i_cast_reg_1255 <= p_neg226_i_i_cast_fu_350_p2;
ref_cast_reg_1267(0) <= ref_cast_fu_362_p1(0);
ref_cast_reg_1267(1) <= ref_cast_fu_362_p1(1);
ref_cast_reg_1267(2) <= ref_cast_fu_362_p1(2);
ref_cast_reg_1267(3) <= ref_cast_fu_362_p1(3);
ref_cast_reg_1267(4) <= ref_cast_fu_362_p1(4);
ref_cast_reg_1267(5) <= ref_cast_fu_362_p1(5);
ref_cast_reg_1267(6) <= ref_cast_fu_362_p1(6);
ref_cast_reg_1267(7) <= ref_cast_fu_362_p1(7);
ref_cast_reg_1267(8) <= ref_cast_fu_362_p1(8);
ref_cast_reg_1267(9) <= ref_cast_fu_362_p1(9);
ref_cast_reg_1267(10) <= ref_cast_fu_362_p1(10);
ref_reg_1261 <= ref_fu_356_p2;
tmp_14_cast_reg_1250(0) <= tmp_14_cast_fu_342_p1(0);
tmp_14_cast_reg_1250(1) <= tmp_14_cast_fu_342_p1(1);
tmp_14_cast_reg_1250(2) <= tmp_14_cast_fu_342_p1(2);
tmp_14_cast_reg_1250(3) <= tmp_14_cast_fu_342_p1(3);
tmp_14_cast_reg_1250(4) <= tmp_14_cast_fu_342_p1(4);
tmp_14_cast_reg_1250(5) <= tmp_14_cast_fu_342_p1(5);
tmp_14_cast_reg_1250(6) <= tmp_14_cast_fu_342_p1(6);
tmp_14_cast_reg_1250(7) <= tmp_14_cast_fu_342_p1(7);
tmp_14_cast_reg_1250(8) <= tmp_14_cast_fu_342_p1(8);
tmp_14_cast_reg_1250(9) <= tmp_14_cast_fu_342_p1(9);
tmp_14_cast_reg_1250(10) <= tmp_14_cast_fu_342_p1(10);
tmp_2_i1_reg_1277 <= tmp_2_i1_fu_376_p2;
tmp_2_i_reg_1272 <= tmp_2_i_fu_366_p2;
widthloop_reg_1245 <= widthloop_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_1286 <= i_V_fu_391_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)))) then
k_buf_0_val_0_addr_reg_1433 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_addr_reg_1439 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_addr_reg_1445 <= tmp_69_fu_755_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond219_i_i_reg_1396 <= or_cond219_i_i_fu_665_p2;
or_cond_i_reg_1409 <= or_cond_i_fu_703_p2;
tmp_117_reg_1400 <= tmp_117_fu_676_p1;
tmp_120_reg_1414 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_i_reg_1405 <= tmp_i_fu_698_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond2_reg_1419 <= or_cond2_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
or_cond_i1_reg_1322 <= or_cond_i1_fu_506_p2;
or_cond_i2_reg_1344 <= or_cond_i2_fu_553_p2;
or_cond_reg_1301 <= or_cond_fu_436_p2;
tmp_104_reg_1306 <= ImagLoc_y_fu_403_p2(11 downto 11);
tmp_105_reg_1310 <= tmp_105_fu_457_p1;
tmp_108_reg_1316 <= tmp_108_fu_473_p3;
tmp_110_reg_1327 <= y_1_fu_481_p2(11 downto 11);
tmp_111_reg_1332 <= tmp_111_fu_520_p1;
tmp_112_reg_1337 <= tmp_112_fu_524_p1;
tmp_114_reg_1349 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_reg_1354 <= tmp_115_fu_567_p1;
tmp_17_reg_1291 <= tmp_17_fu_397_p2;
tmp_23_reg_1296 <= tmp_23_fu_409_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
right_border_buf_0_val_1_0_reg_1464 <= k_buf_0_val_1_q0;
right_border_buf_0_val_2_0_reg_1457 <= k_buf_0_val_0_q0;
src_kernel_win_0_val_2_0_reg_1471 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
right_border_buf_0_val_1_2_1_fu_142 <= right_border_buf_0_val_1_2_8_fu_877_p3;
right_border_buf_0_val_1_2_2_fu_146 <= right_border_buf_0_val_1_2_6_fu_868_p3;
right_border_buf_0_val_1_2_7_fu_150 <= right_border_buf_0_val_1_2_4_fu_851_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3)))) then
src_kernel_win_0_val_0_1_lo_reg_1511 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_lo_reg_1517 <= src_kernel_win_0_val_1_1_fu_122;
temp_0_i_i_i_057_i_i_1_1_1_reg_1523 <= temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it4)))) then
src_kernel_win_0_val_0_2_fu_110 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4)))) then
src_kernel_win_0_val_0_2_lo_reg_1529 <= src_kernel_win_0_val_0_2_fu_110;
temp_0_i_i_i_057_i_i_1_1_2_reg_1534 <= temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3;
tmp_128_2_reg_1539 <= tmp_128_2_fu_1080_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)))) then
src_kernel_win_0_val_1_2_fu_126 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2)))) then
src_kernel_win_0_val_1_2_lo_reg_1496 <= src_kernel_win_0_val_1_2_fu_126;
temp_0_i_i_i_057_i_i_1_0_2_reg_1501 <= temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3;
tmp_128_1_reg_1506 <= tmp_128_1_fu_1033_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
src_kernel_win_0_val_2_2_fu_134 <= src_kernel_win_0_val_2_1_fu_118;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1)))) then
temp_0_i_i_i_057_i_i_1_0_1_reg_1477 <= temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5)))) then
temp_0_i_i_i_057_i_i_1_2_1_reg_1544 <= temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)))) then
tmp_29_reg_1423 <= tmp_29_fu_729_p2;
end if;
end if;
end process;
tmp_14_cast_reg_1250(11) <= '0';
ref_cast_reg_1267(11) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_48, tmp_16_fu_386_p2, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_48)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((tmp_16_fu_386_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
when ap_ST_pp0_stg0_fsm_3 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4))))) then
ap_NS_fsm <= ap_ST_st12_fsm_4;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
end if;
when ap_ST_st12_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ImagLoc_x_fu_670_p2 <= std_logic_vector(unsigned(tmp_18_cast_fu_634_p1) + unsigned(ap_const_lv12_FFF));
ImagLoc_y_fu_403_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFC));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_116 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_135 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_154 assign process. --
ap_sig_bdd_154_assign_proc : process(p_src_data_stream_V_empty_n, brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)
begin
ap_sig_bdd_154 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(p_dst_data_stream_V_full_n, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)
begin
ap_sig_bdd_172 <= ((p_dst_data_stream_V_full_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)));
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_355 assign process. --
ap_sig_bdd_355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_48 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_76 assign process. --
ap_sig_bdd_76_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_3 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_3_assign_proc : process(ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_4 assign process. --
ap_sig_cseq_ST_st12_fsm_4_assign_proc : process(ap_sig_bdd_355)
begin
if (ap_sig_bdd_355) then
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24)
begin
if (ap_sig_bdd_24) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_76)
begin
if (ap_sig_bdd_76) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
brmerge_fu_630_p2 <= (tmp_23_reg_1296 or or_cond_reg_1301);
col_assign_1_fu_762_p2 <= std_logic_vector(unsigned(tmp_121_fu_751_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_assign_fu_734_p2 <= std_logic_vector(unsigned(tmp_118_fu_680_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_buf_0_val_0_0_2_fu_976_p3 <=
col_buf_0_val_0_0_5_fu_130 when (sel_tmp_fu_971_p2(0) = '1') else
col_buf_0_val_0_0_3_fu_114;
col_buf_0_val_0_0_9_fu_989_p3 <=
col_buf_0_val_0_0_6_fu_138 when (sel_tmp2_fu_984_p2(0) = '1') else
col_buf_0_val_0_0_2_fu_976_p3;
heightloop_fu_324_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_5));
i_V_fu_391_p2 <= std_logic_vector(unsigned(p_012_0_i_i_reg_252) + unsigned(ap_const_lv11_1));
icmp2_fu_659_p2 <= "0" when (tmp_116_fu_649_p4 = ap_const_lv10_0) else "1";
icmp_fu_425_p2 <= "1" when (signed(tmp_103_fu_415_p4) > signed(ap_const_lv11_0)) else "0";
j_V_fu_643_p2 <= std_logic_vector(unsigned(p_025_0_i_i_reg_263) + unsigned(ap_const_lv11_1));
k_buf_0_val_0_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_0_address1 <= k_buf_0_val_0_addr_reg_1433;
-- k_buf_0_val_0_ce0 assign process. --
k_buf_0_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce0 <= ap_const_logic_1;
else
k_buf_0_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_0_ce1 assign process. --
k_buf_0_val_0_ce1_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce1 <= ap_const_logic_1;
else
k_buf_0_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_0_d1 <= p_src_data_stream_V_dout;
-- k_buf_0_val_0_we1 assign process. --
k_buf_0_val_0_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))))) then
k_buf_0_val_0_we1 <= ap_const_logic_1;
else
k_buf_0_val_0_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_address1 <= k_buf_0_val_1_addr_reg_1439;
-- k_buf_0_val_1_ce0 assign process. --
k_buf_0_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_1_ce0 <= ap_const_logic_1;
else
k_buf_0_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_1_ce1 assign process. --
k_buf_0_val_1_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_ce1 <= ap_const_logic_1;
else
k_buf_0_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_d1 <= k_buf_0_val_0_q0;
-- k_buf_0_val_1_we1 assign process. --
k_buf_0_val_1_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_we1 <= ap_const_logic_1;
else
k_buf_0_val_1_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_address1 <= k_buf_0_val_2_addr_reg_1445;
-- k_buf_0_val_2_ce0 assign process. --
k_buf_0_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_2_ce0 <= ap_const_logic_1;
else
k_buf_0_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_2_ce1 assign process. --
k_buf_0_val_2_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_ce1 <= ap_const_logic_1;
else
k_buf_0_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_d1 <= k_buf_0_val_1_q0;
-- k_buf_0_val_2_we1 assign process. --
k_buf_0_val_2_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_we1 <= ap_const_logic_1;
else
k_buf_0_val_2_we1 <= ap_const_logic_0;
end if;
end process;
locy_1_t_fu_597_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_80_fu_591_p3));
locy_2_t_fu_625_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_82_fu_619_p3));
locy_fu_571_p2 <= std_logic_vector(unsigned(tmp_105_reg_1310) - unsigned(tmp_108_reg_1316));
or_cond219_i_i_fu_665_p2 <= (tmp_17_reg_1291 and icmp2_fu_659_p2);
or_cond2_fu_723_p2 <= (tmp_26_fu_717_p2 and tmp_i_fu_698_p2);
or_cond_fu_436_p2 <= (icmp_fu_425_p2 and tmp_25_fu_431_p2);
or_cond_i1_fu_506_p2 <= (tmp_i1_fu_501_p2 and rev_fu_495_p2);
or_cond_i2_fu_553_p2 <= (tmp_i2_fu_548_p2 and rev1_fu_542_p2);
or_cond_i_fu_703_p2 <= (tmp_i_fu_698_p2 and rev2_fu_692_p2);
p_assign_1_i_fu_745_p3 <=
tmp_117_reg_1400 when (or_cond_i_reg_1409(0) = '1') else
p_assign_fu_739_p3;
p_assign_fu_739_p3 <=
ap_const_lv11_0 when (tmp_120_reg_1414(0) = '1') else
tmp_2_i_reg_1272;
p_dst_data_stream_V_din <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 when (tmp_128_2_2_fu_1107_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_1_reg_1544;
-- p_dst_data_stream_V_write assign process. --
p_dst_data_stream_V_write_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_dst_data_stream_V_write <= ap_const_logic_1;
else
p_dst_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i_fu_450_p3 <=
ap_const_lv11_2 when (tmp_25_fu_431_p2(0) = '1') else
ref_reg_1261;
p_neg226_i_i_cast_fu_350_p2 <= (tmp_101_fu_346_p1 xor ap_const_lv2_3);
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
ref_cast_fu_362_p1 <= std_logic_vector(resize(unsigned(ref_fu_356_p2),12));
ref_fu_356_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_7FF));
rev1_fu_542_p2 <= (tmp_113_fu_534_p3 xor ap_const_lv1_1);
rev2_fu_692_p2 <= (tmp_119_fu_684_p3 xor ap_const_lv1_1);
rev_fu_495_p2 <= (tmp_109_fu_487_p3 xor ap_const_lv1_1);
right_border_buf_0_val_1_2_11_fu_1006_p3 <=
right_border_buf_0_val_1_2_1_fu_142 when (sel_tmp2_fu_984_p2(0) = '1') else
right_border_buf_0_val_1_2_fu_998_p3;
right_border_buf_0_val_1_2_3_fu_838_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp1_fu_833_p2(0) = '1') else
k_buf_0_val_1_q0;
right_border_buf_0_val_1_2_4_fu_851_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_3_fu_838_p3;
right_border_buf_0_val_1_2_5_fu_860_p3 <=
k_buf_0_val_1_q0 when (sel_tmp1_fu_833_p2(0) = '1') else
right_border_buf_0_val_1_2_2_fu_146;
right_border_buf_0_val_1_2_6_fu_868_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_5_fu_860_p3;
right_border_buf_0_val_1_2_8_fu_877_p3 <=
k_buf_0_val_1_q0 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_1_fu_142;
right_border_buf_0_val_1_2_fu_998_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp_fu_971_p2(0) = '1') else
right_border_buf_0_val_1_2_7_fu_150;
sel_tmp1_fu_833_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1) else "0";
sel_tmp2_fu_984_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0) else "0";
sel_tmp3_fu_579_p2 <= "1" when (locy_fu_571_p2 = ap_const_lv2_1) else "0";
sel_tmp4_fu_602_p2 <= "1" when (tmp_112_reg_1337 = tmp_80_fu_591_p3) else "0";
sel_tmp5_fu_846_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0) else "0";
sel_tmp6_fu_941_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp4_reg_1369(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp7_fu_607_p2 <= "1" when (locy_1_t_fu_597_p2 = ap_const_lv2_1) else "0";
sel_tmp8_fu_575_p2 <= "1" when (tmp_105_reg_1310 = tmp_108_reg_1316) else "0";
sel_tmp9_fu_929_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp8_reg_1359(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp_fu_971_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1) else "0";
src_kernel_win_0_val_0_0_fu_934_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp3_reg_1364(0) = '1') else
sel_tmp9_fu_929_p3;
src_kernel_win_0_val_1_0_fu_946_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp7_reg_1374(0) = '1') else
sel_tmp6_fu_941_p3;
temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_1_fu_904_p2(0) = '1') else
src_kernel_win_0_val_2_2_fu_134;
temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_2_fu_1021_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_1_reg_1477;
temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 <=
src_kernel_win_0_val_1_1_6_reg_1490 when (tmp_128_1_1_fu_1055_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3;
temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 <=
src_kernel_win_0_val_1_1_lo_reg_1517 when (tmp_128_1_2_fu_1070_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_1_reg_1523;
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 <=
src_kernel_win_0_val_1_2_lo_reg_1496 when (tmp_128_1_reg_1506(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_2_reg_1501;
temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 when (tmp_128_2_1_fu_1095_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3;
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 <=
src_kernel_win_0_val_0_2_lo_reg_1529 when (tmp_128_2_reg_1539(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_2_reg_1534;
tmp_100_fu_320_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_101_fu_346_p1 <= p_src_cols_V_read(2 - 1 downto 0);
tmp_102_fu_372_p1 <= p_src_rows_V_read(2 - 1 downto 0);
tmp_103_fu_415_p4 <= ImagLoc_y_fu_403_p2(11 downto 1);
tmp_105_fu_457_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_106_fu_466_p1 <= ImagLoc_y_fu_403_p2(2 - 1 downto 0);
tmp_107_fu_470_p1 <= ref_reg_1261(2 - 1 downto 0);
tmp_108_fu_473_p3 <=
tmp_106_fu_466_p1 when (tmp_i5_fu_461_p2(0) = '1') else
tmp_107_fu_470_p1;
tmp_109_fu_487_p3 <= y_1_fu_481_p2(11 downto 11);
tmp_111_fu_520_p1 <= y_1_fu_481_p2(2 - 1 downto 0);
tmp_112_fu_524_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_113_fu_534_p3 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_fu_567_p1 <= y_1_1_fu_528_p2(2 - 1 downto 0);
tmp_116_fu_649_p4 <= p_025_0_i_i_reg_263(10 downto 1);
tmp_117_fu_676_p1 <= ImagLoc_x_fu_670_p2(11 - 1 downto 0);
tmp_118_fu_680_p1 <= ImagLoc_x_fu_670_p2(2 - 1 downto 0);
tmp_119_fu_684_p3 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_121_fu_751_p1 <= p_assign_1_i_fu_745_p3(2 - 1 downto 0);
tmp_128_0_1_fu_904_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(src_kernel_win_0_val_2_2_fu_134)) else "0";
tmp_128_0_2_fu_1021_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(temp_0_i_i_i_057_i_i_1_0_1_reg_1477)) else "0";
tmp_128_1_1_fu_1055_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_6_reg_1490) > unsigned(temp_0_i_i_i_057_i_i_1_1_fu_1050_p3)) else "0";
tmp_128_1_2_fu_1070_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_lo_reg_1517) > unsigned(temp_0_i_i_i_057_i_i_1_1_1_reg_1523)) else "0";
tmp_128_1_fu_1033_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_2_fu_126) > unsigned(temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3)) else "0";
tmp_128_2_1_fu_1095_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5) > unsigned(temp_0_i_i_i_057_i_i_1_2_fu_1090_p3)) else "0";
tmp_128_2_2_fu_1107_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6) > unsigned(temp_0_i_i_i_057_i_i_1_2_1_reg_1544)) else "0";
tmp_128_2_fu_1080_p2 <= "1" when (unsigned(src_kernel_win_0_val_0_2_fu_110) > unsigned(temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3)) else "0";
tmp_14_cast_fu_342_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_336_p2),12));
tmp_14_fu_336_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FD));
tmp_15_cast_cast_fu_382_p1 <= std_logic_vector(resize(unsigned(p_012_0_i_i_reg_252),12));
tmp_16_fu_386_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) < unsigned(heightloop_reg_1240)) else "0";
tmp_17_fu_397_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) > unsigned(ap_const_lv11_4)) else "0";
tmp_18_cast_fu_634_p1 <= std_logic_vector(resize(unsigned(p_025_0_i_i_reg_263),12));
tmp_19_fu_638_p2 <= "1" when (unsigned(p_025_0_i_i_reg_263) < unsigned(widthloop_reg_1245)) else "0";
tmp_23_fu_409_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ap_const_lv12_FFF)) else "0";
tmp_25_fu_431_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ref_cast_reg_1267)) else "0";
tmp_26_fu_717_p2 <= "0" when (p_025_0_i_i_reg_263 = ap_const_lv11_0) else "1";
tmp_29_fu_729_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(tmp_14_cast_reg_1250)) else "0";
tmp_2_i1_fu_376_p2 <= std_logic_vector(unsigned(tmp_102_fu_372_p1) + unsigned(ap_const_lv2_3));
tmp_2_i_fu_366_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FF));
tmp_69_fu_755_p1 <= std_logic_vector(resize(unsigned(p_assign_1_i_fu_745_p3),64));
tmp_80_fu_591_p3 <=
tmp_111_reg_1332 when (or_cond_i1_reg_1322(0) = '1') else
tmp_s_fu_585_p3;
tmp_81_fu_613_p3 <=
ap_const_lv2_0 when (tmp_114_reg_1349(0) = '1') else
tmp_2_i1_reg_1277;
tmp_82_fu_619_p3 <=
tmp_115_reg_1354 when (or_cond_i2_reg_1344(0) = '1') else
tmp_81_fu_613_p3;
tmp_fu_316_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_i1_fu_501_p2 <= "1" when (signed(y_1_fu_481_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i2_fu_548_p2 <= "1" when (signed(y_1_1_fu_528_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i5_fu_461_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i_fu_698_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(p_src_cols_V_read)) else "0";
tmp_s_fu_585_p3 <=
ap_const_lv2_0 when (tmp_110_reg_1327(0) = '1') else
tmp_2_i1_reg_1277;
widthloop_fu_330_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_2));
y_1_1_fu_528_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFA));
y_1_fu_481_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFB));
end behav;
|
entity issue226 is
end entity;
architecture test of issue226 is
begin
process is
variable l : std.textio.line; -- OK
begin
std.textio.write(l, string'("hello")); -- OK
end process;
process is
variable x : ieee.std_logic_1164.std_logic; -- Error
begin
end process;
end architecture;
|
entity issue226 is
end entity;
architecture test of issue226 is
begin
process is
variable l : std.textio.line; -- OK
begin
std.textio.write(l, string'("hello")); -- OK
end process;
process is
variable x : ieee.std_logic_1164.std_logic; -- Error
begin
end process;
end architecture;
|
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure add10 is
begin
increment(10);
end procedure;
end protected body;
procedure proc_1 (x : integer);
type pt2 is protected
procedure proc_1 (y : integer);
end protected;
type pt2 is protected body
procedure proc_2 is
begin
proc_1(y => 5); -- OK
end procedure;
end protected body;
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3159.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03159ent IS
END c05s03b00x00p16n01i03159ent;
ARCHITECTURE c05s03b00x00p16n01i03159arch OF c05s03b00x00p16n01i03159ent IS
begin
L : block
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03159"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03159 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
end block L;
END c05s03b00x00p16n01i03159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3159.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03159ent IS
END c05s03b00x00p16n01i03159ent;
ARCHITECTURE c05s03b00x00p16n01i03159arch OF c05s03b00x00p16n01i03159ent IS
begin
L : block
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03159"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03159 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
end block L;
END c05s03b00x00p16n01i03159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3159.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03159ent IS
END c05s03b00x00p16n01i03159ent;
ARCHITECTURE c05s03b00x00p16n01i03159arch OF c05s03b00x00p16n01i03159ent IS
begin
L : block
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03159"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03159 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
end block L;
END c05s03b00x00p16n01i03159arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity div_inferred is
generic (
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
dbz : out std_ulogic;
result : out std_ulogic_vector(src1_bits-1 downto 0);
overflow : out std_ulogic
);
end;
|
-- $Id: $
-- File name: SpiSlaveFifoRead
-- Created: 3/17/2012
-- Author: David Kauer
-- Lab Section:
-- Version: 1.0 Initial Design Entry
-- Description: SPI Slave Fifo Read Counter
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FifoRead is
generic
(
gregLength : integer := 16;
addrSize : integer := 4 -- 2^addrSize = gregLength
);
port (
clk : in std_logic;
resetN : in std_logic;
rEnable : in std_logic;
fifoEmpty : in std_logic;
rSel : out std_logic_vector(addrSize-1 downto 0)
);
end FifoRead;
architecture FifoRead_arch of FifoRead is
signal count,nextCount : std_logic_vector(addrSize-1 downto 0);
begin
process(clk,resetN)
begin
if resetN = '0' then
count <= (others => '0');
elsif rising_edge(clk) then
count <= nextCount;
end if;
end process;
nextCount <= count when fifoEmpty = '1' -- cannot read if fifo empty
else (others => '0') when ((conv_integer(count)) = gregLength-1) and rEnable = '1' -- reset
else count+1 when rEnable = '1' -- increment
else count;
rSel <= count;
end FifoRead_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity tb_and3 is
end tb_and3;
architecture behav of tb_and3 is
signal i0, i1, i2 : std_logic;
signal o : std_logic;
begin
dut : entity work.and3
port map (i0 => i0, i1 => i1, i2 => i2, o => o);
process
constant v0 : std_logic_vector := b"1011";
constant v1 : std_logic_vector := b"1111";
constant v2 : std_logic_vector := b"1101";
constant ov : std_logic_vector := b"1001";
begin
for i in ov'range loop
i0 <= v0 (i);
i1 <= v1 (i);
i2 <= v2 (i);
wait for 1 ns;
assert o = ov(i) severity failure;
end loop;
wait;
end process;
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
fDz59amcD2ea+YXum3GKfONiBJG3innBsRyUxV1rlQ6FNkoMgcSlxK4oSOrp9LymStTqicyi5lQY
EMQ922Gzkw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EW81/8fUAjGFZlQVWZ19DYMecRfWlAb/dNiQn3NV+A91XEgqi4AUWVHT9kB/hDInZfThvsDIDkcp
It1yyv49lnQuenoFJJ8wG6MF4o+N4oR4sQm4+czP//FJPyQDS6VTzukywSYgSPQ/fsC64od3txrG
uijrf5tvZnNo8hhIpzI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hDTapXr9KHjx9D3P4lG8z/KVOZ1wdoMxS/J0v5I40F7suEMgNlb5jT4S9EWblCSsQyRbUZ2cJgzM
7n07b8TvYUcQEaZazJ5n4KFQaN54IdcngMDM4l0bZEYd4SuPpRvlZXQ+iqf5uyNLcovPTy8GFC+q
ZbiJ2Qc69Q0yAOp4n9cRZV8RhXPx0VeXmwCeJWrs9yQm5AmA+9qd+p0vymu3hKKhqPL3b5avcrlX
HiakdOlRulVojAao0jv6wCjj5yIDRPxF4jJ8vPDApTipaoGedhL43ZmHJA6F4/hjghTXAkTMOB2w
kwNgNo1uE1v5l4Xj/pAGFaDv5jUEHT48ERpaDQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
E7bd781u1eMZ4Frt/gBOy9RrvyjBBiDai/k5W0Q9P0CJVoe2p98APo3SxRo5oMwZ4pWOIJgT2A/Q
9nnBnAwgK7IpR03S2LGE63uCNpqXJuGJD+GIwSORDTMOsx2E68Y0i3zTWnmENXRVccWqQKs4y+Th
zvS6J08q/9B9RQE/uiI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
CpQQN/xTLl948/fZK1U2+mcJlhjJsd+JX0+exFNvqzrIE+QLcVxZjt3puwA+EoZZFvUsBz7g8hWk
jvsac65QBoBF/ZWZlQA2buttvfB49MV4ngXYXsbyiAtLdxTzlDpUaH2dp5xTUsgrHjpcT+CVy79X
f++f5tO4wI9ASgWK8kQhAvbmNCXpUoHSX1nKgu70hDOhPQgUYASwCniYA8FkVrmcWYd3WLVIlvuy
11UhogAa0sjhRLwn+G+jPCDP13aJnq4TCwLxHoZ20hU4Cob2Q1TnKKqLV2MCTDo0mNhHmN20R0C8
CbQdZ9eLGVLcsaamLpO1jlqxcL0EDymH4y9P5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 46416)
`protect data_block
vgJFCS/D/CTvRcP8wxhI+ZG6re3ln3+LWGs2BtEvb486albsgZY/GmkjwvA2oKt+zOlU2xSM2aho
cT1BDA9vdeAHrRl4VScAdbWC0xtGovMM6/OkJmImhXSzoQdLSVxIG4jneW8fn3ZZweUqeB8rbBXL
BxOVM8cuDu1C2cPGIIzxFMtWXM0bxbHyN5R8DEP9pcI7BsyBxkFEwJqZ9upWADocRKCxgjET5Y9h
A3h4RC1AlMv9bm8A3YF6bATcBOkEKKQ6zfQxsIuaGEzVNGIX52E/aqCtu7GQ1hyGjNKCYkgK2s98
3sUzV2AoUhNE2e7y7IStefhb7w8Z/B2Df4KMGq+N9HMJfYuCVlNAXkKJFZMHZCzHdY4v7ZFapXpC
oCBIPNRRUufNsil9OBfj4AL2TjB6eDfgjNUGCYyBXyrgVk84UeCSEraRvLEi3Wxex8VQ8a77e0FC
SqfEg/au36HbQeccHQ16ywlCUiJCGsDiB7VYOJGqZuuiUt/8HgQDpQj7YZStSrJP8/+eWcN84Ttg
5ufn/eidiT/haQkN/5zaaNbJELLozYhuxTj4zHnis+8Zbx/ZM41cq2XRfT+fuZirhv2qOAn8m8Tg
r3oOnn2z/YuRsGTlg7TF6Vd4ScODW60NcNKZihzgXHEdIX8FaGVEWyXQr3UpY+LOb3U6Qftf4ghA
7VbTsPCC3Gk62U5g5ENoZQ4lb5YKY8KNvFvIqh/woUOcywBBi00gExLrQKn6c7HzpZSucZmkJL5c
eR3Pm1ARU5MObfhgSOtO8/EQBiWVsg2NhZ4OwSOMuC5ylB7b3r1JUM30gxXqLoAXbUy0CGtAiVSX
rK0vEVzvbFFqeC/MV3APFmzHI6twhVzAshMPnaXUiWWfCkLq7ScZ639J2dFlPi/sR+y5LqtM8BLa
LoIsETVAdmkHt6UW8qAkKx+XJLFsft+svCm2PNIdb5SJVpu9vhqVdIWHbSBUqtYNsJEFXod8Ip5B
Ee6GYBR9hWhVf4HZ8PiND1lt+VlnQ6FyuhSkE1Xp2TrAPKy/CISrNd2ilkD14DhktDuyEK+zU2Sp
kAgqb/xGisAS0dBHL/QdmmqM6OleHpICkpWwBffcmOK8EzDWGV/hIm2NzzhP4Yfck5jZkUijyElO
o1eHuVGRySB3gSptjNnvyGO1XQxvHOQMpD/oNTmKgWwthpXYfyu3Xy+0mCDPr8r49LzTQ1ILFDCQ
mbxJ0XwhNRTWdlUCPWn/C8DJrpOH9skacoZW4BKcPRckC6z2ePVnzUVrTz8kkFY8a/vD7lwAeqnf
oy4jggOLwmeIFLNCFq4YqJbjB6m1m4HJOoOxftX9SjZdOBc37Jc2IiE6R5MKW0JvgNpw6+Er7PEV
mQSp44HuON4T3+XwARarpa012bOFrnDH4jPNw2qT2MoGkdhLv/3zlKSZ43DUsm0hN4r9ueREbyG5
LWtaJdnK/h849GijRkmD9g/N2biWQ4PKXXyFsLNXg1vMEirPlRm0X8HyAMn4exxiWOJlp5fEH0WI
i4fhcyymD8U7M97iByo+LgVAPS0IFGE1Ww+JmhV6StML04BXlTGNN1z2lxAJNH2aB7Rg/pMbGyC+
2Sxz2suj/ZXZgUChLHsmKi08fxZcqXSATCrqytAAoJCXDXWcgoqtL8k7U4iiSmwUGUY/xQkj+rLf
jO8efWor73rNtL7gQcjFZ2H29cadMD9pfJieZR322wKr6V8+/n3D4E61Fv55+OsAQYnlsAhBPj+4
yevgEHkoF9ifTlCWN4w58qxm6bPDjWCfTmzdcqohvgruWfz5Yuak3ovSSuL2oirxdNZ8Aada+htD
xGeHnOuK1aB7WjGAeRsnq1qeVhm+iGs/m8mtjHshxuaf0rcRiyeiWVWJeZIeVnZnwxiB/fVmDjqE
8ScP6mNxAP1/GXVKEBWH6O6CPQaeLxUAF3SZgfaThkgR7o/5E/tRWlTZAZuQkxvDCfstRqZLO+Bg
rtjpxoL4HmJVYIwpNSspRWwJjkG17fzC96yaA0EzPFC6LL3poSz6OpZ90nsMPhyW4E12a3OLmFpj
sz02VWc+N7ckTNilmgylkNPgNmAu9JAD6PfKbzHEtSOpoRRHDtMubn2Z2pQDpchDONEiU78+Kmsv
0ey4itjYVfFnRQO/QqCg0b3dw73qEAbkuswYiJX9KuBKgYv1QPG2U0UYxm1SSrrzyGzvXre2065F
7rX6JoQROZENAtGGaykqZM5EpFKsjnr9DIBBjoh2dB5SsMrM+rCjNSfmw6ERZgngo5Gcud8EDW+W
CYQvqeKV6VsOuk6Xn7DA1n6PRV0+ooi5SHZlH9HEgVALm5K7wjWJpkHnoZ7WzwLkrowCHPItZKM0
dScUqT6l6rWEKbcqSfX9VoBxZnIBWE3z2z37mhI6xYxsKD096b+eQAk+pmkkY7YBOs9MMKt5KzcP
w1lpR/xKjzAR+tnWT3L1E8AIMKu2y9sCa6OjP3ISzNWkyNOKgDzuxbAH+lTkt+ne3c+sjrFRni9X
YqlRd1v7fdqgc434WLY2DJ2BtKg+eaillDcXobEJAdAXgSrdWs+pQBILAZgNdEei36p5R3PhtePQ
iMwBArxKpKV0zLJbDUFTOilbtLiv57q1VyorEs2jsLAntnEqsQdU7DkHGa4VLU1YBfFmw4pAuW52
do2fYJJoJBH0k3idMOGw5ePMZvime1F/rHu/xzs8zmYMmX/aPbzUND/9FPpmq0BOQvTZKtXPx3DN
iY1gZdOSPQlHZWce3dDdYDhaj7zE0MBCb9mbVCWF53T/d5VXuWYodVeXofz5svJm7wS8FCBvZ0DB
2Iybz38u7ic3wiatz/AJf5aYDX4DSBEqgRRmhCxmOjFrsqvAmJi4ss0jLBpQ1qgGArdREpuMPYFO
BLC62d81p/vVyp44F8TvAhKpD7Bw2uIl+8PoNExXjkQeHt6Ewwrf+NY2i0Bt0PJYymB4mpXdgM9i
NLVtDZEe0sWyaiqN5jtlDB8zmntqX7dTvzlhuqfQnkQyfouHOfJbpoJLGO65jLhtWJ8pjqvYFsGL
lCQQY0SLeVXr5qsIGgqt8HHdrmICy+bD+EbvNzpRttrYN9eMvlT+OL8liENJiu8bTORFhL4G94FS
1/1NmExYi5bTkNKHtcqkity0ifi2CO/99ogINS0VmGC+Bkmemw/7+qBMQ6FmwcksiPqRNwt8NKx6
VL0xtGZ70L/T+8WSUjLmn0YRqCGriOUyGj/NLoJS7jyKh4E4SjJtI9bqBgTcY5dl/cxJbioJoQaW
zqQYzHuda+mBquiQ1FVpWdu7hMZJsNrRpGPxEHgkbmfEBWrHJ6FuHZhyZYquetNhVAWOvQ+sHKXk
M5Fh2tFKAllBnXnYF+zbGNiedbhzf/8/e/US/t5+FfF+jNUy70LcMWjnFd91uxvnbpMOqoAIswkj
b0i3sInIIlQwo/CEkXBDtGl2xOUJE9gyjIoRyP5zPG738pTkm6TfqUhZvvSsT/QJ2yp5d5dVZZm7
FjNlBV5BRPd5Z0JfbwolZCHSPv6uuxYVaYd0RO6b5TrTEQKAPuI8hVlL0gpNmVyoFx4A2hvVEdD+
OxsdLGSOi9GbmF7jr6QYTEWt9zVR4pYfhk5LlKF7ozc+tQx8MVc07Ad6sGDfxbndJz0Qkhu8b06G
urYsdQV6cEfAm6VFp6P5G8aQHYQEN3WGjmW6byRqYGGNrP76Gt9GM07fRtRMr8UAmIK/WvzMU2CY
YOOyZMuWuEK6z3m/dQ0bc0r///iIm/qoji0NceqJgaW2foDC4srA4YLU2JsSKxX6h6To744mCWTC
8Q6kciAqEmKcErnyDPCbxWQsexO0vCgp3ojikr+5jFWDYRdb5L65tAdyqYIXkIbm+uPLZ/RfXCKl
qAdY51BF8amjrRsUtSroQMxJGm0PNIzDU5ONoYQ5gYVIu1jacPSsO3gNQKc/NYLYgowecaiuIK/9
1jABkeTryWlv+KmshPf/oG1seR4WqUskYqbF+Y7f2dQjgFfZN1FPXF/70fOluQONT9GrRWXtjfwm
I5bDVORKjspvcRkgZ+bWEVuzDato8A6sJrUUAdLVtoY8JuLaxnDOhRCzXjcfKJ8KVws0xDFv1wd6
L4kIFjvXQC51UCE0d0c6Izq074sLnJJ0xpPJMIgYfGux+kRSe7MlNhILhZdQ3Yl1RkPWSNUvFDSp
o/JRiIkgv7FjimPeHQvTNResy5n1vruZVM467KgLVAyBERRY+WxbPjxHKo2BCh/B9vDFO5fxtIUu
2iDia1032b3N9bbaxPp8qVlqfzd9ux02B45fYWm3O44u66IDRctbLcHm0hwxc3GiMZCqVs98vk0P
9s0D3jRVNaeVXd0Yy4Gfm/p73DCeOkDqMWEijUSQGvlhT80BM0aJtofLRpCMbJvvmL3CQgMK9CSY
XhGudwMsQGltaOAPs3befa6khdrJjAcb8pxuMpYO5e2B34UFbPDZVJgJySIRzZD1g1tHLuH8GpPI
tqexneauPWthmsAr1xE/GJEz6HDUKHupIDIqzIf7WFMjKcY1rQVi8q2RfYFQYp+vQpPRtDRFFjiS
HLEoiSZTwa0Rsl/25jMNQCH8XwmETRD+jocBVOWP7U//UMFgfT5Abvt2gwNqhhtC6AvD0KKYtOse
fADL1GUKtgWL8jMKsADXE5JkVWMi2TaMsVhgRl9rSc6fAo+muFa9YZMt4IjeFFosHhCscOigcNYM
zGTPaZHEhndwW+25RgR8Obt5ozdM+EloC2yOatdZRHWN4gGGZWgFPCfJ7v+k0xWYo5WbbFm/Pqqa
9VEH6jhTDDHWCs0nuOdYTguGzxJNJban/i87VzUD1pj9olHkw5rOgSRixx2FEHXIoGupIV6szq+w
2VNIs1oUMRqo/wQtJ6FDH9fG7zFUPCVOS0LG6aBv1uLkr3KrejnFAC2XaN4MYARXtUWhx35EwLhU
YSjMbZPxiw7W0U34D32NNyklcvqyI0b7geldFOxm7IIQ7Pxl9CXEbXeor8vB1XdtW278Tr4kG5BM
nQJtwAsNRe8oPiLzG50XvCX5uETmcHTMmtSmBXUbqzVP/s9ufOn70IAW221OApnQ+2RMK30iFoMh
5syIOQ/N15t2DLgdSGUIah2DcbjeNeTg4LiixjcaiFtvNHLoEaFrc0/Fg22uECRQTg/D9+z7AAYG
u/aJdqUD74ML7i24EEyuhM3w6Z9CXR2vVRXNaimJy3l0x12W8+QK5XSKn3UWeHjTpKG53ein5D44
I0kUzdFfPW3urnRrU5JHeHDcKiVmXLs3GhY4SYCx+FOu5JOZ9Z4hR78LS5Z50qJv9B+XK694opF6
7NjAMO7F8BWklLJIau55FeQG+E39YdlcxkXOMCn0pJKDzVFnixWLhM19t2nvfmA0kEbhrL6rTM03
BJRAxMMsMeYwae9Yc0KP0o7NUbGm5xYqGxI9TKmvNqJgdBxlEdgljmS3gvVGyMikUiwq1jlJr3z4
REIMaZCqa2vw6T8eCCqxOyD3hKgyfnGmtgog9v7GvNi+sNnlpPhysaP54B7AvtSe4Ax7gWKDblMO
3PSAzzECc6UgV8srdjhOYW49vCFAdxBlc3KRlCytiejAB1C3/BulX+/XgxUkt2XxEgU2ZLONrotp
nCvxGf5WGi2rPZS+7NAOrb9SD3z/h67pV7GDqXLRI3fXI3IJ/wCWvIYsYGayQm6XdahlL5Uur/md
l7G99eUQHlfc3pb+r0zbTCV1+qk6HCfN+gW6QJnCmIfxolx3V6XOsTP64C1fYmlsDKZgDIceo1E3
D/WtTApvtd12PbhSjrxFiWfkrXDTl64vRdgOBSh2y+7OCD/mJpjvMqPrds63rP0Cl3xRdGZcRYYA
jUnbgVsiqsgx/qkXGGwufbEVCYwoakvBRlJo4Mw24O0AKRddzUzAO8tZKm+Hx2TJHxqMkycs2gMM
FB9wsNesZDWuQbYkYfhrxdxjVMsCzwLrdkKNHySpcqwLNs9r3kLkqnNIfVULf+C5kyogRwpPle/y
p/hnWKBWc/MUK/7pdRu8riQMILBdcQEsr3bcjc5cPMELwx8xukmEGK7Qy2qibCfyJA/DlfjgaiRk
9qxaKep8IrATiErv4hDM6LNrTfmDPOLXmkoSqsZ87u/MvPwhlrwQ00SIyKtXue1jH+jQ2Karopq+
EXHLqgGcrtaf6gkE6DgAAWz3sTKrgRgUzrCwfigs3mVdryIx/Sysymh1NKFF207x4wzzN58vZUk8
fKByHSwz7tkoa7OoBZikuLkz4/F7+Cm2ljuoStc73fgRwpa1TnD0V+k5SLhiWL9lQ/xC5F1I7qTq
wa+Y4MEcp7EvQzlPQVhbKT17Amy4fJsAkS63tvGxUsusTb0a1OPASOO4lMJypyRCHnyrvb31yZW+
o3zJaz3Q1OLPtrYcbc4v9HAsxtqSvE7/KQt+8zh2nxHGi06jfmhCdl4DceV/hgbljJhujKO9gBUl
imARZqw+rdl6eNSx8bYEKa1ykFq/UQEAb0rywpgp2/Zg1gruFTMSBqzYXYnRbpIMoOxGtTrqGvn1
w0a/q1p5d8xqeEFOu5VlehoKkTc2zC4F/NRNKrkniwPwZrGXsCgCAL5xSCR5G+ir984+50Ce8+I5
UcofwUuO9sJWwDxrrSbPRBNuIAaal+2JszGknM/uyOpUU7LJtdfdtALs/lDix7BULXE66IO1lCDF
9YoG3+3Igo5MXtbmOXbmvs2S2y7niTUi8agaRpVD+aQ5X+nSb6WJHX9jirQVzCwaOyQQD7WFCdr1
V425melFTnNH0LtNxzWs1r4cf6hTeF0xczU5H4uQv7S1gd2PlF3BTVG6EFPCthoRoxMn2NBr8s82
oRUIBUP/1OsNPdsH/2fybAZUaD6sfhXjBx23MZ1Zb1i5kXnAT4fJ5PP6qIp7V5LwuhsGhnkpxHik
U07Duk9DyMmdtQHFpluiwPrWoDb+0jOZZH8JyUrLHjvcJg3JC2KUYjQyODsDlR4OsgAJUmXYe5HS
p8KwKJ6ZrKVfoprdFsObTz8xfqwcjwDr2D6235/NKDXqRQGyooWMYPTMTXTbBXNKOkwchKHHizZ6
P31e9nx226vY+wFSajFDXsJRlS5jG3X1VlmbMO/hRiohaOQh5VRTRcxjB7l3G01Px38HDSRs/kr/
sZuNHI5FVDtfmSVV7hUuxDeZ3kBfhF3fha+mi5JPAcsjUsWYMtYDPvKW2dgvY/bxGLyy3GtVCv7X
hW3dPQwOkGdOAFdaGOknzToOTON4XVoUTIg9c5fgp33bEC+siIDA4AZX9J/vWR784hHdnFrq0dYF
o05PCxivxzDA9T06PysM8XvlU/ixbBqoLELJMjKUtWSEJ9fGwTTk/623R2bKvurnR2rEAwkWLQre
VvsRCWHNGZBLH3oRM6ADvvZPTjK5KqCmod0PHtjuBptpKg+v3tB8RnRQXNkscDePTWlVpmM4npGA
ezlHa3NezH+wfTIVjSO/kzwzLa1PCwTSp+FSGluyNo+JDlcqkpHdso291UH1c+ag7l8+yXlqHMyL
+SrCFKJUhSLiS/rxZO5pRFkGR/m1RjTC+W1MHqxSxN44adbd1pqUKP5RopDnjGZ6AlB8RJGB+mwB
kuFDSOqBCbqP7SwHStpzK7WhK21Kr9BU/NrkX4z1c0X54G1w5FVPlr2VQ3PPUanxJbnNLfnckg3A
buo7sCnKEZAHhKiORDOwL/0yXbWtTAZQ4CIcYxVYO6fOCeOyfOFrKAtTeoishrPOoxwN7hYxRzqt
KOk02LChYiKQYCapk5b1Bj1lC//NhvNw+NKXRS0g5t1FpwqJlWt0LtU+7wrvTGcg0isOjR9ZBsOo
3byOjBnNPNgKRzvssaIY+OL7jJyyjxUKdqrKBunGRzoYMiFMzMat6NcNW9RqukVJs7faY/RlogtS
jmzEiwuMvG5j2i/4mLZyrx5td/HutgDhbiVdd1Z1cFISslIrDA5xiuCoPPpeCLdjAU+5l4sqswT5
stp/v6w1GPvWaQNdkWk57SKngDl34WOXTfPTH1+zfkDEbvuo6BZpHfWIk638iGgXlFqf4D4vmpqs
6Dbpj1/avOFInPLvgtPYBx8iCP7z2f76YNA70jZSRF7ani7vLsKOeAWIFMQJQH+0mAtZD6uPnyMS
/nuhe5GYsN47bDr+Rl8crPpGX7gAe+NgwBZzAr8DT+M5J06JSFcd0fkoHCyzD6uKPF/SGw3TKR00
c6b9+XZJnNyJ5ZvK+wqvy1jGIa9poaDLE3Qz4a8yd5JquMsgJowDe7HkFIV/duBH1OsMYCmS97k+
pbwEXBD7xQvf1kfPuMACZKrLIQ/Qfm53UlajquZPw0nSIYKKnM9V64W/8D/CZUTkeDV+EOgA2bcq
eZ8KLs5+LvQx7bqK8E1qOmHKUVTzXY9Nc0kffweFX/wLgLmdXNbVOaFhrhzYg8lr7Nl9lNAwfmoV
cWEkcbUopNFL2O93QEeCYlMCnOyWWuf4e+SsqGdbYr5TqYxSv78XgGKbey6PWU/BiJLl46QzxxAC
3KrXD4VT7kHU0lNfw0Qv2YfOAkF7vOvFhNUA1TAqGLAWPpZwZJRoi7K71JPI6FUW4VoLCVXh/Glo
7ECy0xlVKGD6subXBb4WvTq0YMWEmQfOMNhu/se9O/X1RJt8t6vwrqaSS+F9Cc+svqgG93rh/XN8
IEUrQtbmzaooqQ5lANNT52roGNjVtpS9IjUVu0gZSrmk2UVmi7nhT3eQYcuaFwrTfIyVv+EtuUyC
etOnsEp0oaqmx3cbPBQZ9IqVZAqnAvxqakLDf/+DVnvagHIY0YTmm6T/G5dvvDd1me6rlxNFEkTb
LLbJqiS/Wd7Whd8rte9bpCClb6DF4ithTVutK/autLk2KsuvynwEQHfN+dWlBkrKLPvnUf9fSrUP
Y/Lg77Ppvszz26jlHdqJP1yW7k7vHM7mCjU2bev36dWYeXg6/L8nat6mpWWtm+zRoQkZHd300+Az
JOmGkYxqtv74bQinO0tbX8nW2jXpJ9DHk38ckyZRnjgC3OrSInaiKsHBlpRkktEYTt9YT0aV+qbZ
NU214I1BgKfrnvIR4FLEcwv5A1HUUp2YjZpRQJ05IykBmwNc09YA5iGgOEWfAyNFLF2USLn+Ui3x
8XT9CkcrYSouFk4g5y2e8hXkIXepQgn76Iz6D6nwiyr/vKualMSAUnMCq7zS0+586Xa7/yU2Y9Y0
zeA5RynVxRPIh0IleQi9mLHGuyRKLU/JpE6cFyEnowhBAvmLZAS6kW5SJkQEyOtzv9LPnbLzl+dl
gj4MGIOTH1RI1DQUnJtam4Vl5uL5YjPlicwhCDKzUN+R0ozgMSEqqgz3xRVAwxeUO99WEP2KcEJ8
ySGLB/DK6mwwQmi2wJJrEOHmSOv3Sycoidh5AySEmVl8I9z/qbozdUVEZWRvKb4wD6+41plnpUN+
2OB1ZPO4O7v6J+ziplfe9036cWi3OPW3l3dyzqka7CkZ0vde6ufdgyx2PpJBqjlJzQ3vt3qPsCS/
bvGQ37lf9JQSFwDLagqg4LC5cF1rthNAZ5UMEqAKCB4yrvwncl7qxNlD4XCVbLGCXWW0xyoJgfBv
PzjaHQuLBPT/oZTQIICQIJoak6rR3lOVEu2VVGGfsFGkuh85qKezQ0DLBxdZUhpN6ykiIvGXfUt5
3I966qbCSjD8WCqd98t6R7XIoRcSOuNi8DSqbrQwfjrjcdt3TsXijHr/T9ukc0nkGmufJRc8dnDT
rVHzPN3Pe+O8liKk8Vmurr8jvoCgGZXgV3qGeK1kcPie5gUu6Xtse5nZKFerUoBEdypA+qGgbkWb
AlK0eZhDmt11yRVW1wn/d6JOQEKYMm0CznY7jBb4YCyZAPmRY4GuLKeVSD0zqg1ML00U5qeTOMEq
jGby/rFgpPhtli8c4g7NC+XVhG9mX0ztu0Gh0PUDt5s5F471RYzYrJBgK0dMD0kudH39Pqzj8nli
WcfqjFQ4zgPpH0TzWoPLgy8t/ylpwY55iZUXgCoK3Ixfnmi4jHsatQUBTbcdex2uHAThMbBjXUo+
yDAO/rrkkg83jA4FwD0DzPrQyBn1cd85Fqpd3Nf+hiWfPE75rvoYwYMuD8DN4vEGje7bGGk4W14Y
jqh96ZCWldyc8UnyjJDhRk6cEu//wK+7BjdVDyc5XZIYpqc6LZEtTz2x1XGwZlKG17Oqjlyi4ePM
hz/0/GJcdLzI3SMI+7xBUvKrzRD3XPYLSSekpZ3bbIhoQ5L2+gx0Zedjm0BWuPcwCepINnbbtt9h
aUB37Kr0fwo4+x+OwnbqUYZBT89M7MEjicu4Idy6L9l3Babjy5d5ZUp/IYKuMMI3ngE0drqoxaWL
vlhvn3UENy2uJRhuJAd/QH6YoGtugcOBFDFWrn8NdOFUMUnzXDvPhbPlFX33BOGYMpsnMIvinnuC
2JYBKsb4w+YglyDgC7nKzU9NlsabAiHWfwzRGNRTcz3HvZ8m9e0reW5pPmwKi9bZzaSsHtAexZ8E
cmOB6RDpDwuL3i8PksHwoZKekjYOXKhM7lrYBmna4x4BKb4Un18q2h36eDn0b1SVO7hPU0zsPbrR
bDwIl3jfpd9V05wRAPcye8NV3it+6bV6I/14TIWJA+9Owrlk0ldRhHK9NlQbaqNRBM0rPqzmQduQ
C5I6IpWthh4OECZVkI47M/rwgW6cvYbBvnD32dVrlDDOwitzXrybkMMeQHXeIrY8brvggz0zfDPC
uzLj1Ht5bbxpCECQm/S2sjfVndEll+po6mTaWQzVwKOVUqxoxM92eIrflvjQh7R+ghnNaJgQ5cZp
z0iKEWzAcFoVUvtrVwtr3DG+T0I+4zOljwk6c0cNi7YNPrEH4QsETWM/4l2w/I8TQkEBCna6YNLB
32NpMYnYISikMxBYrrSq+059OTD7frVqz0g6dzPgVbT4mzEUMWnPonI5DiRYd8KH3fHTqJs240Nj
Wy29B/puQtUx/Q332lCVWx0EMd8mFGS5jPLj56DvrRj+43LvyPcy+2wHNdoO+ZsjiBIfuxmdXN1f
tU8DF/kkqxy9fRNzGl6q8StlaOOPyYDRXzlfIkmAj2Q+4/hSKBxj+bR+xhGT8D2xlXs/qKNMTwHw
LvEdWUuJMi0cni/A77P745jnEUrDCkNBSzI08QceWxWjuJZed9tz/riLdZXOIGgWpIJKVs6IlqGP
s6/zEbOHLMcuEck5we4M519HoJXTXl7dXDYuG8J4mY1wcJL4aebbBi7KDd62BcAMz/GOFWFI24M1
nsz8su2uC4g6/3OxXy8Q5aR7teVW9PkaW/3cQpBIj2A9Q5YLvlEeNt6L2NKJl/wRnYGjCAU86/ZV
NwyC64HkchvY61+1Ny4w3Hrpzo7lqnt8v2FzuDVobEKRQkc/IH45zZkCEB9tjQICwh6EyPCLsfW+
vqNljUzhdeBoP6thb5dJm9Jph5HyPJc74qRylIRsddVPOb8L9Ib82MsuBk4GDwcYwLoUHjKTbK9A
SzfQlIlZBf24wMEcYotYI74uSMn+M+gJ03ZJZxQ0x9ick+7GlZ1DQTAOLtZouzU7XBW1L3/swpKt
xYJrzjs1w/zi6oP/TT6khBrR0YlYve85Y7MUrZ4e0We5cdnl4uRcZ51rA1A16Ty6ipSnubp3ImjA
DG7o+BxKxuxjWq3EI8s6d6VAOaMIfjwjvrU44roo/pQ+dvAqfyDLySueQlOgeCzpgDdbvXM7Uq3I
qWqLtSyzfR2ZHH11d6UpxDADLIS0elScnQImKhDBj8sNjTmGAoVj+NwpQsIm2gi6sWMwWvLV6HCI
cbi1OzvJqKcNaove5NZacdNR6tZ4HUmLCcQk5BnPdgnLLH1D5fIsvfwPHXI/vOuzdA+uyId4B2GD
BuR94nwrq8TlZKJT2MSrNlfnwl/z58NU0dra/LYsvBc4UZKGwYrTfE2OsTkv5L+c93PPYPYsXfoM
udaqghZsGlBMBR8JPkJp2+isIQIOrQChRuG6vi5j5H1H8x6juM22mz7DRf+VMkAw5RAhaYudo7N9
vYBtHiIdayLaFMXqDokjvHvV30X1G+bJWtprDdtU8G19vIS1DVcXemfkmfg6wtDDSfl79CHZri7e
0kV3ZLbKGDv3wPF3aRZvm+SW+EG6rjPcJVG78IhoCCymJ+22LYXou/e9b2iyutzs+RrqOzwJhPck
ktDiNfemgDkDyoNpuVeF5qn3nznCw65unx4nJvneTDFbjgvx6p53U1KrP4DB8oUwDWb/RDW1qq8k
hup8ZfKsn37WHgsWfIkntEy6G9dVenbOrpX/tmiIsETC1RupYWrQm7V8yZy9/pI4yA1y2C3iNpg5
rkt9IuiwkEKCa610Z3GAE89lAEVbZajehBPNmpEpARcwlyzPNU2/yb4JoE8Zj+pA/MTXa73uBGeh
VXoq7mUIC5zWqXQkntPgudaTLNnwU71LsWM7eBnkNaBLd5zHm7lwcAU5G7NkiwkN/0CA85dRfiER
YPrjGXxlTzhHfiw4tcPLik/ZvjNDNAZqmIY1wKm3fDVuOv/3Hpley8hChULHMXQdYZv66D+hq/1F
IcT4vQAxwW5WoxnhTsbsSsEJuGY3cu0878NlofWbSMfjZPhTar7ZQEZNRPfRdxtWzN/EXc1Id+i1
xkiTU7PJvEAmB7gmhUQAifb+D/h/wHCuYGykZetf010uBLDGS2P/N6GfO97k78i4yl0+YzX5K6h9
Jr/TVBpeCXwqlHZuctZfuS1UuvwQcrjVEpMbzSW0oHNkYHYx7tHuDIPAVGcRUJXDn7f3s0z2SrXA
ekcthUaa4WfsFte9MO3dkCCnqYTM59rmORuFKTRH6rOz7OqfR4HcKS+GPjPyKa4I6JzNJLHVq067
XV6M0M0CEiC2uFCM5UVUMZr/WG1tN5IPnfIlN4+OcsPgj45wJ51nQ7U3byFtIN/MtxlftgRM37Ga
Zd/ksRubXYkRmV5vk7iQY3WI1U3r0dBjje7EUOLN+N2vA65Qw7CJQx/36DgZkAUY9V0Fjf5po3xQ
2snqub5vLoX8vkLZoNMwR16q84BtjEOyWbIb7AGjVwk+NIVHvlBBIFcYXxPO/QEUWQ2pENXOq81t
m5EoUERmDFxAn2k6GeqZqsptwRDD/EO7HH4Q3M0ksiGY2IDK5mDKAhSlHVzH3CM8/1+n9XbKjpdp
06Mt46KxvaGlxZ2GkXa8qseNiTYJECsxdICmF5/RXWzLqlGi5amuh2fexschYfqdRAadbzn+vIpL
h7SweAys9EGrCu9guJ/T9RmPzp1h38tDdqhT8ftGfMrLqV23+EOCGFHIpXuBHl4rWeofOXAm8KxC
mNNsCAznbDosr6TQuzPfffKqc1hZqOszcswpIFU7VUtJG0xfIIr/aCosrQz1kQxqCnSSQJs6jzK5
QlDdoO0vitXelslCS/MtMaV91c6DiB3o8biQsUB4Vc8G/9B4Ka93n6qm1EnuSE0/cA3NQ922VVWz
/2Phna02ZgHI7HV0JUV1A1vG6DZTMVvHv+f/wQQJoaRQO+IhySlWjjtmgA8LPZY+/ASuVPs6jD72
U8ma6qBiIuFEds0aywZiFYyURrObWCwSZ/u+g79pfT8eZ67sXkVU4VC+lMkbhIwuPuP8nRImx+0w
Nbzd877FgcnEv/kOqR3/Bmwi1loj+rqkSA17Sp1tByVOYmdqmI7y1GR6fpgACh20Jx32ciEgKtd+
M75GwDYTYdwPZ/YAo+nnWYdClxX4YtbmXZ3Ij7b7q98IfSVdXymgeebLCOOcv9nRvIRDtW/ecUWW
Y9+mxnKXg8y7fff8yWqWIGBp0N0FhCkIOm2hD+nssFeQSsA1a6efMateJPZHVTQdm/TgrE5q40FX
RLXS3wVG63pQjLMBO+1kUlLve3dwRHFjVZbzOZ5dPrhWqzQjnsKTrxpWBgdaBRZcSn5QkUqbUKQf
TqXxLHIFSEWzbWYNqBfO+NyxfA4rWjRa6ExqxUicudNzBK9yZ0bU/BE4u6B0gHGChe6iNL+5hXU3
MqNtDHKB1Vys23MXV2h5q9+i6hKmnno7H9epP3/ii6KYdCg7erMWX3CBV4+g+B6j7YwB0HHghL5o
FgxW1q5X+Hudx3ChFHReTCBuAkSPZs/2boRb/EHE9+Bj2omnAu4dTP3hiqNrjpNw8q3Myrf7FCkf
AElz3jBPH+YM0X0kr+wHpkw0Piw1zyYRqbEEyj+2b8/juUTz4l8f+88Dy+3cLDbrAkTMPCRHbvwb
mbNWl9qiRjqWifwT9V3rJJ+jbMrvDah9tdW3pSqHfhhRnHJSh6Pxl1PMo+Q3LWy54oAK7/UTfX42
Kp1WE/jV1oDnehI0Q/DwzWzOEKQZ8w6J0r6UZrqs1pVU4SU92R5Q0jTe9RR23JL0uOkTYrs3qKNc
4ECBv2rX6thjlOMKL7LHGLxjeyuT8zmYeWYP1ufYGEbrjSqxDsjkmrLHmWo1fOuOaTkjUTokeRlT
/j6mnpVUrCjqAj4gMhkiNZOW+yfnNk4CadayN+xssktyIi7Fuichzdfo9amGBaHnBv5nIvk5lOEl
5a8bWMa4MVrACyqV1MfhKbPtWIvsL8+aKdVfBay6RHzeZBbvy3isDO1fwiznZgSrG29aFxm/eqDW
3+buaNlda3hOho+KIKEzvpnPPSghJGgmmwaT9zdjNK9+Ua0cg4XIN90wn/SRNdf35ILkZ5wa253A
gBbV5rW6Llh8gx861E8LLPOvsYwPzmHlE+sMVULgHFf2sAjJ2UI4c7EuHDMVXkHUnjYaXzc7wMnq
pELKfrkRQ7iMv4pJnIUM3gQUQhS4qTj4Hy05fNu5LUUa9n4mHibvneh56QSlNXr53xVb6P2k/uJS
yOhX1aRaTsRa0r6thnNI/kXOe43vYBCN6qfehaLmNtvKxDhGhjaoxr0BPIVVqPS/IIaX6arJmdkZ
OdNgD4SokaDYnaz9m1e9n+nOGP6hHbW4Cfd/5+wcn6m73hAlQezpuScVjhSFvNNmq0eZ9/r8U4y5
9mx1swOLcgsvJ+rQzVX0upAnzM4jAta8SE9yoJD7xJj4B7HmBPgVBeLPlc7lyVVq+RpdypJR/GXN
HzspjXh5WrsR/uDYu+iXLoR5o4yQS+gLAPIiv0ADgm7rbY2vjrZ4A/gIfTB1Tex0ROp6k/TwohF0
p1bQXVkC0GBkPSJstEDWaD87/fVRU4vSkBBIWLbiZmh1eBdUHrX66Lbk350WMv0KiSzjoloGkt5f
U+OgyWEnrVUy3U95b6k7hxbZre7J/TxmR8LHg5TiuRcTOVEntKn99RjE6diksCDBrbguhfmooFfB
5yaIXQsf2z0j2LXflEpmzm3ozL0cJ8KTfvwgB83tjiwPcseFlSFuvms7UDC1IA9nCCAoCrtF8Ekl
2JWIGmAtpeHuTKAw5N4EVsSBjNsmOmi4eq5uo6nJjlk9K8pmEqqZdL4dv8Hcd1VZLnuTaLzqAI2L
kx0lzz1WY2QxVhSRvmDFiC4UH4QS3RNVjosrnq/q9rmsYXrvkTS7sL249vD4RHz6Ceijh8nHJlQY
65siYmL0j0nVDYIo5CINpNye0Zai3/TCnYnIuDuRVuERa8kS1+f3hwtUb3Tt1TIeYDGu5MQ3FVVT
ylMamHD7Wb7NxBXmtc7RearRRPx0dDqUa+N1fk2i1ylOdearNDYuquz7MIQwShulUOQjfdt8PIlL
zcgumhzm/bExgkfp4SsoTVgExjKZmdXFbcvT1axtXuX7XUrSMGJcDCHcT7roeLy+bJwf4qIhQbHf
IKy35YAxTEFlkLn5X48oNClTcG9AOPOdaa+3O88oV3Oy7Xh3jlB6FLxZzIOk5aMO12D/+WKAEuCD
OG7r2YdqfQUN682d/TTcKGyynEC2dZn4agHNoA8kHSUug8BpYE4nn/cQrSW40pvUccuJ4UYVvlPI
IZqawPk8XdMIC3W+gjx1BOjEATRqOfotkPuJK82W8gIuHvlPkiLWX+oFWwP4tWQkLmwZAnvPwaBq
/SHSLHXlb33sNzDWtrc8uYdhWOF9ZocwMZPIbeWUj7f96oIE6SgNhdr3IIh7FC/vOrnMQgpVqALi
5CPcLjFudfFMDelG7Y6kTAS3Ohm1n/UBzk0YcUlKd+LCd4ZJI3k3MMjZIWuGmpbrRbSVmgyE/2Xv
uotAIRcbIcgbH/FcAvc19/UZ4u7R3kqfSucyGxuHfdVO6XQCmYZFL0vpESXgdgAd1JFoe1o8aNOD
IrKOnWdyYnqVHy3m/5b0SMFzQ5LiV8MDy002yXlSZORgxLTwMpPR/w1+CRVjIRG9w6Fb6jYdbnAY
HZBM3hpSQKsLgnsSQF2Vy67Vadw9ZWn5m1l6Y89gdiTXqiLiMEnO2zRdY9QSfNTdvaDeXLRO1QHK
CQJbbB2iJ9pUleW2IpUcer8VbM5quFItMZqLIIS6a5T8xQ5PKmhDBectGZxctS5AwUGaiZ/zpAJy
rwMzomCVSwo7B7lIGo1ESpbgikFBBPNe1RgYlotj078jhS46uq35be4t4jFJYrQ2OnY+ovilsqo/
HuwnHbkM2mFM7XUCH/pdHUIzk5QFnnPwkNFk0DTQe3hpcVckonQciUgYKw+OoiTme2PmGxh6ewBb
xfKjoy4A+kI9yIWFfVAfd6O/Ygvv5XlNoUUYA4mPcRMm4ERn5lTDdMMlBT19zMTPSl8XXHwIsaM5
GqePWeohXX7o1PjxaK+6I26KO5P7rOQOlxMiXJCrEGu/RpT1ztywwbGoFFCxC2TbY3zJRXgV71Q8
KMGsQuuVYv2q2Ee8kqQ8LDLCJkWkdSBZuhO/+n2WQPo0MNZMmm7wZ80bLEtvQQpX6434as9CxhA6
YR0/0/jRMVIOAckn3KgbYmWkPM6++Wu91iqdMjtIKlAiU6qEtPJn0LjJdsQ8hMjaXODge5Qvv8ZA
nxrNG2In8vHcWgVV1L3gZQBJrVBWGImnCx55VmrKP+w6i1hRkkpKwUq60qXjrQSSg8dMj6ZxZLGc
2cd7m7VYYF1lYKG/2cT3QTOeNhKuM25xY12TowCXthHiJuqnHyqV+4C6h7AyvA+AYSIGYD72hxD8
QgwXrXjuWdm6st8zVLmvX9qHw/oH43DSWGfCKgcqaA0TtyxOkS+ZJ7hr10uxG++vipmzNrZ9G+OF
6ljHTE0BCbMlVsHPn/cKFQYP6zpaHZKJ58aP71yL8zVpcUzAmyXID5rGrvvfAZSoVEGnrhhnV8xf
9DUYapbwbdEQP3XZN1jKIt8v0AKvz+lO8YcHXcJUGC1veYmlxt8FDTr+dWMvkubootI+8zdT69GL
DDqaB7V9Yyxz/hOKgwPu3Hl9IzL1jePOm+Dm198BOoz9j2/ZWEfgrgDI1bErzVWMojY6FC8kT/UF
MykG1nBVPja7fCn610PtPrD48VIjgKJwpBc15djRirEqoG9JC/btSTdmFfUz7rOvOv+N4nT12ldE
v1u0vI/tUGoA76sYZYCU0fgAFDFIh9SzMIws/67UOLUv/3BKy1PmGkQsjEjdh4KWrdnTe/xVT4xT
2RZ5N7PH7/sc1riQVtQ+A3DrXUwcsWaOogScl4JTvpG8+nTiKQXde6LdtdhrtjmHfVVah5lNYZ8T
mUad5U+b78qYs7+VwEZATfY4rkZU7l/izAeB234Cq+BzF+0JFSwfQQr812ijyh6jDXfb50wj6WPP
E8nVDUwnQl1VEu+xsLu8o+pWHXPcDc6rvgBuAqR+KR/GGRHTxsR9OcAI12btoRR7UlNDuCPxcI5n
roCOnADNnDFdb2yglcZDAbe1zBtV2XMq7sfVuDC9Q29ZuH8Vu1+agQgLQlkI2qSpDYRzt1/TS5cJ
AyqFwqZNlgzMXvpzYtx7+s6BRtTQ8COjM6CVF7D5EYTJZKqFJPeNdUCgEptHIJB0PJOhpuZArtdZ
STEwDPUx76CMKSD0DSbZejcArp3fRU0q85h6nkrPBlyiSE6/hzPl9HSgiTa8EsP/jNqnFXCmfFVb
Oi+wXyi+U2XeXMFUytukeqtXvFNO3z0B5ICPOJj5cUJlHekUiG75/DsjKEKSrmPouHAHa0Kwei90
vqjSfUZv5A96Me18GaFbxweZyKKBcgNC4Djr0mbqfDRhfcg2tBnyLqM/SeYVWDVbrWrlcPKmU5gF
CrH3m+MZ8+SWJkH7Xr8tZgnwsKeudOO9wWae8jpEqGpSxhdbXZXlpKuygfyHdh2/a7fA1VN60/lk
sHK9hlN5ceBo7BcWYg9oMNIbWgdOFIAvclSEaQ8UVFOjFtXDRH6QIGgAXwFBPSjdU5h3boAQ0kcP
CDqHp+JHiiMwZz246bTjejMMY3i/G4IwCwmcxp0EJw30XHGK+7k2OlNUoZGNxp/qNxtKWKaQJSsk
xlsle9wEHoduKVLINz7VlFWJ0dEgmukSJdhJZR4JF7cMH8+1et5DrRk1w7iHOI7/DSzKIdGuF2tp
Tz2SNYStQbUVK49hXcXwcfjgapqbktvUESGqtd3qKigF5B6vQsNs3gbpqRmV3P14nSWUQaqi3nIv
JBxDlPAfWRGF7JWvuOOKGrmqyYjwwbwmdRMC7Apq9ziL6rEdy3CCZ0yaFfLprK7Hy31iCHecVgco
rFPOlHy16MOGsS6B/MEMHRMeT5flNlpLz8gVsd+peELI61h6DFyzO8n083o6ht2rHd3fqUSFpv0j
EnZbY5jnHf5ebiwEBpQ69RgcaFeKJc//RzaD/bfUrjb/xbQrfklCj7Lby6k1GNNsAmb+7xaoEZSI
4JitkNjcFIDCi9UbIwGipFVRhca5T6h2V4+qNoa5UHcchU7bvE5LSpw4F/hYjrjSKDC3I8btDlOU
N0iEz1oT78++UXVmICY62T+NdC4/uMBW1eisxsFB9gTlOTflg8O5N+nYAr7L0MEFbVHYTqPDSma2
4K3guQjcHslczas87pWSRjcK3qjnmA11Kb2rhAMSjjehY83tRGpEzGO9qFDgcciDHrfqwNCO0wsg
/zd94sChsaAg8JegF31WwHQ9roYmJMRialX8unf5Zc2di1A0AEl3IditXhWWbj7GGX+Og5EDxd+z
+rbQrAPMg4DvPzrnlDUdXyBSFJKwYhdATGJqEwyKuXz43nlbw7VeNdbelqW9CcdPCWsBniWDDfj1
aiPN5NCJqdqKqa+UB4wVKC2wVn2PVJKB82oZMjbDsXs5sRa5s1Su5PT/Clex8o3ZRiVpkD7JHiFZ
xKSQoCTiRzm0+e0qas4zMciZR/dKew0045LS4p4P/qv1T2tI+0B0K8mKI8XaiCiWKoVT8oNgg/AP
69F7hV5syAzVVnTeMSK5Fd6lULghtHd7lpdujHBFGxK0MFK+jEDmuEEqVU20jJGPJ7qs0/JOEWYM
qmLib6zGHwvTJIGkUVx2JfM3cMPovTYlJ4p2fzbF4YyKmC0Rhuf0f1otlgNPZ3S/sa2AQuU37WcG
1oljv3gd5SZLKyVSpQTxwL5Fj8UrAQ9VozDe3giwJsWf1OW3C6cu+SYM7GI6bnEHQmi+tGOKtMbU
ydxeNiPlJSmCFPVuae0vMMDWpKkl37Hmb8ykaybBAzG2dhVzkAlOgoD+/USTzFUqq7MTA4dtiaOI
6G00zAjYXwN1kgcEaCC7qkP+5nxCIOFYBPyEPu1I7GvkQrcbDqb5SuEWZCkhZ2f8et8vDs/sVP0E
wQxxRUuxcH1IlNGWrkBE6WkjZEKxAVyt4MfRNYPwbgYODZhE1OtIbtrhEMZ8AMe636AFOd5aCbRn
ma7o3neFdxCZ+m0YZqZMasoiRJ4ycbh3pTJZ9OKYzpETN5xHd0oawFb0goc7sN+WiQr+VKTfjiLC
dvymspF5vuQDl4l8mDnRKokNBlVwFIOMzv3u/4a8zAOxFOiAEjP6gFr+otRP06L0kL9ryPlSF/Ab
ZTN8IbQNFhftbLgYR146YLnzmUXinXyJ87ZRWYdRPjtLJAkX/NtTUbzyGV0fXqJBSHYCWEXJB0pe
ZuhKIWe51GfPHX3ZTs7sbkUlywUcVlu4bNNtlyOmSpV6TH0XQMvI22BQ3m0mZFom7clAsKY3MD9Z
iac3knmpl93T6jvZnSECrthAk5bw4AWiRS/oKy/hygH8MqULc8LO4DfXJPgRrq6IbkR4ZBlbAiET
OJYhjVsqRtM7QOCXD3MFAlDciijue0q2kkt4RxBKxfW3iPEnX5osRIM+2K8XWZUKrJlxg8fabxoB
jCYxISh9AW7f/CxPWnjcyMiMNE8dz6TpOx2vfV5tRUeTFQ65wPeFqMzNIpRHJB24XAw2XjsZS+7k
serY+fgVaAJPuBRI9Y+7Xcl/1nmMk6C61nP3UMKeBNAvcL3GDOOu+LKwZa+sFoq0QMxPMdo4M4d2
TljXCHXkpzxLF7SCfxgcQWmeBNa8rgkkN8gvyNwHeAT+m2LykggTR6VDLPtQh8IUv06Xw0XF9F47
rbTLNXpLpg3oPwP2ASH1hFO2GYc/uexhjvOXEJvq+nijMRfoVsJUXOURwXEd9zKRbFvAUtrhamxm
2x20aA38HnNlslUvPvzX+x5XFoDjc2PKJP+srcuKwI/5Xh17L+6xYfHtqsH7WOkxzheVL7oOrC2c
TSNWw7d3SildiSsUm1yARsnrabgsWtryerQ2cLBpTzQ/rU2PJr7+1lBSYgK99CWiTWnvQGBRu8xk
ViljLigMOqTRz7M3CSMFPXKNOyGP5Vzzmhd+QHwqKyta6y270oOnreX3qZAsLYGz6KHh79SyYNqU
uY89EO5/PnCra046ADhMT9LzVOd55nM/+anhsvBKK2l+qZlhJ6OhccMtN+7tvRB++PBvxsLkCSds
5byNFf/xAV7pJV95NByIxs2GWVekfErD7nBZGQDaB5tV7e11JsKOJq0KelLdSLRXqAXMHWk2vm3U
50ARyDrQQEEpyQKq//qCoe217vpEyzbBjcQBL6cBT4b3tVa8Qdl7IbnEXNJoA6bIkn166VZlhaF6
K3H6K0WNFcPIixD3oga0fXFXEOfDRmCnx/xyfcEjO3VCesTA+z2imIMOGNJ09jPcioG/uaTU6TX2
L3cg6jIlR1PtLLsgP/AWa+WDSBdlKHcyNalfAucWbe0y0feVqZKW4uegCrzm7dRVNyWiPOE4ZIZa
5PbEhUx4O5X2Ic/bW1PfUUlDlQmr4btc9v1yTmilM3SFyIIxdKXmJezpRksKvuMcBT2xHPCXE/+Y
VxJj6MB3TBAFQVbWnoo8wNvZo8ao66RYQdvTwr5QuueI2oMvx+Wab91bfzoAkLN0dAn/ML2ia2/6
RJBcW9ItBm1h/nnKRMb7xqSeTecKsd66V2EPNvxswz+3x9rGDuqVU1haBv3ody4aro4dpbXWK66w
q1ahKKremfeUTEF0+3OIylHLCmmPCPbyqaMm9MMQj/jSzMxTtxtrLsLm9JgFZ7HbtLa8VMv1PYPu
S54Ze2gf7U+7l/16h+cCQokFL7Yko9vx5Cps2BoKMdnx05oG1rYRsXPz9L6L7gtnyHoFvYPoduh0
jYylFernlGwu4a3wF1Wn5KvpMZDAZXG2srw0F4IqbBgOp//94pHdw5eOkXIM14/bLCEXUJYDFuyK
4p1PHYFWBAPjSjjwvgiREUAd/PTidSkZ+rz0AD4pWfXzfaVeGkcIneSOeSZXtGC5y/sAMhDCleNd
cMZYtlsO1PQ5aOGNy9/4ufJ5k940n6ARQGK8sAITO2qYPHJSa7Ff6gAa6RKTiHFvMGbChd2Lc2LQ
5wEzyArbxVAZhIuHgoOIcKkM/LmLDIV3ff5XfWdGsT+4/dmiSaJH+2+W1H9gyu40JDSLZJ20FeAR
yTMWOPyXUN4DkKRGTBesMVAp9JHAifOzHlJ4ceU/NLN0TYhcnOgmCcw/Ibm8+IuIGACQjOGqJEeY
4fErwQ6v7HzM7CT3g/LWNjDc+m989kFH7m8StRqysO2WS6bf16hJDirOr29wni7T+HE/19mSvrM1
iEeRgpz4AnmIlWvy65rINl6Df2xIEdz3ytStdizRtoHEAwH976O73sNmccuYfTewq4mdBztvLGfb
EydjrgqCob1NcoLPurOWFE3fmwZrr30RLqWHcMc7hzkIJP2BCt/LgpofMZUOAnBpymQaZFwAKf4L
hYAsYpYQ/IeSrtGsSXJJss23yGJuzaYJpV/6idtxjcvmeGFl7sZTqwUJ0HQmsskM1UNqSe7owXjg
M5nKz87ZwiAmSjagQ90/nLrZuGm7SrCWxIdLQnQqPGKbTSlrFTFQbKNG2fIEjH1IHOXOY0LQHAo0
bS5CmX0LE/WdPvlTFVw+a0r73k7ah6YvbkhcwWXvwiVI16wpXsVGskD4yG/+DRSOUq+Z78m4PKiv
+guZsr2I9TkBZcabxkSlEtGG+KxaTyXI/LXB3mWo4TLv2FJWxPtJqFok1RxxeofBqyffEmWV3GlE
kj4QwtTmZQAPqq/quK2mPvyPs9Et3uveQgxleMpoNnlEj4+Cx//63+RSx43uP8P2ZuNvMqzKpnNj
5bhTGy4dq+RXBRKKsBxiaqigFSs3Ef+e908V0QnpdMwqZ7Evx+E97m3BXK76rmpalDqsiLlZ4XWF
eK3ULpCnfWENJ12LYifmRAx0XjPjFwFKlhmrWsxLhmH87P3AnbXs5hOqfCN8XhZGsTxxiCPQJuyd
N9wURz7gQhg9GnN3rGhuU/Pc1EC9J1t9i35nwmNkF+Bxs3/YJPUPKPzg8boGsvmpVQaFQKjo6wtM
xrkAziJM1gT3yB1VLc7QA1q+vN7OMSRndGDr5s7UQcasZwvHO+NzCNd8XYV4nuCesDXz6t8WC6zm
pSU1Ia84HRFu7wfOmkr6SQlXCHQVWE8mhgp5jBnwFXPr7B+905hxHAGuGhW0UtK7iItR98HXifUQ
+4o0jFgt3SFmhxSpVFWXZdGyyYMJkOtDlqjadfHZcmVqaKTgWM4BEnNPoai8yQ2egsgF2K1Dem2S
kn1MbpNzHbMubeNO2V/tTiq5jQgz2coLst829sBZOLQ1m67tJ8Wlxgz2ChLp8wunKiiHsn/UwZKh
KBhNKc/6Y20TBKAywhXEcxbNsIgTZN6+frb2iUjffWTlhOt7VZkRU6Sa3HOr+r5qXmdQv/dTYiIr
Ebq3sxnmW3/PXgC5IzHagY9nTtLs+6/no6LqSd6dxK2tKZYq8WbVoUic463NCyhMsFDDm/V3sSty
Du0YtcpOzrgC1swPgDWFtLVPrE0ObNdE4kFcvdN/4hJTggj2nBeMNfjjUG5Tuue3g7ikehbZ73Yo
2iqPCKY/iKf7Y4M66qK/ca/KJwn7YbLpwNysQ0bbQeON6CNI9XdPdZuO53CukF5DgCmzp2iBbxyV
e42UmeAMHO0ZcEGLQrsDrfrX4Fj5lEHbj+Qclv9+jlp26miJiGNIxpdZLQHCqqdt7sHc63MJsOAM
1h1L+LFRsWpGzczxfAuV7L0CyqmneMU71Clxz1xWyokEx9FyannMOJnuEJspXUvu901182hL02pi
lyfnz9tCxKAAGf9W74mcOq3LnZ/APv9AE+1Ay6A/2Yh3Dm+zKYJySM+Y8AwrvwKhSD5On37X3lfI
8cNcNXipr3m6p2KBR0Cv7vBadZR4jUnwb+T9z0cYq1/I6srdKuerbsbbX5VNd83B+bQQv+6ci43M
GhyT9vQ7snTWshU0xbWmffmh9uCdPrhckS8jkElrvz7a3YMUWW2bVLM+2SP0kTEtEqFaHC4fz4oP
X39GGX3MebBjgM98XeLFldh1H2QiTYQHzyU2wd2L3AU/+KXEDRJrygOHIHZSC3hNrEG5lwjsUNNd
BBAzR6PSbws6/a5bfbNBF56LediqHkc9uxa4wgn1DJuVfzLKxYKa8d4R6xzZmw+Ao/IS4u1teGQk
n64m9SK0EY9f3Q0xoyBCpcqUC1Ny0K8c+iIiMekc5vIxcL4HLF3FXJI7IH26Bsaph1/NsPgp/iLl
lobSLIv2T2eQ0pEimKLmMbH0uvimoE77h8Mesn9Yys9OfanAfpYXCqX8TETdE8Ww5U7Gg/3BxsbL
3WX5+XHy1VimWxRpKhWuZJs1wLszfBHqrsaV4/m6h0OTvimPgx6lqhBBksMNFfde1OHVAQZ2AvcT
OoMUrwfs7cU9W//PtLth6Xe/sDCCgsV2/Vg9LTVWPTZz3qdruQKmWoljsCe0G+ek6NgmWkCZSDed
A8MSpdt9j2j2sD6DxjJuy2tknJgK07YMiQXvkBVKunNohs/Nugo8hRDcQWk93krGs8Z50XqICElw
iRGE+0MNsxOYWgfMJHbkq1yfQCvwFyX5lyLqGLsJtSeGC+52kEoew7sjRI6x0QGImhGO9FpVAsdx
yxJ6R3Gf0h2W/YJrLW/Pr1VAwQlfdmq3CX+xMV7wB/k/uItNxHmWqJjRjxxLt9Z9SeIMuHhOpVPy
qMY3/qVnbXFLq4SlRis2DzKAwgS/tLjEncv7quisyLJ7+qR+KFCI735hBHv0PfdbcFGz4YP/LJec
o3BHMtJwaNCew+oJKhX7ZrEwfR3Z7E8fwyWeSdoOGOcuwikVEVmXQDnUjMgTr6eO25qrdhMeGpFX
WkUH2ozKIqBBUVUHrnu9fFK+aTBPiR4uZUZhp26Ty3ahyqErqPmCMoXdt5AAuRHPGrirOKK5Pu1S
Gr0kD8gA5nc080xHKRW3J5KtuIAwmGMP3pq8qO88S0RJyu86mrOgwmD0rfQsD1DR/5LnsVkC2uHZ
Li1sktwYdNBgNUrDlFg2NhTcdUMg+cvtsI8IlX+U7IeSXLIEZSWAE53IiFsbZ27zeiM98tD5V6BR
eiJimv4Aho3Nq3iekqJHkZFDoWEKEaVvVr798eaN8Q50Spy1aRpRaGrywbVG1ZltIzOIW2tJcmls
emxyGsLojn78LPTQ5sAcc8cufiLHq675ZPTWg+DOOL9RL3htUz4IzxAUMfOGIPv3fTOFT1r05aQv
hf0N0mQh2sqndwCmFnLdGi2h7gBijhhTzQe78wheHw7LsMEtnpT7RzPYzfBNphfMrwcKhH3AcYAW
6i4rUxAa1tRB/faZSBKe2VkGNW4DfcczP+NRyVxzyAG1FAVi0U+xcG5Ln78LNSlbJdP8U1q2A9LE
rtWdRfYgwAOANgQ4Z8KZI+f/52baQs2wFzh2vOFvWWZfnuZ1BK1n3Xde6BGt3luru/GVI/f8lqdD
HAX4HRpbwXIFg2Dk56C+dbwX5B5RJUqUP/IZWW6QEEOWsu+yEh12aluRZ4XUNARqzTiNeVJRysRh
57ia0ANbmL54hUOTqtdxdLDzRU81p4Vg3YRHzXR7GeK3FHm0IplVoPuwZdX6oogg4sJZW1/0PREj
xxAkHVKuqGP6auLMIalh1bOp2yBlT6xSpI75Jcqo9D5mBQQJo/fzNRpi8/FCWvwsYJin1WmXle07
SECnKHN71WLe0CoXEeessqygsHv8QfHi7uRtUgiozUH4y0WVA0JqbLY05mhSFLCyoE0p1DWyjIb9
t/se2FpOLhVHewgEvpfPqcOvhvWmLpRQgMMN4NmlNY7bjdgY+bhieB+QtO9Quh47m4XrpJTZ8lRL
gPPPAOX+jlL0HJ3p57qBeKP1HSaw94sNxJY8pzxG78N4guXPd1bJmHetqU1A22oEXh+Ox/ln5xjP
bIbNypx6oVbJPjlnT2QV96hvEu17LikU3RNBVIuYBtWeLoizHB6UH18s9h/C3dsTaS/lE5oUU503
0EX/EoRjxVMSajKNdE+O3gkOVC0nWWcF19qu00b5/NUo7QVxLlpiZVEsI6/GpQLn3z93Z3oX51Sx
rqVYZlLdk35Q/XjfwfQpnVruuVjRLbPeq7wb8HNP5detkOtOcF/+hgSUu1H8nnCVwxf0AygoFErJ
u7exwz2eBLY+dpuK+F0uEVStlJY7Z7rMfuoCuOZtIG+4a4QZxckq/xXgqRUfFRWq5GR9a9GxdC7x
WiAi2GqXw3iqS+XCOYhrLoDdfomH/ZVZc9uu7uIbrwbGMaPKGLCU8zJau3yw9zgNA85plJO8W3ev
rxWljg/OQ1wlSoUjiyUL4GReIRK+el/kpgkuffbt7g+rGp8q/7vgoPEIEPvLIQFQoURmBZDLcHpp
TT3yoZgzioKzuYXA9z3KseUFOw2kwYOlW8KctX1T2tzsEtFMgKylsjlynVn/fIuDJeZYbsVeG62l
b2jopeHxvUWLBtg2ex6uWjegBdyucY5slSfUzwAjH6+y+cvHv511VTS/VxdDrrc7hEm+rXpkQUfS
j9HY0IgMhJsstnvIdac2PaIL8JD3hFg/nVk4TqdLFVMqCUDSdKB/aRHGTtJGKVSSeAlCidBmqT79
VdQxVurLhdENgiAP9uieCcS9rw2fA05qhuzpxnd2je05sR7Bq7bEKJqOz3w9YeAVR1v2+/88WfZd
qWcDnejrJ1oNig4xiMH4Svm0Y7hvmdPXXTmuwT8OwCJlvMM9okjNQcr9ISDerlHYvbpzJvg1S1Zr
1kaF7A2seDCxy9RsjDr/vbGo8i4R6b7Tud6RwpD4lScmdpij0RQnih237u8gd2snAMF4SZJ6Thac
Ug8Ijvt9vsbLMfy/fDVUdBqhg0ZiQKES6A4if98JLfb4Yv33sCE9nxzt/SeclJUJ3/7756LcCpiz
ONvMJJSvrgB0HadytSgGaFDGcBsxk4jKbGxrlYEtj/GM+hooyVz7n/3sV3bd93OS4tfpJyk5vgd+
fs9BARP3XxbHodOEHpURwShlwUv/zMy5S9eVeyLmZLSmH27ODJkAY/T7J1/nKe3tWsil3LgGyl07
IDZh1u2Hl/l0KX0E5RluoIxc8p2teR89Z2SiRMeCsP2eX9oaaqUCTChr6EjVaaEMz6w3l3L7kcGu
+Y5w4fNxNlhRq+L5as/w3VwRuErzTWMmgzcBpTYbg7QCrUp3ICheH2cirj77ErOEtw3uJWfb0lS/
+cyMTqzDvFNIeKCAR4KR3ElJ/56KUiST5EJmgcQxVZlNRPEYrXuEAQ2qwJcgi0fbLnYMwbMoJaTu
rolp6PRrG8jneaMk6axcRd2LnkTnB3lgE+8bmLikrAWu+itBgLjJFR3W/a5ZSPAaa9Vne41XDUWG
HT4iH9szh8rCSi5a4kkxxWCdPNcXjsipW94GxQbYqw8w6/544w4NCArL/cc7QmCJJnDaZ7L42Zp/
3qDw3jZWJbB33oC99JUmZKib69V8xyinWYOlbR8qpxAAtUOkEqOam1wNdr+hmfih5TTkFWz0NTrs
/n7oR6W6wU7I/hMI17pR1cWv2mUCfThARoV2laZhZVrD2FUlXjcn4QKFJACGJ70zwCiebdN/QX7k
xh77pH2H0J7wLP8KZoYdRnEY8DwBpbUjcANfpPRXPZ9yuWXq4iAu+8BnIKmdHAM4y41oqf0WOygE
gfsQdQ0U9HghsEHDoYs68rLh1+YxZ4sVd3nvqX2pRG5YRBs7PlreX2kAH6rIFp2bxsYQO4Blj8x3
uJngaq7Uo57UPiVb2KUXg2ACr3T14iDRVhwKbyJ+WIggtMa0Ppd4ZZyDbN7k2qoR+W+Acn4ndCIo
tg7fAuZttb3NXPBS5Kg/zITIJm1nj7ZKEhC7P3IT+a/W1zZypeV3TNdb4gGJC2o6LHzXdLKcoa8W
mntS4R3AIdoRzLnnychdoucMYuZ6DHlW8eNKrZeFa+4aAjczSBBE4BExWf109nqoIMAB+xP3dMyA
2cztZ5pISkED6xGtiZRKmvSxJ/EJVi1iWZnmuf77W7Mz7m5DhHgpkKoV6IRvtj2/l74dSmRiqBxK
yxq7+jfZcA2rkb08Lmlj+z3Vh4A0FZ4A27ZtwNxE2lytgcRZFJ+9Nh+z6cn7fr8EH7RD1v5aWd2i
4OPajix27VEqcNO1/g7gko1Rwq/PIWkqr5hd5HdgrWjN0UpmqBIY4ijZXxDnB1Jwa9V1rw56Xv1U
IWproMCnjh2dl1afMZ9yUX2aN6WkBJELNiYawfFwFXsB3g6ZqhHNn6rpw4pfVFsRUmZtwdfmEGeq
REnXQBJNLbJ6TzghxohUiPyjgqrDO2P+7zPDnRJzdyBYXsQ/RETU/Q8wPXLmJxDQTZ356UvkL/Ah
PgHaYYKKFpb4fZdNx96K68PNeU3M5mK6MuI9mk2Tliha4JiJKoekbe+h7vXTHGWwL4siHus2FZkE
NoE66QZ0AxtEqJ2/tJ0bsrsvH9By86h/6HETn6j0B/eFA6v/NNWYTaXdYzMgGpMsqhpn9zugyI6l
84PkGdH7okfeMI73JxzgNhEvh/ur97sZ9nkwlnAh9d/efd1J2UM770tZS8hvwAJh8dcuxn5IPc0n
jFDOKom7UuVCWsjML+/5MEb3SXhYiZ7g7CViyyQ22oapOHeA6AeO9C5yM3w0h7gvj+RavZXtUMU2
/PZ1FoJjC46GI3YHhyRsUd5ZEo/Qvh1FcPd18VtjPE1akwPeGQXtn9VaRzfS7foy/Ke+4vbIsOBi
3D2ZOcP9wmmmSIq92Rbe8SxP7WolAt/yMddm5BZ0KiKP2sUGG0rg0INXNnryL7Qh99m6jpmtWHh8
+83G1wA3Uobsg78ZkJkLkJ3Qt5FO5JELFuqchPijb/ENq8ThTwvLIbvxiCn0y5/JIj8qV6SnN6NP
Yocf1+WbxTveSu02qo/ae1Q10J4Zil3zNLloYMZT+R18+AGY/Y1jvaJvg4sqgVOi+QAZh9/f8xwo
VYpURepcbD+alnF6lojAVh8G8oKS4MOYa3YiU46yexf7lLYr/bXiZu9jNIL/9Su8tAKRfkN96lcP
8ahc+L066XOpEdcn5W0AD8UIInNSBoYtjSqEZdMf+2MIDJoZybU0YQZoxMwAO2i/v7z26seELiot
Tafu9NRBERoD6F1PhT2Ls0AIXfPCW8fXfVTq7rGiDa8fsBo+1kYyJyfyEhocfeuuWgmbwXO8jZc8
65GhBO1MJGCb3+1L0YvirzynvtBm/8n56+XLVr1/A28iTP6rO5tPE30K65+BA80Jtl2GAGx2kGFQ
mJr2I8CYymd6qr7UGNlffgT3unuUZPbIt8IftdeB1A9CzulTvuj23w2ZsJEB14Ieydzd0IbzNZjM
fhpQEyCylvjl9ODoieEpszOth7a1WcsPo8ku7rTQLz+wg2VA9Ki2D4rfPsd8BkKn9pVimvUiRqKA
pCUb0TjbhAX3ffxIDZycEIELqHcCWg07h1ADiDOzqmgFOKqwj477O9pXKyLnj+cn3YW++TsmU4yA
emxnnFF8CNpyzN7S3fyLIp8lP200Nw6nLOoDglSaYryTb0W801o66W8AbpGeCKoaPy7JNh24JCU+
ybj7eNlemWcdcNwoyQWP3hrNL1ti6UMc+GpUEjw75buQ6dHBoT0oJWGRyYtekmr5r3W2LD/cq9rb
4hFlNlY2etU7+3cOEx25y+KVkUHMNfJqSmgrZtZkKsdPaFyexSrPVbK2s7NGnXBQ024UYtz0UROM
r4sw1U2SgPCRwK0slKjah9FvkbvLxQ/rUcC+JSNczC0wQ1Y+FmiwphcdvQ09aWqVa1HQfXBYtN9O
g8/L8DDlC3PVtR7TANuuQUhtVdJ8gdDyRtTuH+ovf+G7a9qz8rU1ROh4AED6oQU/TD1juHJR+KIQ
iIH6SE52BOC5kRDuXFJ2JszMjZPQ+/Q1nQA8ngqMOO5r0mfbbbDnD7Ka48PIUHXwL3n42XNn1wOH
bTCEzSn95QuR4FYoqHyfm5KsuUSRNSn3R4csG5PQtM6914pDH41vr/gl3ENyeRCh98bcgjL49CaC
LqfYndgXfQuY6ROwXboVQURL95LDmmGioK8thNyqSAodcxCpCRdI7V6SZqMtbGmNnjKx/fYBcxlg
sFtNOcW3IkVtPJuAICE7P4WyHkfAADkQ/8AWr6WUY3zFbyUeYvA0EV7hcyOSdqxOS8OpjVgP+PHF
YzKDUB7toeA5Jo0fBgJ5jJJOaxrMSTq80CUuQYYZDLI47HLB5DeKgILFRQkrNq3sdulE04ZKaGHn
p6ULFl7vndFwRnyJuV7KoDT6CfM29EKVP9/FJp6dZR8oXNkjfYZFUPDd6Nt+a5iU03zlxnTYS1Ql
lSqTdUjEa8daYGxufpZaiJupBvYC7h66jemwqz37QB5GhjzT6Honrzgu9bu1IPzICwsrkAKGelKO
2+7A6VLwoIU0HYMbsRNHETMIIx5djcTIpyWjofluaTfn0Cfs1WC5ZFJcOsCMppgbVrVoovrXiXDn
EDLt9zEs+rqI9un13lUWa2SnobRENfj2g5kFBw8IC7hk93U89j31Wb7IEDqVGgNhYYm2jsTKR41P
qWR5pWyAbIpwEf0M92AnA6XnYvYsBK9fYniR8dVuIvnvldHR0MSZ8M5Qt1kfYIpSv8mdUtgHOoet
07pOsSgieaU/nsdxtPSxgF/PLbwoQdzrczNM0BC/HFqZSxwOIGsaIN4soq+P1H3UBDggRpgcAMCC
j35wPuEIRGTRpA8U0nPa2KBCCrWWHh9Tft7XVbyJZj/6A9IMRzwP1jelPgOYbVFnroZxi7ZMziPW
aPaJnhc2CLGQt36kiZEAl6FBI62bRYYEgTltA+jVTrgNHFu25OHxUir2rXrY6fa5t89N/u19cN7m
8tIHqefoJ4T9gQJiYj8lu60fqhZDTKkpOGGQbFzrU0tX0YaDvNbhVN968F5cUllegRz52eeS31bP
FxEE6y6MJJQupct5Cr5Im5QMq/78QayZoM59BIe3ihW+dRRU6t3l7/syTg04t3bFV1mRE9fpXE/0
SsBVZtOzpRSLvIaOkQORkONc9dNT6EjboHnq9CxxWUGzDZ812p74gkp/ZncCu9zvcVRgWTAuF4ky
aaEhPGxlVsiCxoM6ExdQ3N7gNaics84IiYKoAPSE6vPemKIjA6NLBhLASqDy6gaiCXxiQ4EsqibW
XNWIimYPMfX5eNRxVJ+1MUB3qVUiQRkFu20ME4/Hq8fAiIiFa1GxbRMUn+s6PA8+kz6pIfPKQggo
3wr/oIyK3zFFvWmScrL0ZgFutpDTWNk0An57nqgu7gm+OjiZpmYjMCqPmi14bgi1I2pEtfyckCh7
hYx5S4O64z2GPi5vrBAdrhujf7xtyKgTcO9LfCbnPAR11Ymz5c24zBlXxZ92ZMQJpN3XQnW3IyO0
FdiyAorOiE66Ng7bR4CUoSm/D0N7tcmvcN/aVptE3g7csgzS7nMUwarRUnIE04ft8LKWNINkvVWB
2iB9em7uEceVeLMPSFkor9WxlsyZ29dD5mePJpkDdxeOcomTrAqXPazpFj5ejyxZ/bCpV1ByX6X2
EDbYqsZi7Y6H2JysEN5q6EaiDVyry7rK7U30H/FZ6ex8G9fHJNLjYs/TEoE2j7+uEYmpG6YPpS/T
ApwM1Mui2hzKQeasJoamSw2SIF9DaEXsOlnOwcdcQAHmhbGZlYYl8sI8P0EqSFVYjjhh1vtaKDhZ
PzBGSVNQroyAK9YLA5V0f4QczygUI/XlZleqAjEMZIcz2STHK7HjYhFqs6mVr0Uw0NO4ORMVE4Tl
Yn25/97wMMIIzgz7i2vzh7EyZIBb3wgwNRpsX21WakXD45XKNKccl+UWPXffHAsBQMgtboC04eSZ
fioHH6RTZ2ITSmxxXhFqj1Aon4iunrVHdARtDyLu59YWglpMtD81Btdi8KgwWhE3+ETgNAFWOTRc
hUV8/dZv9o7UI56FJIYVo7HSgoYRJAdd/UpQNz7D8Rk9nQXSG9nIlyZ6hho15sXOCGudN9/TpgN0
Y+N8QNB1H1R+H6m6sjkGDj7TOnZeaiv/DOqPwE/lzWIyk5BeDWXolFF8e7HF3BIgAC7pemZr9I96
sUYpYFv27KtvG1YKhXFLusunZdAxTCA09jt1I7WQ92SaVcA/ORrXBKNr6i4z57G15iEiqnnIzxrX
F7fW5F6wKZjcVNdnhroHtzPmnMNSBaqnkv5CZBdnnzyReysPoRxpB79AOfoTYbFsh9G/nledj7vK
lVCjViZMUJ7gT3+U7ntGYSpelR3mt/HpZgaqGLWOXbT+hXpUZhz1tQozDHbaIdBXXxr8OMCDZ0GH
kC7WczK/r08qHg2wc/ZjvyvPPviR46+2dEb5AOMYDsk8BFwsELicyrsxPNb87KblQfg+8TZSP4mK
5jaVHKM+oGjg3DooY8OItKwvbLDRMTPm8jDmBizhu4EKFNcgp9aVtlLbBCNhLJRiXAhvSlyYNgco
DTWGs0wA+2kyjTopLXj9Cc6ISECNKscx5fPLiHOTUxZ1k71m3yvVfyYoWF2H5nPwf+82zYRjwOrH
BpbZmeR37PLu5WVxgA+wUhIuwQ/WCM7YKULiUEy/lMxv885ZxPG0TWjtSvBgMPMKtXxeG6LwsA25
6VqreS58xV7PPj/Y129q9gXCtcWB7eJNFyFC8x0Nldw6Dtxv6owzehknV1HA6AIZI+5aTPwhZwK5
feVO6WdMFSF72hlcGEgIx6PWawlm7wytE4pLlVZOZCEw4UcEyXbVLB8Sxm6LSdZauecB5CJHNvit
a/k1Sj4PX4Bb84w2Z0hguT/qMcCUDwzGCB5H7T/IQzYPakAgHm8iw2h+jQ9F6t+kWkaqL8aWcYSy
Y54GOasWHOCaiuTcuGI8uRwOT79ccc56B7cvBzctli+RJtybuFUyJriwxJ/w41OF2rek/5qz86sL
49vNqfeCoMISnX6t8W7YIfZS2YzkPNo5+qituqyE+XwvaMyZVf/tBFFOrP9xXD75JoJM7G8dqzls
wDyuHZvDZLyQ6PxaHrrkMcY5LS9U9GT9zixrpJ3DxvNlNM+LExhmIWrxEJEUHAs8sGZsmKhx6tXY
atqgO9QnYZGiHhLC99Kzdwx1GPcqy/090LPpZ+xy6Iw5xT/7fh70lWZdhD2fupP0tup2SokvCnQO
4ZK15VpYfJMaVwmAVeIxOok13MzISuDJQkC5MbMhr/D1oEeIIT6Tm2V3JCxnV9kQHQWlxYKdyRyp
abjUjJx9Pu81T3a3eB97PLkiJu9jhG1EXoNRTCo4bmiXCxrYYfT2bH0F5ulWkYcPPdcjrTkOK0vL
C27vq9hPo2vHyPiXZh7bi1UV5tnQji1zoELRtHxLA/HuiHMWQza/L7eD7/yGZuhl9Sep9HB+WUqU
FOvRY9KVa+Z6o4QVzfjzd2SH2uHi7srymPA2BK7Un6RKzm9OHkyzi2CzHnuwdfS8mI75kC9rz6He
/y1JxIb3ZReYU8Kpc88FubguU1LdfaEYcwLOz8z1bZlrYW7dUx1q7W1Z8AyOYd9CPO0kHwtTAe5C
kCoqtQw4Ws/LdyGTgafIyIB1A4ds8kYyYRrQJCZskqwyGpexe2EFeBbxzLvKxQuPqI24zTsgslj4
HJaHc8G89Vsg5H1jiIuOsteorKdBbbvBZ58qImAIHOPpCil/XXZ1j1TJfod7G9V4d0P4l0p6HgB+
5nnkpzAEHTf3FMlcesCVFATGYAppyRS4fSs4f1zWQXYCdxZuNsGV2IR01cttFxVANcleM/IHaqe1
BKt47u/XRHSHPOQVP92QIqScJAvZET4BpjIYOSU0YOf7unuresjN9GT4nggCz+OOLocSshUJ3Cof
ZENUh0u3Op2Ky15C97Va8JjcICFoimOog3c8oLy6vhqeZ5q3WMWdPZ63QRv5D7CjvcKQzsyLuyyv
YgKGe2EVn6r8EDVihml4uTUbGL2x2pjR7bdSaicgJyG49tnAbb+5Yak2UdXFKP85F3+zWRdOiL9U
EdX1nJJpVVSjzkJUHt0DumzIGTGhH7P5ZXOPVYHNZHC7Tot4BWXvUEkNQG2f4/cYbXbiB5mNiUMB
1Ze7UYtf3BGZ79TFxIQno553Y2oQW3OLcYMN7mJYxJRizkGtgIoVqRvc4TkgcUTSY39bHd8a+W7y
n3+Rb7wCyUQzI+L6qu94u+8F9IpfB4R+5UTAt4tZt17JHckZfPcDHX6M931hqi3nslJ2wvPc49Vf
MHkGFQHykh7b/L52TUogO8zK+xWK74Y1EPrG+V/GAi75R93t9DcSa2Ek3Q9FFGpNZV6z3uIwgJSU
/6a+yeFJpfaFqwzzGpALNkU3u6Lse5qc2SUTSGrN1KaEYMlfAj4fi3n+WSnooy1NRJWNkQBvIMkB
HpEhp87zPgv6a0gAdZ+q5/9QyWaXW/OdXWvoc3QJtKfJZFRum/7K/LJTBGSFU6sE/loUcq8bNola
l18DElHeYjpYE0Uf8HbgcslSGo52pPdyN17TXGB0d+iXYiLar6LpCgC1yoZkgHZ2B5wSWBGGd7fu
2+KX7C/B2Wb2Uqyp6xyujVV+2nM4F2xeP+roG6yeOLvy1o1t0s+S8D0UVQjvF/rtN577SwVEz/xX
qy7SAfXPemYK0pejv4P6RTxnMFLChxvCEJ8vmpAW9bubU5+UHF2dNtgy5fPpkVvMecW+f/ZXQG2Q
zTyj3qi133y9Oqm1uDROxSvwAJ2V3dgSntki/NewC5NJk2IsMoNq2fl8v0uoolzQ/2L/ozvArkbn
JMKSp7o6KXFxbLV83lCvvdZtuc/RNXYnKQ9Pzu/OwqN9HX9XIXpvsbxobm2eE57OOmt8b3O3gR1j
z0MUEVyGqv2hGpEs+PnUZQBdQabuCejOvdBopUDkKKBU7SBln1g7se43SaZfyCTBQ9fGCJGOI1pO
7UmBU3GtrXtOmkDBW8Ukk5WhPGMBt+3ZAbvXjbCWfEBg5mB2CR08m2EpZMWRtRBKOlpNT9tRscIx
8zJ1Z1pIzUSrMgpIQClgQ991OANMVQ/jCQMoykCrytUslH8cN8XLKHNxXf5jaaybR7HlZ3Py+xUy
DbCxTLUsjIfM4Ohl0ESrDfIlAgD2Wh/E6zEsZyh8gaSlGuYI3pNYZ1+ksfOhV4r8++9SRjtM2GIK
AyZul0Zpg9hHAzUlVj7/555oP8dDuo6Ujq7NJqhVugnUson53/VYmN15ZEQjyL5wa7T8/4iyjBBn
5msbV3tUPnP/Nk8gAPLXKUT+fhkA3JQxW8cjeEBV2lZc36kq7vMShaLeUAjdllkvxvkDwjEsVBhs
Kg3ovNBK21tYOgzm3HJEs2y45GAcONJ9tEDme/iNg10io1imj43BvjSJghQVNnU7L6JSa7L9j3LP
MMJTyIGb6yRyAONOG8Pc9Ymf5rUkVhCYBCrrrhxU9RRiNn3/NHXEVQWmqE9B9QEvmgWAeFKXcOBh
acsudnFHprRXykPsfAUY+rgMBBwyrxIwuXbiTV0chLQVl11EUJ18bBrNDXbL93GEpQ8FvJpDUsVL
RKutrRan/m0+lQhYW8CzPJwoLHR5fDSTHrVG7Pzqqx40OX6aE6kr5DyM/qaFKH2NaK+vDtV2HPaD
hFUHJrELqDRtESXVDlGON5RDbdDYbpe6pbxvQ0cKsFdTXSyY5Xz53aVXFhqw1FIJFU03f5btQAW2
3z2jB4QM0qxIZy96fXCfvO6nzh2xdAOM1vhggLNn4eO30Ipk1OsUs7mewUlqEIvKKgLth1lUdAZk
XPJN/mWHMsxPB3iL1SpXecc6U1B3kc+kM401XPIYSgHDH8ZXvA9S+t1oRbs5FGSkyj815pvDMR9x
c1lHOnEZRsomJJacws5PtV4L6GV2xJIY5vP2rc+10ByD4UGJB0UoYHm4pzzJ3QtrExel5L9QXf08
dl2slUtFbDeG0HzGV6jBXNPhmHEW+RXQVHtfRym+/ADgfixaYQeuuDidJD8YTcRDrs7nwQVEn2ld
utaFSW4+YN4CHXZaqTyY5Dq/J+iIMyqGeYLtkTwGjPq93R9yWkdlhzz0f3z3L5VYC76TEHrcRh0a
Ya/GKFRHFJ5a6LQOXIeVueSyA2iVAs/EP5hcmTvvvrqdTsSVBrH8OtQIxHbE85iNmuhUg/arVOQi
qGSFI9BfbIt52j+gWecZaQnqt/U8+vJ/coM2RgU8K8sWRjVK0gveO+jKvJz9YJYit19iYX+kDLZG
FQGkQq3awKyMsHR05NnBVJWOl+luDVH9tl7/5+uiI/a4KbynP3pcClJG1SRU2LRqh2Nt/1DClbjv
888sgUbtSpVikmB+eq2zU7c4SqlY0KUpy8sOaMIDeHiZb3hdLjVDjKNBBmmru0GClIGC88Jjle0r
W4r+I4XvARhFQL1L4B6+ZuqHeDWBNVoiDtJbUqTlrGL//ZUgxm18TmNrlCux6DLCQuJ2TmIsOfsb
7t7OG8cqmdkmRErQ5zrMQKoQFup+arWxy3M1LBQ3dYc2lgoCwJMF1H2OJsMeLLF5AiAoDV+kS/ns
HezVWRP4x5KgGSDHo1OYfD1429UI1qt9e94dHpA9qKpQyxEIe4e0Pblsh3U3jhnZJHBfmp6MmcMr
oUPIfbEu8+jrAxmxXJq3tK1uS6Oj2YPIba+heIjKjtMt3CM2PFDrf2clzLeEQM7n5JkAw4eV3kv4
ID3M2dOGTLlRWhcmq5fjG4wcK4g9annfh6+QIejIUmeuIVJwBcdKUaE0/WGPqSfQ7OmVyEIunhZb
fUMfZp4+iPS0e7GumQDEr8KSHffirT++4hR9b8dawCZlmvqR1rlt8VoCYdUP2RABwRGtGe2/8lhl
m27IQA3e4ZCy621VQpKLcWgAbDGd+mXALUc4R/gfa1xTgckwDq7lev1H33o1Y3rQEEVzVQwnBv9g
CZiPkzTaApR9Ykf+gdriPbFxY3K4V67qhFf3efNCgdfsUE/ksAssI2/EacIVNUN4aGs9+SW3NkXs
mp9wtDtsI+2Cv0Zps/3v0GNvyFDK+Xhcw6rbhKKEbP7Tpvqpagv9TVFpENOM/rthBA1oNllr/M4O
r9Bp+hNY1vXrveyHJ9oJzzZxWBu0TaX7choJ/F3vHJSkKNh2T3+BIFh7xmni5/calGVP4f4HL66M
QTsupuzVp4BWsXIt/6nCy3+BmsMKWKAlTQJeYDzfQ81TLU+Ad60EHbjrudGrQEflBpDti0OxzUL4
Vh7mD7GR73bVPgWG+LfbBpq3iyuItR/sXA3qvap6K8HDmScSavBHDBepYehFl9DRdhg9zSNM5S2i
unPs9XEIFxvUAU39SnHzWJkPDygx+iY/eGXwcXqf1ssAe7xvdeOmd2Vte3hhTrgBtAWj5D5sNUt4
msfBfU16TQXicd/ssiEW7TX9+PffQb5CFHrOUNeTonBArvk9T+07lyUnMHBozxFSOHS/xfOjADOn
CilqMqdvUnhd9OcNeTYawhxfpZF9fuiqjFx6zYWoj5eD0c9MBwDC0C+Pt/HqS7Pm4A9WrKUevrG1
EmEzEHweOh+p3UCMr0ncoMm4kUt+PxHGxI0pwm9x5G+fWrl3JC6NqNGhpHjiu5+0Xh7hIH8+yn2q
cMsu7Ma2jQMdn0r4VsUMPyM/vJSAYTQj0q+2kU7RtLgT8F4bkL29zWD/67rjf9w+j3wMQQiw3ItH
U5V86HE7i96JROVyT5SVy1si9a2ETssDCj4dDj0I3nT/LnWyJe5OYWzG7KzDDK7dSAzhXdP6iW8z
1uuhGeaNjhma2Zp3L+KmXdax0apCgkmxVf1fQx1FsUQdchC9pH+eDb+J0ccXXyZoR1EMaOr4WhTZ
3f204rrXHizvQ0e4OyAvjr2LP9CZw+ADnF32F4arDOpA9bd6sZiOC1DrDauTD1tVGEViwol9mC6y
b5R4XOY8Y8ljcYkPhn195OxbyZPbT443TXyH9v+clV90SreOjv2Yh+zbeKXv/6CdP7/4JgL4dcEn
TjGPbUqtNs4o5a6EhJnLSdSOyQNyeyrdj+6z24dmIip1JDTYuql5T5RyBu9jnCOfzNJ0BBJei6TC
toE1MtBnxIJxWr8L67i/BQW1uMEPhGwf5kCrQfZfS63R6BSiQ8Rhgf6wPygjtzhEzCw5zNiZcil9
mcqbD76txu+BsvV+EBrXdha0pE/rUMf9Qn5I6eUmGXIAUfci1wI1jkdrv3R43iIArUOrynP/fWUo
E87L5xQTQXZaWOsFo6lbeRPENCqC0I3z4IbRACPCtaAgJb8QLFOuKueu9tJIFd6culC6E+gMbaMF
4SdOb/ihNUJl1w6Q8yqNiGpQzljQlIJhNJGjftNgMLyLl8FXYzbuHalIQGwhr9TkehOQyQTRCVpv
qE9Zw/tQcUQkAEU1CHBldTsSyCWdcnyErOFGjb+hIU9LocXP9HHtBsU4CGtnfnxjU/NrgxaHgLqp
EO3xEDzhxJZnHGUXTfw2OjYAl2lUP5OsWRWirnvwG2bsbpv+4Fr6hCkLLyNeLYbqfzZNP4e1LKsT
6/4WBIiR6yeiwfFD5/PfWHoFTTckFBa9m3n1H8PayWEL2ZgzXf3TDRb6wQrdywPbiz6vtWRZp75j
grDOCl+el8yfRrTdIkH4na30hmTPl8XakWw7j9BBdpAbO7tziVo/5rJHYzpwOAZ8SiK3rsTO6W+2
pol8zGeGFU7Nsx0gO+mwUr8PUI2pgIP+YtpwHrhVl4OQ4Jnm8eHTjKP//P6AERJwN6CSMLsBVZ+4
QaNlxo5TW44cD9xdI10qjJSc6/G4NTiFtBfU4Nk3MBIX+/ELB8JQG2+2J2HR15mj4jbAKoLWanhW
g6d/wiHSTiBovlKfN0AehyB2fMTFJeB3KHax2QTdDYg/PhACEEmwO4bO+HXYKBix6RaTgRoq5cy2
opRzPMjkU9PMYzV/tj8rHYVriSek4oyE3A8h89CxTfbiLPpP/AgJju9BVx3FrhO8XbbCgFrjmnTT
vPbiT3gi54Ap/5KaiNz/6HD7M/CluBp16duC78+3MaG7PQNgcpfvg1N1uLTKOWuSo0h2o87V+oc4
QKqKa/+DP2algz3lk2fFYzr9AIA19FmMTTd4rfs1tQxuLY/GLq+lR/rRVYQqkaOTCa4J/V37fD3O
fy6AE25R4SrVD/NnuW41We/31AOaYzoBYKVrKjc/aZHsfndl+CVPiW8ruTXWqqHaPG56dOSUcN1+
s4XhObo0OQGAesTTV30Aec1m+K4loHnhHbqlw/rWdzGBYDvEzgWEOV2UEUDJv3CvlAhyELTQ6+Ku
FMALwY8wsREECtQSygdSYeIk+F+sHxCFHBkzW0G/lJfPW+6tYB3L3cO7D63pPpSU3Dxrdystl4ew
OHpsEqYj3bZxFFkJVJbSdvo/YiFVqzAE2pufVNgVFBK6rbj545uyL7jAU5NF9WZrqwoFVkrNGrod
mIrnAkti2+ov91HpGe6AkIiCRq+TB+lFxUPfG/JnmuWng65Ew7m/5WCHMg0T1Q86gq40o26bGmu/
v5fhkc65k1954z2j7lejSdZqijEW3imgJ4aloa7IAnlWUBPKnqVV+/z/q/wxEow+hUGdASJyX4bz
mGq+A3Z7H7kG5MwvDSpGU4tVbDZIfwqGgz3T9RFDAczXcHWVIImaJHFCE8rmNhRh7mfbGqWMqfo4
ebDScSAwUGFx7OH5TuCg8pF4FZRg0Muy4zy1PMpyPL6W1ct47+IThxiC6HHyH8N4yF02F98kh0XE
9jiN8mg0t1y2UhsxmTZZuK0SmKq+6WDutPh3AEZDIDZt6uz3auNurCCtjERcUrjLD26wk7tX6QFj
KzcafD9xMuexrHcsCsNQT8m+rv+TdfZ3hRzdZlzdxNpaddL0wMbN2zKUdshscCPBckbPY5rrh7oz
fwQNe0sYsrJe14X6ltPP/GqW5sydY3yiUyBRXMHAcfh3PshsyurQekiEO+/j9Jc3+aHARl9i0GpT
8+06k8/Foq6pErqCZzWkzAz/j9SkzfUUce3HPMCG5liFIEkOrVjDsk77Clr7n86qmuUJarPyu90p
ANMJND1pyqjZhinQTjFRHgH/+LEbGsgMBnzFIwEL5Wlbd53yy1/D03PWhvEHrQsH83QzzNxuKwJX
ZrFdkLVD/9seezRn4AiTix0a/K8yejL1hWEsMi8/PQ/USHLdgMHru4la1iXLGVMHl8lWbR1PRAKG
AOA4vRGnJnyZ+/J2MK7HyTiI+T9XRtQIi3bGzl7AvZSOLyw1JGT7qdLqZBuxKBVtYURkPDRuCN0n
rtZhm9pzcgvG+xbTxoQ90vrkc56cLI9XgvR9oTRuN2dHu8eIXDyu7L/0QDbTNDriLrXeCBWepUHt
BOv/5R0BddB74SgQK/B9adVdZ0M9zL08CMlH+2tUZIm+HXEraZRyM/78AZTcf5SJ6PQaYL5YbD95
3hKl1Obo7aFgdgn8RulZwpN8eKWvzLRHqwWtGWW+U/mbCVWrRXoLT3qJuqHy98c1D2C/otI+0tHv
nlHjudqcoGBc5Ke1xFCTnIfLiDxUbsJlv/MD8cjU+ciBEeKxjLI7OKK5/TTo/XrzWzLY6RFKqwMs
0gqhQSvbALNw4kbVzY9g4u4eky5+IzfV5ZyR77hUlc/45NDk3CcR1P7I97y+ikcJLDxAoiMQ0JIi
9t2F5kCxw69M4ZRv6CVtpPd5htMKcLBA3M9bgmcCd3A4Md7HYYI/kq56QYKkPGZwc8if6EHfrz9V
FiSjX29TRcQVKMcFElr8IHgWyPf68CGH33Lc0HHYTSjUGFUPl1DkvYMbdZy8Icat9fDmWhfP9y28
6gFDnXE6qHOKMcCeUQOyAXcGM+qPXn3G7In/Hna+BM8F4u09Ntw2F//RubNJxTOJVTtZSz6DqYKv
xZJx/ttRp7ITMHjbqn23/T1x3rR6ZiRk4QfBxHGLymda2Jd1r5GphcnQtlmmLI8UykO9AaItp94I
pIunOsZeYYReW6ldZEj/HDborZtFnHowNVC6ZFy/+QNlOLRWE8BeCH/oyWCDIF3PoYFpGC46zcFW
xrOrrL/UPQMS5T5p+kSCbA+AhhCmr8OC/2lB76+teyRJPyHOmlAhrl7KiSaDSqvxt9wZ7bOVrhaU
d+EZDNNHDDdIR++nlhGux0hastOdleO6W42HH9cGvlLazO2xACFLgRCNP3NCc5GEGLesJKI0J2/a
X5cRCpVbd0NMk4tHEJn7AbuocQFBe8E5x+TsyIP9u1RmqnrInJDTH8dY3P6mG6yNzgos922vr0oO
0lBxEaOPeT7Al6Ld9YYKhJVdiChi+Ho8cyPhxxSzz4NO/5SHe8cmy3URi5pQhpjtx2h+ZV22dWUo
2InXrzmg1FkCPMckqzOct70YXPcHLSUqSbrxn43KgvPmzJDJpBxAdDsiWf494soP03VzHUixtehu
ANmpqqLWqQs8r0T7XJU+cyx7vkFDSJVmGRlB9s+d3WBsipF0lTCn7X9TS6kPPKyV2fFVx6js6ukw
jZkXOgJ322sZJuK0KBeqpraBX3mzF4ft1h6ziZABtAoiE4d4SRkm1b93bNOrHLN/z4Pi2dT52aaN
hUaAIn2m1LWhGqJiybG840cRkd40h5GnwWTC4eWq7i/DAPw7Ao7cRpAW3xCoskf4KuLMJbg8J3PU
LDmUrT289ZskaFb7yFb2JOAMyMW91fDAO3Pjweoa7YqQhn2k9HMtWBeYpFY3tX6uPQdjJ+K0VnRd
5nDFKKYnXGhfzsNVMs7h7vA2in0XRJ1VqinMtfhV6/k0wFiHyb9cYhnNc3jgFOhfox6OBe2wig6H
gAhwURa42RECczT5n56EYZBAnq30F9POYOgoSjEm8F/ysDA3iM4gntT0RcYhMzztEZeCEVciUGph
l8RoTTky6i2Lqpvuc2NL4SeZ8Y76PDflmLidknSH2ogad4vQ+ISmBH0fLKSXhQBvJH9S/vu3lMaU
2p3NBLwBvBXnz5o1/5eFzdtwA18O0koKfc223yMs9v2KuIMAVJ1GO+ZznJ+PLveMGGeTlE/YSHVT
D/oiQuIUHcyN8W4ugpIQx6rHOTur9QGWkvkDwfZVkl3kOxJ/AuN49XTKrflpMFFqMQ8BF0vp5H5p
m0eC3Uy1rSetVgly0H7XKnhm2rB96sJZVb/hGidnhUpO1Vj7SnSkvS7cCXfo7Sj1qLL4Wq3puPrq
QO4Nv3GA+POuEkbvJCvZ7dC9UeCGnmrQeeRz/k5aNSFt0ldrohJS9liWbFE1B8tWCdmC0UiWx2rJ
SvhpBOwr8jyLK5tgPlruoPOaNWheG7KliCn+kq6fEktgVqVu707WOLHkujtJ0+Px51NAvwJd6Fmi
NLVSSeHhxHkQyJLYf65lvq5vCYZ5HDsekl7D+EHWrTu4p1smduFJV81ZwZen6dJvAu5+wpX1Abe0
BtIGCpX+wYR9OrLrUzFJ1gyS2OWGOfHeYLxZnCdW1Pqkxdlfc5TKj4gSfMDWahFDSOpKzV5B9/Sj
HOrfFUSk6owaNErFSRks8m7iMCi/AytAz+Flew5pe/E1yLFURTLxQRjvi1wXpJ4BCEeJJD+v8Ndx
gEcBTeiL3c5WcIjjtEqFsQ6YPgVEFvHE2nS1AmUsSGyVXyVshIqqxkiPw5CAt0N6P+yVrhfKsL3t
Yv32co72vpAcQVOnyAeiTrrFeA1MxcMyW7qoahb1bQ681GVb4BUf7O8NuULkeSFv/+nxe2EFFPLd
gLfrMDKlSFrt5y8RVWnXGZNKc/f0Ts/pPrwfI4N6QnreWIz/RvaHk5z2tXNNJw7VnPOnoaRhU2NW
uw/Z6pYaJUqYc+i6ppMe5Ws4JdEgbUO/KM0EqWLFlrEb6A3aFpAUXu4uNeSH/Bih+qYb2EwaroLZ
SwHXY2zjN+6GYEfpVqK+zoFYM4RwGT7CXhFsFDKG+25C0BlrVGdYHhG9wABGof8xe1Kw1KOBKzbj
lszz+1lpzRQm3RrH5Msng/l3vvHDwWYmGfFvyH/z/YSv34ipiYs44culvujSdRcxDsLiG42qEVNh
H7gsZLuNo8swx9ws4emoTm/TiEWMQdpiuvjVrV2O9eoBdkPWpJPazi26GegRkwzMbRBOfhOCU0BP
CVLXRQcvGlpisvHxwlkbPNCRIkd3jlR6/QO8FXHIHIp1sWikPzJDyKmWyCowRxoXNcHyzQ28zLnF
/ymDsdVKCvRUMdUdoeZSaM48t9Lg3vSQVSs7fN8XO0u76cmoQ7JesNicxvGoC4A1j/HL8dq2F8P0
azDJdvf1xfYyI0kCu86yF5R209J8JwG5+7GTXlcUdMsPX3hOBn2Mmgz74O0WfsyyGz41Lme9VlLf
tbatTWL9VWZlWfe0QrRzpZp5HkXi4xHmQg3YFK0hATL9dJrkNxGJlcVbdyaW8OX1GVc3ye7flB8l
ocR85lxzvAHNd/f1QnUFktye61u4Y5cpmtOSn5G+VYRVCalj5d5x20BqLpd4geCAZMicU7x9Jqpa
ZUy0pPHF3p01v8LvttRsHSvYvEqyanKbfZ8X3Y0WOGAeEbwP4fifmJGmHyznjHZVt6CjVZ1R8Sgz
mot/L03BVKRITkZIWGMWGk86U6FsatV6RfWIfcD4LUJteFTxl+fodmpHc6X5KYybqDL86g1//svH
PiylUEch2VRx+lEJL2R4vnQ7qPBcGqiIh+vcExP3JeEPEk5mFxvcjiINZq52mee145eneGUA+kUK
dmmYa25uWbzDa6GD01NKWfcKTL78AUEMbVR6O6mywXnaQ4R0zTi9ZFqC9HrWGdLkAFKNktAbD6FY
9VQ7CWHaPQyIY0YLOaZ4DjaoG5W60nQCqh1WP5768AaODzwOp01PSaZsLNA61v4mdX3LS7pSbdX1
/si9+ivwt3AGe+jNTpPMyY23TDnYhGiPUYyBPERQnW9kVt/iaWhuxtk7NpsmquhDNB84bFfW7wbc
zFGqBoZFy3CCSmS/ymByzsMYHgSMVNf1Wgp/srqlmeGhicRRmlMx68b0BTLb7fEzyM0gNvOlaBfL
4sKDC8S1CWwbNZJZYeQa43DqM3FH11UIMJ3WYI19tJAxixS1KzMAGx1/RY7ur93baAczSj8Ngk7t
Wdxh/1r/GnSZ/IeW7Xiy0+DND+y6Y8JsAjSaHuEBFlM03UxWnlZrYrYuEOnr5yz0CHAyv9c01xwx
ge0sx24LpUyFT9c1BbZ6gbOm2FVBqekiWjb+Nn262miSoe+S6WS/72W/oJyY07rAbQI5zoBlJK9a
HPCAAq9tfKqwExqE0Q4BDtA7XS/ghLLkbWIMkHjAA8Lclb0x2BdxAzDSpmAsT9qYF2a1RArOdHyw
au5B8V31B1qXhIZFGKdgxEmWIx81bGQjLgD1WMINUsISw0NUwn4nZfP/r0N4w+WeCcfCXROqd2/n
4fbWQToiCn8g0LFnCc3UNdeE79evtQ/v4VDUcGqZhZ4fCOXjvS6N0kzqidNN7pfEN1dgEzCiOchD
sLJcaLcDpD+7jlOvKbu0eR0ylPQHmZeeOwm+GrZqkuWDJ6Bxj22kjj4S4L60X5QcK3644CAb2YfO
TGhB10GlDab6wH0y1Ckxp+PvOCy8klj7QHLQ0aVDvkxpgA7MCfQoEHLej4uqosk+nZ0vZyGJQ5j9
3D6exhpcfoQAwo9YGI6Icv3Yw69WAfulsKRrUJsbLBiZLryrJ2giu6XjCg0a0myGfKMrvaaYqbcx
kWgvyDQotPq7GRNhBJPSOosA0WQeZ4Q/kkW6HPmL1qaiO9GE07wlJ5Imkz0HNWP5CtV+K4UgPtkP
VW2JGbR0DGKOTvV3y3vAh4ODHL3PMwrLUs9Z/53mJmWRUPnoMIJ8pseBgfJWiUD6yuJpHQlUxje9
MB5/AZdFiKA0HBriKIlb4akGWc7g8lU1qXJX8e5TfIhahs/i96bOncSSKleySQUfMXebATBVVduO
o8EweJDmoSR7cFOGAsU2iPYEQZoVMhJjSSRKVkJoI9ZxQZakx4A57uBDkkEaYzkNcxAgMYkluTsk
tm84gdRYzKKYo5+7/YeMtH+XAz/F8nKnEMbHUwiiOAWpMVGzQ/GbLvM0tXWzkyhbv/b/IFhTGVFY
QaACFQHBeIIE+6Atb691mW3zyMZ1zn7btZiBF6FZeS7dJXG56TPbtzhV6Kn5LcDaZ2jHJy5My6W/
hMXyvcQHL52cjzGqSP6yXF1rFQRh711QD8W34uq501kbYHXsPDfoStgAC9ZSlUlCPRZaxeKGmXHk
kedL5Uk3e5/HebBURNTBILwHCbUri0SXAuBRoK3VwQMbNJxBHuklldnftjUSnz69t20xj3qY+0Py
ZNkdDsivC78N+eFF6U/ElRQhkJ1fZv16ecx0AKrOoOU7YpvossdGrQUZcjjsjv7m92yL/9JTkrjB
QRZ8cD+UFFOllsgY1Nldjd506QBhv8Mb937QRpocFXkCyt9MAeX2ngNvZjJfEQmVcq/daO78cJyR
9clKKPA4CVKH5FEjjRgV4o//LKxkvmRjd0ecOBAkALK+fnBpujD1ggldrhrWt92jdvGHb+gKeFm0
YzMAE6U5wIljpv3fzgEDXbIdUN4C8y36pXj+7AwWUu6K+SEJ20TZ4c8ixPzimucFmLVLO9QETxYH
094d+K+DKUjibSnTAT4dwAL8vcLfRH1Ng9kNRLxkMDn9nRjxXW4wMNps3FOoXFKXDEThEXtrNrYk
FD6YVjyqRU2zmCFmQ7MSQCVBBsiy53YvFCMU0APt7Yj/bmCUcEn5fRdqiYEGCUOYOBQDQCDfKWFR
1tL7zs2TB6F8sVvrsdV3zUOmG+K7Ew2YL1k6uGtd7408dqcLLWjIWKz9YTtrbe6TGUNjJFlejRzE
qEWBvYdkyfAHOIHKQEKqi57BVQXbvvYrxCTf2ehrSm+wpl+Mdz6NhxB/fEUYg8F84KZANVpNNP5Z
zWckGnTjSm5Vpdd3k3i/crxqIrJCLDWMytkd8Ba38qu5PWpl5mNZNL64Q2i+bHelUyrEqwpCHUOW
iji66QocBFb4o26o1RWnUfdQMddEJ9nhQRNuDhia44kK0ita0foLeN5vlSLlPYACDyF+ZCDzmtLP
7sas3Hi6U1BG1Rwg6yOYMs5cBx7N1rp0Fo7wV25dzbFwdSKoLtCoib7D6dPFnWjDleBbprU3cnYS
oNA12B+ZyKHsAiFryn5Ux2Ur3CLs9R/v9z2MKqB2uOUF5QnK9LbCb9awbTp5RINQEtvxNIu3YQ2A
fUM1C/qSKeWZJ8StYFSU3RHlRYTx6ZGBujgTzAB6Qg2XDhKm257q9SnUP26iqgDIGwYi/wpD5Uye
cXfZsAlzEKqWZOAzC9+WR+bOscqi8+MyJrmcCDsljk71Nmob9MmDP6mG4+62DZud5pzb2W2XRH3/
fzovGQOW2m0pCsH0oxNkpLIqB8CZCHYQxRY4GHzza0Ikmbv/TBNnXO3e7n5Gh30fTq/31vhr5RyA
Ku/fd1M8M6JdN78uu4w6j9umoO0XTmAI/PSSYVDtz6qtJVMs3Fmv4iSbf7QwDkyjDioAA4obyE57
lznyDrT996d39OOH7A/xsnqODwXogR2BqGMomDIc+Jkn+WxK5EoHK7l7SaWBdrmjF0uS9GaB325d
j2pPeSEpO4l/5agL26gCygp0ms3Xl9DzW/t5yQNh6MU1jN+DlyBYFHUNTtc8jHTevL8IVylsE0Oi
fcj0vFtAEBqAdylTW/gbNAUli9nIscfu9OR3E5QDu6B3R3sL8EDLkfSqMtj851sX4aAS7ga9Uthk
EqhG8+GmGzsFBFtwzZ+DJfBHW89gn3SDAIhwLoJap6Z6zY5P5iiZTv8NpkXseuwtdWq0lsH55uin
mi6RmvYZmdLeWMB6BO00izY9BJ0NVjgFxIkEdDAThQg0qF5xF1rdTXtkHimRpETHlgPiw729XUbV
JFwWErkS4n3u6Lpvcd5HTjSqz7G9DhZOgLGD4BG+GgcUoA3RSlLJFtDEvJZj9GFkOe978xn29V53
fnqVgf5FgxBCscg3d/c5N75sdP4dQgs326GwlxHarFoFECVB7vT9DWu5aO+QScNGy+s+DqWHY4Qo
ESn+53MhI/321V7R36kbwLDsWEb9qoKqelbvPKqhWQWbR/+piZSi573iGBGbK2x9Q44NdnIEEsZJ
3/ecSnE6TKXCduSEkTP+4YYyhYy+quQiXDjgfBbJ6HZQTNrqSsMzIEcfqMu8+0Wnm1NcFoylQl6l
VRmxd/Z2HAD0oG5aRVEQqbGJRs3xFQ2BhKPVYQQ+GEVd5sy8u3WKCX8V8TW7Tx0mHdyJiADJ3apR
nYKqG9NW8UYIx0UP+dMKG94uNbFP0XVEs6E1V0DlgxhU1zkztYyMoG2YyeU8RMlAXV0q7EErVUZc
cqj9lbXPknikEklOy/boGOS/IoWHzVlEnL0MpQB1rEXbSpsiVub5/VPDSPoiOvSsahWKeNpt82x7
4EPO01LeW8bIOr2okXpGe5izCDFHm/k7FeWAALF1z4RXY6Nz7JnkFShnzZavnis1+gGM78jE1vMe
9FotAg4qE1yL4pruH+X/i/0ZQxEitY3mYtXJbjwl327hDFrcKcm+Yb24jLsfTjswzUZnl1Tc2VoZ
H9Iy3MtPWVKcpPtDwz3iLc0Tk6qzWE3jQaqAWEPw16BVRcx88TFiXV1SVusZFDahzYiBM+3hFSuR
rQQo14pzWrCx3jBiU/hwiVQYtPx8vVjylPRr2zP+zGSRf5S5JuV9D6xV00Jj2k9SzN1oLMSa1+Q7
b3w5453WsT8ds6DgreeEwajZT5aVFI31/qKydvDvMTGZTtCe+fN+2qxjW0KwmmsYQmUyhKG/25j0
w79cVgHQSz1TwVfp/wEpuhpIPFjutQnq4/BuC7r82KY6bWzmm34q/GLwdf/6WJvgxTtfmpd7iXtq
+PEbcAmrZUvtO19bqjLmMRCkAa8QB0uR8IQf0c77W0m3IhjXFMGWJe41fLq24MGlofK7dycYuadG
uUeqiG+v3xNsyF8nFR0Xjz12NU3FVjft8ZkAQv93zz9r4sJPWSUAzwy+BoVAgPWqI4vVxV5CgUGi
ezODd8YfnsM2KSdnOsbFpZZgHOStNWi1jAgO94qSf/fgla/qY/CnifPuD3IJ/nX53vqC8G2DjdLA
geWL4nsw0mCjfvcQXy9o7oZhqHs2r49ynSZzAk1aK+/m7/nRiCGQIJXJPIm5qrBkeROdYXmjw/Ho
3xMrR89ZF3XxLKJAOQwllRfkV9HSoNk5NMIhwaZfmIariiKzHysd2wCO23VD5Wv/mKX87Ckf6Epc
p1W5VNVfq0ZvtL4UtwVFg3eXwE/Qq9HA3jeXPMC2B16tqF7JzRkYs4g7kWrBL0iMN9N3ou2O1sww
aW9ergshn3sOfNd7RKJz9Vmj2Cg1Anmkv3gL2nSxcQx1+lZZAYs1s9U2cDniJMzwxmy58AaKgfwR
uYsnGeHZiA7Yu9tEXW+E5XlHnBv4xl+Egt3hZuuW7op9jfA2z36qQfBeZ0W9JVDq+FD/w+mdMMUc
DD/kJUk3JmhWjqCe3wjtEazD/QzRqb3X34XbnHtlnUPtJ26ThyLbnWqmfvC/7Y8jy9n1w95HrWTk
LgyjaGpetKhfOCNiHXujhTHz7uApEogWkmtzoxEFY1CWKygVDPmhunS3LHkUVgO3k9Q/9Q/vWJUK
k2iVlQLNLRExFkJtRjpLg7hNWUcuBBjqv+bb+xLSuIK/d5P2Ar1OqeRz2r1UbXmJXp5xoM5SDZ+o
K0uoo/92mkwt4GadtseOg0QnJJZlfSGINSFK2oCnDm+capn3K9hM4uau/qEyVu6TUoGYlGuz8+i9
QKYr0RcMxl2WZHsJmR9XKXkWh4C3rp/sLDyeDg5bO6NEQKAnMWi61MO+rwKWVBrCg4HZg/DYNUk/
XzX6gKGrEjLPnhRGgv2PSli9Wg59x6AHgmthvbfGJKBhbs0WiK6Ogx4C9fTgVZoYmvcXtt+GC4EA
3GbMzidEe3q7pBfmAIVTGbK5YEuZXjCT0tfUklkgOgvrNgsOASXX1//Zjaf9eSq3Wue9CKWGrivK
RfMaPh2MeqO5+6FjhMgvfnSh8LMm9Re+wuZE4a0SIKcZRm0hA3yA/IEYl77HxDot6QtkFLUtNTIY
ij+nF8/c6Zz3sGkuziN1cmEstuuLnLYBGmf0+wrQJBwnwle6iEXDU76NHJxbyAZynQ3owKkCyrUj
Vuy0mnNMsUmlOY7ptnBx608epw9KWBu5dP59hK2Pek9OhXFi4Png7unHM2liJIVx8zmsvlzxbY9L
CrCbBEdP1CQ86VWu20pxxyWj9a8y5ax2sJ/iqh0kwHdgwMjubihojw0OHAVA3qGlVObgDOdgqp6K
IAaLR0f8N8RciyazkUWhnhbsOa3YfSZLxHRmVy3rTQcCaVh/utNylbIpgR2BEL/C1jdBsKaGsNHj
xsxAWqdgBiedIcH2y3onhKrmFI+2sAn6Ns+v4hdEUK5Bsww+Vzo6KA/OCbKjd5cHDyu6nQk4jzhh
8l0/3UrtQSBvaESjz9YEqyoYI8g0IfiZFoCrolsPSxEsHhfkZT4YEodbBb9xoYXG9XY51PI41J4E
Bms3/UIziGkYZEgRYjQJuhQUhJqvZD0nqc8nfCONOHbiKI21ny+gYzKeLqfx/96SoOxG4BUcsklY
dlHrviirVcg/sMRuEbJNjekWo4IACRfxX9iCiRCW2kJPJ0o/v/Aa0mlGpL3tUsL5xyA+tOBmQsce
Jnzx3rLT2+rYzL3LTG0Dh/L/x/vChGILpS3h8Cv5vsSq8zO0spyp/LlX0i3EE4zDzTL5nZIIJYL5
cmEIxBGLXT1hg2pI9JbuQmotqt88724y/RTbCjZN70ohWoKJgPTwVG5SOAn8oLHg645XzmQUYNgt
38EgUUczDDs+Y+qWi4gY7/v8/gzvUXHJAnthk7ORJRfO/uFH/pJa9bEmuMr19kWj2kvN4Rn5Jf18
W/HtJ53v2ptTURu05rD3X9UZOBwum20mfevPT6MgFVAlhl6mZFz/kZduBthwmTdUmA2aMO9qM2uN
Gcvu6TcvAz6ETqWNp84uewcIbr7mmtA7KTm8MT1HRMnm/hJIrPD6NiyWfS4gDEIcOQy1rYB+Ob5B
pFPfejqaEjWcf+QCDTT+ZZ/uQdxlmGcpzubmAuYCeGJXJuhab4ksRESBAGMMgzmzgvEE7vlYaL+O
VlhT53GDt3rSCRFhPb2JNvsp5Jjbs+tS5SNzpuYGVgtaDhADlu9wc6BjQ4WYo193j41EpPfsDiUV
oTTCA/gQYfFR0LyB0pQdyhdv+5Da8A7DokZYmw+SfZg5ZkDGgnCY06bKsjjfEdbAsyUsgEvUxWNh
/kQ2cLzlTDATNJYJ03C2aDXENtCjQzywQ2q0VNtU3pbIPtIrRVioV4miDn99k+YmtFzdWSIxC3TS
X7cz/UrOJEs4b4tVHLKwNh5apk/Q/ooWrqhROH2Xzf8mjVpnlMGFbYRn7cfQJiBFVM099BJ7bQuN
plcgej43Rra2iuR3ArdUIuRo3M8pXOIttic3lpWBgf1/kUZa9zKnMw3cqhe00j3fVmM/hV9VaanP
7DrNggDeBz5ajBate0c2PYER3ivwubdvnwTS01QUsw0v2/yGFN+B006WaH9DluB10F5wCn+/NyJA
GYOXDt6+Bur3Xo5YZFu/IX70FvDEg460LB1c788xzlwu4OjGGVWUELRJgNpWSiSw4sIVagRF8Cut
M06Lx6uCbJZQ2vyIZ3Tjkk/DRKMoTtXEPt9HkGVcYe5qZaOQ6uEL6kDM4gJPC084R+a8SfmPGmnx
YTsJL9pbIG5ZRyDBFdUiijCeVygDcjSy17YdEUmWTm8XoaQgS4Dmzs0+sZk8pMg7qw/sx265FxTZ
u1OhObHYJ6aAzYnrZ/paNFK6uMEsky0M7DPo1ca9/x2vULv1njLkQxIL9A9sNT5lzVeV1xmUBWKe
7Y5Eufj6E/367ASbgXK48LMo8iO5ceA45OnQZv0pPRBWc8SmpzWHSoPn64sf5Gm1mFYtQT5FuiX2
PxpdU0crWmn0niWg1LQEmbWG+kM31ujZ+T3hpuLW2r4AIo4Gg2/5Ofd1vX7dWDADwD2lCqNyE0BS
B5HPuDV6epTpvKIBgCWM/oKgkInq65+hEyUO6QeXHMJqAY5twr4SHB1PcSQvxCrymKDOiLtjh1AR
rxOWa9KE0weJybiW9QBKdIp29xOkFN0gTSUonxecKNjG3TBAXrbWNYHW9X2LvmfJegtmZFk7MrCJ
/uh+0xe6tucWvPu6EqAcaM29Gu2REUSKRcjb94muXemorT/aDtWxPrP2Cse7W4/eFN+s/2BSK+pO
od3OjcZf/MJMysxjCQw/kisB40u17I4HJMzEN+TQRdOfPc/Ewfu7BxZvYG7Dq71vpy/AY68KDpLu
dWhJnIstM4n9uBO8qcbl1tbMZgRrlvpLER0kDCRmGUUOgNoLDu1bMNdpdH+mPFCY0JASTYuTO5Nk
lDpRqg7m4KjVPrs1n2HqrlrOiZvhoMLGnkQC+6WdRtLYIywqWr1lXcpwnEmVHd3rffAdr1PMIRhA
KB7UpUHadwj0zTIH+z/q/vBR9XlPogvA84MJs+DXIXGjUH2cGmAYoy2u7PSjNQcFa7SEIs5yqRn9
3//iwsAoK5wwHpGrGNiE1aj/oYiTohHU1x5lFJltsN9K9cyjZaobJNRZaYJ68hYnqFTxUSdoisDA
8Of2NVnOrgfsJxFaNdqy9pFbhmpPWtXHj7Qd6mtrH6cZaQql5GdDl2ZQsDINfLkyeMhtDpH5qk1H
QcdwBvEn8lPsLjXuLtg72r7/RYekacw0WU0PQ6W0E1fXoIAFtfbT0O/w8Vqt5i37FTP/muWBl/Dy
ufyYdcc7/igrL24UwRVz1umbslgzOIcBqNt7rCKijtlgNWtyDUbdMbdwel8oR5l6wNDGLputPvy2
bgQhdTlgeOlVg66FG3HCFbsrT2gFRM45CdWflIVeFpc0altPvE4BdXi6MQNdNZk8cGVIQfg8VGYt
i0nwtQsKzGkV88/pVEbyOEkuDP/3UhN7J5nAIoR0QByeSDgPJ6ImYu6+o3sxbcqClmtuiq2uOm/b
oQFxYIdqW9ce9fDHaIW24gvsgbbaan6XWtLcCRSbqd0sbwfLc9o3xmhQ3vNWRT5j0Vyiji0HufV7
UJOLfathGSWSMtJidL2JIGA54sSZeicNpxIxPG8R+Sor7mron3MNG3nAQxIJZuRr+97m2Hsr2aMK
gbYOiMNo2Yx2GuVpXRXBRwMntlyAq+95nC61ZrWRKja11dYDFsdNgO6cRyCzbhraE38zejRpnQY5
5Hr1+QzdiY1rQ0UKJ6C98jtZrGzqT6uycgCGbi1GHU0PDvpEMftNwuTEs4CdDtCZUxT/mmg86b33
o2dxSw0ra4yeNH2RmTzKU/+3ci96ehlCHjEVlimMyobXhCxt4kXmm/jnJ9cAir/QOH02Kx+PZa25
KjFcp3amXEIZAXZ65XcwAwjLN+uK1DkjViV1ycgImBEFsbGAP0+RlIYKyXk+om76N0YoPgobTfZh
tcmirYm43OGPdi0Amx1fGvqTXHX1WtXr/Q3vupZ9sp7W12quMq3cKbaVA8RVWE2Rp4E7kM2PeULI
IyCArnWkoYg9uUkn2SpiMvFNTkf17A0pp5r0rOcQxH8lTZHysRBvucwW2ItUDWuYmf6pSpDStl4F
n8YcfQNckh5h/lTvOzlTk68tTRc24vFgHwB8P7sg2yWKCCNmyYHX45CWTPxTYOzOmSiwIiMV1PjA
xbQkzDwjI9MduSJjZOPlruwXYs2Q85MBx4ZtNZ+E6S4U8SHt1lB9E9DKQoj0OmHtVsABK5HatoTD
HvayY7DzdBRuZUIxWM2AX1UuC8sEOYFfwJSGRPQVLib1Z9UGIT1lEhYA44Cv0h564yLUrx6+chzq
mmdB/Xhp6HekcoGWvGkbwhiQXEXoIDqXd4yynDruHTONWbIX0cdALItrKlZ+yq68FIcOAE8VxgVc
b3ZekSjDk8Vm21ICpYidnUCrAJ0w6ZNmOgGIAiEcyrzuhn+RD5+pbZV3eyUzdxsrXV+SYVFshLGe
EZsXJV5LOnL2PZAPb55jgzej91ofCLvtpl+zmoguTvFpSTsgNIHBb2MU+AY3xZYwng/7WW3rx+l9
I0AJcpMuqPFknmzRVpPq7RimMgc97Z3sqZOWNt4WVsZ+wGHFHRflHaJM2/yTkOovCnQQO/ehJ64u
5yKsBUTlRzyjy+SC0Wt1KziJnJsc2KDwXWd3BPmQrY88F85sXxJd+GlHCoJGXJTidxGAGIBqja1Z
dKEL0R9TL8AefaiDDdl1kwSFQDD0WAaHiYhTZt2nlu/w2vQKKgz1AwbW+B0EZjg6UJud2VT3RyEE
3y+zFtprbDHJkC6RR7/bCHEVgUcjKejV4ADSlqejeFjQMj4uW49Zca/fTYrB/BXSLthFI9siuy4L
dLMgK8uW2od7TcaVtjJCY++aGOnA0Wc24AnvmFMUdfzV1/9KqbgHLmAtXobiJdyY19pNtu2FAVWm
DkKOMIz9OPIQ7z2tMZZTXLL68lZPi9Bsr20PqwuUi9XKhWAE1r/AMjzQqp5muxBu0eXDkdDkAqs/
qrYrc86fkst80bLtf+A7KTML14ZZ4rGKQaCJJ4rFgdzkXjM2Ci48N2/fedaqIuhd3i1RmSnYvXKP
b0Yg4ODAhT86SUiY7NBznV6L/auYd3uRHj6HO5st+Eano82UiQZgKf5fl5dJ/RVN+vHjmQxhVsxF
kf5TmxbWcgOKJoS4XppqWvYTbBb0wyks2fkcdAk1hZIcl1apSUHeEcj4T0avd0SzC7zqUmp39NvX
4eosmPe52h1eJoVSr41VOc9QZyg712OBsEMGBT7sYEoIIhy6b74PZ3YG+83uuJQEO9lrhwj65jmP
WeJUpuciYyqT/l49wkZHoq7//4isEOdMCPw/yAKwoiQFY7WrlMONX41hqDkMEpfxov7FUWyknqi2
Z7ZdBVeKyTWh6LPvx/dTtVFGEYaVibzak2/p7rliP61Cdvkst5ccza7Mb1vF/k4Qui5wPEvN5R//
4Zv9fRbs0BxHpPgRk8IwHvJCo2coQJZJZsWbtUhMTatsmYC+O38Smk2qCmDh1gTV4ECOrYGYV5ry
uDQ9K+IP7XNXQWhaz9GuMzCwXMLZqeYKNHt7fjq3jmxnmRo6bKOO34ChOTrXOQZUUaSCS8zGu8EK
rCSVaEh6M6hoX56DgxSQS26KX2UDsJ8cj6kpFleKhRXLZSCupvHh52vrVzhg9r08v04T+s28H2US
mNGmMcT/HZDJ0bH348TFfRaJgqrSkx2/bnCFehY6UjzP0fcSWDnxwypyddSm5B317aNjDgUuM7Vm
bosPmwre1fUBGJ+Bb99MNGrV1i8ZYl2I6nN07/29ySYo0+NBcEi6CXjWEEJgQsSdyFc2dWKAnlpr
eBNoHq7M3Lg4U5Hqa4dL/PouczvbDyDj6Oz6j9R6aUbaNGsSGqGIlexdjdFhZDLPEOw+HzOsLFxj
TUsw2z4B0tqWoniWG77l2QlYirL/KiP6y9+ndLqpeEGJs1X4nElt1TPcTVBm/MnhJ4lbi+B7+jJA
bHH1WOISsE6EatGdNqlrVrbU+wcTkEVKjEHCe9YOhTlHn+HJ6bwNYjZcDERl33vjZTHEoEB00tHV
J6LApkkYeYbqhsPaJErUkjnU7A6VkVPZbWQjDXiOE/KAwl961Ylnvw94ntkOoBwqxJVOmKaTdFHt
HcPiLp6i/zdVQKHd8JZ2oc2txph/rY4uB0sK7+d2UVw1kCGAw0e+Tdwlb1ZIA/tLHOt0vm0pnSvN
WHJLBrsXWF55+PqJMd04cNp4ciyrgCNqOBp3HFo/LLZFymZ/Tjkij48sqHUZQkkbxRxSFGUz+sQ5
Si/pFtKBPK5GR/eSEv1xKlKmxIcUp+zEM1thq9C8F8PuS4sYg+fsn1HWvsC5ux7uPLYao57d8JMu
glmjBmiqkhE69Qb778/EQFMeSsxDAGuvtA/Tyi6bn/+lRbCBYTF4gv9J3VOqIsuaciu2+BK9Rx4/
J+tfdTmt2cpartZ+nNXXpxDoKlrSpO7KU4K+l5XyKB+k+yjQ/uRAfVrLsRGqnXguwQfAocRu31d8
Q3LR77N0Fw1mr+TaYkamzJm1XXmYPIH+/crS76g7U7KhgbpwaMeKuArLLqbHZSuPR1sZL0Z0k4aV
LmCpNwtay73U2Uitei33Ofd2DnCLb0kWC8eCrL0imvNpV+UI7oEHN3t1cntsbqU9cYBgnDemQi6N
Ky9SMAOobE6S/6T6t84UcNFowCFeKcq5x7+X6Vep7SnQG5dIFap7GCL5U/Zw8HNrgoiNJ9+leZzI
ZjZU432nVWMpTP+Kxq7QKoo3YRZeQeZtcD+EfiauB6VkqZCXYBN4aNlsd3kns409l/1/gGNedwzW
A1VNaqSLG0ES8tiA9c4Tcrf+ARakR5To7SIW0kjzB+sz9c9O6VPKvsjMHc3B0b/h7uwWeY35lNKh
+qa8FsAfEhqmd39VTH0d6Acex9yQJ+xrkBhEYCkMzo5y9vuxmOGj/T7o7p831i9FA/Qe/rd/SuNh
Emaw3ffUgt5jCM3qWsNHoMlaIM0wG8J65FBy0828jR2t6dUE27omBztEPywfmvPuzWQ+K8qvquVw
WM6abW4tqfamK1HR+qQoZSeNKltiOOfzFseBe+spMpIxRgwVsdF01thfRFZdqKoB3iuSQON+UiaK
ijTm4XZ4w+qVg00RAUSjfPHHuJitTjS451LpotrLUFkYGQu/mMKtAkfJyY3V1fXRMFTYxw3frhBL
hyEJH6IqyGmkAYy7cekDD//fSsROXKGYkq5rOxSAzkTf4pE0+4VA3qUu5HWlDbiebGTmntUyXBAy
CZi0jhi2AKGDBTQukPDRVLfab9EDYMgDaZdmD8+3WpdJNqhp1DY8uKzKxGqvrdawz5lzby7U5k2y
WovFaokOp94Mnhdo7X/6py4xj9mWqmDIAyp0lBt4R5AB1hTaQ6LKUSJh7+YfdhkM2l+kyYCMHIU6
51BudaTggl+CUOyt9GIyhzt8O071axLtfGWodexMRUON4Q+q9bsle33+iwerZLqAIPW8jB9yhhq0
8xVh1I4JZGArfKEOyGGNjxglPULIqMIpvFyk/lHJvPyUwqqUtUvyZqaTaYOaCArg6TFvQVDKo9vW
z7D7iM7XCQBAU/mTLPMXgzSiyQxfhXjjjQQSv+LeiGNw/oHSm9qbKO9J3q1oxmrvrk1i6UWK0gU0
kyifqUnVHzwoRATW5BPHULcKDsJhY7mE/NKUGeufALva6NsZfKdx1C9RQ2PxI66wVroCScaOI1o9
Q7TrH7beTraLCQi2GdiASSeiXiLp1IohvhwXr2YQ1djdy1NJNqTrXT8cg73mUjgeFrGZ5nh5dEGw
qHvABvT9RLhN6Pfwd1b307iFOiOwbTQUAHdjYef+a4l1mOGoG+/IBRGyjg6OSuZTSH8J2L4Zlcg2
qJvdOOhbQ38fsLQCkFGTMOvIkc1bVps5krOXZJr/GetehTOj7n38i3EQdjntuVc1C6GmvoCiuvTE
53eOxjKLkA5sxSiWKE9vSZbk30+Pp9S5Gfmvu2raLOX9coAOAebMSyIx9GexbjdCRsqidp/AFuc3
AqRXmXMJO+rGQqkZI3ixVz1W6ASQBXjDf3ohrrd5Rh7fKzWsworzCPeXrKT7Iix/95nTp8U60pyD
aKuD87yGHhWpj1bvewOLOLnhAxm9J2LugpbrEFT4TZAYZnTZR93sf/3/iSj2zBhlZLDLiNr0BW1H
SP5QvSLitO9KsWKyd4j4+8UqgnjJdyAPf4DMciO7qg5LylRkVLLr5uvn3F4+3FgWtkOm2+6k1tEy
H2thztCsPOUTRRVE4L4oraa3QZq9TuW+RIm3G3SiX6SImEr4FsPqjNw7/3p++32A2efFkeNLoubh
HTukhGy29b0GNHohljG94l4tsnGat04xHGro1m+9oLx/4BU0w2gpgRVpirsVtdafG4xsQNDQxKoc
j0okmukjrHeCz0YzemEp4lg97L9KqiTT3J/H5lJO8hcKFcfArXP8+cdziHR8QHpBcHduwDBkGqvT
tWtw99tqiEPCwOb29eX7ne6/r/2ooSEWdW+sgp63TJ6UzxfKigmohdDGSl47qDMXg+HXrVadMeR0
Vl2M24F/PPkfGLt3a5pxKTAM1yHmTzvh1k6Mhh12f1bsoYlf0H9inrkGYtkFb3FPBxoFy7yddTFx
WGGmW0KHTUS/l5eYPhMxt5lfB/TUoczsgywAj1VxZLLbpkN0mDiziaEEIuomc3p500o830KoP/yE
v5tBtrtzFOSOdrF+M09NpKIZsR1slWTKp6B3TAT/2DUqsjN4x53B0mFpZIPvPyc8jfjyhIoCDOUm
poBs44TtFAVkJeT/KxpVbD5R4s22zkxZ9hF5cu9uKttpoM9l07CRnLkozkXXrISv9M608EU03q9m
8Z5EHlTtNn2aoVYk4WaAd4ilEFxov/lSH1VPEHx0P2F02GHmXttoMqyatfXCYbjENPV3MMwoRy9+
uy9x4HdLdWvsawI4a9exjUutSjDXhk15c33j0Io/N8QvivG9btrodw8/pCTKSF/Y29DsYsZZGhZz
h0qGfncvFsdGm9bHTDkmahR8t2+IMZ8VqfESMbA3o7Vaq2eUsZf8cQ5dXnaLvuQ7ZJ7vJ5qhQxW/
9jKDAK2FDJ4+ZSpqzMmjbKqdDRfMzoFXMVPQZFNIg5X2dkiH7WH5E3shALPA++z2oMvRTOSYxx1q
04QLVDihHs+2u6WgfGm1agJBVuVHw0/Y6Q3iBYXeQ/WeAEYTQz5FnEg8iH7e06g3N3vPW146o7qE
W+7L4Y8dgu4dLblh3D9OMm7EPRUkXvw5B3atm27OY51x/nR2mIH8hYSLIt8xTP6BeWpJGbAdu1QU
ZCUm5lwn+uS8REO6njCkzIvXo9EejB9hdJt1jJAX/+uf+syttWh+isyw6qt1PyzMeSoW0ju4PpjT
PiR3nTz+7xbk1daGivQ0lVAHLOGV+UTHAX1SdVXMPSAlNNftilSkdk/GsC4bW1A2pWLfu5XSyfAh
gRQ2yYqhiQGU8U+K5LR5gEeMnxSVfALeKRcUqUpI4iWEfgGjpnjq81mQUnbb2dVvcgapKHa7jD4V
H+RjnKD1ujAUaY9TVpfErd3yhXgjjLgW4q3ELx4orpVNI43W1vVkjDMfZcisIaNgVUjikaS8nGfk
AufZKDAbaMQXvnQ4AI+LYaYXOOR2vxrA3qR8KCI4Ych/4p5/b5sqztIGD9I1M3plh7+B27sY4onQ
N6RA1SolzlUkyCyzv3syTHhahdea2fWtOnIfEJc72t8U/OXKy8VJXLOUZbPkL6MJvVrFz/aJFQRE
XksM3OpERutNfGTZnIyyF/iMh1R1OGV4EbFuBjwQGq3DeO9UqfFxo8q9i//ZRzG+scXouZDSmok6
JtD1lS5jJg9Dan00eyeyP9tC5cU31DmwvLfw+6WQ3FMqYvME4843v6bmx1UhzP7nEiNvCMwTWXkw
BJd6KrJhuSUgF29B2ikpXz1iuVL8XtEuQ0kwLNS47E5BJ42mHZx0Bunkm0UHf5SwgPWge6o1WrWl
JlYZ4RoSTpAko4EEKArfgQ2FxxRMkBbXZTYMDkX+ySK6xuiaAccEW3Pp0X0EpiRnjgBpCha7B2Ef
obJwELbxe98JV6Vm36tj0VknqMUluYDaRxHFcfElHDFBrwKKRnb4aIvZTVFfvRIqWkyelIkfsU6K
ggPrQqRgPOPRmjT7ZO4UMAo8VbRTxFsR5l7RiJo5gOYHOXUDhRI2XI2aOY2RQmyTnlb73mUNB9lu
G8U4MJyCOGH67y5mqyrjfYw/RYU5lbgSmehlOOdWYnaPRXWd3poEnfehQT0yyI8w8IU3TKVfLmnr
BJcB/dnCMUevFQDG44W/LI8P/Lg2qwIb/hVkauDUAC86xZCD6a7R5+etqaQd227CfLl5g6Ar1wze
lRDm/OszzTmvV3VshwhiLkMztwM6D3HKt2Hbd9AB4P/oIU4aiL6svOhKm3nHR92Vfj/baOJnvN/e
khmWJ/a3cDePtMnIr2NFPLQIOV42jih0yQykpWEDCpGtZ0BAIBr2TJg4mnNRrsFiOe7UpnrqwWOZ
01069WgqJZcAbp/YTelJ3Kz3FZRLDHR0zOqmexgLAQlj1Gw7vuF8aZAL+BeSPantJR0wbcdLQNhG
BIStQ6baMFH1QwQWSe/QbQJaHe7ZwkYKSh1+yanjIjGYi1QpmmFYA/lAHBTBC7zwu3Gxsbj0aWCC
opFvsHDOsW0KKasCCzQFD/q8lGmquhOp36bQE/PwfQ2kFOfwqP2IzxKjNU3kr5q2jHPScKYAgRp1
0lOmlQDOVkR555WRXEsho+/5CgAlIR/M77uYx+3In1p5cMcUj1NizbUQDzI8dlvq5o2A5+gALIMY
ZwrtKEggCGULMhyPTvVyVWtj2doV8CNzVVbmZm8Xqua5s8qOvoJ6REWj33lDtTGXaXauIyccxgql
6pVxj4augQiDhOO1+yZSlJHuRWcH506pxHCmgsk+CTTNv5yDSQALtNShsMWgky30w5SC+RtIaMHE
li9EVVPJi3a3iGoS3T60OCdu42hzoNphzVBARS5V/DbfTIHxZxO1VtQdmrMV2d80hi90m8VbTPAn
cC0VWgKP6/k6GTiaLM8ezJcu8wANnyCPkar/TkGARdFxPRukOn3IsMxQ9QoN6ezoaq98LjRmCly2
XSOcqLUokuECNzQ8eAI+SmYMFx9MMUNe3FzeDaawSbCuFdPHTROZU6nZ7O4Yqf8cYdBrbcBPhToS
JkLm2UzNgu8N7ERcMTOVauOG1AzxRoWsdMeaq7YBYh2BfmaSABINzuJEHOIRemJgGg2xyuFdJPvx
tfFXrw1ADz2EKjiGfBftcZNcXMgIHyiUVlxakPQEf5ZmHD7uDb0rTqGNbEgDdMsRceRC0MNIxpaj
XViCXxCwfcL4fb8E07s2hVHLP6ZbcKhgFa+TiCmghEypT9IOF8qRY3kXFAgDbdmqFHqq/gAXeXPi
Q/fMFIlOL7rONe3JrobhBiv8O8lJa23pfoQgUxcomWj1DuHCcM4r+xJ+pBv1Czf+XgVi+gxy1vQg
LVHmGwGqxq7RYQHUuuR8FK8t6zSE2zapbPoKXw2FZXTI9GytY3SvhIl2Gk35ENPgTitsIHuleOoO
Lf3/a2iBAc3MNVNZfFhr+Xmw/GTwarBKJPYHICfM3Q2CxKS5L1sgdLEGN8xEufAoQfPrUnru0NJQ
pbwjM94TqWWSRbmvpWSe+rukZqkX7oWCdMtS2SzYGRHxITAj0+y9YJ6SJ/iuSRIW/GKNNIFxfdLK
uOtSleiYinSTGxQquMe++c+PQgd8TyZBeJc+o/Kkk+bhJdeHaBZ/nDIDHWlub/Ov4PGfGlFRGKTp
krb4FlOjmIpiDjP6KqR3X1JqV+PHEVtQ67H6inrxXG2GN+B8PDPpwiVrees8fsB5NK4qsp8FY84p
qMsYCrylazB0Oxjm/2ipaY+dMcuhRnWKPSpT46rO9hZCQutzAQa9lP2L2x9dtcPIrUlzMi62ef/W
wiw3mXmH2FZJ8OVJ6EQWk/QEG3CpILRZLzXtRoTVbPncXYrrKkF1/h/hG5K6fpKoiZolSQ0h2rMT
bcOiIBVMxVUqkYPdzOKTfCSfZboC+4ynwIyCAJMxpPea6Jxa29Kfl+O6L2vWODNOKeagGnXnoWqS
ASXh3og4goaxWNHFYJ6h174un89yTXakAAYPvmIs7h133/aBoPWyo4ZUNkhGRG16NvBQ4EGut4wb
XsD/GO5womVlY58VgdtFfHn38YulcryrT22zX22nBZgzN1jr4XmVJMjNXpZKR0WuVzEbtvgliX6O
QK6e6y71MbMfbtb12PPECaDgbAQnzqfSzZCoOuw64MoNvK6eA/wc09PdPUTmF4rlte+hR8r2gqsj
2sbvKCtVZWVJR8ymMUPXoacEODT66YEPsgqwkPLTUbJXCFqEj4H3KIGMhz+ET3DXv+FGQ9a4NbWv
52Jr5H23zWhjLyyxawj0frB4uBeb4JbEwouzcNEyv3Axssyt5aAvSqjgNjnoyHmS8rOmVYf6Bxkf
kEZKQF5igO3ncTooEu1KqY6nOyFVQY+sYYOqIWGeoLSUqmzA0uBAPuoeS9lRIjoFD5uaJtV8oPO7
oUXfVLrCZAv/t/XPTNkFSkzi5NrNq9YFBU1fu+XjFvCHsHJxjSuMgv3lACzCQJvTlc2qHv5rFOGb
cMIxfpKfsGt9Xa98PpHotYg4XPEfiqQCPGN9CrvpgQMpD2pWGIF2WOeTDQ7N0/5k2Pdrr81VjvyS
1sFKVs6xQSRiDarx88aCRQRGSwPfgMa8+moJI4A2YaAf0RKvv+fZQmEBhhXytlSvwd5l1DdyhvkO
A4HRY8+5PWvq9eAvbHOh+GVNYaXg5OUdhUUZ+LU9KJqwlrarePPCMA+O/QjI7UuLbfVuU850B7cE
JpeJkg2r7qFwljMSnuhs39BhKdnG4vdFhFjQDaAjsZ1CfNGn2YIgTXXYCKXtGIxmqkFGi/+bk2GN
jbcLWC70ayxKp9GX4v08+yYIshA3TAfKX3LsqbtUUA8oTnlY3h1dUYiCy7AXflueAjExiFN4/5wM
2IVq/nD6wQevyR9SST+ZbwwN8vfs94Sjbu+9jK4eKb05TNsZjVveVfgyISL1EO89GdqezLeg5na+
MvLSULnkVhq+2cTtitRsTkZBttavwg2FFhTzHVdA7Xfs/5iOwVZlYQVBwwmd8HT8/8mqqFbD0G8c
+wsFBNjNG7bt38pHECP6cBxXTtNOMfIKH/WyBC8nvQYq0DzpEbtG0Lcb8vXulbGZTh7CjphSILQA
/3HpQhOPXH7rxNEpH+hkyydKUNVTZ55NfMdeXk6NdPXhYNIpfeFnJOd/yKsTvfjSdgjs6eBgHJWx
JvajsPuFgAmbfim4l0QFVmtaZfz4KkY5cNJCBNovghDrz4LEhBDdMXRXbZncce+0ROSN+PdhRQVR
ncq3Hf69kGN9V4rPK02EjPhVh3XtVojzsAmmCxqvgkbBKnAnVqMQHCplI8cIA1jD4TeG/zc+fFsi
W14/a5Ir92ZNurO+WTzc80yiCJ6RmkCLuEvzd1JEsl0dcqkN10NpTrdnHWJdJwUzDkgkFk6AalnA
AgAwCkh7KGyJ+FkFgyZR8Q7klFwkX8SKllyWpRkYohao6F0Uzbfv2u77aNOHHVYltkf0pTjbUfNn
jndcPGk7uAguf8Y6zekJFfrut1TVKxDZJac63uc/bz5fBBixpOVyZ0mvbeOCdtGgXT/RaScrgUgs
qlvyCjYecxMPVH6Qzgac/jIy
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
fDz59amcD2ea+YXum3GKfONiBJG3innBsRyUxV1rlQ6FNkoMgcSlxK4oSOrp9LymStTqicyi5lQY
EMQ922Gzkw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EW81/8fUAjGFZlQVWZ19DYMecRfWlAb/dNiQn3NV+A91XEgqi4AUWVHT9kB/hDInZfThvsDIDkcp
It1yyv49lnQuenoFJJ8wG6MF4o+N4oR4sQm4+czP//FJPyQDS6VTzukywSYgSPQ/fsC64od3txrG
uijrf5tvZnNo8hhIpzI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hDTapXr9KHjx9D3P4lG8z/KVOZ1wdoMxS/J0v5I40F7suEMgNlb5jT4S9EWblCSsQyRbUZ2cJgzM
7n07b8TvYUcQEaZazJ5n4KFQaN54IdcngMDM4l0bZEYd4SuPpRvlZXQ+iqf5uyNLcovPTy8GFC+q
ZbiJ2Qc69Q0yAOp4n9cRZV8RhXPx0VeXmwCeJWrs9yQm5AmA+9qd+p0vymu3hKKhqPL3b5avcrlX
HiakdOlRulVojAao0jv6wCjj5yIDRPxF4jJ8vPDApTipaoGedhL43ZmHJA6F4/hjghTXAkTMOB2w
kwNgNo1uE1v5l4Xj/pAGFaDv5jUEHT48ERpaDQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
E7bd781u1eMZ4Frt/gBOy9RrvyjBBiDai/k5W0Q9P0CJVoe2p98APo3SxRo5oMwZ4pWOIJgT2A/Q
9nnBnAwgK7IpR03S2LGE63uCNpqXJuGJD+GIwSORDTMOsx2E68Y0i3zTWnmENXRVccWqQKs4y+Th
zvS6J08q/9B9RQE/uiI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
CpQQN/xTLl948/fZK1U2+mcJlhjJsd+JX0+exFNvqzrIE+QLcVxZjt3puwA+EoZZFvUsBz7g8hWk
jvsac65QBoBF/ZWZlQA2buttvfB49MV4ngXYXsbyiAtLdxTzlDpUaH2dp5xTUsgrHjpcT+CVy79X
f++f5tO4wI9ASgWK8kQhAvbmNCXpUoHSX1nKgu70hDOhPQgUYASwCniYA8FkVrmcWYd3WLVIlvuy
11UhogAa0sjhRLwn+G+jPCDP13aJnq4TCwLxHoZ20hU4Cob2Q1TnKKqLV2MCTDo0mNhHmN20R0C8
CbQdZ9eLGVLcsaamLpO1jlqxcL0EDymH4y9P5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 46416)
`protect data_block
vgJFCS/D/CTvRcP8wxhI+ZG6re3ln3+LWGs2BtEvb486albsgZY/GmkjwvA2oKt+zOlU2xSM2aho
cT1BDA9vdeAHrRl4VScAdbWC0xtGovMM6/OkJmImhXSzoQdLSVxIG4jneW8fn3ZZweUqeB8rbBXL
BxOVM8cuDu1C2cPGIIzxFMtWXM0bxbHyN5R8DEP9pcI7BsyBxkFEwJqZ9upWADocRKCxgjET5Y9h
A3h4RC1AlMv9bm8A3YF6bATcBOkEKKQ6zfQxsIuaGEzVNGIX52E/aqCtu7GQ1hyGjNKCYkgK2s98
3sUzV2AoUhNE2e7y7IStefhb7w8Z/B2Df4KMGq+N9HMJfYuCVlNAXkKJFZMHZCzHdY4v7ZFapXpC
oCBIPNRRUufNsil9OBfj4AL2TjB6eDfgjNUGCYyBXyrgVk84UeCSEraRvLEi3Wxex8VQ8a77e0FC
SqfEg/au36HbQeccHQ16ywlCUiJCGsDiB7VYOJGqZuuiUt/8HgQDpQj7YZStSrJP8/+eWcN84Ttg
5ufn/eidiT/haQkN/5zaaNbJELLozYhuxTj4zHnis+8Zbx/ZM41cq2XRfT+fuZirhv2qOAn8m8Tg
r3oOnn2z/YuRsGTlg7TF6Vd4ScODW60NcNKZihzgXHEdIX8FaGVEWyXQr3UpY+LOb3U6Qftf4ghA
7VbTsPCC3Gk62U5g5ENoZQ4lb5YKY8KNvFvIqh/woUOcywBBi00gExLrQKn6c7HzpZSucZmkJL5c
eR3Pm1ARU5MObfhgSOtO8/EQBiWVsg2NhZ4OwSOMuC5ylB7b3r1JUM30gxXqLoAXbUy0CGtAiVSX
rK0vEVzvbFFqeC/MV3APFmzHI6twhVzAshMPnaXUiWWfCkLq7ScZ639J2dFlPi/sR+y5LqtM8BLa
LoIsETVAdmkHt6UW8qAkKx+XJLFsft+svCm2PNIdb5SJVpu9vhqVdIWHbSBUqtYNsJEFXod8Ip5B
Ee6GYBR9hWhVf4HZ8PiND1lt+VlnQ6FyuhSkE1Xp2TrAPKy/CISrNd2ilkD14DhktDuyEK+zU2Sp
kAgqb/xGisAS0dBHL/QdmmqM6OleHpICkpWwBffcmOK8EzDWGV/hIm2NzzhP4Yfck5jZkUijyElO
o1eHuVGRySB3gSptjNnvyGO1XQxvHOQMpD/oNTmKgWwthpXYfyu3Xy+0mCDPr8r49LzTQ1ILFDCQ
mbxJ0XwhNRTWdlUCPWn/C8DJrpOH9skacoZW4BKcPRckC6z2ePVnzUVrTz8kkFY8a/vD7lwAeqnf
oy4jggOLwmeIFLNCFq4YqJbjB6m1m4HJOoOxftX9SjZdOBc37Jc2IiE6R5MKW0JvgNpw6+Er7PEV
mQSp44HuON4T3+XwARarpa012bOFrnDH4jPNw2qT2MoGkdhLv/3zlKSZ43DUsm0hN4r9ueREbyG5
LWtaJdnK/h849GijRkmD9g/N2biWQ4PKXXyFsLNXg1vMEirPlRm0X8HyAMn4exxiWOJlp5fEH0WI
i4fhcyymD8U7M97iByo+LgVAPS0IFGE1Ww+JmhV6StML04BXlTGNN1z2lxAJNH2aB7Rg/pMbGyC+
2Sxz2suj/ZXZgUChLHsmKi08fxZcqXSATCrqytAAoJCXDXWcgoqtL8k7U4iiSmwUGUY/xQkj+rLf
jO8efWor73rNtL7gQcjFZ2H29cadMD9pfJieZR322wKr6V8+/n3D4E61Fv55+OsAQYnlsAhBPj+4
yevgEHkoF9ifTlCWN4w58qxm6bPDjWCfTmzdcqohvgruWfz5Yuak3ovSSuL2oirxdNZ8Aada+htD
xGeHnOuK1aB7WjGAeRsnq1qeVhm+iGs/m8mtjHshxuaf0rcRiyeiWVWJeZIeVnZnwxiB/fVmDjqE
8ScP6mNxAP1/GXVKEBWH6O6CPQaeLxUAF3SZgfaThkgR7o/5E/tRWlTZAZuQkxvDCfstRqZLO+Bg
rtjpxoL4HmJVYIwpNSspRWwJjkG17fzC96yaA0EzPFC6LL3poSz6OpZ90nsMPhyW4E12a3OLmFpj
sz02VWc+N7ckTNilmgylkNPgNmAu9JAD6PfKbzHEtSOpoRRHDtMubn2Z2pQDpchDONEiU78+Kmsv
0ey4itjYVfFnRQO/QqCg0b3dw73qEAbkuswYiJX9KuBKgYv1QPG2U0UYxm1SSrrzyGzvXre2065F
7rX6JoQROZENAtGGaykqZM5EpFKsjnr9DIBBjoh2dB5SsMrM+rCjNSfmw6ERZgngo5Gcud8EDW+W
CYQvqeKV6VsOuk6Xn7DA1n6PRV0+ooi5SHZlH9HEgVALm5K7wjWJpkHnoZ7WzwLkrowCHPItZKM0
dScUqT6l6rWEKbcqSfX9VoBxZnIBWE3z2z37mhI6xYxsKD096b+eQAk+pmkkY7YBOs9MMKt5KzcP
w1lpR/xKjzAR+tnWT3L1E8AIMKu2y9sCa6OjP3ISzNWkyNOKgDzuxbAH+lTkt+ne3c+sjrFRni9X
YqlRd1v7fdqgc434WLY2DJ2BtKg+eaillDcXobEJAdAXgSrdWs+pQBILAZgNdEei36p5R3PhtePQ
iMwBArxKpKV0zLJbDUFTOilbtLiv57q1VyorEs2jsLAntnEqsQdU7DkHGa4VLU1YBfFmw4pAuW52
do2fYJJoJBH0k3idMOGw5ePMZvime1F/rHu/xzs8zmYMmX/aPbzUND/9FPpmq0BOQvTZKtXPx3DN
iY1gZdOSPQlHZWce3dDdYDhaj7zE0MBCb9mbVCWF53T/d5VXuWYodVeXofz5svJm7wS8FCBvZ0DB
2Iybz38u7ic3wiatz/AJf5aYDX4DSBEqgRRmhCxmOjFrsqvAmJi4ss0jLBpQ1qgGArdREpuMPYFO
BLC62d81p/vVyp44F8TvAhKpD7Bw2uIl+8PoNExXjkQeHt6Ewwrf+NY2i0Bt0PJYymB4mpXdgM9i
NLVtDZEe0sWyaiqN5jtlDB8zmntqX7dTvzlhuqfQnkQyfouHOfJbpoJLGO65jLhtWJ8pjqvYFsGL
lCQQY0SLeVXr5qsIGgqt8HHdrmICy+bD+EbvNzpRttrYN9eMvlT+OL8liENJiu8bTORFhL4G94FS
1/1NmExYi5bTkNKHtcqkity0ifi2CO/99ogINS0VmGC+Bkmemw/7+qBMQ6FmwcksiPqRNwt8NKx6
VL0xtGZ70L/T+8WSUjLmn0YRqCGriOUyGj/NLoJS7jyKh4E4SjJtI9bqBgTcY5dl/cxJbioJoQaW
zqQYzHuda+mBquiQ1FVpWdu7hMZJsNrRpGPxEHgkbmfEBWrHJ6FuHZhyZYquetNhVAWOvQ+sHKXk
M5Fh2tFKAllBnXnYF+zbGNiedbhzf/8/e/US/t5+FfF+jNUy70LcMWjnFd91uxvnbpMOqoAIswkj
b0i3sInIIlQwo/CEkXBDtGl2xOUJE9gyjIoRyP5zPG738pTkm6TfqUhZvvSsT/QJ2yp5d5dVZZm7
FjNlBV5BRPd5Z0JfbwolZCHSPv6uuxYVaYd0RO6b5TrTEQKAPuI8hVlL0gpNmVyoFx4A2hvVEdD+
OxsdLGSOi9GbmF7jr6QYTEWt9zVR4pYfhk5LlKF7ozc+tQx8MVc07Ad6sGDfxbndJz0Qkhu8b06G
urYsdQV6cEfAm6VFp6P5G8aQHYQEN3WGjmW6byRqYGGNrP76Gt9GM07fRtRMr8UAmIK/WvzMU2CY
YOOyZMuWuEK6z3m/dQ0bc0r///iIm/qoji0NceqJgaW2foDC4srA4YLU2JsSKxX6h6To744mCWTC
8Q6kciAqEmKcErnyDPCbxWQsexO0vCgp3ojikr+5jFWDYRdb5L65tAdyqYIXkIbm+uPLZ/RfXCKl
qAdY51BF8amjrRsUtSroQMxJGm0PNIzDU5ONoYQ5gYVIu1jacPSsO3gNQKc/NYLYgowecaiuIK/9
1jABkeTryWlv+KmshPf/oG1seR4WqUskYqbF+Y7f2dQjgFfZN1FPXF/70fOluQONT9GrRWXtjfwm
I5bDVORKjspvcRkgZ+bWEVuzDato8A6sJrUUAdLVtoY8JuLaxnDOhRCzXjcfKJ8KVws0xDFv1wd6
L4kIFjvXQC51UCE0d0c6Izq074sLnJJ0xpPJMIgYfGux+kRSe7MlNhILhZdQ3Yl1RkPWSNUvFDSp
o/JRiIkgv7FjimPeHQvTNResy5n1vruZVM467KgLVAyBERRY+WxbPjxHKo2BCh/B9vDFO5fxtIUu
2iDia1032b3N9bbaxPp8qVlqfzd9ux02B45fYWm3O44u66IDRctbLcHm0hwxc3GiMZCqVs98vk0P
9s0D3jRVNaeVXd0Yy4Gfm/p73DCeOkDqMWEijUSQGvlhT80BM0aJtofLRpCMbJvvmL3CQgMK9CSY
XhGudwMsQGltaOAPs3befa6khdrJjAcb8pxuMpYO5e2B34UFbPDZVJgJySIRzZD1g1tHLuH8GpPI
tqexneauPWthmsAr1xE/GJEz6HDUKHupIDIqzIf7WFMjKcY1rQVi8q2RfYFQYp+vQpPRtDRFFjiS
HLEoiSZTwa0Rsl/25jMNQCH8XwmETRD+jocBVOWP7U//UMFgfT5Abvt2gwNqhhtC6AvD0KKYtOse
fADL1GUKtgWL8jMKsADXE5JkVWMi2TaMsVhgRl9rSc6fAo+muFa9YZMt4IjeFFosHhCscOigcNYM
zGTPaZHEhndwW+25RgR8Obt5ozdM+EloC2yOatdZRHWN4gGGZWgFPCfJ7v+k0xWYo5WbbFm/Pqqa
9VEH6jhTDDHWCs0nuOdYTguGzxJNJban/i87VzUD1pj9olHkw5rOgSRixx2FEHXIoGupIV6szq+w
2VNIs1oUMRqo/wQtJ6FDH9fG7zFUPCVOS0LG6aBv1uLkr3KrejnFAC2XaN4MYARXtUWhx35EwLhU
YSjMbZPxiw7W0U34D32NNyklcvqyI0b7geldFOxm7IIQ7Pxl9CXEbXeor8vB1XdtW278Tr4kG5BM
nQJtwAsNRe8oPiLzG50XvCX5uETmcHTMmtSmBXUbqzVP/s9ufOn70IAW221OApnQ+2RMK30iFoMh
5syIOQ/N15t2DLgdSGUIah2DcbjeNeTg4LiixjcaiFtvNHLoEaFrc0/Fg22uECRQTg/D9+z7AAYG
u/aJdqUD74ML7i24EEyuhM3w6Z9CXR2vVRXNaimJy3l0x12W8+QK5XSKn3UWeHjTpKG53ein5D44
I0kUzdFfPW3urnRrU5JHeHDcKiVmXLs3GhY4SYCx+FOu5JOZ9Z4hR78LS5Z50qJv9B+XK694opF6
7NjAMO7F8BWklLJIau55FeQG+E39YdlcxkXOMCn0pJKDzVFnixWLhM19t2nvfmA0kEbhrL6rTM03
BJRAxMMsMeYwae9Yc0KP0o7NUbGm5xYqGxI9TKmvNqJgdBxlEdgljmS3gvVGyMikUiwq1jlJr3z4
REIMaZCqa2vw6T8eCCqxOyD3hKgyfnGmtgog9v7GvNi+sNnlpPhysaP54B7AvtSe4Ax7gWKDblMO
3PSAzzECc6UgV8srdjhOYW49vCFAdxBlc3KRlCytiejAB1C3/BulX+/XgxUkt2XxEgU2ZLONrotp
nCvxGf5WGi2rPZS+7NAOrb9SD3z/h67pV7GDqXLRI3fXI3IJ/wCWvIYsYGayQm6XdahlL5Uur/md
l7G99eUQHlfc3pb+r0zbTCV1+qk6HCfN+gW6QJnCmIfxolx3V6XOsTP64C1fYmlsDKZgDIceo1E3
D/WtTApvtd12PbhSjrxFiWfkrXDTl64vRdgOBSh2y+7OCD/mJpjvMqPrds63rP0Cl3xRdGZcRYYA
jUnbgVsiqsgx/qkXGGwufbEVCYwoakvBRlJo4Mw24O0AKRddzUzAO8tZKm+Hx2TJHxqMkycs2gMM
FB9wsNesZDWuQbYkYfhrxdxjVMsCzwLrdkKNHySpcqwLNs9r3kLkqnNIfVULf+C5kyogRwpPle/y
p/hnWKBWc/MUK/7pdRu8riQMILBdcQEsr3bcjc5cPMELwx8xukmEGK7Qy2qibCfyJA/DlfjgaiRk
9qxaKep8IrATiErv4hDM6LNrTfmDPOLXmkoSqsZ87u/MvPwhlrwQ00SIyKtXue1jH+jQ2Karopq+
EXHLqgGcrtaf6gkE6DgAAWz3sTKrgRgUzrCwfigs3mVdryIx/Sysymh1NKFF207x4wzzN58vZUk8
fKByHSwz7tkoa7OoBZikuLkz4/F7+Cm2ljuoStc73fgRwpa1TnD0V+k5SLhiWL9lQ/xC5F1I7qTq
wa+Y4MEcp7EvQzlPQVhbKT17Amy4fJsAkS63tvGxUsusTb0a1OPASOO4lMJypyRCHnyrvb31yZW+
o3zJaz3Q1OLPtrYcbc4v9HAsxtqSvE7/KQt+8zh2nxHGi06jfmhCdl4DceV/hgbljJhujKO9gBUl
imARZqw+rdl6eNSx8bYEKa1ykFq/UQEAb0rywpgp2/Zg1gruFTMSBqzYXYnRbpIMoOxGtTrqGvn1
w0a/q1p5d8xqeEFOu5VlehoKkTc2zC4F/NRNKrkniwPwZrGXsCgCAL5xSCR5G+ir984+50Ce8+I5
UcofwUuO9sJWwDxrrSbPRBNuIAaal+2JszGknM/uyOpUU7LJtdfdtALs/lDix7BULXE66IO1lCDF
9YoG3+3Igo5MXtbmOXbmvs2S2y7niTUi8agaRpVD+aQ5X+nSb6WJHX9jirQVzCwaOyQQD7WFCdr1
V425melFTnNH0LtNxzWs1r4cf6hTeF0xczU5H4uQv7S1gd2PlF3BTVG6EFPCthoRoxMn2NBr8s82
oRUIBUP/1OsNPdsH/2fybAZUaD6sfhXjBx23MZ1Zb1i5kXnAT4fJ5PP6qIp7V5LwuhsGhnkpxHik
U07Duk9DyMmdtQHFpluiwPrWoDb+0jOZZH8JyUrLHjvcJg3JC2KUYjQyODsDlR4OsgAJUmXYe5HS
p8KwKJ6ZrKVfoprdFsObTz8xfqwcjwDr2D6235/NKDXqRQGyooWMYPTMTXTbBXNKOkwchKHHizZ6
P31e9nx226vY+wFSajFDXsJRlS5jG3X1VlmbMO/hRiohaOQh5VRTRcxjB7l3G01Px38HDSRs/kr/
sZuNHI5FVDtfmSVV7hUuxDeZ3kBfhF3fha+mi5JPAcsjUsWYMtYDPvKW2dgvY/bxGLyy3GtVCv7X
hW3dPQwOkGdOAFdaGOknzToOTON4XVoUTIg9c5fgp33bEC+siIDA4AZX9J/vWR784hHdnFrq0dYF
o05PCxivxzDA9T06PysM8XvlU/ixbBqoLELJMjKUtWSEJ9fGwTTk/623R2bKvurnR2rEAwkWLQre
VvsRCWHNGZBLH3oRM6ADvvZPTjK5KqCmod0PHtjuBptpKg+v3tB8RnRQXNkscDePTWlVpmM4npGA
ezlHa3NezH+wfTIVjSO/kzwzLa1PCwTSp+FSGluyNo+JDlcqkpHdso291UH1c+ag7l8+yXlqHMyL
+SrCFKJUhSLiS/rxZO5pRFkGR/m1RjTC+W1MHqxSxN44adbd1pqUKP5RopDnjGZ6AlB8RJGB+mwB
kuFDSOqBCbqP7SwHStpzK7WhK21Kr9BU/NrkX4z1c0X54G1w5FVPlr2VQ3PPUanxJbnNLfnckg3A
buo7sCnKEZAHhKiORDOwL/0yXbWtTAZQ4CIcYxVYO6fOCeOyfOFrKAtTeoishrPOoxwN7hYxRzqt
KOk02LChYiKQYCapk5b1Bj1lC//NhvNw+NKXRS0g5t1FpwqJlWt0LtU+7wrvTGcg0isOjR9ZBsOo
3byOjBnNPNgKRzvssaIY+OL7jJyyjxUKdqrKBunGRzoYMiFMzMat6NcNW9RqukVJs7faY/RlogtS
jmzEiwuMvG5j2i/4mLZyrx5td/HutgDhbiVdd1Z1cFISslIrDA5xiuCoPPpeCLdjAU+5l4sqswT5
stp/v6w1GPvWaQNdkWk57SKngDl34WOXTfPTH1+zfkDEbvuo6BZpHfWIk638iGgXlFqf4D4vmpqs
6Dbpj1/avOFInPLvgtPYBx8iCP7z2f76YNA70jZSRF7ani7vLsKOeAWIFMQJQH+0mAtZD6uPnyMS
/nuhe5GYsN47bDr+Rl8crPpGX7gAe+NgwBZzAr8DT+M5J06JSFcd0fkoHCyzD6uKPF/SGw3TKR00
c6b9+XZJnNyJ5ZvK+wqvy1jGIa9poaDLE3Qz4a8yd5JquMsgJowDe7HkFIV/duBH1OsMYCmS97k+
pbwEXBD7xQvf1kfPuMACZKrLIQ/Qfm53UlajquZPw0nSIYKKnM9V64W/8D/CZUTkeDV+EOgA2bcq
eZ8KLs5+LvQx7bqK8E1qOmHKUVTzXY9Nc0kffweFX/wLgLmdXNbVOaFhrhzYg8lr7Nl9lNAwfmoV
cWEkcbUopNFL2O93QEeCYlMCnOyWWuf4e+SsqGdbYr5TqYxSv78XgGKbey6PWU/BiJLl46QzxxAC
3KrXD4VT7kHU0lNfw0Qv2YfOAkF7vOvFhNUA1TAqGLAWPpZwZJRoi7K71JPI6FUW4VoLCVXh/Glo
7ECy0xlVKGD6subXBb4WvTq0YMWEmQfOMNhu/se9O/X1RJt8t6vwrqaSS+F9Cc+svqgG93rh/XN8
IEUrQtbmzaooqQ5lANNT52roGNjVtpS9IjUVu0gZSrmk2UVmi7nhT3eQYcuaFwrTfIyVv+EtuUyC
etOnsEp0oaqmx3cbPBQZ9IqVZAqnAvxqakLDf/+DVnvagHIY0YTmm6T/G5dvvDd1me6rlxNFEkTb
LLbJqiS/Wd7Whd8rte9bpCClb6DF4ithTVutK/autLk2KsuvynwEQHfN+dWlBkrKLPvnUf9fSrUP
Y/Lg77Ppvszz26jlHdqJP1yW7k7vHM7mCjU2bev36dWYeXg6/L8nat6mpWWtm+zRoQkZHd300+Az
JOmGkYxqtv74bQinO0tbX8nW2jXpJ9DHk38ckyZRnjgC3OrSInaiKsHBlpRkktEYTt9YT0aV+qbZ
NU214I1BgKfrnvIR4FLEcwv5A1HUUp2YjZpRQJ05IykBmwNc09YA5iGgOEWfAyNFLF2USLn+Ui3x
8XT9CkcrYSouFk4g5y2e8hXkIXepQgn76Iz6D6nwiyr/vKualMSAUnMCq7zS0+586Xa7/yU2Y9Y0
zeA5RynVxRPIh0IleQi9mLHGuyRKLU/JpE6cFyEnowhBAvmLZAS6kW5SJkQEyOtzv9LPnbLzl+dl
gj4MGIOTH1RI1DQUnJtam4Vl5uL5YjPlicwhCDKzUN+R0ozgMSEqqgz3xRVAwxeUO99WEP2KcEJ8
ySGLB/DK6mwwQmi2wJJrEOHmSOv3Sycoidh5AySEmVl8I9z/qbozdUVEZWRvKb4wD6+41plnpUN+
2OB1ZPO4O7v6J+ziplfe9036cWi3OPW3l3dyzqka7CkZ0vde6ufdgyx2PpJBqjlJzQ3vt3qPsCS/
bvGQ37lf9JQSFwDLagqg4LC5cF1rthNAZ5UMEqAKCB4yrvwncl7qxNlD4XCVbLGCXWW0xyoJgfBv
PzjaHQuLBPT/oZTQIICQIJoak6rR3lOVEu2VVGGfsFGkuh85qKezQ0DLBxdZUhpN6ykiIvGXfUt5
3I966qbCSjD8WCqd98t6R7XIoRcSOuNi8DSqbrQwfjrjcdt3TsXijHr/T9ukc0nkGmufJRc8dnDT
rVHzPN3Pe+O8liKk8Vmurr8jvoCgGZXgV3qGeK1kcPie5gUu6Xtse5nZKFerUoBEdypA+qGgbkWb
AlK0eZhDmt11yRVW1wn/d6JOQEKYMm0CznY7jBb4YCyZAPmRY4GuLKeVSD0zqg1ML00U5qeTOMEq
jGby/rFgpPhtli8c4g7NC+XVhG9mX0ztu0Gh0PUDt5s5F471RYzYrJBgK0dMD0kudH39Pqzj8nli
WcfqjFQ4zgPpH0TzWoPLgy8t/ylpwY55iZUXgCoK3Ixfnmi4jHsatQUBTbcdex2uHAThMbBjXUo+
yDAO/rrkkg83jA4FwD0DzPrQyBn1cd85Fqpd3Nf+hiWfPE75rvoYwYMuD8DN4vEGje7bGGk4W14Y
jqh96ZCWldyc8UnyjJDhRk6cEu//wK+7BjdVDyc5XZIYpqc6LZEtTz2x1XGwZlKG17Oqjlyi4ePM
hz/0/GJcdLzI3SMI+7xBUvKrzRD3XPYLSSekpZ3bbIhoQ5L2+gx0Zedjm0BWuPcwCepINnbbtt9h
aUB37Kr0fwo4+x+OwnbqUYZBT89M7MEjicu4Idy6L9l3Babjy5d5ZUp/IYKuMMI3ngE0drqoxaWL
vlhvn3UENy2uJRhuJAd/QH6YoGtugcOBFDFWrn8NdOFUMUnzXDvPhbPlFX33BOGYMpsnMIvinnuC
2JYBKsb4w+YglyDgC7nKzU9NlsabAiHWfwzRGNRTcz3HvZ8m9e0reW5pPmwKi9bZzaSsHtAexZ8E
cmOB6RDpDwuL3i8PksHwoZKekjYOXKhM7lrYBmna4x4BKb4Un18q2h36eDn0b1SVO7hPU0zsPbrR
bDwIl3jfpd9V05wRAPcye8NV3it+6bV6I/14TIWJA+9Owrlk0ldRhHK9NlQbaqNRBM0rPqzmQduQ
C5I6IpWthh4OECZVkI47M/rwgW6cvYbBvnD32dVrlDDOwitzXrybkMMeQHXeIrY8brvggz0zfDPC
uzLj1Ht5bbxpCECQm/S2sjfVndEll+po6mTaWQzVwKOVUqxoxM92eIrflvjQh7R+ghnNaJgQ5cZp
z0iKEWzAcFoVUvtrVwtr3DG+T0I+4zOljwk6c0cNi7YNPrEH4QsETWM/4l2w/I8TQkEBCna6YNLB
32NpMYnYISikMxBYrrSq+059OTD7frVqz0g6dzPgVbT4mzEUMWnPonI5DiRYd8KH3fHTqJs240Nj
Wy29B/puQtUx/Q332lCVWx0EMd8mFGS5jPLj56DvrRj+43LvyPcy+2wHNdoO+ZsjiBIfuxmdXN1f
tU8DF/kkqxy9fRNzGl6q8StlaOOPyYDRXzlfIkmAj2Q+4/hSKBxj+bR+xhGT8D2xlXs/qKNMTwHw
LvEdWUuJMi0cni/A77P745jnEUrDCkNBSzI08QceWxWjuJZed9tz/riLdZXOIGgWpIJKVs6IlqGP
s6/zEbOHLMcuEck5we4M519HoJXTXl7dXDYuG8J4mY1wcJL4aebbBi7KDd62BcAMz/GOFWFI24M1
nsz8su2uC4g6/3OxXy8Q5aR7teVW9PkaW/3cQpBIj2A9Q5YLvlEeNt6L2NKJl/wRnYGjCAU86/ZV
NwyC64HkchvY61+1Ny4w3Hrpzo7lqnt8v2FzuDVobEKRQkc/IH45zZkCEB9tjQICwh6EyPCLsfW+
vqNljUzhdeBoP6thb5dJm9Jph5HyPJc74qRylIRsddVPOb8L9Ib82MsuBk4GDwcYwLoUHjKTbK9A
SzfQlIlZBf24wMEcYotYI74uSMn+M+gJ03ZJZxQ0x9ick+7GlZ1DQTAOLtZouzU7XBW1L3/swpKt
xYJrzjs1w/zi6oP/TT6khBrR0YlYve85Y7MUrZ4e0We5cdnl4uRcZ51rA1A16Ty6ipSnubp3ImjA
DG7o+BxKxuxjWq3EI8s6d6VAOaMIfjwjvrU44roo/pQ+dvAqfyDLySueQlOgeCzpgDdbvXM7Uq3I
qWqLtSyzfR2ZHH11d6UpxDADLIS0elScnQImKhDBj8sNjTmGAoVj+NwpQsIm2gi6sWMwWvLV6HCI
cbi1OzvJqKcNaove5NZacdNR6tZ4HUmLCcQk5BnPdgnLLH1D5fIsvfwPHXI/vOuzdA+uyId4B2GD
BuR94nwrq8TlZKJT2MSrNlfnwl/z58NU0dra/LYsvBc4UZKGwYrTfE2OsTkv5L+c93PPYPYsXfoM
udaqghZsGlBMBR8JPkJp2+isIQIOrQChRuG6vi5j5H1H8x6juM22mz7DRf+VMkAw5RAhaYudo7N9
vYBtHiIdayLaFMXqDokjvHvV30X1G+bJWtprDdtU8G19vIS1DVcXemfkmfg6wtDDSfl79CHZri7e
0kV3ZLbKGDv3wPF3aRZvm+SW+EG6rjPcJVG78IhoCCymJ+22LYXou/e9b2iyutzs+RrqOzwJhPck
ktDiNfemgDkDyoNpuVeF5qn3nznCw65unx4nJvneTDFbjgvx6p53U1KrP4DB8oUwDWb/RDW1qq8k
hup8ZfKsn37WHgsWfIkntEy6G9dVenbOrpX/tmiIsETC1RupYWrQm7V8yZy9/pI4yA1y2C3iNpg5
rkt9IuiwkEKCa610Z3GAE89lAEVbZajehBPNmpEpARcwlyzPNU2/yb4JoE8Zj+pA/MTXa73uBGeh
VXoq7mUIC5zWqXQkntPgudaTLNnwU71LsWM7eBnkNaBLd5zHm7lwcAU5G7NkiwkN/0CA85dRfiER
YPrjGXxlTzhHfiw4tcPLik/ZvjNDNAZqmIY1wKm3fDVuOv/3Hpley8hChULHMXQdYZv66D+hq/1F
IcT4vQAxwW5WoxnhTsbsSsEJuGY3cu0878NlofWbSMfjZPhTar7ZQEZNRPfRdxtWzN/EXc1Id+i1
xkiTU7PJvEAmB7gmhUQAifb+D/h/wHCuYGykZetf010uBLDGS2P/N6GfO97k78i4yl0+YzX5K6h9
Jr/TVBpeCXwqlHZuctZfuS1UuvwQcrjVEpMbzSW0oHNkYHYx7tHuDIPAVGcRUJXDn7f3s0z2SrXA
ekcthUaa4WfsFte9MO3dkCCnqYTM59rmORuFKTRH6rOz7OqfR4HcKS+GPjPyKa4I6JzNJLHVq067
XV6M0M0CEiC2uFCM5UVUMZr/WG1tN5IPnfIlN4+OcsPgj45wJ51nQ7U3byFtIN/MtxlftgRM37Ga
Zd/ksRubXYkRmV5vk7iQY3WI1U3r0dBjje7EUOLN+N2vA65Qw7CJQx/36DgZkAUY9V0Fjf5po3xQ
2snqub5vLoX8vkLZoNMwR16q84BtjEOyWbIb7AGjVwk+NIVHvlBBIFcYXxPO/QEUWQ2pENXOq81t
m5EoUERmDFxAn2k6GeqZqsptwRDD/EO7HH4Q3M0ksiGY2IDK5mDKAhSlHVzH3CM8/1+n9XbKjpdp
06Mt46KxvaGlxZ2GkXa8qseNiTYJECsxdICmF5/RXWzLqlGi5amuh2fexschYfqdRAadbzn+vIpL
h7SweAys9EGrCu9guJ/T9RmPzp1h38tDdqhT8ftGfMrLqV23+EOCGFHIpXuBHl4rWeofOXAm8KxC
mNNsCAznbDosr6TQuzPfffKqc1hZqOszcswpIFU7VUtJG0xfIIr/aCosrQz1kQxqCnSSQJs6jzK5
QlDdoO0vitXelslCS/MtMaV91c6DiB3o8biQsUB4Vc8G/9B4Ka93n6qm1EnuSE0/cA3NQ922VVWz
/2Phna02ZgHI7HV0JUV1A1vG6DZTMVvHv+f/wQQJoaRQO+IhySlWjjtmgA8LPZY+/ASuVPs6jD72
U8ma6qBiIuFEds0aywZiFYyURrObWCwSZ/u+g79pfT8eZ67sXkVU4VC+lMkbhIwuPuP8nRImx+0w
Nbzd877FgcnEv/kOqR3/Bmwi1loj+rqkSA17Sp1tByVOYmdqmI7y1GR6fpgACh20Jx32ciEgKtd+
M75GwDYTYdwPZ/YAo+nnWYdClxX4YtbmXZ3Ij7b7q98IfSVdXymgeebLCOOcv9nRvIRDtW/ecUWW
Y9+mxnKXg8y7fff8yWqWIGBp0N0FhCkIOm2hD+nssFeQSsA1a6efMateJPZHVTQdm/TgrE5q40FX
RLXS3wVG63pQjLMBO+1kUlLve3dwRHFjVZbzOZ5dPrhWqzQjnsKTrxpWBgdaBRZcSn5QkUqbUKQf
TqXxLHIFSEWzbWYNqBfO+NyxfA4rWjRa6ExqxUicudNzBK9yZ0bU/BE4u6B0gHGChe6iNL+5hXU3
MqNtDHKB1Vys23MXV2h5q9+i6hKmnno7H9epP3/ii6KYdCg7erMWX3CBV4+g+B6j7YwB0HHghL5o
FgxW1q5X+Hudx3ChFHReTCBuAkSPZs/2boRb/EHE9+Bj2omnAu4dTP3hiqNrjpNw8q3Myrf7FCkf
AElz3jBPH+YM0X0kr+wHpkw0Piw1zyYRqbEEyj+2b8/juUTz4l8f+88Dy+3cLDbrAkTMPCRHbvwb
mbNWl9qiRjqWifwT9V3rJJ+jbMrvDah9tdW3pSqHfhhRnHJSh6Pxl1PMo+Q3LWy54oAK7/UTfX42
Kp1WE/jV1oDnehI0Q/DwzWzOEKQZ8w6J0r6UZrqs1pVU4SU92R5Q0jTe9RR23JL0uOkTYrs3qKNc
4ECBv2rX6thjlOMKL7LHGLxjeyuT8zmYeWYP1ufYGEbrjSqxDsjkmrLHmWo1fOuOaTkjUTokeRlT
/j6mnpVUrCjqAj4gMhkiNZOW+yfnNk4CadayN+xssktyIi7Fuichzdfo9amGBaHnBv5nIvk5lOEl
5a8bWMa4MVrACyqV1MfhKbPtWIvsL8+aKdVfBay6RHzeZBbvy3isDO1fwiznZgSrG29aFxm/eqDW
3+buaNlda3hOho+KIKEzvpnPPSghJGgmmwaT9zdjNK9+Ua0cg4XIN90wn/SRNdf35ILkZ5wa253A
gBbV5rW6Llh8gx861E8LLPOvsYwPzmHlE+sMVULgHFf2sAjJ2UI4c7EuHDMVXkHUnjYaXzc7wMnq
pELKfrkRQ7iMv4pJnIUM3gQUQhS4qTj4Hy05fNu5LUUa9n4mHibvneh56QSlNXr53xVb6P2k/uJS
yOhX1aRaTsRa0r6thnNI/kXOe43vYBCN6qfehaLmNtvKxDhGhjaoxr0BPIVVqPS/IIaX6arJmdkZ
OdNgD4SokaDYnaz9m1e9n+nOGP6hHbW4Cfd/5+wcn6m73hAlQezpuScVjhSFvNNmq0eZ9/r8U4y5
9mx1swOLcgsvJ+rQzVX0upAnzM4jAta8SE9yoJD7xJj4B7HmBPgVBeLPlc7lyVVq+RpdypJR/GXN
HzspjXh5WrsR/uDYu+iXLoR5o4yQS+gLAPIiv0ADgm7rbY2vjrZ4A/gIfTB1Tex0ROp6k/TwohF0
p1bQXVkC0GBkPSJstEDWaD87/fVRU4vSkBBIWLbiZmh1eBdUHrX66Lbk350WMv0KiSzjoloGkt5f
U+OgyWEnrVUy3U95b6k7hxbZre7J/TxmR8LHg5TiuRcTOVEntKn99RjE6diksCDBrbguhfmooFfB
5yaIXQsf2z0j2LXflEpmzm3ozL0cJ8KTfvwgB83tjiwPcseFlSFuvms7UDC1IA9nCCAoCrtF8Ekl
2JWIGmAtpeHuTKAw5N4EVsSBjNsmOmi4eq5uo6nJjlk9K8pmEqqZdL4dv8Hcd1VZLnuTaLzqAI2L
kx0lzz1WY2QxVhSRvmDFiC4UH4QS3RNVjosrnq/q9rmsYXrvkTS7sL249vD4RHz6Ceijh8nHJlQY
65siYmL0j0nVDYIo5CINpNye0Zai3/TCnYnIuDuRVuERa8kS1+f3hwtUb3Tt1TIeYDGu5MQ3FVVT
ylMamHD7Wb7NxBXmtc7RearRRPx0dDqUa+N1fk2i1ylOdearNDYuquz7MIQwShulUOQjfdt8PIlL
zcgumhzm/bExgkfp4SsoTVgExjKZmdXFbcvT1axtXuX7XUrSMGJcDCHcT7roeLy+bJwf4qIhQbHf
IKy35YAxTEFlkLn5X48oNClTcG9AOPOdaa+3O88oV3Oy7Xh3jlB6FLxZzIOk5aMO12D/+WKAEuCD
OG7r2YdqfQUN682d/TTcKGyynEC2dZn4agHNoA8kHSUug8BpYE4nn/cQrSW40pvUccuJ4UYVvlPI
IZqawPk8XdMIC3W+gjx1BOjEATRqOfotkPuJK82W8gIuHvlPkiLWX+oFWwP4tWQkLmwZAnvPwaBq
/SHSLHXlb33sNzDWtrc8uYdhWOF9ZocwMZPIbeWUj7f96oIE6SgNhdr3IIh7FC/vOrnMQgpVqALi
5CPcLjFudfFMDelG7Y6kTAS3Ohm1n/UBzk0YcUlKd+LCd4ZJI3k3MMjZIWuGmpbrRbSVmgyE/2Xv
uotAIRcbIcgbH/FcAvc19/UZ4u7R3kqfSucyGxuHfdVO6XQCmYZFL0vpESXgdgAd1JFoe1o8aNOD
IrKOnWdyYnqVHy3m/5b0SMFzQ5LiV8MDy002yXlSZORgxLTwMpPR/w1+CRVjIRG9w6Fb6jYdbnAY
HZBM3hpSQKsLgnsSQF2Vy67Vadw9ZWn5m1l6Y89gdiTXqiLiMEnO2zRdY9QSfNTdvaDeXLRO1QHK
CQJbbB2iJ9pUleW2IpUcer8VbM5quFItMZqLIIS6a5T8xQ5PKmhDBectGZxctS5AwUGaiZ/zpAJy
rwMzomCVSwo7B7lIGo1ESpbgikFBBPNe1RgYlotj078jhS46uq35be4t4jFJYrQ2OnY+ovilsqo/
HuwnHbkM2mFM7XUCH/pdHUIzk5QFnnPwkNFk0DTQe3hpcVckonQciUgYKw+OoiTme2PmGxh6ewBb
xfKjoy4A+kI9yIWFfVAfd6O/Ygvv5XlNoUUYA4mPcRMm4ERn5lTDdMMlBT19zMTPSl8XXHwIsaM5
GqePWeohXX7o1PjxaK+6I26KO5P7rOQOlxMiXJCrEGu/RpT1ztywwbGoFFCxC2TbY3zJRXgV71Q8
KMGsQuuVYv2q2Ee8kqQ8LDLCJkWkdSBZuhO/+n2WQPo0MNZMmm7wZ80bLEtvQQpX6434as9CxhA6
YR0/0/jRMVIOAckn3KgbYmWkPM6++Wu91iqdMjtIKlAiU6qEtPJn0LjJdsQ8hMjaXODge5Qvv8ZA
nxrNG2In8vHcWgVV1L3gZQBJrVBWGImnCx55VmrKP+w6i1hRkkpKwUq60qXjrQSSg8dMj6ZxZLGc
2cd7m7VYYF1lYKG/2cT3QTOeNhKuM25xY12TowCXthHiJuqnHyqV+4C6h7AyvA+AYSIGYD72hxD8
QgwXrXjuWdm6st8zVLmvX9qHw/oH43DSWGfCKgcqaA0TtyxOkS+ZJ7hr10uxG++vipmzNrZ9G+OF
6ljHTE0BCbMlVsHPn/cKFQYP6zpaHZKJ58aP71yL8zVpcUzAmyXID5rGrvvfAZSoVEGnrhhnV8xf
9DUYapbwbdEQP3XZN1jKIt8v0AKvz+lO8YcHXcJUGC1veYmlxt8FDTr+dWMvkubootI+8zdT69GL
DDqaB7V9Yyxz/hOKgwPu3Hl9IzL1jePOm+Dm198BOoz9j2/ZWEfgrgDI1bErzVWMojY6FC8kT/UF
MykG1nBVPja7fCn610PtPrD48VIjgKJwpBc15djRirEqoG9JC/btSTdmFfUz7rOvOv+N4nT12ldE
v1u0vI/tUGoA76sYZYCU0fgAFDFIh9SzMIws/67UOLUv/3BKy1PmGkQsjEjdh4KWrdnTe/xVT4xT
2RZ5N7PH7/sc1riQVtQ+A3DrXUwcsWaOogScl4JTvpG8+nTiKQXde6LdtdhrtjmHfVVah5lNYZ8T
mUad5U+b78qYs7+VwEZATfY4rkZU7l/izAeB234Cq+BzF+0JFSwfQQr812ijyh6jDXfb50wj6WPP
E8nVDUwnQl1VEu+xsLu8o+pWHXPcDc6rvgBuAqR+KR/GGRHTxsR9OcAI12btoRR7UlNDuCPxcI5n
roCOnADNnDFdb2yglcZDAbe1zBtV2XMq7sfVuDC9Q29ZuH8Vu1+agQgLQlkI2qSpDYRzt1/TS5cJ
AyqFwqZNlgzMXvpzYtx7+s6BRtTQ8COjM6CVF7D5EYTJZKqFJPeNdUCgEptHIJB0PJOhpuZArtdZ
STEwDPUx76CMKSD0DSbZejcArp3fRU0q85h6nkrPBlyiSE6/hzPl9HSgiTa8EsP/jNqnFXCmfFVb
Oi+wXyi+U2XeXMFUytukeqtXvFNO3z0B5ICPOJj5cUJlHekUiG75/DsjKEKSrmPouHAHa0Kwei90
vqjSfUZv5A96Me18GaFbxweZyKKBcgNC4Djr0mbqfDRhfcg2tBnyLqM/SeYVWDVbrWrlcPKmU5gF
CrH3m+MZ8+SWJkH7Xr8tZgnwsKeudOO9wWae8jpEqGpSxhdbXZXlpKuygfyHdh2/a7fA1VN60/lk
sHK9hlN5ceBo7BcWYg9oMNIbWgdOFIAvclSEaQ8UVFOjFtXDRH6QIGgAXwFBPSjdU5h3boAQ0kcP
CDqHp+JHiiMwZz246bTjejMMY3i/G4IwCwmcxp0EJw30XHGK+7k2OlNUoZGNxp/qNxtKWKaQJSsk
xlsle9wEHoduKVLINz7VlFWJ0dEgmukSJdhJZR4JF7cMH8+1et5DrRk1w7iHOI7/DSzKIdGuF2tp
Tz2SNYStQbUVK49hXcXwcfjgapqbktvUESGqtd3qKigF5B6vQsNs3gbpqRmV3P14nSWUQaqi3nIv
JBxDlPAfWRGF7JWvuOOKGrmqyYjwwbwmdRMC7Apq9ziL6rEdy3CCZ0yaFfLprK7Hy31iCHecVgco
rFPOlHy16MOGsS6B/MEMHRMeT5flNlpLz8gVsd+peELI61h6DFyzO8n083o6ht2rHd3fqUSFpv0j
EnZbY5jnHf5ebiwEBpQ69RgcaFeKJc//RzaD/bfUrjb/xbQrfklCj7Lby6k1GNNsAmb+7xaoEZSI
4JitkNjcFIDCi9UbIwGipFVRhca5T6h2V4+qNoa5UHcchU7bvE5LSpw4F/hYjrjSKDC3I8btDlOU
N0iEz1oT78++UXVmICY62T+NdC4/uMBW1eisxsFB9gTlOTflg8O5N+nYAr7L0MEFbVHYTqPDSma2
4K3guQjcHslczas87pWSRjcK3qjnmA11Kb2rhAMSjjehY83tRGpEzGO9qFDgcciDHrfqwNCO0wsg
/zd94sChsaAg8JegF31WwHQ9roYmJMRialX8unf5Zc2di1A0AEl3IditXhWWbj7GGX+Og5EDxd+z
+rbQrAPMg4DvPzrnlDUdXyBSFJKwYhdATGJqEwyKuXz43nlbw7VeNdbelqW9CcdPCWsBniWDDfj1
aiPN5NCJqdqKqa+UB4wVKC2wVn2PVJKB82oZMjbDsXs5sRa5s1Su5PT/Clex8o3ZRiVpkD7JHiFZ
xKSQoCTiRzm0+e0qas4zMciZR/dKew0045LS4p4P/qv1T2tI+0B0K8mKI8XaiCiWKoVT8oNgg/AP
69F7hV5syAzVVnTeMSK5Fd6lULghtHd7lpdujHBFGxK0MFK+jEDmuEEqVU20jJGPJ7qs0/JOEWYM
qmLib6zGHwvTJIGkUVx2JfM3cMPovTYlJ4p2fzbF4YyKmC0Rhuf0f1otlgNPZ3S/sa2AQuU37WcG
1oljv3gd5SZLKyVSpQTxwL5Fj8UrAQ9VozDe3giwJsWf1OW3C6cu+SYM7GI6bnEHQmi+tGOKtMbU
ydxeNiPlJSmCFPVuae0vMMDWpKkl37Hmb8ykaybBAzG2dhVzkAlOgoD+/USTzFUqq7MTA4dtiaOI
6G00zAjYXwN1kgcEaCC7qkP+5nxCIOFYBPyEPu1I7GvkQrcbDqb5SuEWZCkhZ2f8et8vDs/sVP0E
wQxxRUuxcH1IlNGWrkBE6WkjZEKxAVyt4MfRNYPwbgYODZhE1OtIbtrhEMZ8AMe636AFOd5aCbRn
ma7o3neFdxCZ+m0YZqZMasoiRJ4ycbh3pTJZ9OKYzpETN5xHd0oawFb0goc7sN+WiQr+VKTfjiLC
dvymspF5vuQDl4l8mDnRKokNBlVwFIOMzv3u/4a8zAOxFOiAEjP6gFr+otRP06L0kL9ryPlSF/Ab
ZTN8IbQNFhftbLgYR146YLnzmUXinXyJ87ZRWYdRPjtLJAkX/NtTUbzyGV0fXqJBSHYCWEXJB0pe
ZuhKIWe51GfPHX3ZTs7sbkUlywUcVlu4bNNtlyOmSpV6TH0XQMvI22BQ3m0mZFom7clAsKY3MD9Z
iac3knmpl93T6jvZnSECrthAk5bw4AWiRS/oKy/hygH8MqULc8LO4DfXJPgRrq6IbkR4ZBlbAiET
OJYhjVsqRtM7QOCXD3MFAlDciijue0q2kkt4RxBKxfW3iPEnX5osRIM+2K8XWZUKrJlxg8fabxoB
jCYxISh9AW7f/CxPWnjcyMiMNE8dz6TpOx2vfV5tRUeTFQ65wPeFqMzNIpRHJB24XAw2XjsZS+7k
serY+fgVaAJPuBRI9Y+7Xcl/1nmMk6C61nP3UMKeBNAvcL3GDOOu+LKwZa+sFoq0QMxPMdo4M4d2
TljXCHXkpzxLF7SCfxgcQWmeBNa8rgkkN8gvyNwHeAT+m2LykggTR6VDLPtQh8IUv06Xw0XF9F47
rbTLNXpLpg3oPwP2ASH1hFO2GYc/uexhjvOXEJvq+nijMRfoVsJUXOURwXEd9zKRbFvAUtrhamxm
2x20aA38HnNlslUvPvzX+x5XFoDjc2PKJP+srcuKwI/5Xh17L+6xYfHtqsH7WOkxzheVL7oOrC2c
TSNWw7d3SildiSsUm1yARsnrabgsWtryerQ2cLBpTzQ/rU2PJr7+1lBSYgK99CWiTWnvQGBRu8xk
ViljLigMOqTRz7M3CSMFPXKNOyGP5Vzzmhd+QHwqKyta6y270oOnreX3qZAsLYGz6KHh79SyYNqU
uY89EO5/PnCra046ADhMT9LzVOd55nM/+anhsvBKK2l+qZlhJ6OhccMtN+7tvRB++PBvxsLkCSds
5byNFf/xAV7pJV95NByIxs2GWVekfErD7nBZGQDaB5tV7e11JsKOJq0KelLdSLRXqAXMHWk2vm3U
50ARyDrQQEEpyQKq//qCoe217vpEyzbBjcQBL6cBT4b3tVa8Qdl7IbnEXNJoA6bIkn166VZlhaF6
K3H6K0WNFcPIixD3oga0fXFXEOfDRmCnx/xyfcEjO3VCesTA+z2imIMOGNJ09jPcioG/uaTU6TX2
L3cg6jIlR1PtLLsgP/AWa+WDSBdlKHcyNalfAucWbe0y0feVqZKW4uegCrzm7dRVNyWiPOE4ZIZa
5PbEhUx4O5X2Ic/bW1PfUUlDlQmr4btc9v1yTmilM3SFyIIxdKXmJezpRksKvuMcBT2xHPCXE/+Y
VxJj6MB3TBAFQVbWnoo8wNvZo8ao66RYQdvTwr5QuueI2oMvx+Wab91bfzoAkLN0dAn/ML2ia2/6
RJBcW9ItBm1h/nnKRMb7xqSeTecKsd66V2EPNvxswz+3x9rGDuqVU1haBv3ody4aro4dpbXWK66w
q1ahKKremfeUTEF0+3OIylHLCmmPCPbyqaMm9MMQj/jSzMxTtxtrLsLm9JgFZ7HbtLa8VMv1PYPu
S54Ze2gf7U+7l/16h+cCQokFL7Yko9vx5Cps2BoKMdnx05oG1rYRsXPz9L6L7gtnyHoFvYPoduh0
jYylFernlGwu4a3wF1Wn5KvpMZDAZXG2srw0F4IqbBgOp//94pHdw5eOkXIM14/bLCEXUJYDFuyK
4p1PHYFWBAPjSjjwvgiREUAd/PTidSkZ+rz0AD4pWfXzfaVeGkcIneSOeSZXtGC5y/sAMhDCleNd
cMZYtlsO1PQ5aOGNy9/4ufJ5k940n6ARQGK8sAITO2qYPHJSa7Ff6gAa6RKTiHFvMGbChd2Lc2LQ
5wEzyArbxVAZhIuHgoOIcKkM/LmLDIV3ff5XfWdGsT+4/dmiSaJH+2+W1H9gyu40JDSLZJ20FeAR
yTMWOPyXUN4DkKRGTBesMVAp9JHAifOzHlJ4ceU/NLN0TYhcnOgmCcw/Ibm8+IuIGACQjOGqJEeY
4fErwQ6v7HzM7CT3g/LWNjDc+m989kFH7m8StRqysO2WS6bf16hJDirOr29wni7T+HE/19mSvrM1
iEeRgpz4AnmIlWvy65rINl6Df2xIEdz3ytStdizRtoHEAwH976O73sNmccuYfTewq4mdBztvLGfb
EydjrgqCob1NcoLPurOWFE3fmwZrr30RLqWHcMc7hzkIJP2BCt/LgpofMZUOAnBpymQaZFwAKf4L
hYAsYpYQ/IeSrtGsSXJJss23yGJuzaYJpV/6idtxjcvmeGFl7sZTqwUJ0HQmsskM1UNqSe7owXjg
M5nKz87ZwiAmSjagQ90/nLrZuGm7SrCWxIdLQnQqPGKbTSlrFTFQbKNG2fIEjH1IHOXOY0LQHAo0
bS5CmX0LE/WdPvlTFVw+a0r73k7ah6YvbkhcwWXvwiVI16wpXsVGskD4yG/+DRSOUq+Z78m4PKiv
+guZsr2I9TkBZcabxkSlEtGG+KxaTyXI/LXB3mWo4TLv2FJWxPtJqFok1RxxeofBqyffEmWV3GlE
kj4QwtTmZQAPqq/quK2mPvyPs9Et3uveQgxleMpoNnlEj4+Cx//63+RSx43uP8P2ZuNvMqzKpnNj
5bhTGy4dq+RXBRKKsBxiaqigFSs3Ef+e908V0QnpdMwqZ7Evx+E97m3BXK76rmpalDqsiLlZ4XWF
eK3ULpCnfWENJ12LYifmRAx0XjPjFwFKlhmrWsxLhmH87P3AnbXs5hOqfCN8XhZGsTxxiCPQJuyd
N9wURz7gQhg9GnN3rGhuU/Pc1EC9J1t9i35nwmNkF+Bxs3/YJPUPKPzg8boGsvmpVQaFQKjo6wtM
xrkAziJM1gT3yB1VLc7QA1q+vN7OMSRndGDr5s7UQcasZwvHO+NzCNd8XYV4nuCesDXz6t8WC6zm
pSU1Ia84HRFu7wfOmkr6SQlXCHQVWE8mhgp5jBnwFXPr7B+905hxHAGuGhW0UtK7iItR98HXifUQ
+4o0jFgt3SFmhxSpVFWXZdGyyYMJkOtDlqjadfHZcmVqaKTgWM4BEnNPoai8yQ2egsgF2K1Dem2S
kn1MbpNzHbMubeNO2V/tTiq5jQgz2coLst829sBZOLQ1m67tJ8Wlxgz2ChLp8wunKiiHsn/UwZKh
KBhNKc/6Y20TBKAywhXEcxbNsIgTZN6+frb2iUjffWTlhOt7VZkRU6Sa3HOr+r5qXmdQv/dTYiIr
Ebq3sxnmW3/PXgC5IzHagY9nTtLs+6/no6LqSd6dxK2tKZYq8WbVoUic463NCyhMsFDDm/V3sSty
Du0YtcpOzrgC1swPgDWFtLVPrE0ObNdE4kFcvdN/4hJTggj2nBeMNfjjUG5Tuue3g7ikehbZ73Yo
2iqPCKY/iKf7Y4M66qK/ca/KJwn7YbLpwNysQ0bbQeON6CNI9XdPdZuO53CukF5DgCmzp2iBbxyV
e42UmeAMHO0ZcEGLQrsDrfrX4Fj5lEHbj+Qclv9+jlp26miJiGNIxpdZLQHCqqdt7sHc63MJsOAM
1h1L+LFRsWpGzczxfAuV7L0CyqmneMU71Clxz1xWyokEx9FyannMOJnuEJspXUvu901182hL02pi
lyfnz9tCxKAAGf9W74mcOq3LnZ/APv9AE+1Ay6A/2Yh3Dm+zKYJySM+Y8AwrvwKhSD5On37X3lfI
8cNcNXipr3m6p2KBR0Cv7vBadZR4jUnwb+T9z0cYq1/I6srdKuerbsbbX5VNd83B+bQQv+6ci43M
GhyT9vQ7snTWshU0xbWmffmh9uCdPrhckS8jkElrvz7a3YMUWW2bVLM+2SP0kTEtEqFaHC4fz4oP
X39GGX3MebBjgM98XeLFldh1H2QiTYQHzyU2wd2L3AU/+KXEDRJrygOHIHZSC3hNrEG5lwjsUNNd
BBAzR6PSbws6/a5bfbNBF56LediqHkc9uxa4wgn1DJuVfzLKxYKa8d4R6xzZmw+Ao/IS4u1teGQk
n64m9SK0EY9f3Q0xoyBCpcqUC1Ny0K8c+iIiMekc5vIxcL4HLF3FXJI7IH26Bsaph1/NsPgp/iLl
lobSLIv2T2eQ0pEimKLmMbH0uvimoE77h8Mesn9Yys9OfanAfpYXCqX8TETdE8Ww5U7Gg/3BxsbL
3WX5+XHy1VimWxRpKhWuZJs1wLszfBHqrsaV4/m6h0OTvimPgx6lqhBBksMNFfde1OHVAQZ2AvcT
OoMUrwfs7cU9W//PtLth6Xe/sDCCgsV2/Vg9LTVWPTZz3qdruQKmWoljsCe0G+ek6NgmWkCZSDed
A8MSpdt9j2j2sD6DxjJuy2tknJgK07YMiQXvkBVKunNohs/Nugo8hRDcQWk93krGs8Z50XqICElw
iRGE+0MNsxOYWgfMJHbkq1yfQCvwFyX5lyLqGLsJtSeGC+52kEoew7sjRI6x0QGImhGO9FpVAsdx
yxJ6R3Gf0h2W/YJrLW/Pr1VAwQlfdmq3CX+xMV7wB/k/uItNxHmWqJjRjxxLt9Z9SeIMuHhOpVPy
qMY3/qVnbXFLq4SlRis2DzKAwgS/tLjEncv7quisyLJ7+qR+KFCI735hBHv0PfdbcFGz4YP/LJec
o3BHMtJwaNCew+oJKhX7ZrEwfR3Z7E8fwyWeSdoOGOcuwikVEVmXQDnUjMgTr6eO25qrdhMeGpFX
WkUH2ozKIqBBUVUHrnu9fFK+aTBPiR4uZUZhp26Ty3ahyqErqPmCMoXdt5AAuRHPGrirOKK5Pu1S
Gr0kD8gA5nc080xHKRW3J5KtuIAwmGMP3pq8qO88S0RJyu86mrOgwmD0rfQsD1DR/5LnsVkC2uHZ
Li1sktwYdNBgNUrDlFg2NhTcdUMg+cvtsI8IlX+U7IeSXLIEZSWAE53IiFsbZ27zeiM98tD5V6BR
eiJimv4Aho3Nq3iekqJHkZFDoWEKEaVvVr798eaN8Q50Spy1aRpRaGrywbVG1ZltIzOIW2tJcmls
emxyGsLojn78LPTQ5sAcc8cufiLHq675ZPTWg+DOOL9RL3htUz4IzxAUMfOGIPv3fTOFT1r05aQv
hf0N0mQh2sqndwCmFnLdGi2h7gBijhhTzQe78wheHw7LsMEtnpT7RzPYzfBNphfMrwcKhH3AcYAW
6i4rUxAa1tRB/faZSBKe2VkGNW4DfcczP+NRyVxzyAG1FAVi0U+xcG5Ln78LNSlbJdP8U1q2A9LE
rtWdRfYgwAOANgQ4Z8KZI+f/52baQs2wFzh2vOFvWWZfnuZ1BK1n3Xde6BGt3luru/GVI/f8lqdD
HAX4HRpbwXIFg2Dk56C+dbwX5B5RJUqUP/IZWW6QEEOWsu+yEh12aluRZ4XUNARqzTiNeVJRysRh
57ia0ANbmL54hUOTqtdxdLDzRU81p4Vg3YRHzXR7GeK3FHm0IplVoPuwZdX6oogg4sJZW1/0PREj
xxAkHVKuqGP6auLMIalh1bOp2yBlT6xSpI75Jcqo9D5mBQQJo/fzNRpi8/FCWvwsYJin1WmXle07
SECnKHN71WLe0CoXEeessqygsHv8QfHi7uRtUgiozUH4y0WVA0JqbLY05mhSFLCyoE0p1DWyjIb9
t/se2FpOLhVHewgEvpfPqcOvhvWmLpRQgMMN4NmlNY7bjdgY+bhieB+QtO9Quh47m4XrpJTZ8lRL
gPPPAOX+jlL0HJ3p57qBeKP1HSaw94sNxJY8pzxG78N4guXPd1bJmHetqU1A22oEXh+Ox/ln5xjP
bIbNypx6oVbJPjlnT2QV96hvEu17LikU3RNBVIuYBtWeLoizHB6UH18s9h/C3dsTaS/lE5oUU503
0EX/EoRjxVMSajKNdE+O3gkOVC0nWWcF19qu00b5/NUo7QVxLlpiZVEsI6/GpQLn3z93Z3oX51Sx
rqVYZlLdk35Q/XjfwfQpnVruuVjRLbPeq7wb8HNP5detkOtOcF/+hgSUu1H8nnCVwxf0AygoFErJ
u7exwz2eBLY+dpuK+F0uEVStlJY7Z7rMfuoCuOZtIG+4a4QZxckq/xXgqRUfFRWq5GR9a9GxdC7x
WiAi2GqXw3iqS+XCOYhrLoDdfomH/ZVZc9uu7uIbrwbGMaPKGLCU8zJau3yw9zgNA85plJO8W3ev
rxWljg/OQ1wlSoUjiyUL4GReIRK+el/kpgkuffbt7g+rGp8q/7vgoPEIEPvLIQFQoURmBZDLcHpp
TT3yoZgzioKzuYXA9z3KseUFOw2kwYOlW8KctX1T2tzsEtFMgKylsjlynVn/fIuDJeZYbsVeG62l
b2jopeHxvUWLBtg2ex6uWjegBdyucY5slSfUzwAjH6+y+cvHv511VTS/VxdDrrc7hEm+rXpkQUfS
j9HY0IgMhJsstnvIdac2PaIL8JD3hFg/nVk4TqdLFVMqCUDSdKB/aRHGTtJGKVSSeAlCidBmqT79
VdQxVurLhdENgiAP9uieCcS9rw2fA05qhuzpxnd2je05sR7Bq7bEKJqOz3w9YeAVR1v2+/88WfZd
qWcDnejrJ1oNig4xiMH4Svm0Y7hvmdPXXTmuwT8OwCJlvMM9okjNQcr9ISDerlHYvbpzJvg1S1Zr
1kaF7A2seDCxy9RsjDr/vbGo8i4R6b7Tud6RwpD4lScmdpij0RQnih237u8gd2snAMF4SZJ6Thac
Ug8Ijvt9vsbLMfy/fDVUdBqhg0ZiQKES6A4if98JLfb4Yv33sCE9nxzt/SeclJUJ3/7756LcCpiz
ONvMJJSvrgB0HadytSgGaFDGcBsxk4jKbGxrlYEtj/GM+hooyVz7n/3sV3bd93OS4tfpJyk5vgd+
fs9BARP3XxbHodOEHpURwShlwUv/zMy5S9eVeyLmZLSmH27ODJkAY/T7J1/nKe3tWsil3LgGyl07
IDZh1u2Hl/l0KX0E5RluoIxc8p2teR89Z2SiRMeCsP2eX9oaaqUCTChr6EjVaaEMz6w3l3L7kcGu
+Y5w4fNxNlhRq+L5as/w3VwRuErzTWMmgzcBpTYbg7QCrUp3ICheH2cirj77ErOEtw3uJWfb0lS/
+cyMTqzDvFNIeKCAR4KR3ElJ/56KUiST5EJmgcQxVZlNRPEYrXuEAQ2qwJcgi0fbLnYMwbMoJaTu
rolp6PRrG8jneaMk6axcRd2LnkTnB3lgE+8bmLikrAWu+itBgLjJFR3W/a5ZSPAaa9Vne41XDUWG
HT4iH9szh8rCSi5a4kkxxWCdPNcXjsipW94GxQbYqw8w6/544w4NCArL/cc7QmCJJnDaZ7L42Zp/
3qDw3jZWJbB33oC99JUmZKib69V8xyinWYOlbR8qpxAAtUOkEqOam1wNdr+hmfih5TTkFWz0NTrs
/n7oR6W6wU7I/hMI17pR1cWv2mUCfThARoV2laZhZVrD2FUlXjcn4QKFJACGJ70zwCiebdN/QX7k
xh77pH2H0J7wLP8KZoYdRnEY8DwBpbUjcANfpPRXPZ9yuWXq4iAu+8BnIKmdHAM4y41oqf0WOygE
gfsQdQ0U9HghsEHDoYs68rLh1+YxZ4sVd3nvqX2pRG5YRBs7PlreX2kAH6rIFp2bxsYQO4Blj8x3
uJngaq7Uo57UPiVb2KUXg2ACr3T14iDRVhwKbyJ+WIggtMa0Ppd4ZZyDbN7k2qoR+W+Acn4ndCIo
tg7fAuZttb3NXPBS5Kg/zITIJm1nj7ZKEhC7P3IT+a/W1zZypeV3TNdb4gGJC2o6LHzXdLKcoa8W
mntS4R3AIdoRzLnnychdoucMYuZ6DHlW8eNKrZeFa+4aAjczSBBE4BExWf109nqoIMAB+xP3dMyA
2cztZ5pISkED6xGtiZRKmvSxJ/EJVi1iWZnmuf77W7Mz7m5DhHgpkKoV6IRvtj2/l74dSmRiqBxK
yxq7+jfZcA2rkb08Lmlj+z3Vh4A0FZ4A27ZtwNxE2lytgcRZFJ+9Nh+z6cn7fr8EH7RD1v5aWd2i
4OPajix27VEqcNO1/g7gko1Rwq/PIWkqr5hd5HdgrWjN0UpmqBIY4ijZXxDnB1Jwa9V1rw56Xv1U
IWproMCnjh2dl1afMZ9yUX2aN6WkBJELNiYawfFwFXsB3g6ZqhHNn6rpw4pfVFsRUmZtwdfmEGeq
REnXQBJNLbJ6TzghxohUiPyjgqrDO2P+7zPDnRJzdyBYXsQ/RETU/Q8wPXLmJxDQTZ356UvkL/Ah
PgHaYYKKFpb4fZdNx96K68PNeU3M5mK6MuI9mk2Tliha4JiJKoekbe+h7vXTHGWwL4siHus2FZkE
NoE66QZ0AxtEqJ2/tJ0bsrsvH9By86h/6HETn6j0B/eFA6v/NNWYTaXdYzMgGpMsqhpn9zugyI6l
84PkGdH7okfeMI73JxzgNhEvh/ur97sZ9nkwlnAh9d/efd1J2UM770tZS8hvwAJh8dcuxn5IPc0n
jFDOKom7UuVCWsjML+/5MEb3SXhYiZ7g7CViyyQ22oapOHeA6AeO9C5yM3w0h7gvj+RavZXtUMU2
/PZ1FoJjC46GI3YHhyRsUd5ZEo/Qvh1FcPd18VtjPE1akwPeGQXtn9VaRzfS7foy/Ke+4vbIsOBi
3D2ZOcP9wmmmSIq92Rbe8SxP7WolAt/yMddm5BZ0KiKP2sUGG0rg0INXNnryL7Qh99m6jpmtWHh8
+83G1wA3Uobsg78ZkJkLkJ3Qt5FO5JELFuqchPijb/ENq8ThTwvLIbvxiCn0y5/JIj8qV6SnN6NP
Yocf1+WbxTveSu02qo/ae1Q10J4Zil3zNLloYMZT+R18+AGY/Y1jvaJvg4sqgVOi+QAZh9/f8xwo
VYpURepcbD+alnF6lojAVh8G8oKS4MOYa3YiU46yexf7lLYr/bXiZu9jNIL/9Su8tAKRfkN96lcP
8ahc+L066XOpEdcn5W0AD8UIInNSBoYtjSqEZdMf+2MIDJoZybU0YQZoxMwAO2i/v7z26seELiot
Tafu9NRBERoD6F1PhT2Ls0AIXfPCW8fXfVTq7rGiDa8fsBo+1kYyJyfyEhocfeuuWgmbwXO8jZc8
65GhBO1MJGCb3+1L0YvirzynvtBm/8n56+XLVr1/A28iTP6rO5tPE30K65+BA80Jtl2GAGx2kGFQ
mJr2I8CYymd6qr7UGNlffgT3unuUZPbIt8IftdeB1A9CzulTvuj23w2ZsJEB14Ieydzd0IbzNZjM
fhpQEyCylvjl9ODoieEpszOth7a1WcsPo8ku7rTQLz+wg2VA9Ki2D4rfPsd8BkKn9pVimvUiRqKA
pCUb0TjbhAX3ffxIDZycEIELqHcCWg07h1ADiDOzqmgFOKqwj477O9pXKyLnj+cn3YW++TsmU4yA
emxnnFF8CNpyzN7S3fyLIp8lP200Nw6nLOoDglSaYryTb0W801o66W8AbpGeCKoaPy7JNh24JCU+
ybj7eNlemWcdcNwoyQWP3hrNL1ti6UMc+GpUEjw75buQ6dHBoT0oJWGRyYtekmr5r3W2LD/cq9rb
4hFlNlY2etU7+3cOEx25y+KVkUHMNfJqSmgrZtZkKsdPaFyexSrPVbK2s7NGnXBQ024UYtz0UROM
r4sw1U2SgPCRwK0slKjah9FvkbvLxQ/rUcC+JSNczC0wQ1Y+FmiwphcdvQ09aWqVa1HQfXBYtN9O
g8/L8DDlC3PVtR7TANuuQUhtVdJ8gdDyRtTuH+ovf+G7a9qz8rU1ROh4AED6oQU/TD1juHJR+KIQ
iIH6SE52BOC5kRDuXFJ2JszMjZPQ+/Q1nQA8ngqMOO5r0mfbbbDnD7Ka48PIUHXwL3n42XNn1wOH
bTCEzSn95QuR4FYoqHyfm5KsuUSRNSn3R4csG5PQtM6914pDH41vr/gl3ENyeRCh98bcgjL49CaC
LqfYndgXfQuY6ROwXboVQURL95LDmmGioK8thNyqSAodcxCpCRdI7V6SZqMtbGmNnjKx/fYBcxlg
sFtNOcW3IkVtPJuAICE7P4WyHkfAADkQ/8AWr6WUY3zFbyUeYvA0EV7hcyOSdqxOS8OpjVgP+PHF
YzKDUB7toeA5Jo0fBgJ5jJJOaxrMSTq80CUuQYYZDLI47HLB5DeKgILFRQkrNq3sdulE04ZKaGHn
p6ULFl7vndFwRnyJuV7KoDT6CfM29EKVP9/FJp6dZR8oXNkjfYZFUPDd6Nt+a5iU03zlxnTYS1Ql
lSqTdUjEa8daYGxufpZaiJupBvYC7h66jemwqz37QB5GhjzT6Honrzgu9bu1IPzICwsrkAKGelKO
2+7A6VLwoIU0HYMbsRNHETMIIx5djcTIpyWjofluaTfn0Cfs1WC5ZFJcOsCMppgbVrVoovrXiXDn
EDLt9zEs+rqI9un13lUWa2SnobRENfj2g5kFBw8IC7hk93U89j31Wb7IEDqVGgNhYYm2jsTKR41P
qWR5pWyAbIpwEf0M92AnA6XnYvYsBK9fYniR8dVuIvnvldHR0MSZ8M5Qt1kfYIpSv8mdUtgHOoet
07pOsSgieaU/nsdxtPSxgF/PLbwoQdzrczNM0BC/HFqZSxwOIGsaIN4soq+P1H3UBDggRpgcAMCC
j35wPuEIRGTRpA8U0nPa2KBCCrWWHh9Tft7XVbyJZj/6A9IMRzwP1jelPgOYbVFnroZxi7ZMziPW
aPaJnhc2CLGQt36kiZEAl6FBI62bRYYEgTltA+jVTrgNHFu25OHxUir2rXrY6fa5t89N/u19cN7m
8tIHqefoJ4T9gQJiYj8lu60fqhZDTKkpOGGQbFzrU0tX0YaDvNbhVN968F5cUllegRz52eeS31bP
FxEE6y6MJJQupct5Cr5Im5QMq/78QayZoM59BIe3ihW+dRRU6t3l7/syTg04t3bFV1mRE9fpXE/0
SsBVZtOzpRSLvIaOkQORkONc9dNT6EjboHnq9CxxWUGzDZ812p74gkp/ZncCu9zvcVRgWTAuF4ky
aaEhPGxlVsiCxoM6ExdQ3N7gNaics84IiYKoAPSE6vPemKIjA6NLBhLASqDy6gaiCXxiQ4EsqibW
XNWIimYPMfX5eNRxVJ+1MUB3qVUiQRkFu20ME4/Hq8fAiIiFa1GxbRMUn+s6PA8+kz6pIfPKQggo
3wr/oIyK3zFFvWmScrL0ZgFutpDTWNk0An57nqgu7gm+OjiZpmYjMCqPmi14bgi1I2pEtfyckCh7
hYx5S4O64z2GPi5vrBAdrhujf7xtyKgTcO9LfCbnPAR11Ymz5c24zBlXxZ92ZMQJpN3XQnW3IyO0
FdiyAorOiE66Ng7bR4CUoSm/D0N7tcmvcN/aVptE3g7csgzS7nMUwarRUnIE04ft8LKWNINkvVWB
2iB9em7uEceVeLMPSFkor9WxlsyZ29dD5mePJpkDdxeOcomTrAqXPazpFj5ejyxZ/bCpV1ByX6X2
EDbYqsZi7Y6H2JysEN5q6EaiDVyry7rK7U30H/FZ6ex8G9fHJNLjYs/TEoE2j7+uEYmpG6YPpS/T
ApwM1Mui2hzKQeasJoamSw2SIF9DaEXsOlnOwcdcQAHmhbGZlYYl8sI8P0EqSFVYjjhh1vtaKDhZ
PzBGSVNQroyAK9YLA5V0f4QczygUI/XlZleqAjEMZIcz2STHK7HjYhFqs6mVr0Uw0NO4ORMVE4Tl
Yn25/97wMMIIzgz7i2vzh7EyZIBb3wgwNRpsX21WakXD45XKNKccl+UWPXffHAsBQMgtboC04eSZ
fioHH6RTZ2ITSmxxXhFqj1Aon4iunrVHdARtDyLu59YWglpMtD81Btdi8KgwWhE3+ETgNAFWOTRc
hUV8/dZv9o7UI56FJIYVo7HSgoYRJAdd/UpQNz7D8Rk9nQXSG9nIlyZ6hho15sXOCGudN9/TpgN0
Y+N8QNB1H1R+H6m6sjkGDj7TOnZeaiv/DOqPwE/lzWIyk5BeDWXolFF8e7HF3BIgAC7pemZr9I96
sUYpYFv27KtvG1YKhXFLusunZdAxTCA09jt1I7WQ92SaVcA/ORrXBKNr6i4z57G15iEiqnnIzxrX
F7fW5F6wKZjcVNdnhroHtzPmnMNSBaqnkv5CZBdnnzyReysPoRxpB79AOfoTYbFsh9G/nledj7vK
lVCjViZMUJ7gT3+U7ntGYSpelR3mt/HpZgaqGLWOXbT+hXpUZhz1tQozDHbaIdBXXxr8OMCDZ0GH
kC7WczK/r08qHg2wc/ZjvyvPPviR46+2dEb5AOMYDsk8BFwsELicyrsxPNb87KblQfg+8TZSP4mK
5jaVHKM+oGjg3DooY8OItKwvbLDRMTPm8jDmBizhu4EKFNcgp9aVtlLbBCNhLJRiXAhvSlyYNgco
DTWGs0wA+2kyjTopLXj9Cc6ISECNKscx5fPLiHOTUxZ1k71m3yvVfyYoWF2H5nPwf+82zYRjwOrH
BpbZmeR37PLu5WVxgA+wUhIuwQ/WCM7YKULiUEy/lMxv885ZxPG0TWjtSvBgMPMKtXxeG6LwsA25
6VqreS58xV7PPj/Y129q9gXCtcWB7eJNFyFC8x0Nldw6Dtxv6owzehknV1HA6AIZI+5aTPwhZwK5
feVO6WdMFSF72hlcGEgIx6PWawlm7wytE4pLlVZOZCEw4UcEyXbVLB8Sxm6LSdZauecB5CJHNvit
a/k1Sj4PX4Bb84w2Z0hguT/qMcCUDwzGCB5H7T/IQzYPakAgHm8iw2h+jQ9F6t+kWkaqL8aWcYSy
Y54GOasWHOCaiuTcuGI8uRwOT79ccc56B7cvBzctli+RJtybuFUyJriwxJ/w41OF2rek/5qz86sL
49vNqfeCoMISnX6t8W7YIfZS2YzkPNo5+qituqyE+XwvaMyZVf/tBFFOrP9xXD75JoJM7G8dqzls
wDyuHZvDZLyQ6PxaHrrkMcY5LS9U9GT9zixrpJ3DxvNlNM+LExhmIWrxEJEUHAs8sGZsmKhx6tXY
atqgO9QnYZGiHhLC99Kzdwx1GPcqy/090LPpZ+xy6Iw5xT/7fh70lWZdhD2fupP0tup2SokvCnQO
4ZK15VpYfJMaVwmAVeIxOok13MzISuDJQkC5MbMhr/D1oEeIIT6Tm2V3JCxnV9kQHQWlxYKdyRyp
abjUjJx9Pu81T3a3eB97PLkiJu9jhG1EXoNRTCo4bmiXCxrYYfT2bH0F5ulWkYcPPdcjrTkOK0vL
C27vq9hPo2vHyPiXZh7bi1UV5tnQji1zoELRtHxLA/HuiHMWQza/L7eD7/yGZuhl9Sep9HB+WUqU
FOvRY9KVa+Z6o4QVzfjzd2SH2uHi7srymPA2BK7Un6RKzm9OHkyzi2CzHnuwdfS8mI75kC9rz6He
/y1JxIb3ZReYU8Kpc88FubguU1LdfaEYcwLOz8z1bZlrYW7dUx1q7W1Z8AyOYd9CPO0kHwtTAe5C
kCoqtQw4Ws/LdyGTgafIyIB1A4ds8kYyYRrQJCZskqwyGpexe2EFeBbxzLvKxQuPqI24zTsgslj4
HJaHc8G89Vsg5H1jiIuOsteorKdBbbvBZ58qImAIHOPpCil/XXZ1j1TJfod7G9V4d0P4l0p6HgB+
5nnkpzAEHTf3FMlcesCVFATGYAppyRS4fSs4f1zWQXYCdxZuNsGV2IR01cttFxVANcleM/IHaqe1
BKt47u/XRHSHPOQVP92QIqScJAvZET4BpjIYOSU0YOf7unuresjN9GT4nggCz+OOLocSshUJ3Cof
ZENUh0u3Op2Ky15C97Va8JjcICFoimOog3c8oLy6vhqeZ5q3WMWdPZ63QRv5D7CjvcKQzsyLuyyv
YgKGe2EVn6r8EDVihml4uTUbGL2x2pjR7bdSaicgJyG49tnAbb+5Yak2UdXFKP85F3+zWRdOiL9U
EdX1nJJpVVSjzkJUHt0DumzIGTGhH7P5ZXOPVYHNZHC7Tot4BWXvUEkNQG2f4/cYbXbiB5mNiUMB
1Ze7UYtf3BGZ79TFxIQno553Y2oQW3OLcYMN7mJYxJRizkGtgIoVqRvc4TkgcUTSY39bHd8a+W7y
n3+Rb7wCyUQzI+L6qu94u+8F9IpfB4R+5UTAt4tZt17JHckZfPcDHX6M931hqi3nslJ2wvPc49Vf
MHkGFQHykh7b/L52TUogO8zK+xWK74Y1EPrG+V/GAi75R93t9DcSa2Ek3Q9FFGpNZV6z3uIwgJSU
/6a+yeFJpfaFqwzzGpALNkU3u6Lse5qc2SUTSGrN1KaEYMlfAj4fi3n+WSnooy1NRJWNkQBvIMkB
HpEhp87zPgv6a0gAdZ+q5/9QyWaXW/OdXWvoc3QJtKfJZFRum/7K/LJTBGSFU6sE/loUcq8bNola
l18DElHeYjpYE0Uf8HbgcslSGo52pPdyN17TXGB0d+iXYiLar6LpCgC1yoZkgHZ2B5wSWBGGd7fu
2+KX7C/B2Wb2Uqyp6xyujVV+2nM4F2xeP+roG6yeOLvy1o1t0s+S8D0UVQjvF/rtN577SwVEz/xX
qy7SAfXPemYK0pejv4P6RTxnMFLChxvCEJ8vmpAW9bubU5+UHF2dNtgy5fPpkVvMecW+f/ZXQG2Q
zTyj3qi133y9Oqm1uDROxSvwAJ2V3dgSntki/NewC5NJk2IsMoNq2fl8v0uoolzQ/2L/ozvArkbn
JMKSp7o6KXFxbLV83lCvvdZtuc/RNXYnKQ9Pzu/OwqN9HX9XIXpvsbxobm2eE57OOmt8b3O3gR1j
z0MUEVyGqv2hGpEs+PnUZQBdQabuCejOvdBopUDkKKBU7SBln1g7se43SaZfyCTBQ9fGCJGOI1pO
7UmBU3GtrXtOmkDBW8Ukk5WhPGMBt+3ZAbvXjbCWfEBg5mB2CR08m2EpZMWRtRBKOlpNT9tRscIx
8zJ1Z1pIzUSrMgpIQClgQ991OANMVQ/jCQMoykCrytUslH8cN8XLKHNxXf5jaaybR7HlZ3Py+xUy
DbCxTLUsjIfM4Ohl0ESrDfIlAgD2Wh/E6zEsZyh8gaSlGuYI3pNYZ1+ksfOhV4r8++9SRjtM2GIK
AyZul0Zpg9hHAzUlVj7/555oP8dDuo6Ujq7NJqhVugnUson53/VYmN15ZEQjyL5wa7T8/4iyjBBn
5msbV3tUPnP/Nk8gAPLXKUT+fhkA3JQxW8cjeEBV2lZc36kq7vMShaLeUAjdllkvxvkDwjEsVBhs
Kg3ovNBK21tYOgzm3HJEs2y45GAcONJ9tEDme/iNg10io1imj43BvjSJghQVNnU7L6JSa7L9j3LP
MMJTyIGb6yRyAONOG8Pc9Ymf5rUkVhCYBCrrrhxU9RRiNn3/NHXEVQWmqE9B9QEvmgWAeFKXcOBh
acsudnFHprRXykPsfAUY+rgMBBwyrxIwuXbiTV0chLQVl11EUJ18bBrNDXbL93GEpQ8FvJpDUsVL
RKutrRan/m0+lQhYW8CzPJwoLHR5fDSTHrVG7Pzqqx40OX6aE6kr5DyM/qaFKH2NaK+vDtV2HPaD
hFUHJrELqDRtESXVDlGON5RDbdDYbpe6pbxvQ0cKsFdTXSyY5Xz53aVXFhqw1FIJFU03f5btQAW2
3z2jB4QM0qxIZy96fXCfvO6nzh2xdAOM1vhggLNn4eO30Ipk1OsUs7mewUlqEIvKKgLth1lUdAZk
XPJN/mWHMsxPB3iL1SpXecc6U1B3kc+kM401XPIYSgHDH8ZXvA9S+t1oRbs5FGSkyj815pvDMR9x
c1lHOnEZRsomJJacws5PtV4L6GV2xJIY5vP2rc+10ByD4UGJB0UoYHm4pzzJ3QtrExel5L9QXf08
dl2slUtFbDeG0HzGV6jBXNPhmHEW+RXQVHtfRym+/ADgfixaYQeuuDidJD8YTcRDrs7nwQVEn2ld
utaFSW4+YN4CHXZaqTyY5Dq/J+iIMyqGeYLtkTwGjPq93R9yWkdlhzz0f3z3L5VYC76TEHrcRh0a
Ya/GKFRHFJ5a6LQOXIeVueSyA2iVAs/EP5hcmTvvvrqdTsSVBrH8OtQIxHbE85iNmuhUg/arVOQi
qGSFI9BfbIt52j+gWecZaQnqt/U8+vJ/coM2RgU8K8sWRjVK0gveO+jKvJz9YJYit19iYX+kDLZG
FQGkQq3awKyMsHR05NnBVJWOl+luDVH9tl7/5+uiI/a4KbynP3pcClJG1SRU2LRqh2Nt/1DClbjv
888sgUbtSpVikmB+eq2zU7c4SqlY0KUpy8sOaMIDeHiZb3hdLjVDjKNBBmmru0GClIGC88Jjle0r
W4r+I4XvARhFQL1L4B6+ZuqHeDWBNVoiDtJbUqTlrGL//ZUgxm18TmNrlCux6DLCQuJ2TmIsOfsb
7t7OG8cqmdkmRErQ5zrMQKoQFup+arWxy3M1LBQ3dYc2lgoCwJMF1H2OJsMeLLF5AiAoDV+kS/ns
HezVWRP4x5KgGSDHo1OYfD1429UI1qt9e94dHpA9qKpQyxEIe4e0Pblsh3U3jhnZJHBfmp6MmcMr
oUPIfbEu8+jrAxmxXJq3tK1uS6Oj2YPIba+heIjKjtMt3CM2PFDrf2clzLeEQM7n5JkAw4eV3kv4
ID3M2dOGTLlRWhcmq5fjG4wcK4g9annfh6+QIejIUmeuIVJwBcdKUaE0/WGPqSfQ7OmVyEIunhZb
fUMfZp4+iPS0e7GumQDEr8KSHffirT++4hR9b8dawCZlmvqR1rlt8VoCYdUP2RABwRGtGe2/8lhl
m27IQA3e4ZCy621VQpKLcWgAbDGd+mXALUc4R/gfa1xTgckwDq7lev1H33o1Y3rQEEVzVQwnBv9g
CZiPkzTaApR9Ykf+gdriPbFxY3K4V67qhFf3efNCgdfsUE/ksAssI2/EacIVNUN4aGs9+SW3NkXs
mp9wtDtsI+2Cv0Zps/3v0GNvyFDK+Xhcw6rbhKKEbP7Tpvqpagv9TVFpENOM/rthBA1oNllr/M4O
r9Bp+hNY1vXrveyHJ9oJzzZxWBu0TaX7choJ/F3vHJSkKNh2T3+BIFh7xmni5/calGVP4f4HL66M
QTsupuzVp4BWsXIt/6nCy3+BmsMKWKAlTQJeYDzfQ81TLU+Ad60EHbjrudGrQEflBpDti0OxzUL4
Vh7mD7GR73bVPgWG+LfbBpq3iyuItR/sXA3qvap6K8HDmScSavBHDBepYehFl9DRdhg9zSNM5S2i
unPs9XEIFxvUAU39SnHzWJkPDygx+iY/eGXwcXqf1ssAe7xvdeOmd2Vte3hhTrgBtAWj5D5sNUt4
msfBfU16TQXicd/ssiEW7TX9+PffQb5CFHrOUNeTonBArvk9T+07lyUnMHBozxFSOHS/xfOjADOn
CilqMqdvUnhd9OcNeTYawhxfpZF9fuiqjFx6zYWoj5eD0c9MBwDC0C+Pt/HqS7Pm4A9WrKUevrG1
EmEzEHweOh+p3UCMr0ncoMm4kUt+PxHGxI0pwm9x5G+fWrl3JC6NqNGhpHjiu5+0Xh7hIH8+yn2q
cMsu7Ma2jQMdn0r4VsUMPyM/vJSAYTQj0q+2kU7RtLgT8F4bkL29zWD/67rjf9w+j3wMQQiw3ItH
U5V86HE7i96JROVyT5SVy1si9a2ETssDCj4dDj0I3nT/LnWyJe5OYWzG7KzDDK7dSAzhXdP6iW8z
1uuhGeaNjhma2Zp3L+KmXdax0apCgkmxVf1fQx1FsUQdchC9pH+eDb+J0ccXXyZoR1EMaOr4WhTZ
3f204rrXHizvQ0e4OyAvjr2LP9CZw+ADnF32F4arDOpA9bd6sZiOC1DrDauTD1tVGEViwol9mC6y
b5R4XOY8Y8ljcYkPhn195OxbyZPbT443TXyH9v+clV90SreOjv2Yh+zbeKXv/6CdP7/4JgL4dcEn
TjGPbUqtNs4o5a6EhJnLSdSOyQNyeyrdj+6z24dmIip1JDTYuql5T5RyBu9jnCOfzNJ0BBJei6TC
toE1MtBnxIJxWr8L67i/BQW1uMEPhGwf5kCrQfZfS63R6BSiQ8Rhgf6wPygjtzhEzCw5zNiZcil9
mcqbD76txu+BsvV+EBrXdha0pE/rUMf9Qn5I6eUmGXIAUfci1wI1jkdrv3R43iIArUOrynP/fWUo
E87L5xQTQXZaWOsFo6lbeRPENCqC0I3z4IbRACPCtaAgJb8QLFOuKueu9tJIFd6culC6E+gMbaMF
4SdOb/ihNUJl1w6Q8yqNiGpQzljQlIJhNJGjftNgMLyLl8FXYzbuHalIQGwhr9TkehOQyQTRCVpv
qE9Zw/tQcUQkAEU1CHBldTsSyCWdcnyErOFGjb+hIU9LocXP9HHtBsU4CGtnfnxjU/NrgxaHgLqp
EO3xEDzhxJZnHGUXTfw2OjYAl2lUP5OsWRWirnvwG2bsbpv+4Fr6hCkLLyNeLYbqfzZNP4e1LKsT
6/4WBIiR6yeiwfFD5/PfWHoFTTckFBa9m3n1H8PayWEL2ZgzXf3TDRb6wQrdywPbiz6vtWRZp75j
grDOCl+el8yfRrTdIkH4na30hmTPl8XakWw7j9BBdpAbO7tziVo/5rJHYzpwOAZ8SiK3rsTO6W+2
pol8zGeGFU7Nsx0gO+mwUr8PUI2pgIP+YtpwHrhVl4OQ4Jnm8eHTjKP//P6AERJwN6CSMLsBVZ+4
QaNlxo5TW44cD9xdI10qjJSc6/G4NTiFtBfU4Nk3MBIX+/ELB8JQG2+2J2HR15mj4jbAKoLWanhW
g6d/wiHSTiBovlKfN0AehyB2fMTFJeB3KHax2QTdDYg/PhACEEmwO4bO+HXYKBix6RaTgRoq5cy2
opRzPMjkU9PMYzV/tj8rHYVriSek4oyE3A8h89CxTfbiLPpP/AgJju9BVx3FrhO8XbbCgFrjmnTT
vPbiT3gi54Ap/5KaiNz/6HD7M/CluBp16duC78+3MaG7PQNgcpfvg1N1uLTKOWuSo0h2o87V+oc4
QKqKa/+DP2algz3lk2fFYzr9AIA19FmMTTd4rfs1tQxuLY/GLq+lR/rRVYQqkaOTCa4J/V37fD3O
fy6AE25R4SrVD/NnuW41We/31AOaYzoBYKVrKjc/aZHsfndl+CVPiW8ruTXWqqHaPG56dOSUcN1+
s4XhObo0OQGAesTTV30Aec1m+K4loHnhHbqlw/rWdzGBYDvEzgWEOV2UEUDJv3CvlAhyELTQ6+Ku
FMALwY8wsREECtQSygdSYeIk+F+sHxCFHBkzW0G/lJfPW+6tYB3L3cO7D63pPpSU3Dxrdystl4ew
OHpsEqYj3bZxFFkJVJbSdvo/YiFVqzAE2pufVNgVFBK6rbj545uyL7jAU5NF9WZrqwoFVkrNGrod
mIrnAkti2+ov91HpGe6AkIiCRq+TB+lFxUPfG/JnmuWng65Ew7m/5WCHMg0T1Q86gq40o26bGmu/
v5fhkc65k1954z2j7lejSdZqijEW3imgJ4aloa7IAnlWUBPKnqVV+/z/q/wxEow+hUGdASJyX4bz
mGq+A3Z7H7kG5MwvDSpGU4tVbDZIfwqGgz3T9RFDAczXcHWVIImaJHFCE8rmNhRh7mfbGqWMqfo4
ebDScSAwUGFx7OH5TuCg8pF4FZRg0Muy4zy1PMpyPL6W1ct47+IThxiC6HHyH8N4yF02F98kh0XE
9jiN8mg0t1y2UhsxmTZZuK0SmKq+6WDutPh3AEZDIDZt6uz3auNurCCtjERcUrjLD26wk7tX6QFj
KzcafD9xMuexrHcsCsNQT8m+rv+TdfZ3hRzdZlzdxNpaddL0wMbN2zKUdshscCPBckbPY5rrh7oz
fwQNe0sYsrJe14X6ltPP/GqW5sydY3yiUyBRXMHAcfh3PshsyurQekiEO+/j9Jc3+aHARl9i0GpT
8+06k8/Foq6pErqCZzWkzAz/j9SkzfUUce3HPMCG5liFIEkOrVjDsk77Clr7n86qmuUJarPyu90p
ANMJND1pyqjZhinQTjFRHgH/+LEbGsgMBnzFIwEL5Wlbd53yy1/D03PWhvEHrQsH83QzzNxuKwJX
ZrFdkLVD/9seezRn4AiTix0a/K8yejL1hWEsMi8/PQ/USHLdgMHru4la1iXLGVMHl8lWbR1PRAKG
AOA4vRGnJnyZ+/J2MK7HyTiI+T9XRtQIi3bGzl7AvZSOLyw1JGT7qdLqZBuxKBVtYURkPDRuCN0n
rtZhm9pzcgvG+xbTxoQ90vrkc56cLI9XgvR9oTRuN2dHu8eIXDyu7L/0QDbTNDriLrXeCBWepUHt
BOv/5R0BddB74SgQK/B9adVdZ0M9zL08CMlH+2tUZIm+HXEraZRyM/78AZTcf5SJ6PQaYL5YbD95
3hKl1Obo7aFgdgn8RulZwpN8eKWvzLRHqwWtGWW+U/mbCVWrRXoLT3qJuqHy98c1D2C/otI+0tHv
nlHjudqcoGBc5Ke1xFCTnIfLiDxUbsJlv/MD8cjU+ciBEeKxjLI7OKK5/TTo/XrzWzLY6RFKqwMs
0gqhQSvbALNw4kbVzY9g4u4eky5+IzfV5ZyR77hUlc/45NDk3CcR1P7I97y+ikcJLDxAoiMQ0JIi
9t2F5kCxw69M4ZRv6CVtpPd5htMKcLBA3M9bgmcCd3A4Md7HYYI/kq56QYKkPGZwc8if6EHfrz9V
FiSjX29TRcQVKMcFElr8IHgWyPf68CGH33Lc0HHYTSjUGFUPl1DkvYMbdZy8Icat9fDmWhfP9y28
6gFDnXE6qHOKMcCeUQOyAXcGM+qPXn3G7In/Hna+BM8F4u09Ntw2F//RubNJxTOJVTtZSz6DqYKv
xZJx/ttRp7ITMHjbqn23/T1x3rR6ZiRk4QfBxHGLymda2Jd1r5GphcnQtlmmLI8UykO9AaItp94I
pIunOsZeYYReW6ldZEj/HDborZtFnHowNVC6ZFy/+QNlOLRWE8BeCH/oyWCDIF3PoYFpGC46zcFW
xrOrrL/UPQMS5T5p+kSCbA+AhhCmr8OC/2lB76+teyRJPyHOmlAhrl7KiSaDSqvxt9wZ7bOVrhaU
d+EZDNNHDDdIR++nlhGux0hastOdleO6W42HH9cGvlLazO2xACFLgRCNP3NCc5GEGLesJKI0J2/a
X5cRCpVbd0NMk4tHEJn7AbuocQFBe8E5x+TsyIP9u1RmqnrInJDTH8dY3P6mG6yNzgos922vr0oO
0lBxEaOPeT7Al6Ld9YYKhJVdiChi+Ho8cyPhxxSzz4NO/5SHe8cmy3URi5pQhpjtx2h+ZV22dWUo
2InXrzmg1FkCPMckqzOct70YXPcHLSUqSbrxn43KgvPmzJDJpBxAdDsiWf494soP03VzHUixtehu
ANmpqqLWqQs8r0T7XJU+cyx7vkFDSJVmGRlB9s+d3WBsipF0lTCn7X9TS6kPPKyV2fFVx6js6ukw
jZkXOgJ322sZJuK0KBeqpraBX3mzF4ft1h6ziZABtAoiE4d4SRkm1b93bNOrHLN/z4Pi2dT52aaN
hUaAIn2m1LWhGqJiybG840cRkd40h5GnwWTC4eWq7i/DAPw7Ao7cRpAW3xCoskf4KuLMJbg8J3PU
LDmUrT289ZskaFb7yFb2JOAMyMW91fDAO3Pjweoa7YqQhn2k9HMtWBeYpFY3tX6uPQdjJ+K0VnRd
5nDFKKYnXGhfzsNVMs7h7vA2in0XRJ1VqinMtfhV6/k0wFiHyb9cYhnNc3jgFOhfox6OBe2wig6H
gAhwURa42RECczT5n56EYZBAnq30F9POYOgoSjEm8F/ysDA3iM4gntT0RcYhMzztEZeCEVciUGph
l8RoTTky6i2Lqpvuc2NL4SeZ8Y76PDflmLidknSH2ogad4vQ+ISmBH0fLKSXhQBvJH9S/vu3lMaU
2p3NBLwBvBXnz5o1/5eFzdtwA18O0koKfc223yMs9v2KuIMAVJ1GO+ZznJ+PLveMGGeTlE/YSHVT
D/oiQuIUHcyN8W4ugpIQx6rHOTur9QGWkvkDwfZVkl3kOxJ/AuN49XTKrflpMFFqMQ8BF0vp5H5p
m0eC3Uy1rSetVgly0H7XKnhm2rB96sJZVb/hGidnhUpO1Vj7SnSkvS7cCXfo7Sj1qLL4Wq3puPrq
QO4Nv3GA+POuEkbvJCvZ7dC9UeCGnmrQeeRz/k5aNSFt0ldrohJS9liWbFE1B8tWCdmC0UiWx2rJ
SvhpBOwr8jyLK5tgPlruoPOaNWheG7KliCn+kq6fEktgVqVu707WOLHkujtJ0+Px51NAvwJd6Fmi
NLVSSeHhxHkQyJLYf65lvq5vCYZ5HDsekl7D+EHWrTu4p1smduFJV81ZwZen6dJvAu5+wpX1Abe0
BtIGCpX+wYR9OrLrUzFJ1gyS2OWGOfHeYLxZnCdW1Pqkxdlfc5TKj4gSfMDWahFDSOpKzV5B9/Sj
HOrfFUSk6owaNErFSRks8m7iMCi/AytAz+Flew5pe/E1yLFURTLxQRjvi1wXpJ4BCEeJJD+v8Ndx
gEcBTeiL3c5WcIjjtEqFsQ6YPgVEFvHE2nS1AmUsSGyVXyVshIqqxkiPw5CAt0N6P+yVrhfKsL3t
Yv32co72vpAcQVOnyAeiTrrFeA1MxcMyW7qoahb1bQ681GVb4BUf7O8NuULkeSFv/+nxe2EFFPLd
gLfrMDKlSFrt5y8RVWnXGZNKc/f0Ts/pPrwfI4N6QnreWIz/RvaHk5z2tXNNJw7VnPOnoaRhU2NW
uw/Z6pYaJUqYc+i6ppMe5Ws4JdEgbUO/KM0EqWLFlrEb6A3aFpAUXu4uNeSH/Bih+qYb2EwaroLZ
SwHXY2zjN+6GYEfpVqK+zoFYM4RwGT7CXhFsFDKG+25C0BlrVGdYHhG9wABGof8xe1Kw1KOBKzbj
lszz+1lpzRQm3RrH5Msng/l3vvHDwWYmGfFvyH/z/YSv34ipiYs44culvujSdRcxDsLiG42qEVNh
H7gsZLuNo8swx9ws4emoTm/TiEWMQdpiuvjVrV2O9eoBdkPWpJPazi26GegRkwzMbRBOfhOCU0BP
CVLXRQcvGlpisvHxwlkbPNCRIkd3jlR6/QO8FXHIHIp1sWikPzJDyKmWyCowRxoXNcHyzQ28zLnF
/ymDsdVKCvRUMdUdoeZSaM48t9Lg3vSQVSs7fN8XO0u76cmoQ7JesNicxvGoC4A1j/HL8dq2F8P0
azDJdvf1xfYyI0kCu86yF5R209J8JwG5+7GTXlcUdMsPX3hOBn2Mmgz74O0WfsyyGz41Lme9VlLf
tbatTWL9VWZlWfe0QrRzpZp5HkXi4xHmQg3YFK0hATL9dJrkNxGJlcVbdyaW8OX1GVc3ye7flB8l
ocR85lxzvAHNd/f1QnUFktye61u4Y5cpmtOSn5G+VYRVCalj5d5x20BqLpd4geCAZMicU7x9Jqpa
ZUy0pPHF3p01v8LvttRsHSvYvEqyanKbfZ8X3Y0WOGAeEbwP4fifmJGmHyznjHZVt6CjVZ1R8Sgz
mot/L03BVKRITkZIWGMWGk86U6FsatV6RfWIfcD4LUJteFTxl+fodmpHc6X5KYybqDL86g1//svH
PiylUEch2VRx+lEJL2R4vnQ7qPBcGqiIh+vcExP3JeEPEk5mFxvcjiINZq52mee145eneGUA+kUK
dmmYa25uWbzDa6GD01NKWfcKTL78AUEMbVR6O6mywXnaQ4R0zTi9ZFqC9HrWGdLkAFKNktAbD6FY
9VQ7CWHaPQyIY0YLOaZ4DjaoG5W60nQCqh1WP5768AaODzwOp01PSaZsLNA61v4mdX3LS7pSbdX1
/si9+ivwt3AGe+jNTpPMyY23TDnYhGiPUYyBPERQnW9kVt/iaWhuxtk7NpsmquhDNB84bFfW7wbc
zFGqBoZFy3CCSmS/ymByzsMYHgSMVNf1Wgp/srqlmeGhicRRmlMx68b0BTLb7fEzyM0gNvOlaBfL
4sKDC8S1CWwbNZJZYeQa43DqM3FH11UIMJ3WYI19tJAxixS1KzMAGx1/RY7ur93baAczSj8Ngk7t
Wdxh/1r/GnSZ/IeW7Xiy0+DND+y6Y8JsAjSaHuEBFlM03UxWnlZrYrYuEOnr5yz0CHAyv9c01xwx
ge0sx24LpUyFT9c1BbZ6gbOm2FVBqekiWjb+Nn262miSoe+S6WS/72W/oJyY07rAbQI5zoBlJK9a
HPCAAq9tfKqwExqE0Q4BDtA7XS/ghLLkbWIMkHjAA8Lclb0x2BdxAzDSpmAsT9qYF2a1RArOdHyw
au5B8V31B1qXhIZFGKdgxEmWIx81bGQjLgD1WMINUsISw0NUwn4nZfP/r0N4w+WeCcfCXROqd2/n
4fbWQToiCn8g0LFnCc3UNdeE79evtQ/v4VDUcGqZhZ4fCOXjvS6N0kzqidNN7pfEN1dgEzCiOchD
sLJcaLcDpD+7jlOvKbu0eR0ylPQHmZeeOwm+GrZqkuWDJ6Bxj22kjj4S4L60X5QcK3644CAb2YfO
TGhB10GlDab6wH0y1Ckxp+PvOCy8klj7QHLQ0aVDvkxpgA7MCfQoEHLej4uqosk+nZ0vZyGJQ5j9
3D6exhpcfoQAwo9YGI6Icv3Yw69WAfulsKRrUJsbLBiZLryrJ2giu6XjCg0a0myGfKMrvaaYqbcx
kWgvyDQotPq7GRNhBJPSOosA0WQeZ4Q/kkW6HPmL1qaiO9GE07wlJ5Imkz0HNWP5CtV+K4UgPtkP
VW2JGbR0DGKOTvV3y3vAh4ODHL3PMwrLUs9Z/53mJmWRUPnoMIJ8pseBgfJWiUD6yuJpHQlUxje9
MB5/AZdFiKA0HBriKIlb4akGWc7g8lU1qXJX8e5TfIhahs/i96bOncSSKleySQUfMXebATBVVduO
o8EweJDmoSR7cFOGAsU2iPYEQZoVMhJjSSRKVkJoI9ZxQZakx4A57uBDkkEaYzkNcxAgMYkluTsk
tm84gdRYzKKYo5+7/YeMtH+XAz/F8nKnEMbHUwiiOAWpMVGzQ/GbLvM0tXWzkyhbv/b/IFhTGVFY
QaACFQHBeIIE+6Atb691mW3zyMZ1zn7btZiBF6FZeS7dJXG56TPbtzhV6Kn5LcDaZ2jHJy5My6W/
hMXyvcQHL52cjzGqSP6yXF1rFQRh711QD8W34uq501kbYHXsPDfoStgAC9ZSlUlCPRZaxeKGmXHk
kedL5Uk3e5/HebBURNTBILwHCbUri0SXAuBRoK3VwQMbNJxBHuklldnftjUSnz69t20xj3qY+0Py
ZNkdDsivC78N+eFF6U/ElRQhkJ1fZv16ecx0AKrOoOU7YpvossdGrQUZcjjsjv7m92yL/9JTkrjB
QRZ8cD+UFFOllsgY1Nldjd506QBhv8Mb937QRpocFXkCyt9MAeX2ngNvZjJfEQmVcq/daO78cJyR
9clKKPA4CVKH5FEjjRgV4o//LKxkvmRjd0ecOBAkALK+fnBpujD1ggldrhrWt92jdvGHb+gKeFm0
YzMAE6U5wIljpv3fzgEDXbIdUN4C8y36pXj+7AwWUu6K+SEJ20TZ4c8ixPzimucFmLVLO9QETxYH
094d+K+DKUjibSnTAT4dwAL8vcLfRH1Ng9kNRLxkMDn9nRjxXW4wMNps3FOoXFKXDEThEXtrNrYk
FD6YVjyqRU2zmCFmQ7MSQCVBBsiy53YvFCMU0APt7Yj/bmCUcEn5fRdqiYEGCUOYOBQDQCDfKWFR
1tL7zs2TB6F8sVvrsdV3zUOmG+K7Ew2YL1k6uGtd7408dqcLLWjIWKz9YTtrbe6TGUNjJFlejRzE
qEWBvYdkyfAHOIHKQEKqi57BVQXbvvYrxCTf2ehrSm+wpl+Mdz6NhxB/fEUYg8F84KZANVpNNP5Z
zWckGnTjSm5Vpdd3k3i/crxqIrJCLDWMytkd8Ba38qu5PWpl5mNZNL64Q2i+bHelUyrEqwpCHUOW
iji66QocBFb4o26o1RWnUfdQMddEJ9nhQRNuDhia44kK0ita0foLeN5vlSLlPYACDyF+ZCDzmtLP
7sas3Hi6U1BG1Rwg6yOYMs5cBx7N1rp0Fo7wV25dzbFwdSKoLtCoib7D6dPFnWjDleBbprU3cnYS
oNA12B+ZyKHsAiFryn5Ux2Ur3CLs9R/v9z2MKqB2uOUF5QnK9LbCb9awbTp5RINQEtvxNIu3YQ2A
fUM1C/qSKeWZJ8StYFSU3RHlRYTx6ZGBujgTzAB6Qg2XDhKm257q9SnUP26iqgDIGwYi/wpD5Uye
cXfZsAlzEKqWZOAzC9+WR+bOscqi8+MyJrmcCDsljk71Nmob9MmDP6mG4+62DZud5pzb2W2XRH3/
fzovGQOW2m0pCsH0oxNkpLIqB8CZCHYQxRY4GHzza0Ikmbv/TBNnXO3e7n5Gh30fTq/31vhr5RyA
Ku/fd1M8M6JdN78uu4w6j9umoO0XTmAI/PSSYVDtz6qtJVMs3Fmv4iSbf7QwDkyjDioAA4obyE57
lznyDrT996d39OOH7A/xsnqODwXogR2BqGMomDIc+Jkn+WxK5EoHK7l7SaWBdrmjF0uS9GaB325d
j2pPeSEpO4l/5agL26gCygp0ms3Xl9DzW/t5yQNh6MU1jN+DlyBYFHUNTtc8jHTevL8IVylsE0Oi
fcj0vFtAEBqAdylTW/gbNAUli9nIscfu9OR3E5QDu6B3R3sL8EDLkfSqMtj851sX4aAS7ga9Uthk
EqhG8+GmGzsFBFtwzZ+DJfBHW89gn3SDAIhwLoJap6Z6zY5P5iiZTv8NpkXseuwtdWq0lsH55uin
mi6RmvYZmdLeWMB6BO00izY9BJ0NVjgFxIkEdDAThQg0qF5xF1rdTXtkHimRpETHlgPiw729XUbV
JFwWErkS4n3u6Lpvcd5HTjSqz7G9DhZOgLGD4BG+GgcUoA3RSlLJFtDEvJZj9GFkOe978xn29V53
fnqVgf5FgxBCscg3d/c5N75sdP4dQgs326GwlxHarFoFECVB7vT9DWu5aO+QScNGy+s+DqWHY4Qo
ESn+53MhI/321V7R36kbwLDsWEb9qoKqelbvPKqhWQWbR/+piZSi573iGBGbK2x9Q44NdnIEEsZJ
3/ecSnE6TKXCduSEkTP+4YYyhYy+quQiXDjgfBbJ6HZQTNrqSsMzIEcfqMu8+0Wnm1NcFoylQl6l
VRmxd/Z2HAD0oG5aRVEQqbGJRs3xFQ2BhKPVYQQ+GEVd5sy8u3WKCX8V8TW7Tx0mHdyJiADJ3apR
nYKqG9NW8UYIx0UP+dMKG94uNbFP0XVEs6E1V0DlgxhU1zkztYyMoG2YyeU8RMlAXV0q7EErVUZc
cqj9lbXPknikEklOy/boGOS/IoWHzVlEnL0MpQB1rEXbSpsiVub5/VPDSPoiOvSsahWKeNpt82x7
4EPO01LeW8bIOr2okXpGe5izCDFHm/k7FeWAALF1z4RXY6Nz7JnkFShnzZavnis1+gGM78jE1vMe
9FotAg4qE1yL4pruH+X/i/0ZQxEitY3mYtXJbjwl327hDFrcKcm+Yb24jLsfTjswzUZnl1Tc2VoZ
H9Iy3MtPWVKcpPtDwz3iLc0Tk6qzWE3jQaqAWEPw16BVRcx88TFiXV1SVusZFDahzYiBM+3hFSuR
rQQo14pzWrCx3jBiU/hwiVQYtPx8vVjylPRr2zP+zGSRf5S5JuV9D6xV00Jj2k9SzN1oLMSa1+Q7
b3w5453WsT8ds6DgreeEwajZT5aVFI31/qKydvDvMTGZTtCe+fN+2qxjW0KwmmsYQmUyhKG/25j0
w79cVgHQSz1TwVfp/wEpuhpIPFjutQnq4/BuC7r82KY6bWzmm34q/GLwdf/6WJvgxTtfmpd7iXtq
+PEbcAmrZUvtO19bqjLmMRCkAa8QB0uR8IQf0c77W0m3IhjXFMGWJe41fLq24MGlofK7dycYuadG
uUeqiG+v3xNsyF8nFR0Xjz12NU3FVjft8ZkAQv93zz9r4sJPWSUAzwy+BoVAgPWqI4vVxV5CgUGi
ezODd8YfnsM2KSdnOsbFpZZgHOStNWi1jAgO94qSf/fgla/qY/CnifPuD3IJ/nX53vqC8G2DjdLA
geWL4nsw0mCjfvcQXy9o7oZhqHs2r49ynSZzAk1aK+/m7/nRiCGQIJXJPIm5qrBkeROdYXmjw/Ho
3xMrR89ZF3XxLKJAOQwllRfkV9HSoNk5NMIhwaZfmIariiKzHysd2wCO23VD5Wv/mKX87Ckf6Epc
p1W5VNVfq0ZvtL4UtwVFg3eXwE/Qq9HA3jeXPMC2B16tqF7JzRkYs4g7kWrBL0iMN9N3ou2O1sww
aW9ergshn3sOfNd7RKJz9Vmj2Cg1Anmkv3gL2nSxcQx1+lZZAYs1s9U2cDniJMzwxmy58AaKgfwR
uYsnGeHZiA7Yu9tEXW+E5XlHnBv4xl+Egt3hZuuW7op9jfA2z36qQfBeZ0W9JVDq+FD/w+mdMMUc
DD/kJUk3JmhWjqCe3wjtEazD/QzRqb3X34XbnHtlnUPtJ26ThyLbnWqmfvC/7Y8jy9n1w95HrWTk
LgyjaGpetKhfOCNiHXujhTHz7uApEogWkmtzoxEFY1CWKygVDPmhunS3LHkUVgO3k9Q/9Q/vWJUK
k2iVlQLNLRExFkJtRjpLg7hNWUcuBBjqv+bb+xLSuIK/d5P2Ar1OqeRz2r1UbXmJXp5xoM5SDZ+o
K0uoo/92mkwt4GadtseOg0QnJJZlfSGINSFK2oCnDm+capn3K9hM4uau/qEyVu6TUoGYlGuz8+i9
QKYr0RcMxl2WZHsJmR9XKXkWh4C3rp/sLDyeDg5bO6NEQKAnMWi61MO+rwKWVBrCg4HZg/DYNUk/
XzX6gKGrEjLPnhRGgv2PSli9Wg59x6AHgmthvbfGJKBhbs0WiK6Ogx4C9fTgVZoYmvcXtt+GC4EA
3GbMzidEe3q7pBfmAIVTGbK5YEuZXjCT0tfUklkgOgvrNgsOASXX1//Zjaf9eSq3Wue9CKWGrivK
RfMaPh2MeqO5+6FjhMgvfnSh8LMm9Re+wuZE4a0SIKcZRm0hA3yA/IEYl77HxDot6QtkFLUtNTIY
ij+nF8/c6Zz3sGkuziN1cmEstuuLnLYBGmf0+wrQJBwnwle6iEXDU76NHJxbyAZynQ3owKkCyrUj
Vuy0mnNMsUmlOY7ptnBx608epw9KWBu5dP59hK2Pek9OhXFi4Png7unHM2liJIVx8zmsvlzxbY9L
CrCbBEdP1CQ86VWu20pxxyWj9a8y5ax2sJ/iqh0kwHdgwMjubihojw0OHAVA3qGlVObgDOdgqp6K
IAaLR0f8N8RciyazkUWhnhbsOa3YfSZLxHRmVy3rTQcCaVh/utNylbIpgR2BEL/C1jdBsKaGsNHj
xsxAWqdgBiedIcH2y3onhKrmFI+2sAn6Ns+v4hdEUK5Bsww+Vzo6KA/OCbKjd5cHDyu6nQk4jzhh
8l0/3UrtQSBvaESjz9YEqyoYI8g0IfiZFoCrolsPSxEsHhfkZT4YEodbBb9xoYXG9XY51PI41J4E
Bms3/UIziGkYZEgRYjQJuhQUhJqvZD0nqc8nfCONOHbiKI21ny+gYzKeLqfx/96SoOxG4BUcsklY
dlHrviirVcg/sMRuEbJNjekWo4IACRfxX9iCiRCW2kJPJ0o/v/Aa0mlGpL3tUsL5xyA+tOBmQsce
Jnzx3rLT2+rYzL3LTG0Dh/L/x/vChGILpS3h8Cv5vsSq8zO0spyp/LlX0i3EE4zDzTL5nZIIJYL5
cmEIxBGLXT1hg2pI9JbuQmotqt88724y/RTbCjZN70ohWoKJgPTwVG5SOAn8oLHg645XzmQUYNgt
38EgUUczDDs+Y+qWi4gY7/v8/gzvUXHJAnthk7ORJRfO/uFH/pJa9bEmuMr19kWj2kvN4Rn5Jf18
W/HtJ53v2ptTURu05rD3X9UZOBwum20mfevPT6MgFVAlhl6mZFz/kZduBthwmTdUmA2aMO9qM2uN
Gcvu6TcvAz6ETqWNp84uewcIbr7mmtA7KTm8MT1HRMnm/hJIrPD6NiyWfS4gDEIcOQy1rYB+Ob5B
pFPfejqaEjWcf+QCDTT+ZZ/uQdxlmGcpzubmAuYCeGJXJuhab4ksRESBAGMMgzmzgvEE7vlYaL+O
VlhT53GDt3rSCRFhPb2JNvsp5Jjbs+tS5SNzpuYGVgtaDhADlu9wc6BjQ4WYo193j41EpPfsDiUV
oTTCA/gQYfFR0LyB0pQdyhdv+5Da8A7DokZYmw+SfZg5ZkDGgnCY06bKsjjfEdbAsyUsgEvUxWNh
/kQ2cLzlTDATNJYJ03C2aDXENtCjQzywQ2q0VNtU3pbIPtIrRVioV4miDn99k+YmtFzdWSIxC3TS
X7cz/UrOJEs4b4tVHLKwNh5apk/Q/ooWrqhROH2Xzf8mjVpnlMGFbYRn7cfQJiBFVM099BJ7bQuN
plcgej43Rra2iuR3ArdUIuRo3M8pXOIttic3lpWBgf1/kUZa9zKnMw3cqhe00j3fVmM/hV9VaanP
7DrNggDeBz5ajBate0c2PYER3ivwubdvnwTS01QUsw0v2/yGFN+B006WaH9DluB10F5wCn+/NyJA
GYOXDt6+Bur3Xo5YZFu/IX70FvDEg460LB1c788xzlwu4OjGGVWUELRJgNpWSiSw4sIVagRF8Cut
M06Lx6uCbJZQ2vyIZ3Tjkk/DRKMoTtXEPt9HkGVcYe5qZaOQ6uEL6kDM4gJPC084R+a8SfmPGmnx
YTsJL9pbIG5ZRyDBFdUiijCeVygDcjSy17YdEUmWTm8XoaQgS4Dmzs0+sZk8pMg7qw/sx265FxTZ
u1OhObHYJ6aAzYnrZ/paNFK6uMEsky0M7DPo1ca9/x2vULv1njLkQxIL9A9sNT5lzVeV1xmUBWKe
7Y5Eufj6E/367ASbgXK48LMo8iO5ceA45OnQZv0pPRBWc8SmpzWHSoPn64sf5Gm1mFYtQT5FuiX2
PxpdU0crWmn0niWg1LQEmbWG+kM31ujZ+T3hpuLW2r4AIo4Gg2/5Ofd1vX7dWDADwD2lCqNyE0BS
B5HPuDV6epTpvKIBgCWM/oKgkInq65+hEyUO6QeXHMJqAY5twr4SHB1PcSQvxCrymKDOiLtjh1AR
rxOWa9KE0weJybiW9QBKdIp29xOkFN0gTSUonxecKNjG3TBAXrbWNYHW9X2LvmfJegtmZFk7MrCJ
/uh+0xe6tucWvPu6EqAcaM29Gu2REUSKRcjb94muXemorT/aDtWxPrP2Cse7W4/eFN+s/2BSK+pO
od3OjcZf/MJMysxjCQw/kisB40u17I4HJMzEN+TQRdOfPc/Ewfu7BxZvYG7Dq71vpy/AY68KDpLu
dWhJnIstM4n9uBO8qcbl1tbMZgRrlvpLER0kDCRmGUUOgNoLDu1bMNdpdH+mPFCY0JASTYuTO5Nk
lDpRqg7m4KjVPrs1n2HqrlrOiZvhoMLGnkQC+6WdRtLYIywqWr1lXcpwnEmVHd3rffAdr1PMIRhA
KB7UpUHadwj0zTIH+z/q/vBR9XlPogvA84MJs+DXIXGjUH2cGmAYoy2u7PSjNQcFa7SEIs5yqRn9
3//iwsAoK5wwHpGrGNiE1aj/oYiTohHU1x5lFJltsN9K9cyjZaobJNRZaYJ68hYnqFTxUSdoisDA
8Of2NVnOrgfsJxFaNdqy9pFbhmpPWtXHj7Qd6mtrH6cZaQql5GdDl2ZQsDINfLkyeMhtDpH5qk1H
QcdwBvEn8lPsLjXuLtg72r7/RYekacw0WU0PQ6W0E1fXoIAFtfbT0O/w8Vqt5i37FTP/muWBl/Dy
ufyYdcc7/igrL24UwRVz1umbslgzOIcBqNt7rCKijtlgNWtyDUbdMbdwel8oR5l6wNDGLputPvy2
bgQhdTlgeOlVg66FG3HCFbsrT2gFRM45CdWflIVeFpc0altPvE4BdXi6MQNdNZk8cGVIQfg8VGYt
i0nwtQsKzGkV88/pVEbyOEkuDP/3UhN7J5nAIoR0QByeSDgPJ6ImYu6+o3sxbcqClmtuiq2uOm/b
oQFxYIdqW9ce9fDHaIW24gvsgbbaan6XWtLcCRSbqd0sbwfLc9o3xmhQ3vNWRT5j0Vyiji0HufV7
UJOLfathGSWSMtJidL2JIGA54sSZeicNpxIxPG8R+Sor7mron3MNG3nAQxIJZuRr+97m2Hsr2aMK
gbYOiMNo2Yx2GuVpXRXBRwMntlyAq+95nC61ZrWRKja11dYDFsdNgO6cRyCzbhraE38zejRpnQY5
5Hr1+QzdiY1rQ0UKJ6C98jtZrGzqT6uycgCGbi1GHU0PDvpEMftNwuTEs4CdDtCZUxT/mmg86b33
o2dxSw0ra4yeNH2RmTzKU/+3ci96ehlCHjEVlimMyobXhCxt4kXmm/jnJ9cAir/QOH02Kx+PZa25
KjFcp3amXEIZAXZ65XcwAwjLN+uK1DkjViV1ycgImBEFsbGAP0+RlIYKyXk+om76N0YoPgobTfZh
tcmirYm43OGPdi0Amx1fGvqTXHX1WtXr/Q3vupZ9sp7W12quMq3cKbaVA8RVWE2Rp4E7kM2PeULI
IyCArnWkoYg9uUkn2SpiMvFNTkf17A0pp5r0rOcQxH8lTZHysRBvucwW2ItUDWuYmf6pSpDStl4F
n8YcfQNckh5h/lTvOzlTk68tTRc24vFgHwB8P7sg2yWKCCNmyYHX45CWTPxTYOzOmSiwIiMV1PjA
xbQkzDwjI9MduSJjZOPlruwXYs2Q85MBx4ZtNZ+E6S4U8SHt1lB9E9DKQoj0OmHtVsABK5HatoTD
HvayY7DzdBRuZUIxWM2AX1UuC8sEOYFfwJSGRPQVLib1Z9UGIT1lEhYA44Cv0h564yLUrx6+chzq
mmdB/Xhp6HekcoGWvGkbwhiQXEXoIDqXd4yynDruHTONWbIX0cdALItrKlZ+yq68FIcOAE8VxgVc
b3ZekSjDk8Vm21ICpYidnUCrAJ0w6ZNmOgGIAiEcyrzuhn+RD5+pbZV3eyUzdxsrXV+SYVFshLGe
EZsXJV5LOnL2PZAPb55jgzej91ofCLvtpl+zmoguTvFpSTsgNIHBb2MU+AY3xZYwng/7WW3rx+l9
I0AJcpMuqPFknmzRVpPq7RimMgc97Z3sqZOWNt4WVsZ+wGHFHRflHaJM2/yTkOovCnQQO/ehJ64u
5yKsBUTlRzyjy+SC0Wt1KziJnJsc2KDwXWd3BPmQrY88F85sXxJd+GlHCoJGXJTidxGAGIBqja1Z
dKEL0R9TL8AefaiDDdl1kwSFQDD0WAaHiYhTZt2nlu/w2vQKKgz1AwbW+B0EZjg6UJud2VT3RyEE
3y+zFtprbDHJkC6RR7/bCHEVgUcjKejV4ADSlqejeFjQMj4uW49Zca/fTYrB/BXSLthFI9siuy4L
dLMgK8uW2od7TcaVtjJCY++aGOnA0Wc24AnvmFMUdfzV1/9KqbgHLmAtXobiJdyY19pNtu2FAVWm
DkKOMIz9OPIQ7z2tMZZTXLL68lZPi9Bsr20PqwuUi9XKhWAE1r/AMjzQqp5muxBu0eXDkdDkAqs/
qrYrc86fkst80bLtf+A7KTML14ZZ4rGKQaCJJ4rFgdzkXjM2Ci48N2/fedaqIuhd3i1RmSnYvXKP
b0Yg4ODAhT86SUiY7NBznV6L/auYd3uRHj6HO5st+Eano82UiQZgKf5fl5dJ/RVN+vHjmQxhVsxF
kf5TmxbWcgOKJoS4XppqWvYTbBb0wyks2fkcdAk1hZIcl1apSUHeEcj4T0avd0SzC7zqUmp39NvX
4eosmPe52h1eJoVSr41VOc9QZyg712OBsEMGBT7sYEoIIhy6b74PZ3YG+83uuJQEO9lrhwj65jmP
WeJUpuciYyqT/l49wkZHoq7//4isEOdMCPw/yAKwoiQFY7WrlMONX41hqDkMEpfxov7FUWyknqi2
Z7ZdBVeKyTWh6LPvx/dTtVFGEYaVibzak2/p7rliP61Cdvkst5ccza7Mb1vF/k4Qui5wPEvN5R//
4Zv9fRbs0BxHpPgRk8IwHvJCo2coQJZJZsWbtUhMTatsmYC+O38Smk2qCmDh1gTV4ECOrYGYV5ry
uDQ9K+IP7XNXQWhaz9GuMzCwXMLZqeYKNHt7fjq3jmxnmRo6bKOO34ChOTrXOQZUUaSCS8zGu8EK
rCSVaEh6M6hoX56DgxSQS26KX2UDsJ8cj6kpFleKhRXLZSCupvHh52vrVzhg9r08v04T+s28H2US
mNGmMcT/HZDJ0bH348TFfRaJgqrSkx2/bnCFehY6UjzP0fcSWDnxwypyddSm5B317aNjDgUuM7Vm
bosPmwre1fUBGJ+Bb99MNGrV1i8ZYl2I6nN07/29ySYo0+NBcEi6CXjWEEJgQsSdyFc2dWKAnlpr
eBNoHq7M3Lg4U5Hqa4dL/PouczvbDyDj6Oz6j9R6aUbaNGsSGqGIlexdjdFhZDLPEOw+HzOsLFxj
TUsw2z4B0tqWoniWG77l2QlYirL/KiP6y9+ndLqpeEGJs1X4nElt1TPcTVBm/MnhJ4lbi+B7+jJA
bHH1WOISsE6EatGdNqlrVrbU+wcTkEVKjEHCe9YOhTlHn+HJ6bwNYjZcDERl33vjZTHEoEB00tHV
J6LApkkYeYbqhsPaJErUkjnU7A6VkVPZbWQjDXiOE/KAwl961Ylnvw94ntkOoBwqxJVOmKaTdFHt
HcPiLp6i/zdVQKHd8JZ2oc2txph/rY4uB0sK7+d2UVw1kCGAw0e+Tdwlb1ZIA/tLHOt0vm0pnSvN
WHJLBrsXWF55+PqJMd04cNp4ciyrgCNqOBp3HFo/LLZFymZ/Tjkij48sqHUZQkkbxRxSFGUz+sQ5
Si/pFtKBPK5GR/eSEv1xKlKmxIcUp+zEM1thq9C8F8PuS4sYg+fsn1HWvsC5ux7uPLYao57d8JMu
glmjBmiqkhE69Qb778/EQFMeSsxDAGuvtA/Tyi6bn/+lRbCBYTF4gv9J3VOqIsuaciu2+BK9Rx4/
J+tfdTmt2cpartZ+nNXXpxDoKlrSpO7KU4K+l5XyKB+k+yjQ/uRAfVrLsRGqnXguwQfAocRu31d8
Q3LR77N0Fw1mr+TaYkamzJm1XXmYPIH+/crS76g7U7KhgbpwaMeKuArLLqbHZSuPR1sZL0Z0k4aV
LmCpNwtay73U2Uitei33Ofd2DnCLb0kWC8eCrL0imvNpV+UI7oEHN3t1cntsbqU9cYBgnDemQi6N
Ky9SMAOobE6S/6T6t84UcNFowCFeKcq5x7+X6Vep7SnQG5dIFap7GCL5U/Zw8HNrgoiNJ9+leZzI
ZjZU432nVWMpTP+Kxq7QKoo3YRZeQeZtcD+EfiauB6VkqZCXYBN4aNlsd3kns409l/1/gGNedwzW
A1VNaqSLG0ES8tiA9c4Tcrf+ARakR5To7SIW0kjzB+sz9c9O6VPKvsjMHc3B0b/h7uwWeY35lNKh
+qa8FsAfEhqmd39VTH0d6Acex9yQJ+xrkBhEYCkMzo5y9vuxmOGj/T7o7p831i9FA/Qe/rd/SuNh
Emaw3ffUgt5jCM3qWsNHoMlaIM0wG8J65FBy0828jR2t6dUE27omBztEPywfmvPuzWQ+K8qvquVw
WM6abW4tqfamK1HR+qQoZSeNKltiOOfzFseBe+spMpIxRgwVsdF01thfRFZdqKoB3iuSQON+UiaK
ijTm4XZ4w+qVg00RAUSjfPHHuJitTjS451LpotrLUFkYGQu/mMKtAkfJyY3V1fXRMFTYxw3frhBL
hyEJH6IqyGmkAYy7cekDD//fSsROXKGYkq5rOxSAzkTf4pE0+4VA3qUu5HWlDbiebGTmntUyXBAy
CZi0jhi2AKGDBTQukPDRVLfab9EDYMgDaZdmD8+3WpdJNqhp1DY8uKzKxGqvrdawz5lzby7U5k2y
WovFaokOp94Mnhdo7X/6py4xj9mWqmDIAyp0lBt4R5AB1hTaQ6LKUSJh7+YfdhkM2l+kyYCMHIU6
51BudaTggl+CUOyt9GIyhzt8O071axLtfGWodexMRUON4Q+q9bsle33+iwerZLqAIPW8jB9yhhq0
8xVh1I4JZGArfKEOyGGNjxglPULIqMIpvFyk/lHJvPyUwqqUtUvyZqaTaYOaCArg6TFvQVDKo9vW
z7D7iM7XCQBAU/mTLPMXgzSiyQxfhXjjjQQSv+LeiGNw/oHSm9qbKO9J3q1oxmrvrk1i6UWK0gU0
kyifqUnVHzwoRATW5BPHULcKDsJhY7mE/NKUGeufALva6NsZfKdx1C9RQ2PxI66wVroCScaOI1o9
Q7TrH7beTraLCQi2GdiASSeiXiLp1IohvhwXr2YQ1djdy1NJNqTrXT8cg73mUjgeFrGZ5nh5dEGw
qHvABvT9RLhN6Pfwd1b307iFOiOwbTQUAHdjYef+a4l1mOGoG+/IBRGyjg6OSuZTSH8J2L4Zlcg2
qJvdOOhbQ38fsLQCkFGTMOvIkc1bVps5krOXZJr/GetehTOj7n38i3EQdjntuVc1C6GmvoCiuvTE
53eOxjKLkA5sxSiWKE9vSZbk30+Pp9S5Gfmvu2raLOX9coAOAebMSyIx9GexbjdCRsqidp/AFuc3
AqRXmXMJO+rGQqkZI3ixVz1W6ASQBXjDf3ohrrd5Rh7fKzWsworzCPeXrKT7Iix/95nTp8U60pyD
aKuD87yGHhWpj1bvewOLOLnhAxm9J2LugpbrEFT4TZAYZnTZR93sf/3/iSj2zBhlZLDLiNr0BW1H
SP5QvSLitO9KsWKyd4j4+8UqgnjJdyAPf4DMciO7qg5LylRkVLLr5uvn3F4+3FgWtkOm2+6k1tEy
H2thztCsPOUTRRVE4L4oraa3QZq9TuW+RIm3G3SiX6SImEr4FsPqjNw7/3p++32A2efFkeNLoubh
HTukhGy29b0GNHohljG94l4tsnGat04xHGro1m+9oLx/4BU0w2gpgRVpirsVtdafG4xsQNDQxKoc
j0okmukjrHeCz0YzemEp4lg97L9KqiTT3J/H5lJO8hcKFcfArXP8+cdziHR8QHpBcHduwDBkGqvT
tWtw99tqiEPCwOb29eX7ne6/r/2ooSEWdW+sgp63TJ6UzxfKigmohdDGSl47qDMXg+HXrVadMeR0
Vl2M24F/PPkfGLt3a5pxKTAM1yHmTzvh1k6Mhh12f1bsoYlf0H9inrkGYtkFb3FPBxoFy7yddTFx
WGGmW0KHTUS/l5eYPhMxt5lfB/TUoczsgywAj1VxZLLbpkN0mDiziaEEIuomc3p500o830KoP/yE
v5tBtrtzFOSOdrF+M09NpKIZsR1slWTKp6B3TAT/2DUqsjN4x53B0mFpZIPvPyc8jfjyhIoCDOUm
poBs44TtFAVkJeT/KxpVbD5R4s22zkxZ9hF5cu9uKttpoM9l07CRnLkozkXXrISv9M608EU03q9m
8Z5EHlTtNn2aoVYk4WaAd4ilEFxov/lSH1VPEHx0P2F02GHmXttoMqyatfXCYbjENPV3MMwoRy9+
uy9x4HdLdWvsawI4a9exjUutSjDXhk15c33j0Io/N8QvivG9btrodw8/pCTKSF/Y29DsYsZZGhZz
h0qGfncvFsdGm9bHTDkmahR8t2+IMZ8VqfESMbA3o7Vaq2eUsZf8cQ5dXnaLvuQ7ZJ7vJ5qhQxW/
9jKDAK2FDJ4+ZSpqzMmjbKqdDRfMzoFXMVPQZFNIg5X2dkiH7WH5E3shALPA++z2oMvRTOSYxx1q
04QLVDihHs+2u6WgfGm1agJBVuVHw0/Y6Q3iBYXeQ/WeAEYTQz5FnEg8iH7e06g3N3vPW146o7qE
W+7L4Y8dgu4dLblh3D9OMm7EPRUkXvw5B3atm27OY51x/nR2mIH8hYSLIt8xTP6BeWpJGbAdu1QU
ZCUm5lwn+uS8REO6njCkzIvXo9EejB9hdJt1jJAX/+uf+syttWh+isyw6qt1PyzMeSoW0ju4PpjT
PiR3nTz+7xbk1daGivQ0lVAHLOGV+UTHAX1SdVXMPSAlNNftilSkdk/GsC4bW1A2pWLfu5XSyfAh
gRQ2yYqhiQGU8U+K5LR5gEeMnxSVfALeKRcUqUpI4iWEfgGjpnjq81mQUnbb2dVvcgapKHa7jD4V
H+RjnKD1ujAUaY9TVpfErd3yhXgjjLgW4q3ELx4orpVNI43W1vVkjDMfZcisIaNgVUjikaS8nGfk
AufZKDAbaMQXvnQ4AI+LYaYXOOR2vxrA3qR8KCI4Ych/4p5/b5sqztIGD9I1M3plh7+B27sY4onQ
N6RA1SolzlUkyCyzv3syTHhahdea2fWtOnIfEJc72t8U/OXKy8VJXLOUZbPkL6MJvVrFz/aJFQRE
XksM3OpERutNfGTZnIyyF/iMh1R1OGV4EbFuBjwQGq3DeO9UqfFxo8q9i//ZRzG+scXouZDSmok6
JtD1lS5jJg9Dan00eyeyP9tC5cU31DmwvLfw+6WQ3FMqYvME4843v6bmx1UhzP7nEiNvCMwTWXkw
BJd6KrJhuSUgF29B2ikpXz1iuVL8XtEuQ0kwLNS47E5BJ42mHZx0Bunkm0UHf5SwgPWge6o1WrWl
JlYZ4RoSTpAko4EEKArfgQ2FxxRMkBbXZTYMDkX+ySK6xuiaAccEW3Pp0X0EpiRnjgBpCha7B2Ef
obJwELbxe98JV6Vm36tj0VknqMUluYDaRxHFcfElHDFBrwKKRnb4aIvZTVFfvRIqWkyelIkfsU6K
ggPrQqRgPOPRmjT7ZO4UMAo8VbRTxFsR5l7RiJo5gOYHOXUDhRI2XI2aOY2RQmyTnlb73mUNB9lu
G8U4MJyCOGH67y5mqyrjfYw/RYU5lbgSmehlOOdWYnaPRXWd3poEnfehQT0yyI8w8IU3TKVfLmnr
BJcB/dnCMUevFQDG44W/LI8P/Lg2qwIb/hVkauDUAC86xZCD6a7R5+etqaQd227CfLl5g6Ar1wze
lRDm/OszzTmvV3VshwhiLkMztwM6D3HKt2Hbd9AB4P/oIU4aiL6svOhKm3nHR92Vfj/baOJnvN/e
khmWJ/a3cDePtMnIr2NFPLQIOV42jih0yQykpWEDCpGtZ0BAIBr2TJg4mnNRrsFiOe7UpnrqwWOZ
01069WgqJZcAbp/YTelJ3Kz3FZRLDHR0zOqmexgLAQlj1Gw7vuF8aZAL+BeSPantJR0wbcdLQNhG
BIStQ6baMFH1QwQWSe/QbQJaHe7ZwkYKSh1+yanjIjGYi1QpmmFYA/lAHBTBC7zwu3Gxsbj0aWCC
opFvsHDOsW0KKasCCzQFD/q8lGmquhOp36bQE/PwfQ2kFOfwqP2IzxKjNU3kr5q2jHPScKYAgRp1
0lOmlQDOVkR555WRXEsho+/5CgAlIR/M77uYx+3In1p5cMcUj1NizbUQDzI8dlvq5o2A5+gALIMY
ZwrtKEggCGULMhyPTvVyVWtj2doV8CNzVVbmZm8Xqua5s8qOvoJ6REWj33lDtTGXaXauIyccxgql
6pVxj4augQiDhOO1+yZSlJHuRWcH506pxHCmgsk+CTTNv5yDSQALtNShsMWgky30w5SC+RtIaMHE
li9EVVPJi3a3iGoS3T60OCdu42hzoNphzVBARS5V/DbfTIHxZxO1VtQdmrMV2d80hi90m8VbTPAn
cC0VWgKP6/k6GTiaLM8ezJcu8wANnyCPkar/TkGARdFxPRukOn3IsMxQ9QoN6ezoaq98LjRmCly2
XSOcqLUokuECNzQ8eAI+SmYMFx9MMUNe3FzeDaawSbCuFdPHTROZU6nZ7O4Yqf8cYdBrbcBPhToS
JkLm2UzNgu8N7ERcMTOVauOG1AzxRoWsdMeaq7YBYh2BfmaSABINzuJEHOIRemJgGg2xyuFdJPvx
tfFXrw1ADz2EKjiGfBftcZNcXMgIHyiUVlxakPQEf5ZmHD7uDb0rTqGNbEgDdMsRceRC0MNIxpaj
XViCXxCwfcL4fb8E07s2hVHLP6ZbcKhgFa+TiCmghEypT9IOF8qRY3kXFAgDbdmqFHqq/gAXeXPi
Q/fMFIlOL7rONe3JrobhBiv8O8lJa23pfoQgUxcomWj1DuHCcM4r+xJ+pBv1Czf+XgVi+gxy1vQg
LVHmGwGqxq7RYQHUuuR8FK8t6zSE2zapbPoKXw2FZXTI9GytY3SvhIl2Gk35ENPgTitsIHuleOoO
Lf3/a2iBAc3MNVNZfFhr+Xmw/GTwarBKJPYHICfM3Q2CxKS5L1sgdLEGN8xEufAoQfPrUnru0NJQ
pbwjM94TqWWSRbmvpWSe+rukZqkX7oWCdMtS2SzYGRHxITAj0+y9YJ6SJ/iuSRIW/GKNNIFxfdLK
uOtSleiYinSTGxQquMe++c+PQgd8TyZBeJc+o/Kkk+bhJdeHaBZ/nDIDHWlub/Ov4PGfGlFRGKTp
krb4FlOjmIpiDjP6KqR3X1JqV+PHEVtQ67H6inrxXG2GN+B8PDPpwiVrees8fsB5NK4qsp8FY84p
qMsYCrylazB0Oxjm/2ipaY+dMcuhRnWKPSpT46rO9hZCQutzAQa9lP2L2x9dtcPIrUlzMi62ef/W
wiw3mXmH2FZJ8OVJ6EQWk/QEG3CpILRZLzXtRoTVbPncXYrrKkF1/h/hG5K6fpKoiZolSQ0h2rMT
bcOiIBVMxVUqkYPdzOKTfCSfZboC+4ynwIyCAJMxpPea6Jxa29Kfl+O6L2vWODNOKeagGnXnoWqS
ASXh3og4goaxWNHFYJ6h174un89yTXakAAYPvmIs7h133/aBoPWyo4ZUNkhGRG16NvBQ4EGut4wb
XsD/GO5womVlY58VgdtFfHn38YulcryrT22zX22nBZgzN1jr4XmVJMjNXpZKR0WuVzEbtvgliX6O
QK6e6y71MbMfbtb12PPECaDgbAQnzqfSzZCoOuw64MoNvK6eA/wc09PdPUTmF4rlte+hR8r2gqsj
2sbvKCtVZWVJR8ymMUPXoacEODT66YEPsgqwkPLTUbJXCFqEj4H3KIGMhz+ET3DXv+FGQ9a4NbWv
52Jr5H23zWhjLyyxawj0frB4uBeb4JbEwouzcNEyv3Axssyt5aAvSqjgNjnoyHmS8rOmVYf6Bxkf
kEZKQF5igO3ncTooEu1KqY6nOyFVQY+sYYOqIWGeoLSUqmzA0uBAPuoeS9lRIjoFD5uaJtV8oPO7
oUXfVLrCZAv/t/XPTNkFSkzi5NrNq9YFBU1fu+XjFvCHsHJxjSuMgv3lACzCQJvTlc2qHv5rFOGb
cMIxfpKfsGt9Xa98PpHotYg4XPEfiqQCPGN9CrvpgQMpD2pWGIF2WOeTDQ7N0/5k2Pdrr81VjvyS
1sFKVs6xQSRiDarx88aCRQRGSwPfgMa8+moJI4A2YaAf0RKvv+fZQmEBhhXytlSvwd5l1DdyhvkO
A4HRY8+5PWvq9eAvbHOh+GVNYaXg5OUdhUUZ+LU9KJqwlrarePPCMA+O/QjI7UuLbfVuU850B7cE
JpeJkg2r7qFwljMSnuhs39BhKdnG4vdFhFjQDaAjsZ1CfNGn2YIgTXXYCKXtGIxmqkFGi/+bk2GN
jbcLWC70ayxKp9GX4v08+yYIshA3TAfKX3LsqbtUUA8oTnlY3h1dUYiCy7AXflueAjExiFN4/5wM
2IVq/nD6wQevyR9SST+ZbwwN8vfs94Sjbu+9jK4eKb05TNsZjVveVfgyISL1EO89GdqezLeg5na+
MvLSULnkVhq+2cTtitRsTkZBttavwg2FFhTzHVdA7Xfs/5iOwVZlYQVBwwmd8HT8/8mqqFbD0G8c
+wsFBNjNG7bt38pHECP6cBxXTtNOMfIKH/WyBC8nvQYq0DzpEbtG0Lcb8vXulbGZTh7CjphSILQA
/3HpQhOPXH7rxNEpH+hkyydKUNVTZ55NfMdeXk6NdPXhYNIpfeFnJOd/yKsTvfjSdgjs6eBgHJWx
JvajsPuFgAmbfim4l0QFVmtaZfz4KkY5cNJCBNovghDrz4LEhBDdMXRXbZncce+0ROSN+PdhRQVR
ncq3Hf69kGN9V4rPK02EjPhVh3XtVojzsAmmCxqvgkbBKnAnVqMQHCplI8cIA1jD4TeG/zc+fFsi
W14/a5Ir92ZNurO+WTzc80yiCJ6RmkCLuEvzd1JEsl0dcqkN10NpTrdnHWJdJwUzDkgkFk6AalnA
AgAwCkh7KGyJ+FkFgyZR8Q7klFwkX8SKllyWpRkYohao6F0Uzbfv2u77aNOHHVYltkf0pTjbUfNn
jndcPGk7uAguf8Y6zekJFfrut1TVKxDZJac63uc/bz5fBBixpOVyZ0mvbeOCdtGgXT/RaScrgUgs
qlvyCjYecxMPVH6Qzgac/jIy
`protect end_protected
|
-- NEED RESULT: ARCH00539: Local port/generic visibility test passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00539
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (8)
-- 10.3 (9)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00539(ARCH00539)
-- PKG00539
-- ENT00539_Test_Bench(ARCH00539_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00539 is
generic (G : CHARACTER) ;
port (P1 : inout INTEGER; P2 : out BIT; P3 : in BOOLEAN);
end ENT00539 ;
--
architecture ARCH00539 of ENT00539 is
begin
process ( P1 )
begin
P2 <= transport '1' after 0 ns ;
end process ;
end ARCH00539 ;
--
package PKG00539 is
component PkgCOMP generic (DDD : CHARACTER) ;
port (AAA : inout INTEGER;
BBB : out BIT;
CCC : in BOOLEAN) ;
end component;
end PKG00539 ;
--
use WORK.STANDARD_TYPES.all, WORK.PKG00539 ;
entity ENT00539_Test_Bench is
end ENT00539_Test_Bench ;
architecture ARCH00539_Test_Bench of ENT00539_Test_Bench is
component COMP1 generic (D : CHARACTER) ;
port (A : inout INTEGER := 0 ;
B : out BIT := '0' ;
C : in BOOLEAN := false);
end component;
component COMP2 generic (DD : CHARACTER) ;
port (AA : inout INTEGER := 0 ;
BB : out BIT := '0' ;
CC : in BOOLEAN := false) ;
end component;
signal SA : INTEGER := 0 ;
signal SB : BIT := '0' ;
signal SC : BOOLEAN := false ;
constant SD : CHARACTER := 'D';
signal AA : INTEGER := 0 ;
signal BB : BIT := '0' ;
signal CC : BOOLEAN := false ;
constant DD : CHARACTER := 'D';
signal PSA : INTEGER := 0 ;
signal PSB : BIT := '0' ;
signal PSC : BOOLEAN := false ;
constant PSD : CHARACTER := 'D';
for A1 : COMP1 use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => D )
port map ( A, B, C ) ;
-- names denoting local port or generic are permitted
for others : COMP2 use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => DD )
port map ( AA, BB, CC ) ;
-- names denoting local port or generic are permitted
for all : PKG00539.PkgCOMP use entity WORK.ENT00539 ( ARCH00539 )
generic map ( G => DDD )
port map ( AAA, BBB, CCC ) ;
-- names denoting local port or generic are permitted
begin
A1 : COMP1 generic map (D => SD)
port map (A => SA, B => SB, C => SC) ;
-- names denoting local port or generic are permitted
A2 : COMP2 generic map (DD => DD)
port map (AA => AA, BB => BB, CC => CC) ;
-- names denoting local port or generic are permitted
A3 : PKG00539.PkgCOMP generic map (DDD => PSD)
port map (AAA => PSA, BBB => PSB, CCC => PSC) ;
-- names denoting local port or generic are permitted
process
begin
wait for 10 ns ;
test_report ( "ARCH00539" ,
"Local port/generic visibility test" ,
(SB = '1') and
(BB = '1') and
(PSB = '1') ) ;
wait;
end process ;
end ARCH00539_Test_Bench ;
--
|
-- addr_gen.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- Address generation component for pipelined FFT.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addr_gen is
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
lvl: in std_logic_vector(FFTEXP-2 downto 0); -- iteration level of butterflies
bfno: in std_logic_vector(FFTEXP-2 downto 0); -- butterfly number in current level
addra1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank A
addra2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank A
en_wrta: out std_logic; -- write enable for membank A, high active
addrb1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank B
addrb2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank B
en_wrtb: out std_logic; -- write enable for membank B, high active
addrtf: out std_logic_vector(FFTEXP-2 downto 0)); -- twiddle factor address
end addr_gen;
architecture behavioral of addr_gen is
signal en_wrta_tmp: std_logic := '0';
signal addrtf_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal bfno_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal lvl_tmp: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
begin
-- if lvl is even then en_wrtb is active
-- if lvl is odd then en_wrta is active
en_wrta_tmp <= lvl(0);
bfno_tmp <= '0' & bfno;
lvl_tmp <= '0' & lvl;
addrtf <= addrtf_tmp(FFTEXP-2 downto 0);
process(rst, clk) is
-- reset this component
procedure reset is
begin
addra1 <= (others => '0');
addra2 <= (others => '0');
en_wrta <= '0';
addrb1 <= (others => '0');
addrb2 <= (others => '0');
en_wrtb <= '0';
addrtf_tmp <= (others => '0');
end;
-- calculates the read address
function read_addr(x: std_logic_vector(FFTEXP-1 downto 0);
y: std_logic_vector(FFTEXP-1 downto 0))
return std_logic_vector is
begin
-- rotate left y times
return std_logic_vector(rotate_left(unsigned(x), to_integer(unsigned(y))));
end function;
variable tfidx: natural := 0;
variable j: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
variable j_inc: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
if swrst = RSTDEF then
-- software reset to reinitialize component
-- if needed
reset;
elsif en = '1' then
-- make sure only one write enable is set at a time
en_wrta <= en_wrta_tmp;
en_wrtb <= not en_wrta_tmp;
-- calc twiddle factor address
tfidx := FFTEXP-1-to_integer(unsigned(lvl_tmp));
addrtf_tmp <= (others => '0');
addrtf_tmp(FFTEXP-1 downto tfidx) <= bfno_tmp(FFTEXP-1 downto tfidx);
-- pre compute j for address generation
j := std_logic_vector(shift_left(unsigned(bfno_tmp), 1));
j_inc := std_logic_vector(unsigned(j) + 1);
if en_wrta_tmp = '1' then
-- a is the one to write
-- target write address is simply in order
-- addr1: current bfno * 2
-- addr2: (current bfno * 2) + 1
addra1 <= j;
addra2 <= j_inc;
addrb1 <= read_addr(j, lvl_tmp);
addrb2 <= read_addr(j_inc, lvl_tmp);
else
-- b is the one to write
-- target write address is simply in order
-- addr1: current bfno * 2
-- addr2: (current bfno * 2) + 1
addrb1 <= j;
addrb2 <= j_inc;
addra1 <= read_addr(j, lvl_tmp);
addra2 <= read_addr(j_inc, lvl_tmp);
end if;
end if;
end if;
end process;
end behavioral;
|
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TDC_parser is
port(
clock:in std_logic;
in_data:in std_logic;
dataWORD:in std_logic_vector(31 downto 0);
channel_offset:in std_logic_vector(15 downto 0);
eventID: in std_logic_vector(31 downto 0);
triggerID: in std_logic_vector(31 downto 0);
out_data: out std_logic;
time_isrising:out std_logic;
time_channel: out std_logic_vector(15 downto 0);
time_epoch: out std_logic_vector(27 downto 0);
time_fine: out std_logic_vector(9 downto 0);
time_coasser:out std_logic_vector(10 downto 0)
);
end TDC_parser;
architecture Behavioral of TDC_parser is
signal saved_channel_offset: std_logic_vector(15 downto 0);
signal saved_eventID: std_logic_vector(31 downto 0);
signal saved_triggerID: std_logic_vector(31 downto 0);
signal reset:std_logic:='0';
signal parse:std_logic:='0';
signal offset:integer:=0;
type tdc_state is(IDLE,HEADER_READ,EPOCH_READ);
signal current_tdc_state,next_tdc_state:tdc_state:=IDLE;
begin
state_change:process(reset,in_data)
begin
if rising_edge(clock) then
if reset='1' then
current_tdc_state<=IDLE;
elsif in_data='0' then
current_tdc_state<=next_tdc_state;
end if;
end if;
end process state_change;
trigger_change_check:process(clock)
begin
if rising_edge(clock) then
if(not(saved_eventID=eventID))or
(not(saved_triggerID=triggerID))or
(not(saved_channel_offset=channel_offset))then
reset<='1';
end if;
if(reset='1')and(current_tdc_state=IDLE)then
saved_eventID<=eventID;
saved_triggerID<=triggerID;
saved_channel_offset<=channel_offset;
reset<='0';
end if;
end if;
end process trigger_change_check;
in_data_to_parse:process(in_data, clock)
begin
if rising_edge(clock) then
parse <= in_data;
end if;
end process in_data_to_parse;
state_machine:process(parse, clock)
variable channel:integer:=0;
begin
if rising_edge(clock) then
if parse = '1' then
case current_tdc_state is
when IDLE =>
if(dataWORD(31)='0')and(dataWORD(30)='0')and(dataWORD(29)='1')then
next_tdc_state<=HEADER_READ;
for i in 15 downto 0 loop
if dataWORD(i)='1' then
next_tdc_state<=IDLE;
end if;
end loop;
offset<=0;
for i in 15 downto 0 loop
offset<=offset*2;
if channel_offset(i)='1' then
offset<=offset+1;
end if;
end loop;
end if;
when HEADER_READ =>
if(dataWORD(31)='0')and(dataWORD(30)='1')and(dataWORD(29)='1')then
next_tdc_state<=EPOCH_READ;
end if;
when EPOCH_READ =>
if dataWORD(31)='1' then
for i in 9 downto 0 loop
time_fine(i)<=dataWORD(i+12);
end loop;
for i in 10 downto 0 loop
time_coasser(i)<=dataWORD(i);
end loop;
time_isrising<=dataWORD(11);
channel:=0;
for i in 6 downto 0 loop
channel:=channel*2;
if dataWORD(i+22)='1'then
channel:=channel+1;
end if;
end loop;
channel:=channel+offset;
for i in 0 to 15 loop
if channel mod 2 = 1 then
time_channel(i)<='1';
else
time_channel(i)<='0';
end if;
channel:=channel/2;
end loop;
out_data<='1';
end if;
end case;
if(dataWORD(31)='0')and(dataWORD(30)='1')and(dataWORD(29)='1')then
for i in 27 downto 0 loop
time_epoch(i)<=dataWORD(i);
end loop;
end if;
elsif parse = '0' then
out_data<='0';
end if;
end if;
end process state_machine;
end Behavioral;
|
-- CPU core top-level entity
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu is
generic
(
RESET_ADDRESS: word
);
port
(
clk: in std_logic;
reset_n: in std_logic;
-- Standard Wishbone signals
--
cyc_o: out std_logic;
stb_o: out std_logic;
we_o: out std_logic;
sel_o: out std_logic_vector(3 downto 0);
adr_o: out word;
data_o: out word;
ack_i: in std_logic;
err_i: in std_logic;
data_i: in word;
-- IRQs
--
irq_i: in word;
-- '1' when the CPU executes the 'halt' instruction
--
halt: out std_logic;
-- '1' when the CPU fetches an instruction from the bus
--
ifetch: out std_logic;
-- core regs ports
--
core_reg_read_sel: out core_reg_sel;
core_reg_read_data: in word;
core_reg_write_sel: out core_reg_sel;
core_reg_write_strobe: out std_logic;
core_reg_write_data: out word
);
end luz_cpu;
architecture luz_cpu_arc of luz_cpu is
signal mem_read: std_logic;
signal mem_write: std_logic;
signal mem_bytesel: std_logic_vector(3 downto 0);
signal mem_addr: word;
signal mem_data_out: word;
signal mem_ack: std_logic;
signal mem_data_in: word;
signal reg_sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: word;
signal reg_sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: word;
signal reg_sel_c: std_logic_vector(4 downto 0);
signal reg_c_out: word;
signal reg_sel_y: std_logic_vector(4 downto 0);
signal reg_write_y: std_logic;
signal reg_y_in: word;
signal reg_sel_z: std_logic_vector(4 downto 0);
signal reg_write_z: std_logic;
signal reg_z_in: word;
signal alu_op: cpu_opcode;
signal alu_rs_in: word;
signal alu_rd_in: word;
signal alu_rt_in: word;
signal alu_imm_in: word;
signal alu_output_a: word;
signal alu_output_b: word;
signal pc_in: word;
signal pc_out: word;
signal pc_write: std_logic;
begin
controller_map: entity work.controller(controller_arc)
port map
(
clk => clk,
reset_n => reset_n,
mem_read => mem_read,
mem_write => mem_write,
mem_bytesel => mem_bytesel,
mem_addr => mem_addr,
mem_data_out => mem_data_out,
mem_ack => mem_ack,
mem_data_in => mem_data_in,
reg_sel_a => reg_sel_a,
reg_a_out => reg_a_out,
reg_sel_b => reg_sel_b,
reg_b_out => reg_b_out,
reg_sel_c => reg_sel_c,
reg_c_out => reg_c_out,
reg_sel_y => reg_sel_y,
reg_write_y => reg_write_y,
reg_y_in => reg_y_in,
reg_sel_z => reg_sel_z,
reg_write_z => reg_write_z,
reg_z_in => reg_z_in,
alu_op => alu_op,
alu_rs_in => alu_rs_in,
alu_rd_in => alu_rd_in,
alu_rt_in => alu_rt_in,
alu_imm_in => alu_imm_in,
alu_output_a => alu_output_a,
alu_output_b => alu_output_b,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
-- Bridging the controller memory interface to Wishbone
--
mem_ack <= ack_i;
mem_data_in <= data_i;
cyc_o <= mem_write or mem_read;
stb_o <= mem_write or mem_read;
we_o <= mem_write;
sel_o <= mem_bytesel;
adr_o <= mem_addr;
data_o <= mem_data_out;
alu_map: entity work.alu(alu_arc)
port map
(
clk => clk,
reset_n => reset_n,
op => alu_op,
rs_in => alu_rs_in,
rt_in => alu_rt_in,
rd_in => alu_rd_in,
imm_in => alu_imm_in,
output_a => alu_output_a,
output_b => alu_output_b
);
gp_registers_map: entity work.registers(registers_arc)
generic map
(
NREGS_LOG2 => 5
)
port map
(
clk => clk,
reset_n => reset_n,
sel_a => reg_sel_a,
reg_a_out => reg_a_out,
sel_b => reg_sel_b,
reg_b_out => reg_b_out,
sel_c => reg_sel_c,
reg_c_out => reg_c_out,
sel_y => reg_sel_y,
write_y => reg_write_y,
reg_y_in => reg_y_in,
sel_z => reg_sel_z,
write_z => reg_write_z,
reg_z_in => reg_z_in
);
pc_map: entity work.program_counter(program_counter_arc)
generic map
(
INIT => RESET_ADDRESS
)
port map
(
clk => clk,
reset_n => reset_n,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
end;
|
-- CPU core top-level entity
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu is
generic
(
RESET_ADDRESS: word
);
port
(
clk: in std_logic;
reset_n: in std_logic;
-- Standard Wishbone signals
--
cyc_o: out std_logic;
stb_o: out std_logic;
we_o: out std_logic;
sel_o: out std_logic_vector(3 downto 0);
adr_o: out word;
data_o: out word;
ack_i: in std_logic;
err_i: in std_logic;
data_i: in word;
-- IRQs
--
irq_i: in word;
-- '1' when the CPU executes the 'halt' instruction
--
halt: out std_logic;
-- '1' when the CPU fetches an instruction from the bus
--
ifetch: out std_logic;
-- core regs ports
--
core_reg_read_sel: out core_reg_sel;
core_reg_read_data: in word;
core_reg_write_sel: out core_reg_sel;
core_reg_write_strobe: out std_logic;
core_reg_write_data: out word
);
end luz_cpu;
architecture luz_cpu_arc of luz_cpu is
signal mem_read: std_logic;
signal mem_write: std_logic;
signal mem_bytesel: std_logic_vector(3 downto 0);
signal mem_addr: word;
signal mem_data_out: word;
signal mem_ack: std_logic;
signal mem_data_in: word;
signal reg_sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: word;
signal reg_sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: word;
signal reg_sel_c: std_logic_vector(4 downto 0);
signal reg_c_out: word;
signal reg_sel_y: std_logic_vector(4 downto 0);
signal reg_write_y: std_logic;
signal reg_y_in: word;
signal reg_sel_z: std_logic_vector(4 downto 0);
signal reg_write_z: std_logic;
signal reg_z_in: word;
signal alu_op: cpu_opcode;
signal alu_rs_in: word;
signal alu_rd_in: word;
signal alu_rt_in: word;
signal alu_imm_in: word;
signal alu_output_a: word;
signal alu_output_b: word;
signal pc_in: word;
signal pc_out: word;
signal pc_write: std_logic;
begin
controller_map: entity work.controller(controller_arc)
port map
(
clk => clk,
reset_n => reset_n,
mem_read => mem_read,
mem_write => mem_write,
mem_bytesel => mem_bytesel,
mem_addr => mem_addr,
mem_data_out => mem_data_out,
mem_ack => mem_ack,
mem_data_in => mem_data_in,
reg_sel_a => reg_sel_a,
reg_a_out => reg_a_out,
reg_sel_b => reg_sel_b,
reg_b_out => reg_b_out,
reg_sel_c => reg_sel_c,
reg_c_out => reg_c_out,
reg_sel_y => reg_sel_y,
reg_write_y => reg_write_y,
reg_y_in => reg_y_in,
reg_sel_z => reg_sel_z,
reg_write_z => reg_write_z,
reg_z_in => reg_z_in,
alu_op => alu_op,
alu_rs_in => alu_rs_in,
alu_rd_in => alu_rd_in,
alu_rt_in => alu_rt_in,
alu_imm_in => alu_imm_in,
alu_output_a => alu_output_a,
alu_output_b => alu_output_b,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
-- Bridging the controller memory interface to Wishbone
--
mem_ack <= ack_i;
mem_data_in <= data_i;
cyc_o <= mem_write or mem_read;
stb_o <= mem_write or mem_read;
we_o <= mem_write;
sel_o <= mem_bytesel;
adr_o <= mem_addr;
data_o <= mem_data_out;
alu_map: entity work.alu(alu_arc)
port map
(
clk => clk,
reset_n => reset_n,
op => alu_op,
rs_in => alu_rs_in,
rt_in => alu_rt_in,
rd_in => alu_rd_in,
imm_in => alu_imm_in,
output_a => alu_output_a,
output_b => alu_output_b
);
gp_registers_map: entity work.registers(registers_arc)
generic map
(
NREGS_LOG2 => 5
)
port map
(
clk => clk,
reset_n => reset_n,
sel_a => reg_sel_a,
reg_a_out => reg_a_out,
sel_b => reg_sel_b,
reg_b_out => reg_b_out,
sel_c => reg_sel_c,
reg_c_out => reg_c_out,
sel_y => reg_sel_y,
write_y => reg_write_y,
reg_y_in => reg_y_in,
sel_z => reg_sel_z,
write_z => reg_write_z,
reg_z_in => reg_z_in
);
pc_map: entity work.program_counter(program_counter_arc)
generic map
(
INIT => RESET_ADDRESS
)
port map
(
clk => clk,
reset_n => reset_n,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_tb IS
END ENTITY;
ARCHITECTURE RAM_tb_ARCH OF RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_synth_inst:ENTITY work.RAM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_tb IS
END ENTITY;
ARCHITECTURE RAM_tb_ARCH OF RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_synth_inst:ENTITY work.RAM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--memData_inst : memData PORT MAP (
-- address => address_sig,
-- clock => clock_sig,
-- data => data_sig,
-- wren => wren_sig,
-- q => q_sig
-- );
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
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