content stringlengths 1 1.04M ⌀ |
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:40:41 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair42";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair43";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair54";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair54";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_2\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_3\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 12 downto 3 );
signal \save_init_bram_addr_ld[12]_i_6_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_2\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_3\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_5\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_6\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair55";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\save_init_bram_addr_ld_reg[12]_2\ <= \^save_init_bram_addr_ld_reg[12]_2\;
\save_init_bram_addr_ld_reg[12]_3\ <= \^save_init_bram_addr_ld_reg[12]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => D(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[12]_1\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[12]_2\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[12]_3\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[12]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[12]_2\
);
\save_init_bram_addr_ld[12]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[12]_3\
);
\save_init_bram_addr_ld[12]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0\,
O => \save_init_bram_addr_ld[12]_i_6_n_0\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \save_init_bram_addr_ld[12]_i_6_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => SR(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => SR(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => save_init_bram_addr_ld(12),
R => SR(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => SR(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => SR(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => SR(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => SR(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => SR(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => SR(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => SR(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2__0_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2__0_n_0\,
I4 => \wrap_burst_total[1]_i_3__0_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2__0_n_0\
);
\wrap_burst_total[1]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => SR(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => SR(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[12]_1\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
axi_araddr_full : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[12]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[12]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^save_init_bram_addr_ld_reg[12]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_1\ : label is "soft_lutpair0";
begin
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[12]_0\(0) <= \^save_init_bram_addr_ld_reg[12]_0\(0);
\save_init_bram_addr_ld_reg[12]_1\ <= \^save_init_bram_addr_ld_reg[12]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => D(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(8),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => D(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I4 => Q(1),
I5 => Q(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => Q(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
O => D(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_1\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => D(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => D(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => D(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => D(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => D(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(5),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => D(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(6),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => D(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(3),
I1 => Q(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => Q(2),
I3 => Q(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => Q(3),
I3 => Q(2),
I4 => Q(1),
I5 => Q(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[12]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[12]_1\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[12]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^save_init_bram_addr_ld_reg[12]_0\(0)
);
\save_init_bram_addr_ld[12]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[12]_i_3__0_n_0\
);
\save_init_bram_addr_ld[12]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => Q(0),
I2 => Q(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[12]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^save_init_bram_addr_ld_reg[12]_0\(0),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20CF000000000000"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_arsize_pipe(0),
I2 => axi_araddr_full,
I3 => \^wrap_burst_total_reg[0]_1\,
I4 => \^wrap_burst_total_reg[0]_3\,
I5 => \^wrap_burst_total_reg[0]_2\,
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000D580"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => s_axi_arlen(2),
I4 => \wrap_burst_total[2]_i_2_n_0\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF5F5F3FFFFFFF"
)
port map (
I0 => s_axi_arlen(3),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I2 => \^wrap_burst_total_reg[0]_3\,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I4 => axi_araddr_full,
I5 => s_axi_arlen(1),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_arready : out STD_LOGIC;
bram_addr_b : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_5_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld_en : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_10_n_0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of last_bram_addr_i_6 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of last_bram_addr_i_8 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair11";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
bram_addr_b(0) <= \^bram_addr_b\(0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_23,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_5_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_23,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_20,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => I_WRAP_BRST_n_7,
I2 => \^bram_addr_b\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_10,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_9,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_b\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_11,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
port map (
D(9) => I_WRAP_BRST_n_9,
D(8) => I_WRAP_BRST_n_10,
D(7) => I_WRAP_BRST_n_11,
D(6) => I_WRAP_BRST_n_12,
D(5) => I_WRAP_BRST_n_13,
D(4) => I_WRAP_BRST_n_14,
D(3) => I_WRAP_BRST_n_15,
D(2) => I_WRAP_BRST_n_16,
D(1) => I_WRAP_BRST_n_17,
D(0) => I_WRAP_BRST_n_18,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_20,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_24,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_22,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[12]_0\(0) => I_WRAP_BRST_n_21,
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_23,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_8_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"02000004FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_6_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_24,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_24,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_4,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_3,
I5 => I_WRAP_BRST_n_2,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_25,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_24,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_0,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"3330131003001310"
)
port map (
I0 => \rd_data_sm_cs[2]_i_5_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => axi_rd_burst_two_reg_n_0,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_3,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_7_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_5,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_9_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_7_n_0,
I2 => s_axi_aresetn,
I3 => last_bram_addr_i_3_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FE7D0000FE7DFE7D"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF57550000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => last_bram_addr_i_4_n_0,
I3 => last_bram_addr_i_5_n_0,
I4 => last_bram_addr_i_6_n_0,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr0
);
last_bram_addr_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_10_n_0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AABFFFBFFFBFFFBF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => last_bram_addr_i_8_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => p_0_in13_in,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFDFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_9_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => last_bram_addr_i_10_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_25,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBBABB00"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => pend_rd_op_i_5_n_0,
I3 => bram_addr_ld_en,
I4 => pend_rd_op_i_7_n_0,
I5 => I_WRAP_BRST_n_25,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_25,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_22,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_24,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_24,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCCBBBB3000B888"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 10 to 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair63";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair61";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair60";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(10 downto 0) <= \^bram_addr_a\(10 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_17,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_16,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_18,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_18,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_17,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_17,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_14,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^bram_addr_a\(10),
I1 => bram_addr_ld_en_mod,
I2 => bram_addr_ld(10),
I3 => I_WRAP_BRST_n_0,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_4,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_3,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0\,
Q => \^bram_addr_a\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_6,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_5,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
port map (
D(9) => I_WRAP_BRST_n_3,
D(8) => I_WRAP_BRST_n_4,
D(7) => I_WRAP_BRST_n_5,
D(6) => I_WRAP_BRST_n_6,
D(5) => I_WRAP_BRST_n_7,
D(4) => I_WRAP_BRST_n_8,
D(3) => I_WRAP_BRST_n_9,
D(2) => I_WRAP_BRST_n_10,
D(1) => I_WRAP_BRST_n_11,
D(0) => I_WRAP_BRST_n_12,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_14,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_19,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_20,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[12]_0\(0) => bram_addr_ld(10),
\save_init_bram_addr_ld_reg[12]_1\ => I_WRAP_BRST_n_16,
\save_init_bram_addr_ld_reg[12]_2\ => I_WRAP_BRST_n_17,
\save_init_bram_addr_ld_reg[12]_3\ => I_WRAP_BRST_n_18,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5000303050003000"
)
port map (
I0 => axi_awlen_pipe(3),
I1 => s_axi_awlen(3),
I2 => curr_awlen_reg_1_or_2_i_2_n_0,
I3 => curr_awlen_reg_1_or_2_i_3_n_0,
I4 => axi_awaddr_full,
I5 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => axi_awlen_pipe(4),
I1 => axi_awlen_pipe(7),
I2 => axi_awlen_pipe(6),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(5),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_19,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_20,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi : entity is "full_axi";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(9 downto 0) => bram_addr_b(9 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_b(0) => bram_addr_b(10),
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
port map (
bram_addr_a(10 downto 0) => bram_addr_a(10 downto 0),
bram_addr_b(10 downto 0) => bram_addr_b(10 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(12 downto 2) <= \^bram_addr_a\(12 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(12 downto 2) <= \^bram_addr_b\(12 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
port map (
bram_addr_a(10 downto 0) => \^bram_addr_a\(12 downto 2),
bram_addr_b(10 downto 0) => \^bram_addr_b\(12 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(10 downto 0) => s_axi_araddr(12 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(12 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2.1";
end zqynq_lab_1_design_axi_bram_ctrl_0_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0 is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 11;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 2048;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 13;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
port map (
bram_addr_a(12 downto 0) => bram_addr_a(12 downto 0),
bram_addr_b(12 downto 0) => bram_addr_b(12 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(12 downto 0) => s_axi_araddr(12 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(12 downto 0) => s_axi_awaddr(12 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- ROM package
library ieee;
use ieee.std_logic_1164.all;
package trap_rom is
constant w:integer:= 32; --width of ROM
constant l:integer:= 25; --lenght of ROM
subtype rom_word is std_logic_vector(w-1 downto 0);
type rom_table is array (0 to l-1) of rom_word;
constant rom_image:rom_table:=rom_table'(
"00000000000000000000000000000000",
"11100100001000000000000000000000",
"10110100010000010000001100000000",
"01001100010000000000000000001101",
"10110100010000010000001000000000",
"01100000011000000001000000000000",
"10001100100000000000000000000000",
"00000000100001000001100000000000",
"10011100100000000000000000000000",
"10110100010000010000000100000000",
"01100000011000000001000000000000",
"10001100100000000000000000000001",
"00000000100001000001100000000000",
"10011100100000000000000000000000",
"11110100000000000000001100000000",
"01111100000111110000000000000001",
"10011100000000000000000000000000",
"10011100000000000000000000000001",
"00000100001000001111111111111111",
"00001000010000000111111111111111",
"11000000001000010001000000000000",
"00010000010000010000100000000000",
"11111111111111111111111111111111",
"01001100000000001111111111111011",
"00000000000000000000000000000000");
end;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 4.5e-07
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 7e-07,
W => Wsrc_2,
Wsrc_2init => 2.085e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 7e-07,
W => Wsrc_2,
Wsrc_2init => 2.085e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.5e-07,
W => Wcm_1,
Wcm_1init => 1.365e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.5e-07,
W => Wcmout_1,
Wcmout_1init => 7.995e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 6.9e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 6.9e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- ML505
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- ML505
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for di_tnr
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Version: Revision: 1.3 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity di_tnr
--
entity di_tnr is
-- Generics:
-- No Generated Generics for Entity di_tnr
-- Generated Port Declaration:
port(
-- Generated Port for Entity di_tnr
af_c1_o : out std_ulogic;
af_p0_i : in std_ulogic;
al_c1_o : out std_ulogic;
al_p0_i : in std_ulogic;
ap_c1_o : out std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
c0_p0_i : in std_ulogic_vector(7 downto 0);
c0_p0_o : out std_ulogic_vector(7 downto 0);
c1_p1_i : in std_ulogic_vector(7 downto 0);
c1_p1_o : out std_ulogic_vector(7 downto 0);
cblack_p_i : in std_ulogic_vector(7 downto 0);
clkin : in std_ulogic;
field_p0_i : in std_ulogic;
fieldc_c1_o : out std_ulogic;
fieldy0_c1_o : out std_ulogic;
fieldy1_c1_o : out std_ulogic;
frafiesel_iic_i : in std_ulogic;
hsync_c1_o : out std_ulogic;
hsync_p0_i : in std_ulogic;
nr_dis_c_i : in std_ulogic;
nron_iic_i : in std_ulogic;
req_p1_o : out std_ulogic;
tnrabs_iic_i : in std_ulogic;
tnrclc_iic_i : in std_ulogic_vector(3 downto 0);
tnrcly_iic_i : in std_ulogic_vector(3 downto 0);
tnrmd4y_iic_i : in std_ulogic;
tnrmdnr4c_iic_i : in std_ulogic;
tnrnr4y_iic_i : in std_ulogic;
tnrs0c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs0y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs1c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs1y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs2c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs2y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs3c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs3y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs4c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs4y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs5c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs5y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs6c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs6y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs7c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs7y_iic_i : in std_ulogic_vector(3 downto 0);
tnrsel_iic_i : in std_ulogic;
tnrssc_iic_i : in std_ulogic_vector(3 downto 0);
tnrssy_iic_i : in std_ulogic_vector(3 downto 0);
uen_c1_o : out std_ulogic;
uen_p0_i : in std_ulogic;
vsync_c1_o : out std_ulogic;
vsync_p0_i : in std_ulogic;
y0_p0_i : in std_ulogic_vector(7 downto 0);
y0_p0_o : out std_ulogic_vector(7 downto 0);
y1_p1_i : in std_ulogic_vector(7 downto 0);
y1_p1_o : out std_ulogic_vector(7 downto 0);
y2_p1_i : in std_ulogic_vector(7 downto 0);
y2_p1_o : out std_ulogic_vector(7 downto 0);
yblack_p_i : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity di_tnr
);
end di_tnr;
--
-- End of Generated Entity di_tnr
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
entity E3 is
end entity;
architecture A of E3 is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
-- partially constrained array -> constrained outer array (vector)
subtype P2 is A(15 downto 0)(open);
signal S2 : P2(open)(7 downto 0); -- finally constraining the element size line 14
begin
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10976)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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w6VCfz/Wq0aoj9wNIgenlqOjs3dGoAxkCyRBPmO9mFU=
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6502 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6502 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"A2";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"BD";
when x"003" => DATA <= x"00";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"9D";
when x"006" => DATA <= x"00";
when x"007" => DATA <= x"FF";
when x"008" => DATA <= x"CA";
when x"009" => DATA <= x"D0";
when x"00A" => DATA <= x"F7";
when x"00B" => DATA <= x"A2";
when x"00C" => DATA <= x"36";
when x"00D" => DATA <= x"BD";
when x"00E" => DATA <= x"80";
when x"00F" => DATA <= x"FF";
when x"010" => DATA <= x"9D";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"02";
when x"013" => DATA <= x"CA";
when x"014" => DATA <= x"10";
when x"015" => DATA <= x"F7";
when x"016" => DATA <= x"9A";
when x"017" => DATA <= x"A2";
when x"018" => DATA <= x"F0";
when x"019" => DATA <= x"BD";
when x"01A" => DATA <= x"FF";
when x"01B" => DATA <= x"FD";
when x"01C" => DATA <= x"9D";
when x"01D" => DATA <= x"FF";
when x"01E" => DATA <= x"FD";
when x"01F" => DATA <= x"CA";
when x"020" => DATA <= x"D0";
when x"021" => DATA <= x"F7";
when x"022" => DATA <= x"A0";
when x"023" => DATA <= x"00";
when x"024" => DATA <= x"84";
when x"025" => DATA <= x"F8";
when x"026" => DATA <= x"A9";
when x"027" => DATA <= x"F8";
when x"028" => DATA <= x"85";
when x"029" => DATA <= x"F9";
when x"02A" => DATA <= x"B1";
when x"02B" => DATA <= x"F8";
when x"02C" => DATA <= x"91";
when x"02D" => DATA <= x"F8";
when x"02E" => DATA <= x"C8";
when x"02F" => DATA <= x"D0";
when x"030" => DATA <= x"F9";
when x"031" => DATA <= x"E6";
when x"032" => DATA <= x"F9";
when x"033" => DATA <= x"A5";
when x"034" => DATA <= x"F9";
when x"035" => DATA <= x"C9";
when x"036" => DATA <= x"FE";
when x"037" => DATA <= x"D0";
when x"038" => DATA <= x"F1";
when x"039" => DATA <= x"A2";
when x"03A" => DATA <= x"10";
when x"03B" => DATA <= x"BD";
when x"03C" => DATA <= x"59";
when x"03D" => DATA <= x"F8";
when x"03E" => DATA <= x"9D";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"01";
when x"041" => DATA <= x"CA";
when x"042" => DATA <= x"10";
when x"043" => DATA <= x"F7";
when x"044" => DATA <= x"A5";
when x"045" => DATA <= x"EE";
when x"046" => DATA <= x"85";
when x"047" => DATA <= x"F6";
when x"048" => DATA <= x"A5";
when x"049" => DATA <= x"EF";
when x"04A" => DATA <= x"85";
when x"04B" => DATA <= x"F7";
when x"04C" => DATA <= x"A9";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"85";
when x"04F" => DATA <= x"FF";
when x"050" => DATA <= x"85";
when x"051" => DATA <= x"F2";
when x"052" => DATA <= x"A9";
when x"053" => DATA <= x"F8";
when x"054" => DATA <= x"85";
when x"055" => DATA <= x"F3";
when x"056" => DATA <= x"4C";
when x"057" => DATA <= x"00";
when x"058" => DATA <= x"01";
when x"059" => DATA <= x"AD";
when x"05A" => DATA <= x"F8";
when x"05B" => DATA <= x"FE";
when x"05C" => DATA <= x"58";
when x"05D" => DATA <= x"4C";
when x"05E" => DATA <= x"60";
when x"05F" => DATA <= x"F8";
when x"060" => DATA <= x"20";
when x"061" => DATA <= x"98";
when x"062" => DATA <= x"FE";
when x"063" => DATA <= x"0A";
when x"064" => DATA <= x"41";
when x"065" => DATA <= x"63";
when x"066" => DATA <= x"6F";
when x"067" => DATA <= x"72";
when x"068" => DATA <= x"6E";
when x"069" => DATA <= x"20";
when x"06A" => DATA <= x"54";
when x"06B" => DATA <= x"55";
when x"06C" => DATA <= x"42";
when x"06D" => DATA <= x"45";
when x"06E" => DATA <= x"20";
when x"06F" => DATA <= x"36";
when x"070" => DATA <= x"35";
when x"071" => DATA <= x"30";
when x"072" => DATA <= x"32";
when x"073" => DATA <= x"20";
when x"074" => DATA <= x"36";
when x"075" => DATA <= x"34";
when x"076" => DATA <= x"4B";
when x"077" => DATA <= x"0A";
when x"078" => DATA <= x"0A";
when x"079" => DATA <= x"0D";
when x"07A" => DATA <= x"00";
when x"07B" => DATA <= x"EA";
when x"07C" => DATA <= x"A9";
when x"07D" => DATA <= x"8D";
when x"07E" => DATA <= x"8D";
when x"07F" => DATA <= x"5E";
when x"080" => DATA <= x"F8";
when x"081" => DATA <= x"A9";
when x"082" => DATA <= x"F8";
when x"083" => DATA <= x"8D";
when x"084" => DATA <= x"5F";
when x"085" => DATA <= x"F8";
when x"086" => DATA <= x"20";
when x"087" => DATA <= x"75";
when x"088" => DATA <= x"F9";
when x"089" => DATA <= x"C9";
when x"08A" => DATA <= x"80";
when x"08B" => DATA <= x"F0";
when x"08C" => DATA <= x"28";
when x"08D" => DATA <= x"A9";
when x"08E" => DATA <= x"2A";
when x"08F" => DATA <= x"20";
when x"090" => DATA <= x"EE";
when x"091" => DATA <= x"FF";
when x"092" => DATA <= x"A2";
when x"093" => DATA <= x"5D";
when x"094" => DATA <= x"A0";
when x"095" => DATA <= x"F9";
when x"096" => DATA <= x"A9";
when x"097" => DATA <= x"00";
when x"098" => DATA <= x"20";
when x"099" => DATA <= x"F1";
when x"09A" => DATA <= x"FF";
when x"09B" => DATA <= x"B0";
when x"09C" => DATA <= x"0A";
when x"09D" => DATA <= x"A2";
when x"09E" => DATA <= x"36";
when x"09F" => DATA <= x"A0";
when x"0A0" => DATA <= x"02";
when x"0A1" => DATA <= x"20";
when x"0A2" => DATA <= x"F7";
when x"0A3" => DATA <= x"FF";
when x"0A4" => DATA <= x"4C";
when x"0A5" => DATA <= x"8D";
when x"0A6" => DATA <= x"F8";
when x"0A7" => DATA <= x"A9";
when x"0A8" => DATA <= x"7E";
when x"0A9" => DATA <= x"20";
when x"0AA" => DATA <= x"F4";
when x"0AB" => DATA <= x"FF";
when x"0AC" => DATA <= x"00";
when x"0AD" => DATA <= x"11";
when x"0AE" => DATA <= x"45";
when x"0AF" => DATA <= x"73";
when x"0B0" => DATA <= x"63";
when x"0B1" => DATA <= x"61";
when x"0B2" => DATA <= x"70";
when x"0B3" => DATA <= x"65";
when x"0B4" => DATA <= x"00";
when x"0B5" => DATA <= x"A5";
when x"0B6" => DATA <= x"F6";
when x"0B7" => DATA <= x"85";
when x"0B8" => DATA <= x"EE";
when x"0B9" => DATA <= x"85";
when x"0BA" => DATA <= x"F2";
when x"0BB" => DATA <= x"A5";
when x"0BC" => DATA <= x"F7";
when x"0BD" => DATA <= x"85";
when x"0BE" => DATA <= x"EF";
when x"0BF" => DATA <= x"85";
when x"0C0" => DATA <= x"F3";
when x"0C1" => DATA <= x"A0";
when x"0C2" => DATA <= x"07";
when x"0C3" => DATA <= x"B1";
when x"0C4" => DATA <= x"EE";
when x"0C5" => DATA <= x"D8";
when x"0C6" => DATA <= x"18";
when x"0C7" => DATA <= x"65";
when x"0C8" => DATA <= x"EE";
when x"0C9" => DATA <= x"85";
when x"0CA" => DATA <= x"FD";
when x"0CB" => DATA <= x"A9";
when x"0CC" => DATA <= x"00";
when x"0CD" => DATA <= x"65";
when x"0CE" => DATA <= x"EF";
when x"0CF" => DATA <= x"85";
when x"0D0" => DATA <= x"FE";
when x"0D1" => DATA <= x"A0";
when x"0D2" => DATA <= x"00";
when x"0D3" => DATA <= x"B1";
when x"0D4" => DATA <= x"FD";
when x"0D5" => DATA <= x"D0";
when x"0D6" => DATA <= x"23";
when x"0D7" => DATA <= x"C8";
when x"0D8" => DATA <= x"B1";
when x"0D9" => DATA <= x"FD";
when x"0DA" => DATA <= x"C9";
when x"0DB" => DATA <= x"28";
when x"0DC" => DATA <= x"D0";
when x"0DD" => DATA <= x"1C";
when x"0DE" => DATA <= x"C8";
when x"0DF" => DATA <= x"B1";
when x"0E0" => DATA <= x"FD";
when x"0E1" => DATA <= x"C9";
when x"0E2" => DATA <= x"43";
when x"0E3" => DATA <= x"D0";
when x"0E4" => DATA <= x"15";
when x"0E5" => DATA <= x"C8";
when x"0E6" => DATA <= x"B1";
when x"0E7" => DATA <= x"FD";
when x"0E8" => DATA <= x"C9";
when x"0E9" => DATA <= x"29";
when x"0EA" => DATA <= x"D0";
when x"0EB" => DATA <= x"0E";
when x"0EC" => DATA <= x"A0";
when x"0ED" => DATA <= x"06";
when x"0EE" => DATA <= x"B1";
when x"0EF" => DATA <= x"EE";
when x"0F0" => DATA <= x"29";
when x"0F1" => DATA <= x"4F";
when x"0F2" => DATA <= x"C9";
when x"0F3" => DATA <= x"40";
when x"0F4" => DATA <= x"90";
when x"0F5" => DATA <= x"09";
when x"0F6" => DATA <= x"29";
when x"0F7" => DATA <= x"0D";
when x"0F8" => DATA <= x"D0";
when x"0F9" => DATA <= x"28";
when x"0FA" => DATA <= x"A9";
when x"0FB" => DATA <= x"01";
when x"0FC" => DATA <= x"6C";
when x"0FD" => DATA <= x"F2";
when x"0FE" => DATA <= x"00";
when x"0FF" => DATA <= x"A9";
when x"100" => DATA <= x"45";
when x"101" => DATA <= x"8D";
when x"102" => DATA <= x"02";
when x"103" => DATA <= x"02";
when x"104" => DATA <= x"A9";
when x"105" => DATA <= x"F9";
when x"106" => DATA <= x"8D";
when x"107" => DATA <= x"03";
when x"108" => DATA <= x"02";
when x"109" => DATA <= x"00";
when x"10A" => DATA <= x"00";
when x"10B" => DATA <= x"54";
when x"10C" => DATA <= x"68";
when x"10D" => DATA <= x"69";
when x"10E" => DATA <= x"73";
when x"10F" => DATA <= x"20";
when x"110" => DATA <= x"69";
when x"111" => DATA <= x"73";
when x"112" => DATA <= x"20";
when x"113" => DATA <= x"6E";
when x"114" => DATA <= x"6F";
when x"115" => DATA <= x"74";
when x"116" => DATA <= x"20";
when x"117" => DATA <= x"61";
when x"118" => DATA <= x"20";
when x"119" => DATA <= x"6C";
when x"11A" => DATA <= x"61";
when x"11B" => DATA <= x"6E";
when x"11C" => DATA <= x"67";
when x"11D" => DATA <= x"75";
when x"11E" => DATA <= x"61";
when x"11F" => DATA <= x"67";
when x"120" => DATA <= x"65";
when x"121" => DATA <= x"00";
when x"122" => DATA <= x"A9";
when x"123" => DATA <= x"45";
when x"124" => DATA <= x"8D";
when x"125" => DATA <= x"02";
when x"126" => DATA <= x"02";
when x"127" => DATA <= x"A9";
when x"128" => DATA <= x"F9";
when x"129" => DATA <= x"8D";
when x"12A" => DATA <= x"03";
when x"12B" => DATA <= x"02";
when x"12C" => DATA <= x"00";
when x"12D" => DATA <= x"00";
when x"12E" => DATA <= x"49";
when x"12F" => DATA <= x"20";
when x"130" => DATA <= x"63";
when x"131" => DATA <= x"61";
when x"132" => DATA <= x"6E";
when x"133" => DATA <= x"6E";
when x"134" => DATA <= x"6F";
when x"135" => DATA <= x"74";
when x"136" => DATA <= x"20";
when x"137" => DATA <= x"72";
when x"138" => DATA <= x"75";
when x"139" => DATA <= x"6E";
when x"13A" => DATA <= x"20";
when x"13B" => DATA <= x"74";
when x"13C" => DATA <= x"68";
when x"13D" => DATA <= x"69";
when x"13E" => DATA <= x"73";
when x"13F" => DATA <= x"20";
when x"140" => DATA <= x"63";
when x"141" => DATA <= x"6F";
when x"142" => DATA <= x"64";
when x"143" => DATA <= x"65";
when x"144" => DATA <= x"00";
when x"145" => DATA <= x"A2";
when x"146" => DATA <= x"FF";
when x"147" => DATA <= x"9A";
when x"148" => DATA <= x"20";
when x"149" => DATA <= x"E7";
when x"14A" => DATA <= x"FF";
when x"14B" => DATA <= x"A0";
when x"14C" => DATA <= x"01";
when x"14D" => DATA <= x"B1";
when x"14E" => DATA <= x"FD";
when x"14F" => DATA <= x"F0";
when x"150" => DATA <= x"06";
when x"151" => DATA <= x"20";
when x"152" => DATA <= x"EE";
when x"153" => DATA <= x"FF";
when x"154" => DATA <= x"C8";
when x"155" => DATA <= x"D0";
when x"156" => DATA <= x"F6";
when x"157" => DATA <= x"20";
when x"158" => DATA <= x"E7";
when x"159" => DATA <= x"FF";
when x"15A" => DATA <= x"4C";
when x"15B" => DATA <= x"8D";
when x"15C" => DATA <= x"F8";
when x"15D" => DATA <= x"36";
when x"15E" => DATA <= x"02";
when x"15F" => DATA <= x"CA";
when x"160" => DATA <= x"20";
when x"161" => DATA <= x"FF";
when x"162" => DATA <= x"2C";
when x"163" => DATA <= x"F8";
when x"164" => DATA <= x"FE";
when x"165" => DATA <= x"EA";
when x"166" => DATA <= x"50";
when x"167" => DATA <= x"FA";
when x"168" => DATA <= x"8D";
when x"169" => DATA <= x"F9";
when x"16A" => DATA <= x"FE";
when x"16B" => DATA <= x"60";
when x"16C" => DATA <= x"A9";
when x"16D" => DATA <= x"00";
when x"16E" => DATA <= x"20";
when x"16F" => DATA <= x"4A";
when x"170" => DATA <= x"FC";
when x"171" => DATA <= x"20";
when x"172" => DATA <= x"75";
when x"173" => DATA <= x"F9";
when x"174" => DATA <= x"0A";
when x"175" => DATA <= x"2C";
when x"176" => DATA <= x"FA";
when x"177" => DATA <= x"FE";
when x"178" => DATA <= x"10";
when x"179" => DATA <= x"FB";
when x"17A" => DATA <= x"AD";
when x"17B" => DATA <= x"FB";
when x"17C" => DATA <= x"FE";
when x"17D" => DATA <= x"60";
when x"17E" => DATA <= x"C8";
when x"17F" => DATA <= x"B1";
when x"180" => DATA <= x"F8";
when x"181" => DATA <= x"C9";
when x"182" => DATA <= x"20";
when x"183" => DATA <= x"F0";
when x"184" => DATA <= x"F9";
when x"185" => DATA <= x"60";
when x"186" => DATA <= x"A2";
when x"187" => DATA <= x"00";
when x"188" => DATA <= x"86";
when x"189" => DATA <= x"F0";
when x"18A" => DATA <= x"86";
when x"18B" => DATA <= x"F1";
when x"18C" => DATA <= x"B1";
when x"18D" => DATA <= x"F8";
when x"18E" => DATA <= x"C9";
when x"18F" => DATA <= x"30";
when x"190" => DATA <= x"90";
when x"191" => DATA <= x"1F";
when x"192" => DATA <= x"C9";
when x"193" => DATA <= x"3A";
when x"194" => DATA <= x"90";
when x"195" => DATA <= x"0A";
when x"196" => DATA <= x"29";
when x"197" => DATA <= x"DF";
when x"198" => DATA <= x"E9";
when x"199" => DATA <= x"07";
when x"19A" => DATA <= x"90";
when x"19B" => DATA <= x"15";
when x"19C" => DATA <= x"C9";
when x"19D" => DATA <= x"40";
when x"19E" => DATA <= x"B0";
when x"19F" => DATA <= x"11";
when x"1A0" => DATA <= x"0A";
when x"1A1" => DATA <= x"0A";
when x"1A2" => DATA <= x"0A";
when x"1A3" => DATA <= x"0A";
when x"1A4" => DATA <= x"A2";
when x"1A5" => DATA <= x"03";
when x"1A6" => DATA <= x"0A";
when x"1A7" => DATA <= x"26";
when x"1A8" => DATA <= x"F0";
when x"1A9" => DATA <= x"26";
when x"1AA" => DATA <= x"F1";
when x"1AB" => DATA <= x"CA";
when x"1AC" => DATA <= x"10";
when x"1AD" => DATA <= x"F8";
when x"1AE" => DATA <= x"C8";
when x"1AF" => DATA <= x"D0";
when x"1B0" => DATA <= x"DB";
when x"1B1" => DATA <= x"60";
when x"1B2" => DATA <= x"86";
when x"1B3" => DATA <= x"F8";
when x"1B4" => DATA <= x"84";
when x"1B5" => DATA <= x"F9";
when x"1B6" => DATA <= x"A0";
when x"1B7" => DATA <= x"00";
when x"1B8" => DATA <= x"2C";
when x"1B9" => DATA <= x"FA";
when x"1BA" => DATA <= x"FE";
when x"1BB" => DATA <= x"50";
when x"1BC" => DATA <= x"FB";
when x"1BD" => DATA <= x"B1";
when x"1BE" => DATA <= x"F8";
when x"1BF" => DATA <= x"8D";
when x"1C0" => DATA <= x"FB";
when x"1C1" => DATA <= x"FE";
when x"1C2" => DATA <= x"C8";
when x"1C3" => DATA <= x"C9";
when x"1C4" => DATA <= x"0D";
when x"1C5" => DATA <= x"D0";
when x"1C6" => DATA <= x"F1";
when x"1C7" => DATA <= x"A4";
when x"1C8" => DATA <= x"F9";
when x"1C9" => DATA <= x"60";
when x"1CA" => DATA <= x"48";
when x"1CB" => DATA <= x"86";
when x"1CC" => DATA <= x"F8";
when x"1CD" => DATA <= x"84";
when x"1CE" => DATA <= x"F9";
when x"1CF" => DATA <= x"A0";
when x"1D0" => DATA <= x"00";
when x"1D1" => DATA <= x"20";
when x"1D2" => DATA <= x"7F";
when x"1D3" => DATA <= x"F9";
when x"1D4" => DATA <= x"C8";
when x"1D5" => DATA <= x"C9";
when x"1D6" => DATA <= x"2A";
when x"1D7" => DATA <= x"F0";
when x"1D8" => DATA <= x"F8";
when x"1D9" => DATA <= x"29";
when x"1DA" => DATA <= x"DF";
when x"1DB" => DATA <= x"AA";
when x"1DC" => DATA <= x"B1";
when x"1DD" => DATA <= x"F8";
when x"1DE" => DATA <= x"E0";
when x"1DF" => DATA <= x"47";
when x"1E0" => DATA <= x"F0";
when x"1E1" => DATA <= x"5C";
when x"1E2" => DATA <= x"E0";
when x"1E3" => DATA <= x"48";
when x"1E4" => DATA <= x"D0";
when x"1E5" => DATA <= x"47";
when x"1E6" => DATA <= x"C9";
when x"1E7" => DATA <= x"2E";
when x"1E8" => DATA <= x"F0";
when x"1E9" => DATA <= x"2D";
when x"1EA" => DATA <= x"29";
when x"1EB" => DATA <= x"DF";
when x"1EC" => DATA <= x"C9";
when x"1ED" => DATA <= x"45";
when x"1EE" => DATA <= x"D0";
when x"1EF" => DATA <= x"3D";
when x"1F0" => DATA <= x"C8";
when x"1F1" => DATA <= x"B1";
when x"1F2" => DATA <= x"F8";
when x"1F3" => DATA <= x"C9";
when x"1F4" => DATA <= x"2E";
when x"1F5" => DATA <= x"F0";
when x"1F6" => DATA <= x"20";
when x"1F7" => DATA <= x"29";
when x"1F8" => DATA <= x"DF";
when x"1F9" => DATA <= x"C9";
when x"1FA" => DATA <= x"4C";
when x"1FB" => DATA <= x"D0";
when x"1FC" => DATA <= x"30";
when x"1FD" => DATA <= x"C8";
when x"1FE" => DATA <= x"B1";
when x"1FF" => DATA <= x"F8";
when x"200" => DATA <= x"C9";
when x"201" => DATA <= x"2E";
when x"202" => DATA <= x"F0";
when x"203" => DATA <= x"13";
when x"204" => DATA <= x"29";
when x"205" => DATA <= x"DF";
when x"206" => DATA <= x"C9";
when x"207" => DATA <= x"50";
when x"208" => DATA <= x"D0";
when x"209" => DATA <= x"23";
when x"20A" => DATA <= x"C8";
when x"20B" => DATA <= x"B1";
when x"20C" => DATA <= x"F8";
when x"20D" => DATA <= x"29";
when x"20E" => DATA <= x"DF";
when x"20F" => DATA <= x"C9";
when x"210" => DATA <= x"41";
when x"211" => DATA <= x"90";
when x"212" => DATA <= x"04";
when x"213" => DATA <= x"C9";
when x"214" => DATA <= x"5B";
when x"215" => DATA <= x"90";
when x"216" => DATA <= x"16";
when x"217" => DATA <= x"20";
when x"218" => DATA <= x"98";
when x"219" => DATA <= x"FE";
when x"21A" => DATA <= x"0A";
when x"21B" => DATA <= x"0D";
when x"21C" => DATA <= x"36";
when x"21D" => DATA <= x"35";
when x"21E" => DATA <= x"30";
when x"21F" => DATA <= x"32";
when x"220" => DATA <= x"20";
when x"221" => DATA <= x"54";
when x"222" => DATA <= x"55";
when x"223" => DATA <= x"42";
when x"224" => DATA <= x"45";
when x"225" => DATA <= x"20";
when x"226" => DATA <= x"31";
when x"227" => DATA <= x"2E";
when x"228" => DATA <= x"31";
when x"229" => DATA <= x"30";
when x"22A" => DATA <= x"0A";
when x"22B" => DATA <= x"0D";
when x"22C" => DATA <= x"EA";
when x"22D" => DATA <= x"A9";
when x"22E" => DATA <= x"02";
when x"22F" => DATA <= x"20";
when x"230" => DATA <= x"4A";
when x"231" => DATA <= x"FC";
when x"232" => DATA <= x"20";
when x"233" => DATA <= x"B6";
when x"234" => DATA <= x"F9";
when x"235" => DATA <= x"20";
when x"236" => DATA <= x"75";
when x"237" => DATA <= x"F9";
when x"238" => DATA <= x"C9";
when x"239" => DATA <= x"80";
when x"23A" => DATA <= x"F0";
when x"23B" => DATA <= x"20";
when x"23C" => DATA <= x"68";
when x"23D" => DATA <= x"60";
when x"23E" => DATA <= x"29";
when x"23F" => DATA <= x"DF";
when x"240" => DATA <= x"C9";
when x"241" => DATA <= x"4F";
when x"242" => DATA <= x"D0";
when x"243" => DATA <= x"E9";
when x"244" => DATA <= x"20";
when x"245" => DATA <= x"7E";
when x"246" => DATA <= x"F9";
when x"247" => DATA <= x"20";
when x"248" => DATA <= x"86";
when x"249" => DATA <= x"F9";
when x"24A" => DATA <= x"20";
when x"24B" => DATA <= x"7F";
when x"24C" => DATA <= x"F9";
when x"24D" => DATA <= x"C9";
when x"24E" => DATA <= x"0D";
when x"24F" => DATA <= x"D0";
when x"250" => DATA <= x"DC";
when x"251" => DATA <= x"8A";
when x"252" => DATA <= x"F0";
when x"253" => DATA <= x"08";
when x"254" => DATA <= x"A5";
when x"255" => DATA <= x"F0";
when x"256" => DATA <= x"85";
when x"257" => DATA <= x"F6";
when x"258" => DATA <= x"A5";
when x"259" => DATA <= x"F1";
when x"25A" => DATA <= x"85";
when x"25B" => DATA <= x"F7";
when x"25C" => DATA <= x"A5";
when x"25D" => DATA <= x"EF";
when x"25E" => DATA <= x"48";
when x"25F" => DATA <= x"A5";
when x"260" => DATA <= x"EE";
when x"261" => DATA <= x"48";
when x"262" => DATA <= x"20";
when x"263" => DATA <= x"B5";
when x"264" => DATA <= x"F8";
when x"265" => DATA <= x"68";
when x"266" => DATA <= x"85";
when x"267" => DATA <= x"EE";
when x"268" => DATA <= x"85";
when x"269" => DATA <= x"F2";
when x"26A" => DATA <= x"68";
when x"26B" => DATA <= x"85";
when x"26C" => DATA <= x"EF";
when x"26D" => DATA <= x"85";
when x"26E" => DATA <= x"F3";
when x"26F" => DATA <= x"68";
when x"270" => DATA <= x"60";
when x"271" => DATA <= x"F0";
when x"272" => DATA <= x"C2";
when x"273" => DATA <= x"C9";
when x"274" => DATA <= x"80";
when x"275" => DATA <= x"B0";
when x"276" => DATA <= x"25";
when x"277" => DATA <= x"48";
when x"278" => DATA <= x"A9";
when x"279" => DATA <= x"04";
when x"27A" => DATA <= x"2C";
when x"27B" => DATA <= x"FA";
when x"27C" => DATA <= x"FE";
when x"27D" => DATA <= x"50";
when x"27E" => DATA <= x"FB";
when x"27F" => DATA <= x"8D";
when x"280" => DATA <= x"FB";
when x"281" => DATA <= x"FE";
when x"282" => DATA <= x"2C";
when x"283" => DATA <= x"FA";
when x"284" => DATA <= x"FE";
when x"285" => DATA <= x"50";
when x"286" => DATA <= x"FB";
when x"287" => DATA <= x"8E";
when x"288" => DATA <= x"FB";
when x"289" => DATA <= x"FE";
when x"28A" => DATA <= x"68";
when x"28B" => DATA <= x"2C";
when x"28C" => DATA <= x"FA";
when x"28D" => DATA <= x"FE";
when x"28E" => DATA <= x"50";
when x"28F" => DATA <= x"FB";
when x"290" => DATA <= x"8D";
when x"291" => DATA <= x"FB";
when x"292" => DATA <= x"FE";
when x"293" => DATA <= x"2C";
when x"294" => DATA <= x"FA";
when x"295" => DATA <= x"FE";
when x"296" => DATA <= x"10";
when x"297" => DATA <= x"FB";
when x"298" => DATA <= x"AE";
when x"299" => DATA <= x"FB";
when x"29A" => DATA <= x"FE";
when x"29B" => DATA <= x"60";
when x"29C" => DATA <= x"C9";
when x"29D" => DATA <= x"82";
when x"29E" => DATA <= x"F0";
when x"29F" => DATA <= x"5A";
when x"2A0" => DATA <= x"C9";
when x"2A1" => DATA <= x"83";
when x"2A2" => DATA <= x"F0";
when x"2A3" => DATA <= x"51";
when x"2A4" => DATA <= x"C9";
when x"2A5" => DATA <= x"84";
when x"2A6" => DATA <= x"F0";
when x"2A7" => DATA <= x"48";
when x"2A8" => DATA <= x"48";
when x"2A9" => DATA <= x"A9";
when x"2AA" => DATA <= x"06";
when x"2AB" => DATA <= x"2C";
when x"2AC" => DATA <= x"FA";
when x"2AD" => DATA <= x"FE";
when x"2AE" => DATA <= x"50";
when x"2AF" => DATA <= x"FB";
when x"2B0" => DATA <= x"8D";
when x"2B1" => DATA <= x"FB";
when x"2B2" => DATA <= x"FE";
when x"2B3" => DATA <= x"2C";
when x"2B4" => DATA <= x"FA";
when x"2B5" => DATA <= x"FE";
when x"2B6" => DATA <= x"50";
when x"2B7" => DATA <= x"FB";
when x"2B8" => DATA <= x"8E";
when x"2B9" => DATA <= x"FB";
when x"2BA" => DATA <= x"FE";
when x"2BB" => DATA <= x"2C";
when x"2BC" => DATA <= x"FA";
when x"2BD" => DATA <= x"FE";
when x"2BE" => DATA <= x"50";
when x"2BF" => DATA <= x"FB";
when x"2C0" => DATA <= x"8C";
when x"2C1" => DATA <= x"FB";
when x"2C2" => DATA <= x"FE";
when x"2C3" => DATA <= x"68";
when x"2C4" => DATA <= x"2C";
when x"2C5" => DATA <= x"FA";
when x"2C6" => DATA <= x"FE";
when x"2C7" => DATA <= x"50";
when x"2C8" => DATA <= x"FB";
when x"2C9" => DATA <= x"8D";
when x"2CA" => DATA <= x"FB";
when x"2CB" => DATA <= x"FE";
when x"2CC" => DATA <= x"C9";
when x"2CD" => DATA <= x"8E";
when x"2CE" => DATA <= x"F0";
when x"2CF" => DATA <= x"A1";
when x"2D0" => DATA <= x"C9";
when x"2D1" => DATA <= x"9D";
when x"2D2" => DATA <= x"F0";
when x"2D3" => DATA <= x"1B";
when x"2D4" => DATA <= x"48";
when x"2D5" => DATA <= x"2C";
when x"2D6" => DATA <= x"FA";
when x"2D7" => DATA <= x"FE";
when x"2D8" => DATA <= x"10";
when x"2D9" => DATA <= x"FB";
when x"2DA" => DATA <= x"AD";
when x"2DB" => DATA <= x"FB";
when x"2DC" => DATA <= x"FE";
when x"2DD" => DATA <= x"0A";
when x"2DE" => DATA <= x"68";
when x"2DF" => DATA <= x"2C";
when x"2E0" => DATA <= x"FA";
when x"2E1" => DATA <= x"FE";
when x"2E2" => DATA <= x"10";
when x"2E3" => DATA <= x"FB";
when x"2E4" => DATA <= x"AC";
when x"2E5" => DATA <= x"FB";
when x"2E6" => DATA <= x"FE";
when x"2E7" => DATA <= x"2C";
when x"2E8" => DATA <= x"FA";
when x"2E9" => DATA <= x"FE";
when x"2EA" => DATA <= x"10";
when x"2EB" => DATA <= x"FB";
when x"2EC" => DATA <= x"AE";
when x"2ED" => DATA <= x"FB";
when x"2EE" => DATA <= x"FE";
when x"2EF" => DATA <= x"60";
when x"2F0" => DATA <= x"A6";
when x"2F1" => DATA <= x"F2";
when x"2F2" => DATA <= x"A4";
when x"2F3" => DATA <= x"F3";
when x"2F4" => DATA <= x"60";
when x"2F5" => DATA <= x"A2";
when x"2F6" => DATA <= x"00";
when x"2F7" => DATA <= x"A0";
when x"2F8" => DATA <= x"08";
when x"2F9" => DATA <= x"60";
when x"2FA" => DATA <= x"A2";
when x"2FB" => DATA <= x"00";
when x"2FC" => DATA <= x"A0";
when x"2FD" => DATA <= x"00";
when x"2FE" => DATA <= x"60";
when x"2FF" => DATA <= x"86";
when x"300" => DATA <= x"F8";
when x"301" => DATA <= x"84";
when x"302" => DATA <= x"F9";
when x"303" => DATA <= x"A8";
when x"304" => DATA <= x"F0";
when x"305" => DATA <= x"71";
when x"306" => DATA <= x"48";
when x"307" => DATA <= x"A0";
when x"308" => DATA <= x"08";
when x"309" => DATA <= x"2C";
when x"30A" => DATA <= x"FA";
when x"30B" => DATA <= x"FE";
when x"30C" => DATA <= x"50";
when x"30D" => DATA <= x"FB";
when x"30E" => DATA <= x"8C";
when x"30F" => DATA <= x"FB";
when x"310" => DATA <= x"FE";
when x"311" => DATA <= x"2C";
when x"312" => DATA <= x"FA";
when x"313" => DATA <= x"FE";
when x"314" => DATA <= x"50";
when x"315" => DATA <= x"FB";
when x"316" => DATA <= x"8D";
when x"317" => DATA <= x"FB";
when x"318" => DATA <= x"FE";
when x"319" => DATA <= x"AA";
when x"31A" => DATA <= x"10";
when x"31B" => DATA <= x"08";
when x"31C" => DATA <= x"A0";
when x"31D" => DATA <= x"00";
when x"31E" => DATA <= x"B1";
when x"31F" => DATA <= x"F8";
when x"320" => DATA <= x"A8";
when x"321" => DATA <= x"4C";
when x"322" => DATA <= x"2D";
when x"323" => DATA <= x"FB";
when x"324" => DATA <= x"BC";
when x"325" => DATA <= x"BC";
when x"326" => DATA <= x"FC";
when x"327" => DATA <= x"E0";
when x"328" => DATA <= x"15";
when x"329" => DATA <= x"90";
when x"32A" => DATA <= x"02";
when x"32B" => DATA <= x"A0";
when x"32C" => DATA <= x"10";
when x"32D" => DATA <= x"2C";
when x"32E" => DATA <= x"FA";
when x"32F" => DATA <= x"FE";
when x"330" => DATA <= x"50";
when x"331" => DATA <= x"FB";
when x"332" => DATA <= x"8C";
when x"333" => DATA <= x"FB";
when x"334" => DATA <= x"FE";
when x"335" => DATA <= x"88";
when x"336" => DATA <= x"30";
when x"337" => DATA <= x"0D";
when x"338" => DATA <= x"2C";
when x"339" => DATA <= x"FA";
when x"33A" => DATA <= x"FE";
when x"33B" => DATA <= x"50";
when x"33C" => DATA <= x"FB";
when x"33D" => DATA <= x"B1";
when x"33E" => DATA <= x"F8";
when x"33F" => DATA <= x"8D";
when x"340" => DATA <= x"FB";
when x"341" => DATA <= x"FE";
when x"342" => DATA <= x"88";
when x"343" => DATA <= x"10";
when x"344" => DATA <= x"F3";
when x"345" => DATA <= x"8A";
when x"346" => DATA <= x"10";
when x"347" => DATA <= x"08";
when x"348" => DATA <= x"A0";
when x"349" => DATA <= x"01";
when x"34A" => DATA <= x"B1";
when x"34B" => DATA <= x"F8";
when x"34C" => DATA <= x"A8";
when x"34D" => DATA <= x"4C";
when x"34E" => DATA <= x"59";
when x"34F" => DATA <= x"FB";
when x"350" => DATA <= x"BC";
when x"351" => DATA <= x"D0";
when x"352" => DATA <= x"FC";
when x"353" => DATA <= x"E0";
when x"354" => DATA <= x"15";
when x"355" => DATA <= x"90";
when x"356" => DATA <= x"02";
when x"357" => DATA <= x"A0";
when x"358" => DATA <= x"10";
when x"359" => DATA <= x"2C";
when x"35A" => DATA <= x"FA";
when x"35B" => DATA <= x"FE";
when x"35C" => DATA <= x"50";
when x"35D" => DATA <= x"FB";
when x"35E" => DATA <= x"8C";
when x"35F" => DATA <= x"FB";
when x"360" => DATA <= x"FE";
when x"361" => DATA <= x"88";
when x"362" => DATA <= x"30";
when x"363" => DATA <= x"0D";
when x"364" => DATA <= x"2C";
when x"365" => DATA <= x"FA";
when x"366" => DATA <= x"FE";
when x"367" => DATA <= x"10";
when x"368" => DATA <= x"FB";
when x"369" => DATA <= x"AD";
when x"36A" => DATA <= x"FB";
when x"36B" => DATA <= x"FE";
when x"36C" => DATA <= x"91";
when x"36D" => DATA <= x"F8";
when x"36E" => DATA <= x"88";
when x"36F" => DATA <= x"10";
when x"370" => DATA <= x"F3";
when x"371" => DATA <= x"A4";
when x"372" => DATA <= x"F9";
when x"373" => DATA <= x"A6";
when x"374" => DATA <= x"F8";
when x"375" => DATA <= x"68";
when x"376" => DATA <= x"60";
when x"377" => DATA <= x"A9";
when x"378" => DATA <= x"0A";
when x"379" => DATA <= x"20";
when x"37A" => DATA <= x"4A";
when x"37B" => DATA <= x"FC";
when x"37C" => DATA <= x"A0";
when x"37D" => DATA <= x"04";
when x"37E" => DATA <= x"2C";
when x"37F" => DATA <= x"FA";
when x"380" => DATA <= x"FE";
when x"381" => DATA <= x"50";
when x"382" => DATA <= x"FB";
when x"383" => DATA <= x"B1";
when x"384" => DATA <= x"F8";
when x"385" => DATA <= x"8D";
when x"386" => DATA <= x"FB";
when x"387" => DATA <= x"FE";
when x"388" => DATA <= x"88";
when x"389" => DATA <= x"C0";
when x"38A" => DATA <= x"01";
when x"38B" => DATA <= x"D0";
when x"38C" => DATA <= x"F1";
when x"38D" => DATA <= x"A9";
when x"38E" => DATA <= x"07";
when x"38F" => DATA <= x"20";
when x"390" => DATA <= x"4A";
when x"391" => DATA <= x"FC";
when x"392" => DATA <= x"B1";
when x"393" => DATA <= x"F8";
when x"394" => DATA <= x"48";
when x"395" => DATA <= x"88";
when x"396" => DATA <= x"2C";
when x"397" => DATA <= x"FA";
when x"398" => DATA <= x"FE";
when x"399" => DATA <= x"50";
when x"39A" => DATA <= x"FB";
when x"39B" => DATA <= x"8C";
when x"39C" => DATA <= x"FB";
when x"39D" => DATA <= x"FE";
when x"39E" => DATA <= x"B1";
when x"39F" => DATA <= x"F8";
when x"3A0" => DATA <= x"48";
when x"3A1" => DATA <= x"A2";
when x"3A2" => DATA <= x"FF";
when x"3A3" => DATA <= x"20";
when x"3A4" => DATA <= x"75";
when x"3A5" => DATA <= x"F9";
when x"3A6" => DATA <= x"C9";
when x"3A7" => DATA <= x"80";
when x"3A8" => DATA <= x"B0";
when x"3A9" => DATA <= x"1D";
when x"3AA" => DATA <= x"68";
when x"3AB" => DATA <= x"85";
when x"3AC" => DATA <= x"F8";
when x"3AD" => DATA <= x"68";
when x"3AE" => DATA <= x"85";
when x"3AF" => DATA <= x"F9";
when x"3B0" => DATA <= x"A0";
when x"3B1" => DATA <= x"00";
when x"3B2" => DATA <= x"2C";
when x"3B3" => DATA <= x"FA";
when x"3B4" => DATA <= x"FE";
when x"3B5" => DATA <= x"10";
when x"3B6" => DATA <= x"FB";
when x"3B7" => DATA <= x"AD";
when x"3B8" => DATA <= x"FB";
when x"3B9" => DATA <= x"FE";
when x"3BA" => DATA <= x"91";
when x"3BB" => DATA <= x"F8";
when x"3BC" => DATA <= x"C8";
when x"3BD" => DATA <= x"C9";
when x"3BE" => DATA <= x"0D";
when x"3BF" => DATA <= x"D0";
when x"3C0" => DATA <= x"F1";
when x"3C1" => DATA <= x"A9";
when x"3C2" => DATA <= x"00";
when x"3C3" => DATA <= x"88";
when x"3C4" => DATA <= x"18";
when x"3C5" => DATA <= x"E8";
when x"3C6" => DATA <= x"60";
when x"3C7" => DATA <= x"68";
when x"3C8" => DATA <= x"68";
when x"3C9" => DATA <= x"A9";
when x"3CA" => DATA <= x"00";
when x"3CB" => DATA <= x"60";
when x"3CC" => DATA <= x"48";
when x"3CD" => DATA <= x"A9";
when x"3CE" => DATA <= x"0C";
when x"3CF" => DATA <= x"20";
when x"3D0" => DATA <= x"4A";
when x"3D1" => DATA <= x"FC";
when x"3D2" => DATA <= x"2C";
when x"3D3" => DATA <= x"FA";
when x"3D4" => DATA <= x"FE";
when x"3D5" => DATA <= x"50";
when x"3D6" => DATA <= x"FB";
when x"3D7" => DATA <= x"8C";
when x"3D8" => DATA <= x"FB";
when x"3D9" => DATA <= x"FE";
when x"3DA" => DATA <= x"B5";
when x"3DB" => DATA <= x"03";
when x"3DC" => DATA <= x"20";
when x"3DD" => DATA <= x"4A";
when x"3DE" => DATA <= x"FC";
when x"3DF" => DATA <= x"B5";
when x"3E0" => DATA <= x"02";
when x"3E1" => DATA <= x"20";
when x"3E2" => DATA <= x"4A";
when x"3E3" => DATA <= x"FC";
when x"3E4" => DATA <= x"B5";
when x"3E5" => DATA <= x"01";
when x"3E6" => DATA <= x"20";
when x"3E7" => DATA <= x"4A";
when x"3E8" => DATA <= x"FC";
when x"3E9" => DATA <= x"B5";
when x"3EA" => DATA <= x"00";
when x"3EB" => DATA <= x"20";
when x"3EC" => DATA <= x"4A";
when x"3ED" => DATA <= x"FC";
when x"3EE" => DATA <= x"68";
when x"3EF" => DATA <= x"20";
when x"3F0" => DATA <= x"4A";
when x"3F1" => DATA <= x"FC";
when x"3F2" => DATA <= x"20";
when x"3F3" => DATA <= x"75";
when x"3F4" => DATA <= x"F9";
when x"3F5" => DATA <= x"48";
when x"3F6" => DATA <= x"20";
when x"3F7" => DATA <= x"75";
when x"3F8" => DATA <= x"F9";
when x"3F9" => DATA <= x"95";
when x"3FA" => DATA <= x"03";
when x"3FB" => DATA <= x"20";
when x"3FC" => DATA <= x"75";
when x"3FD" => DATA <= x"F9";
when x"3FE" => DATA <= x"95";
when x"3FF" => DATA <= x"02";
when x"400" => DATA <= x"20";
when x"401" => DATA <= x"75";
when x"402" => DATA <= x"F9";
when x"403" => DATA <= x"95";
when x"404" => DATA <= x"01";
when x"405" => DATA <= x"20";
when x"406" => DATA <= x"75";
when x"407" => DATA <= x"F9";
when x"408" => DATA <= x"95";
when x"409" => DATA <= x"00";
when x"40A" => DATA <= x"68";
when x"40B" => DATA <= x"60";
when x"40C" => DATA <= x"48";
when x"40D" => DATA <= x"A9";
when x"40E" => DATA <= x"12";
when x"40F" => DATA <= x"20";
when x"410" => DATA <= x"4A";
when x"411" => DATA <= x"FC";
when x"412" => DATA <= x"68";
when x"413" => DATA <= x"20";
when x"414" => DATA <= x"4A";
when x"415" => DATA <= x"FC";
when x"416" => DATA <= x"C9";
when x"417" => DATA <= x"00";
when x"418" => DATA <= x"D0";
when x"419" => DATA <= x"0A";
when x"41A" => DATA <= x"48";
when x"41B" => DATA <= x"98";
when x"41C" => DATA <= x"20";
when x"41D" => DATA <= x"4A";
when x"41E" => DATA <= x"FC";
when x"41F" => DATA <= x"20";
when x"420" => DATA <= x"75";
when x"421" => DATA <= x"F9";
when x"422" => DATA <= x"68";
when x"423" => DATA <= x"60";
when x"424" => DATA <= x"20";
when x"425" => DATA <= x"B2";
when x"426" => DATA <= x"F9";
when x"427" => DATA <= x"4C";
when x"428" => DATA <= x"75";
when x"429" => DATA <= x"F9";
when x"42A" => DATA <= x"A9";
when x"42B" => DATA <= x"0E";
when x"42C" => DATA <= x"20";
when x"42D" => DATA <= x"4A";
when x"42E" => DATA <= x"FC";
when x"42F" => DATA <= x"98";
when x"430" => DATA <= x"20";
when x"431" => DATA <= x"4A";
when x"432" => DATA <= x"FC";
when x"433" => DATA <= x"4C";
when x"434" => DATA <= x"71";
when x"435" => DATA <= x"F9";
when x"436" => DATA <= x"48";
when x"437" => DATA <= x"A9";
when x"438" => DATA <= x"10";
when x"439" => DATA <= x"20";
when x"43A" => DATA <= x"4A";
when x"43B" => DATA <= x"FC";
when x"43C" => DATA <= x"98";
when x"43D" => DATA <= x"20";
when x"43E" => DATA <= x"4A";
when x"43F" => DATA <= x"FC";
when x"440" => DATA <= x"68";
when x"441" => DATA <= x"20";
when x"442" => DATA <= x"4A";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"48";
when x"445" => DATA <= x"20";
when x"446" => DATA <= x"75";
when x"447" => DATA <= x"F9";
when x"448" => DATA <= x"68";
when x"449" => DATA <= x"60";
when x"44A" => DATA <= x"2C";
when x"44B" => DATA <= x"FA";
when x"44C" => DATA <= x"FE";
when x"44D" => DATA <= x"50";
when x"44E" => DATA <= x"FB";
when x"44F" => DATA <= x"8D";
when x"450" => DATA <= x"FB";
when x"451" => DATA <= x"FE";
when x"452" => DATA <= x"60";
when x"453" => DATA <= x"84";
when x"454" => DATA <= x"FB";
when x"455" => DATA <= x"86";
when x"456" => DATA <= x"FA";
when x"457" => DATA <= x"48";
when x"458" => DATA <= x"A9";
when x"459" => DATA <= x"14";
when x"45A" => DATA <= x"20";
when x"45B" => DATA <= x"4A";
when x"45C" => DATA <= x"FC";
when x"45D" => DATA <= x"A0";
when x"45E" => DATA <= x"11";
when x"45F" => DATA <= x"B1";
when x"460" => DATA <= x"FA";
when x"461" => DATA <= x"20";
when x"462" => DATA <= x"4A";
when x"463" => DATA <= x"FC";
when x"464" => DATA <= x"88";
when x"465" => DATA <= x"C0";
when x"466" => DATA <= x"01";
when x"467" => DATA <= x"D0";
when x"468" => DATA <= x"F6";
when x"469" => DATA <= x"88";
when x"46A" => DATA <= x"B1";
when x"46B" => DATA <= x"FA";
when x"46C" => DATA <= x"AA";
when x"46D" => DATA <= x"C8";
when x"46E" => DATA <= x"B1";
when x"46F" => DATA <= x"FA";
when x"470" => DATA <= x"A8";
when x"471" => DATA <= x"20";
when x"472" => DATA <= x"B2";
when x"473" => DATA <= x"F9";
when x"474" => DATA <= x"68";
when x"475" => DATA <= x"20";
when x"476" => DATA <= x"4A";
when x"477" => DATA <= x"FC";
when x"478" => DATA <= x"20";
when x"479" => DATA <= x"75";
when x"47A" => DATA <= x"F9";
when x"47B" => DATA <= x"48";
when x"47C" => DATA <= x"A0";
when x"47D" => DATA <= x"11";
when x"47E" => DATA <= x"20";
when x"47F" => DATA <= x"75";
when x"480" => DATA <= x"F9";
when x"481" => DATA <= x"91";
when x"482" => DATA <= x"FA";
when x"483" => DATA <= x"88";
when x"484" => DATA <= x"C0";
when x"485" => DATA <= x"01";
when x"486" => DATA <= x"D0";
when x"487" => DATA <= x"F6";
when x"488" => DATA <= x"A4";
when x"489" => DATA <= x"FB";
when x"48A" => DATA <= x"A6";
when x"48B" => DATA <= x"FA";
when x"48C" => DATA <= x"68";
when x"48D" => DATA <= x"60";
when x"48E" => DATA <= x"84";
when x"48F" => DATA <= x"FB";
when x"490" => DATA <= x"86";
when x"491" => DATA <= x"FA";
when x"492" => DATA <= x"48";
when x"493" => DATA <= x"A9";
when x"494" => DATA <= x"16";
when x"495" => DATA <= x"20";
when x"496" => DATA <= x"4A";
when x"497" => DATA <= x"FC";
when x"498" => DATA <= x"A0";
when x"499" => DATA <= x"0C";
when x"49A" => DATA <= x"B1";
when x"49B" => DATA <= x"FA";
when x"49C" => DATA <= x"20";
when x"49D" => DATA <= x"4A";
when x"49E" => DATA <= x"FC";
when x"49F" => DATA <= x"88";
when x"4A0" => DATA <= x"10";
when x"4A1" => DATA <= x"F8";
when x"4A2" => DATA <= x"68";
when x"4A3" => DATA <= x"20";
when x"4A4" => DATA <= x"4A";
when x"4A5" => DATA <= x"FC";
when x"4A6" => DATA <= x"A0";
when x"4A7" => DATA <= x"0C";
when x"4A8" => DATA <= x"20";
when x"4A9" => DATA <= x"75";
when x"4AA" => DATA <= x"F9";
when x"4AB" => DATA <= x"91";
when x"4AC" => DATA <= x"FA";
when x"4AD" => DATA <= x"88";
when x"4AE" => DATA <= x"10";
when x"4AF" => DATA <= x"F8";
when x"4B0" => DATA <= x"A4";
when x"4B1" => DATA <= x"FB";
when x"4B2" => DATA <= x"A6";
when x"4B3" => DATA <= x"FA";
when x"4B4" => DATA <= x"4C";
when x"4B5" => DATA <= x"71";
when x"4B6" => DATA <= x"F9";
when x"4B7" => DATA <= x"00";
when x"4B8" => DATA <= x"FF";
when x"4B9" => DATA <= x"42";
when x"4BA" => DATA <= x"61";
when x"4BB" => DATA <= x"64";
when x"4BC" => DATA <= x"00";
when x"4BD" => DATA <= x"00";
when x"4BE" => DATA <= x"05";
when x"4BF" => DATA <= x"00";
when x"4C0" => DATA <= x"05";
when x"4C1" => DATA <= x"02";
when x"4C2" => DATA <= x"05";
when x"4C3" => DATA <= x"08";
when x"4C4" => DATA <= x"0E";
when x"4C5" => DATA <= x"04";
when x"4C6" => DATA <= x"01";
when x"4C7" => DATA <= x"01";
when x"4C8" => DATA <= x"05";
when x"4C9" => DATA <= x"00";
when x"4CA" => DATA <= x"01";
when x"4CB" => DATA <= x"20";
when x"4CC" => DATA <= x"10";
when x"4CD" => DATA <= x"0D";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"04";
when x"4D0" => DATA <= x"80";
when x"4D1" => DATA <= x"05";
when x"4D2" => DATA <= x"00";
when x"4D3" => DATA <= x"05";
when x"4D4" => DATA <= x"00";
when x"4D5" => DATA <= x"05";
when x"4D6" => DATA <= x"00";
when x"4D7" => DATA <= x"00";
when x"4D8" => DATA <= x"00";
when x"4D9" => DATA <= x"05";
when x"4DA" => DATA <= x"09";
when x"4DB" => DATA <= x"05";
when x"4DC" => DATA <= x"00";
when x"4DD" => DATA <= x"08";
when x"4DE" => DATA <= x"18";
when x"4DF" => DATA <= x"00";
when x"4E0" => DATA <= x"01";
when x"4E1" => DATA <= x"0D";
when x"4E2" => DATA <= x"80";
when x"4E3" => DATA <= x"04";
when x"4E4" => DATA <= x"80";
when x"4E5" => DATA <= x"85";
when x"4E6" => DATA <= x"FC";
when x"4E7" => DATA <= x"68";
when x"4E8" => DATA <= x"48";
when x"4E9" => DATA <= x"29";
when x"4EA" => DATA <= x"10";
when x"4EB" => DATA <= x"D0";
when x"4EC" => DATA <= x"10";
when x"4ED" => DATA <= x"6C";
when x"4EE" => DATA <= x"04";
when x"4EF" => DATA <= x"02";
when x"4F0" => DATA <= x"2C";
when x"4F1" => DATA <= x"FE";
when x"4F2" => DATA <= x"FE";
when x"4F3" => DATA <= x"30";
when x"4F4" => DATA <= x"4A";
when x"4F5" => DATA <= x"2C";
when x"4F6" => DATA <= x"F8";
when x"4F7" => DATA <= x"FE";
when x"4F8" => DATA <= x"30";
when x"4F9" => DATA <= x"1E";
when x"4FA" => DATA <= x"6C";
when x"4FB" => DATA <= x"06";
when x"4FC" => DATA <= x"02";
when x"4FD" => DATA <= x"8A";
when x"4FE" => DATA <= x"48";
when x"4FF" => DATA <= x"BA";
when x"500" => DATA <= x"BD";
when x"501" => DATA <= x"03";
when x"502" => DATA <= x"01";
when x"503" => DATA <= x"D8";
when x"504" => DATA <= x"38";
when x"505" => DATA <= x"E9";
when x"506" => DATA <= x"01";
when x"507" => DATA <= x"85";
when x"508" => DATA <= x"FD";
when x"509" => DATA <= x"BD";
when x"50A" => DATA <= x"04";
when x"50B" => DATA <= x"01";
when x"50C" => DATA <= x"E9";
when x"50D" => DATA <= x"00";
when x"50E" => DATA <= x"85";
when x"50F" => DATA <= x"FE";
when x"510" => DATA <= x"68";
when x"511" => DATA <= x"AA";
when x"512" => DATA <= x"A5";
when x"513" => DATA <= x"FC";
when x"514" => DATA <= x"58";
when x"515" => DATA <= x"6C";
when x"516" => DATA <= x"02";
when x"517" => DATA <= x"02";
when x"518" => DATA <= x"AD";
when x"519" => DATA <= x"F9";
when x"51A" => DATA <= x"FE";
when x"51B" => DATA <= x"30";
when x"51C" => DATA <= x"1C";
when x"51D" => DATA <= x"98";
when x"51E" => DATA <= x"48";
when x"51F" => DATA <= x"8A";
when x"520" => DATA <= x"48";
when x"521" => DATA <= x"20";
when x"522" => DATA <= x"80";
when x"523" => DATA <= x"FE";
when x"524" => DATA <= x"A8";
when x"525" => DATA <= x"20";
when x"526" => DATA <= x"80";
when x"527" => DATA <= x"FE";
when x"528" => DATA <= x"AA";
when x"529" => DATA <= x"20";
when x"52A" => DATA <= x"80";
when x"52B" => DATA <= x"FE";
when x"52C" => DATA <= x"20";
when x"52D" => DATA <= x"36";
when x"52E" => DATA <= x"FD";
when x"52F" => DATA <= x"68";
when x"530" => DATA <= x"AA";
when x"531" => DATA <= x"68";
when x"532" => DATA <= x"A8";
when x"533" => DATA <= x"A5";
when x"534" => DATA <= x"FC";
when x"535" => DATA <= x"40";
when x"536" => DATA <= x"6C";
when x"537" => DATA <= x"20";
when x"538" => DATA <= x"02";
when x"539" => DATA <= x"0A";
when x"53A" => DATA <= x"85";
when x"53B" => DATA <= x"FF";
when x"53C" => DATA <= x"A5";
when x"53D" => DATA <= x"FC";
when x"53E" => DATA <= x"40";
when x"53F" => DATA <= x"AD";
when x"540" => DATA <= x"FF";
when x"541" => DATA <= x"FE";
when x"542" => DATA <= x"10";
when x"543" => DATA <= x"21";
when x"544" => DATA <= x"58";
when x"545" => DATA <= x"2C";
when x"546" => DATA <= x"FA";
when x"547" => DATA <= x"FE";
when x"548" => DATA <= x"10";
when x"549" => DATA <= x"FB";
when x"54A" => DATA <= x"AD";
when x"54B" => DATA <= x"FB";
when x"54C" => DATA <= x"FE";
when x"54D" => DATA <= x"A9";
when x"54E" => DATA <= x"00";
when x"54F" => DATA <= x"8D";
when x"550" => DATA <= x"36";
when x"551" => DATA <= x"02";
when x"552" => DATA <= x"A8";
when x"553" => DATA <= x"20";
when x"554" => DATA <= x"75";
when x"555" => DATA <= x"F9";
when x"556" => DATA <= x"8D";
when x"557" => DATA <= x"37";
when x"558" => DATA <= x"02";
when x"559" => DATA <= x"C8";
when x"55A" => DATA <= x"20";
when x"55B" => DATA <= x"75";
when x"55C" => DATA <= x"F9";
when x"55D" => DATA <= x"99";
when x"55E" => DATA <= x"37";
when x"55F" => DATA <= x"02";
when x"560" => DATA <= x"D0";
when x"561" => DATA <= x"F7";
when x"562" => DATA <= x"4C";
when x"563" => DATA <= x"36";
when x"564" => DATA <= x"02";
when x"565" => DATA <= x"8D";
when x"566" => DATA <= x"FA";
when x"567" => DATA <= x"FF";
when x"568" => DATA <= x"98";
when x"569" => DATA <= x"48";
when x"56A" => DATA <= x"AC";
when x"56B" => DATA <= x"FA";
when x"56C" => DATA <= x"FF";
when x"56D" => DATA <= x"B9";
when x"56E" => DATA <= x"70";
when x"56F" => DATA <= x"FE";
when x"570" => DATA <= x"8D";
when x"571" => DATA <= x"FA";
when x"572" => DATA <= x"FF";
when x"573" => DATA <= x"B9";
when x"574" => DATA <= x"78";
when x"575" => DATA <= x"FE";
when x"576" => DATA <= x"8D";
when x"577" => DATA <= x"FB";
when x"578" => DATA <= x"FF";
when x"579" => DATA <= x"B9";
when x"57A" => DATA <= x"60";
when x"57B" => DATA <= x"FE";
when x"57C" => DATA <= x"85";
when x"57D" => DATA <= x"F4";
when x"57E" => DATA <= x"B9";
when x"57F" => DATA <= x"68";
when x"580" => DATA <= x"FE";
when x"581" => DATA <= x"85";
when x"582" => DATA <= x"F5";
when x"583" => DATA <= x"2C";
when x"584" => DATA <= x"FE";
when x"585" => DATA <= x"FE";
when x"586" => DATA <= x"10";
when x"587" => DATA <= x"FB";
when x"588" => DATA <= x"AD";
when x"589" => DATA <= x"FF";
when x"58A" => DATA <= x"FE";
when x"58B" => DATA <= x"C0";
when x"58C" => DATA <= x"05";
when x"58D" => DATA <= x"F0";
when x"58E" => DATA <= x"58";
when x"58F" => DATA <= x"98";
when x"590" => DATA <= x"48";
when x"591" => DATA <= x"A0";
when x"592" => DATA <= x"01";
when x"593" => DATA <= x"2C";
when x"594" => DATA <= x"FE";
when x"595" => DATA <= x"FE";
when x"596" => DATA <= x"10";
when x"597" => DATA <= x"FB";
when x"598" => DATA <= x"AD";
when x"599" => DATA <= x"FF";
when x"59A" => DATA <= x"FE";
when x"59B" => DATA <= x"2C";
when x"59C" => DATA <= x"FE";
when x"59D" => DATA <= x"FE";
when x"59E" => DATA <= x"10";
when x"59F" => DATA <= x"FB";
when x"5A0" => DATA <= x"AD";
when x"5A1" => DATA <= x"FF";
when x"5A2" => DATA <= x"FE";
when x"5A3" => DATA <= x"2C";
when x"5A4" => DATA <= x"FE";
when x"5A5" => DATA <= x"FE";
when x"5A6" => DATA <= x"10";
when x"5A7" => DATA <= x"FB";
when x"5A8" => DATA <= x"AD";
when x"5A9" => DATA <= x"FF";
when x"5AA" => DATA <= x"FE";
when x"5AB" => DATA <= x"91";
when x"5AC" => DATA <= x"F4";
when x"5AD" => DATA <= x"88";
when x"5AE" => DATA <= x"2C";
when x"5AF" => DATA <= x"FE";
when x"5B0" => DATA <= x"FE";
when x"5B1" => DATA <= x"10";
when x"5B2" => DATA <= x"FB";
when x"5B3" => DATA <= x"AD";
when x"5B4" => DATA <= x"FF";
when x"5B5" => DATA <= x"FE";
when x"5B6" => DATA <= x"91";
when x"5B7" => DATA <= x"F4";
when x"5B8" => DATA <= x"2C";
when x"5B9" => DATA <= x"FD";
when x"5BA" => DATA <= x"FE";
when x"5BB" => DATA <= x"2C";
when x"5BC" => DATA <= x"FD";
when x"5BD" => DATA <= x"FE";
when x"5BE" => DATA <= x"2C";
when x"5BF" => DATA <= x"FE";
when x"5C0" => DATA <= x"FE";
when x"5C1" => DATA <= x"10";
when x"5C2" => DATA <= x"FB";
when x"5C3" => DATA <= x"AD";
when x"5C4" => DATA <= x"FF";
when x"5C5" => DATA <= x"FE";
when x"5C6" => DATA <= x"68";
when x"5C7" => DATA <= x"C9";
when x"5C8" => DATA <= x"06";
when x"5C9" => DATA <= x"90";
when x"5CA" => DATA <= x"1C";
when x"5CB" => DATA <= x"D0";
when x"5CC" => DATA <= x"1F";
when x"5CD" => DATA <= x"A0";
when x"5CE" => DATA <= x"00";
when x"5CF" => DATA <= x"AD";
when x"5D0" => DATA <= x"FC";
when x"5D1" => DATA <= x"FE";
when x"5D2" => DATA <= x"29";
when x"5D3" => DATA <= x"80";
when x"5D4" => DATA <= x"10";
when x"5D5" => DATA <= x"F9";
when x"5D6" => DATA <= x"B9";
when x"5D7" => DATA <= x"FF";
when x"5D8" => DATA <= x"FF";
when x"5D9" => DATA <= x"8D";
when x"5DA" => DATA <= x"FD";
when x"5DB" => DATA <= x"FE";
when x"5DC" => DATA <= x"C8";
when x"5DD" => DATA <= x"D0";
when x"5DE" => DATA <= x"F0";
when x"5DF" => DATA <= x"2C";
when x"5E0" => DATA <= x"FC";
when x"5E1" => DATA <= x"FE";
when x"5E2" => DATA <= x"10";
when x"5E3" => DATA <= x"FB";
when x"5E4" => DATA <= x"8D";
when x"5E5" => DATA <= x"FD";
when x"5E6" => DATA <= x"FE";
when x"5E7" => DATA <= x"68";
when x"5E8" => DATA <= x"A8";
when x"5E9" => DATA <= x"A5";
when x"5EA" => DATA <= x"FC";
when x"5EB" => DATA <= x"40";
when x"5EC" => DATA <= x"A0";
when x"5ED" => DATA <= x"00";
when x"5EE" => DATA <= x"AD";
when x"5EF" => DATA <= x"FC";
when x"5F0" => DATA <= x"FE";
when x"5F1" => DATA <= x"29";
when x"5F2" => DATA <= x"80";
when x"5F3" => DATA <= x"10";
when x"5F4" => DATA <= x"F9";
when x"5F5" => DATA <= x"AD";
when x"5F6" => DATA <= x"FD";
when x"5F7" => DATA <= x"FE";
when x"5F8" => DATA <= x"99";
when x"5F9" => DATA <= x"FF";
when x"5FA" => DATA <= x"FF";
when x"5FB" => DATA <= x"C8";
when x"5FC" => DATA <= x"D0";
when x"5FD" => DATA <= x"F0";
when x"5FE" => DATA <= x"F0";
when x"5FF" => DATA <= x"E7";
when x"600" => DATA <= x"48";
when x"601" => DATA <= x"AD";
when x"602" => DATA <= x"FF";
when x"603" => DATA <= x"FF";
when x"604" => DATA <= x"8D";
when x"605" => DATA <= x"FD";
when x"606" => DATA <= x"FE";
when x"607" => DATA <= x"EE";
when x"608" => DATA <= x"02";
when x"609" => DATA <= x"FE";
when x"60A" => DATA <= x"D0";
when x"60B" => DATA <= x"03";
when x"60C" => DATA <= x"EE";
when x"60D" => DATA <= x"03";
when x"60E" => DATA <= x"FE";
when x"60F" => DATA <= x"68";
when x"610" => DATA <= x"40";
when x"611" => DATA <= x"48";
when x"612" => DATA <= x"AD";
when x"613" => DATA <= x"FD";
when x"614" => DATA <= x"FE";
when x"615" => DATA <= x"8D";
when x"616" => DATA <= x"FF";
when x"617" => DATA <= x"FF";
when x"618" => DATA <= x"EE";
when x"619" => DATA <= x"16";
when x"61A" => DATA <= x"FE";
when x"61B" => DATA <= x"D0";
when x"61C" => DATA <= x"03";
when x"61D" => DATA <= x"EE";
when x"61E" => DATA <= x"17";
when x"61F" => DATA <= x"FE";
when x"620" => DATA <= x"68";
when x"621" => DATA <= x"40";
when x"622" => DATA <= x"48";
when x"623" => DATA <= x"98";
when x"624" => DATA <= x"48";
when x"625" => DATA <= x"A0";
when x"626" => DATA <= x"00";
when x"627" => DATA <= x"B1";
when x"628" => DATA <= x"F6";
when x"629" => DATA <= x"8D";
when x"62A" => DATA <= x"FD";
when x"62B" => DATA <= x"FE";
when x"62C" => DATA <= x"E6";
when x"62D" => DATA <= x"F6";
when x"62E" => DATA <= x"D0";
when x"62F" => DATA <= x"02";
when x"630" => DATA <= x"E6";
when x"631" => DATA <= x"F7";
when x"632" => DATA <= x"B1";
when x"633" => DATA <= x"F6";
when x"634" => DATA <= x"8D";
when x"635" => DATA <= x"FD";
when x"636" => DATA <= x"FE";
when x"637" => DATA <= x"E6";
when x"638" => DATA <= x"F6";
when x"639" => DATA <= x"D0";
when x"63A" => DATA <= x"02";
when x"63B" => DATA <= x"E6";
when x"63C" => DATA <= x"F7";
when x"63D" => DATA <= x"68";
when x"63E" => DATA <= x"A8";
when x"63F" => DATA <= x"68";
when x"640" => DATA <= x"40";
when x"641" => DATA <= x"48";
when x"642" => DATA <= x"98";
when x"643" => DATA <= x"48";
when x"644" => DATA <= x"A0";
when x"645" => DATA <= x"00";
when x"646" => DATA <= x"AD";
when x"647" => DATA <= x"FD";
when x"648" => DATA <= x"FE";
when x"649" => DATA <= x"91";
when x"64A" => DATA <= x"F6";
when x"64B" => DATA <= x"E6";
when x"64C" => DATA <= x"F6";
when x"64D" => DATA <= x"D0";
when x"64E" => DATA <= x"02";
when x"64F" => DATA <= x"E6";
when x"650" => DATA <= x"F7";
when x"651" => DATA <= x"AD";
when x"652" => DATA <= x"FD";
when x"653" => DATA <= x"FE";
when x"654" => DATA <= x"91";
when x"655" => DATA <= x"F6";
when x"656" => DATA <= x"E6";
when x"657" => DATA <= x"F6";
when x"658" => DATA <= x"D0";
when x"659" => DATA <= x"02";
when x"65A" => DATA <= x"E6";
when x"65B" => DATA <= x"F7";
when x"65C" => DATA <= x"68";
when x"65D" => DATA <= x"A8";
when x"65E" => DATA <= x"68";
when x"65F" => DATA <= x"40";
when x"660" => DATA <= x"02";
when x"661" => DATA <= x"16";
when x"662" => DATA <= x"F6";
when x"663" => DATA <= x"F6";
when x"664" => DATA <= x"F6";
when x"665" => DATA <= x"F6";
when x"666" => DATA <= x"D7";
when x"667" => DATA <= x"F9";
when x"668" => DATA <= x"FE";
when x"669" => DATA <= x"FE";
when x"66A" => DATA <= x"00";
when x"66B" => DATA <= x"00";
when x"66C" => DATA <= x"00";
when x"66D" => DATA <= x"00";
when x"66E" => DATA <= x"FD";
when x"66F" => DATA <= x"FD";
when x"670" => DATA <= x"00";
when x"671" => DATA <= x"11";
when x"672" => DATA <= x"22";
when x"673" => DATA <= x"41";
when x"674" => DATA <= x"B3";
when x"675" => DATA <= x"B3";
when x"676" => DATA <= x"B3";
when x"677" => DATA <= x"B3";
when x"678" => DATA <= x"FE";
when x"679" => DATA <= x"FE";
when x"67A" => DATA <= x"FE";
when x"67B" => DATA <= x"FE";
when x"67C" => DATA <= x"FE";
when x"67D" => DATA <= x"FE";
when x"67E" => DATA <= x"FE";
when x"67F" => DATA <= x"FE";
when x"680" => DATA <= x"2C";
when x"681" => DATA <= x"F8";
when x"682" => DATA <= x"FE";
when x"683" => DATA <= x"30";
when x"684" => DATA <= x"0F";
when x"685" => DATA <= x"2C";
when x"686" => DATA <= x"FE";
when x"687" => DATA <= x"FE";
when x"688" => DATA <= x"10";
when x"689" => DATA <= x"F6";
when x"68A" => DATA <= x"A5";
when x"68B" => DATA <= x"FC";
when x"68C" => DATA <= x"08";
when x"68D" => DATA <= x"58";
when x"68E" => DATA <= x"28";
when x"68F" => DATA <= x"85";
when x"690" => DATA <= x"FC";
when x"691" => DATA <= x"4C";
when x"692" => DATA <= x"80";
when x"693" => DATA <= x"FE";
when x"694" => DATA <= x"AD";
when x"695" => DATA <= x"F9";
when x"696" => DATA <= x"FE";
when x"697" => DATA <= x"60";
when x"698" => DATA <= x"68";
when x"699" => DATA <= x"85";
when x"69A" => DATA <= x"FA";
when x"69B" => DATA <= x"68";
when x"69C" => DATA <= x"85";
when x"69D" => DATA <= x"FB";
when x"69E" => DATA <= x"A0";
when x"69F" => DATA <= x"00";
when x"6A0" => DATA <= x"E6";
when x"6A1" => DATA <= x"FA";
when x"6A2" => DATA <= x"D0";
when x"6A3" => DATA <= x"02";
when x"6A4" => DATA <= x"E6";
when x"6A5" => DATA <= x"FB";
when x"6A6" => DATA <= x"B1";
when x"6A7" => DATA <= x"FA";
when x"6A8" => DATA <= x"30";
when x"6A9" => DATA <= x"06";
when x"6AA" => DATA <= x"20";
when x"6AB" => DATA <= x"EE";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"4C";
when x"6AE" => DATA <= x"A0";
when x"6AF" => DATA <= x"FE";
when x"6B0" => DATA <= x"6C";
when x"6B1" => DATA <= x"FA";
when x"6B2" => DATA <= x"00";
when x"6B3" => DATA <= x"8D";
when x"6B4" => DATA <= x"FD";
when x"6B5" => DATA <= x"FE";
when x"6B6" => DATA <= x"40";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"FF";
when x"6E1" => DATA <= x"FF";
when x"6E2" => DATA <= x"FF";
when x"6E3" => DATA <= x"FF";
when x"6E4" => DATA <= x"FF";
when x"6E5" => DATA <= x"FF";
when x"6E6" => DATA <= x"FF";
when x"6E7" => DATA <= x"FF";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"00";
when x"6F1" => DATA <= x"00";
when x"6F2" => DATA <= x"00";
when x"6F3" => DATA <= x"00";
when x"6F4" => DATA <= x"00";
when x"6F5" => DATA <= x"00";
when x"6F6" => DATA <= x"00";
when x"6F7" => DATA <= x"00";
when x"6F8" => DATA <= x"00";
when x"6F9" => DATA <= x"00";
when x"6FA" => DATA <= x"00";
when x"6FB" => DATA <= x"00";
when x"6FC" => DATA <= x"00";
when x"6FD" => DATA <= x"00";
when x"6FE" => DATA <= x"00";
when x"6FF" => DATA <= x"00";
when x"700" => DATA <= x"FF";
when x"701" => DATA <= x"FF";
when x"702" => DATA <= x"FF";
when x"703" => DATA <= x"FF";
when x"704" => DATA <= x"FF";
when x"705" => DATA <= x"FF";
when x"706" => DATA <= x"FF";
when x"707" => DATA <= x"FF";
when x"708" => DATA <= x"FF";
when x"709" => DATA <= x"FF";
when x"70A" => DATA <= x"FF";
when x"70B" => DATA <= x"FF";
when x"70C" => DATA <= x"FF";
when x"70D" => DATA <= x"FF";
when x"70E" => DATA <= x"FF";
when x"70F" => DATA <= x"FF";
when x"710" => DATA <= x"FF";
when x"711" => DATA <= x"FF";
when x"712" => DATA <= x"FF";
when x"713" => DATA <= x"FF";
when x"714" => DATA <= x"FF";
when x"715" => DATA <= x"FF";
when x"716" => DATA <= x"FF";
when x"717" => DATA <= x"FF";
when x"718" => DATA <= x"FF";
when x"719" => DATA <= x"FF";
when x"71A" => DATA <= x"FF";
when x"71B" => DATA <= x"FF";
when x"71C" => DATA <= x"FF";
when x"71D" => DATA <= x"FF";
when x"71E" => DATA <= x"FF";
when x"71F" => DATA <= x"FF";
when x"720" => DATA <= x"FF";
when x"721" => DATA <= x"FF";
when x"722" => DATA <= x"FF";
when x"723" => DATA <= x"FF";
when x"724" => DATA <= x"FF";
when x"725" => DATA <= x"FF";
when x"726" => DATA <= x"FF";
when x"727" => DATA <= x"FF";
when x"728" => DATA <= x"FF";
when x"729" => DATA <= x"FF";
when x"72A" => DATA <= x"FF";
when x"72B" => DATA <= x"FF";
when x"72C" => DATA <= x"FF";
when x"72D" => DATA <= x"FF";
when x"72E" => DATA <= x"FF";
when x"72F" => DATA <= x"FF";
when x"730" => DATA <= x"FF";
when x"731" => DATA <= x"FF";
when x"732" => DATA <= x"FF";
when x"733" => DATA <= x"FF";
when x"734" => DATA <= x"FF";
when x"735" => DATA <= x"FF";
when x"736" => DATA <= x"FF";
when x"737" => DATA <= x"FF";
when x"738" => DATA <= x"FF";
when x"739" => DATA <= x"FF";
when x"73A" => DATA <= x"FF";
when x"73B" => DATA <= x"FF";
when x"73C" => DATA <= x"FF";
when x"73D" => DATA <= x"FF";
when x"73E" => DATA <= x"FF";
when x"73F" => DATA <= x"FF";
when x"740" => DATA <= x"FF";
when x"741" => DATA <= x"FF";
when x"742" => DATA <= x"FF";
when x"743" => DATA <= x"FF";
when x"744" => DATA <= x"FF";
when x"745" => DATA <= x"FF";
when x"746" => DATA <= x"FF";
when x"747" => DATA <= x"FF";
when x"748" => DATA <= x"FF";
when x"749" => DATA <= x"FF";
when x"74A" => DATA <= x"FF";
when x"74B" => DATA <= x"FF";
when x"74C" => DATA <= x"FF";
when x"74D" => DATA <= x"FF";
when x"74E" => DATA <= x"FF";
when x"74F" => DATA <= x"FF";
when x"750" => DATA <= x"FF";
when x"751" => DATA <= x"FF";
when x"752" => DATA <= x"FF";
when x"753" => DATA <= x"FF";
when x"754" => DATA <= x"FF";
when x"755" => DATA <= x"FF";
when x"756" => DATA <= x"FF";
when x"757" => DATA <= x"FF";
when x"758" => DATA <= x"FF";
when x"759" => DATA <= x"FF";
when x"75A" => DATA <= x"FF";
when x"75B" => DATA <= x"FF";
when x"75C" => DATA <= x"FF";
when x"75D" => DATA <= x"FF";
when x"75E" => DATA <= x"FF";
when x"75F" => DATA <= x"FF";
when x"760" => DATA <= x"FF";
when x"761" => DATA <= x"FF";
when x"762" => DATA <= x"FF";
when x"763" => DATA <= x"FF";
when x"764" => DATA <= x"FF";
when x"765" => DATA <= x"FF";
when x"766" => DATA <= x"FF";
when x"767" => DATA <= x"FF";
when x"768" => DATA <= x"FF";
when x"769" => DATA <= x"FF";
when x"76A" => DATA <= x"FF";
when x"76B" => DATA <= x"FF";
when x"76C" => DATA <= x"FF";
when x"76D" => DATA <= x"FF";
when x"76E" => DATA <= x"FF";
when x"76F" => DATA <= x"FF";
when x"770" => DATA <= x"FF";
when x"771" => DATA <= x"FF";
when x"772" => DATA <= x"FF";
when x"773" => DATA <= x"FF";
when x"774" => DATA <= x"FF";
when x"775" => DATA <= x"FF";
when x"776" => DATA <= x"FF";
when x"777" => DATA <= x"FF";
when x"778" => DATA <= x"FF";
when x"779" => DATA <= x"FF";
when x"77A" => DATA <= x"FF";
when x"77B" => DATA <= x"FF";
when x"77C" => DATA <= x"FF";
when x"77D" => DATA <= x"FF";
when x"77E" => DATA <= x"FF";
when x"77F" => DATA <= x"FF";
when x"780" => DATA <= x"B7";
when x"781" => DATA <= x"FC";
when x"782" => DATA <= x"45";
when x"783" => DATA <= x"F9";
when x"784" => DATA <= x"F0";
when x"785" => DATA <= x"FC";
when x"786" => DATA <= x"B7";
when x"787" => DATA <= x"FC";
when x"788" => DATA <= x"CA";
when x"789" => DATA <= x"F9";
when x"78A" => DATA <= x"73";
when x"78B" => DATA <= x"FA";
when x"78C" => DATA <= x"FF";
when x"78D" => DATA <= x"FA";
when x"78E" => DATA <= x"62";
when x"78F" => DATA <= x"F9";
when x"790" => DATA <= x"6C";
when x"791" => DATA <= x"F9";
when x"792" => DATA <= x"53";
when x"793" => DATA <= x"FC";
when x"794" => DATA <= x"CC";
when x"795" => DATA <= x"FB";
when x"796" => DATA <= x"2A";
when x"797" => DATA <= x"FC";
when x"798" => DATA <= x"36";
when x"799" => DATA <= x"FC";
when x"79A" => DATA <= x"8E";
when x"79B" => DATA <= x"FC";
when x"79C" => DATA <= x"0C";
when x"79D" => DATA <= x"FC";
when x"79E" => DATA <= x"B7";
when x"79F" => DATA <= x"FC";
when x"7A0" => DATA <= x"7D";
when x"7A1" => DATA <= x"F9";
when x"7A2" => DATA <= x"B7";
when x"7A3" => DATA <= x"FC";
when x"7A4" => DATA <= x"B7";
when x"7A5" => DATA <= x"FC";
when x"7A6" => DATA <= x"B7";
when x"7A7" => DATA <= x"FC";
when x"7A8" => DATA <= x"B7";
when x"7A9" => DATA <= x"FC";
when x"7AA" => DATA <= x"B7";
when x"7AB" => DATA <= x"FC";
when x"7AC" => DATA <= x"B7";
when x"7AD" => DATA <= x"FC";
when x"7AE" => DATA <= x"B7";
when x"7AF" => DATA <= x"FC";
when x"7B0" => DATA <= x"7D";
when x"7B1" => DATA <= x"F9";
when x"7B2" => DATA <= x"7D";
when x"7B3" => DATA <= x"F9";
when x"7B4" => DATA <= x"7D";
when x"7B5" => DATA <= x"F9";
when x"7B6" => DATA <= x"36";
when x"7B7" => DATA <= x"80";
when x"7B8" => DATA <= x"FF";
when x"7B9" => DATA <= x"4C";
when x"7BA" => DATA <= x"B7";
when x"7BB" => DATA <= x"FC";
when x"7BC" => DATA <= x"4C";
when x"7BD" => DATA <= x"B7";
when x"7BE" => DATA <= x"FC";
when x"7BF" => DATA <= x"4C";
when x"7C0" => DATA <= x"B7";
when x"7C1" => DATA <= x"FC";
when x"7C2" => DATA <= x"4C";
when x"7C3" => DATA <= x"B7";
when x"7C4" => DATA <= x"FC";
when x"7C5" => DATA <= x"4C";
when x"7C6" => DATA <= x"B7";
when x"7C7" => DATA <= x"FC";
when x"7C8" => DATA <= x"4C";
when x"7C9" => DATA <= x"6C";
when x"7CA" => DATA <= x"F9";
when x"7CB" => DATA <= x"4C";
when x"7CC" => DATA <= x"62";
when x"7CD" => DATA <= x"F9";
when x"7CE" => DATA <= x"6C";
when x"7CF" => DATA <= x"1C";
when x"7D0" => DATA <= x"02";
when x"7D1" => DATA <= x"6C";
when x"7D2" => DATA <= x"1A";
when x"7D3" => DATA <= x"02";
when x"7D4" => DATA <= x"6C";
when x"7D5" => DATA <= x"18";
when x"7D6" => DATA <= x"02";
when x"7D7" => DATA <= x"6C";
when x"7D8" => DATA <= x"16";
when x"7D9" => DATA <= x"02";
when x"7DA" => DATA <= x"6C";
when x"7DB" => DATA <= x"14";
when x"7DC" => DATA <= x"02";
when x"7DD" => DATA <= x"6C";
when x"7DE" => DATA <= x"12";
when x"7DF" => DATA <= x"02";
when x"7E0" => DATA <= x"6C";
when x"7E1" => DATA <= x"10";
when x"7E2" => DATA <= x"02";
when x"7E3" => DATA <= x"C9";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"D0";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"A9";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"20";
when x"7EA" => DATA <= x"EE";
when x"7EB" => DATA <= x"FF";
when x"7EC" => DATA <= x"A9";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"6C";
when x"7EF" => DATA <= x"0E";
when x"7F0" => DATA <= x"02";
when x"7F1" => DATA <= x"6C";
when x"7F2" => DATA <= x"0C";
when x"7F3" => DATA <= x"02";
when x"7F4" => DATA <= x"6C";
when x"7F5" => DATA <= x"0A";
when x"7F6" => DATA <= x"02";
when x"7F7" => DATA <= x"6C";
when x"7F8" => DATA <= x"08";
when x"7F9" => DATA <= x"02";
when x"7FA" => DATA <= x"00";
when x"7FB" => DATA <= x"FE";
when x"7FC" => DATA <= x"00";
when x"7FD" => DATA <= x"F8";
when x"7FE" => DATA <= x"E5";
when x"7FF" => DATA <= x"FC";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 03:26:46 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.vhdl
-- Design : system_vga_buffer_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_buffer_1_0_vga_buffer : entity is "vga_buffer";
end system_vga_buffer_1_0_vga_buffer;
architecture STRUCTURE of system_vga_buffer_1_0_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_data_reg_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 24 );
signal NLW_data_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg : label is 24576;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(9),
Q => c_addr_w(9),
R => '0'
);
data_reg: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addr_w(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addr_r(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_DBITERR_UNCONNECTED,
DIADI(31 downto 24) => B"00000000",
DIADI(23 downto 0) => data_w(23 downto 0),
DIBDI(31 downto 0) => B"00000000111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 24) => NLW_data_reg_DOBDO_UNCONNECTED(31 downto 24),
DOBDO(23 downto 0) => data_r(23 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_1_0 : entity is "system_vga_buffer_1_0,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_1_0 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_1_0;
architecture STRUCTURE of system_vga_buffer_1_0 is
begin
U0: entity work.system_vga_buffer_1_0_vga_buffer
port map (
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
x_addr_r(9 downto 0) => x_addr_r(9 downto 0),
x_addr_w(9 downto 0) => x_addr_w(9 downto 0)
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- Title : SPW_NODE package
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Carl Treudler
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reset_pkg.all;
use work.bus_pkg.all;
package spw_node_pkg is
--
-- SPW_NODE
--
component spw_node
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
RESET_IMPL : reset_type := none
);
port(
-- spacewire interface
-- (differential buffers should be placed in toplevel.)
do_p : out std_logic;
so_p : out std_logic;
di_p : in std_logic;
si_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic);
end component;
end spw_node_pkg;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
package td_target_support_pkg is
signal global_vvc_ack : std_logic; -- ACK on global triggers
signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers
shared variable protected_multicast_semaphore : t_protected_semaphore;
shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx;
type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods
trigger : std_logic;
vvc_name : string(1 to C_VVC_NAME_MAX_LENGTH); -- as scope is vvc_name & ',' and number
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := (
trigger => 'L',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved;
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved;
subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved;
-------------------------------------------
-- to_string
-------------------------------------------
-- to_string method for VVC name, instance and channel
-- - If channel is set to NA, it will not be included in the string
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel := NA
) return string;
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Returns an encapsulated command index as string
impure function format_command_idx(
command : t_vvc_cmd_record -- VVC dedicated
) return string;
-------------------------------------------
-- send_command_to_vvc
-------------------------------------------
-- Sends command to VVC and waits for ACK or timeout
-- - Logs with ID_UVVM_SEND_CMD when sending to VVC
-- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs
procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
);
-------------------------------------------
-- set_vvc_target_defaults
-------------------------------------------
-- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record;
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- acknowledge_cmd
-------------------------------------------
-- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'.
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
);
end package td_target_support_pkg;
package body td_target_support_pkg is
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is
-- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name)
constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length
variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low);
variable v_cnt : integer := 0;
variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL);
variable v_line : line;
variable v_width : integer := 0;
begin
if input_vector'length = 1 then
return input_vector(input_vector'low);
else
for i in input_vector'range loop
-- The VVC is used if instance_idx is not -1 (which is the default value)
if input_vector(i).vvc_instance_idx /= -1 then
-- count the number of sequencer trying to access the VVC
v_cnt := v_cnt + 1;
v_result := input_vector(i);
-- generating string with all instance_idx for report in case of failure
write(v_line, string'(" "));
write(v_line, input_vector(i).vvc_instance_idx);
-- Ensure there is room for the last item and dots
v_width := v_line'length;
if v_width > (C_LINE_LENGTH_MAX-15) then
write(v_line, string'("..."));
exit;
end if;
end if;
end loop;
if v_width > 0 then
v_instance_string(1 to v_width) := v_line.all;
end if;
deallocate(v_line);
check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), C_SCOPE, ID_NEVER);
return v_result;
end if;
end resolved;
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel:= NA
) return string is
variable v_instance : integer;
variable v_channel : t_channel;
begin
if vvc_instance = -1 then
v_instance := value.vvc_instance_idx;
else
v_instance := vvc_instance;
end if;
if vvc_channel = NA then
v_channel := value.vvc_channel;
else
v_channel := vvc_channel;
end if;
if v_channel = NA then
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES";
else
return to_string(value.vvc_name) & "," & to_string(v_instance);
end if;
else
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES" & "," & to_string(v_channel);
else
return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel);
end if;
end if;
end;
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record is
variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT;
begin
if vvc_name'length > C_MAX_VVC_NAME_LENGTH then
alert(TB_FAILURE, "vvc_name is too long. Shorten name or set C_MAX_VVC_NAME_LENGTH in adaptation_pkg to desired length.", C_SCOPE);
end if;
v_rec.vvc_name := (others => NUL);
v_rec.vvc_name(1 to vvc_name'length) := vvc_name;
return v_rec;
end function;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
-- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here.
-- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command.
-- It is guaranteed that no time delay occurs, only delta cycle delay.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
target.vvc_instance_idx <= vvc_instance_idx;
target.vvc_channel <= vvc_channel;
shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length);
shared_vvc_cmd.msg := (others => NUL); -- default empty
shared_vvc_cmd.msg(1 to msg'length) := msg;
shared_vvc_cmd.command_type := command_type;
shared_vvc_cmd.operation := operation;
end procedure;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation);
end procedure;
impure function format_command_idx(
command : t_vvc_cmd_record
) return string is
begin
return format_command_idx(command.cmd_idx);
end;
procedure send_command_to_vvc(
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
) is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": ";
variable v_ack_cmd_idx : integer := -1;
variable v_start_time : time;
variable v_local_vvc_cmd : t_vvc_cmd_record;
variable v_local_cmd_idx : integer;
variable v_was_multicast : boolean := false;
begin
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER);
-- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
shared_vvc_cmd.cmd_idx := shared_cmd_idx;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), C_SCOPE);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
wait for 0 ns;
if (vvc_target.vvc_instance_idx = ALL_INSTANCES) then
await_semaphore_in_delta_cycles(protected_multicast_semaphore);
if global_vvc_busy /= 'L' then
wait until global_vvc_busy = 'L';
end if;
v_was_multicast := true;
end if;
v_start_time := now;
-- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer
-- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs.
v_local_vvc_cmd := shared_vvc_cmd;
-- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released
v_local_cmd_idx := shared_cmd_idx;
-- trigger the target -> vvc continues in await_cmd_from_sequencer
vvc_target.trigger <= '1';
wait for 0 ns;
-- the default value of vvc_target drives trigger to 'L' again
vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name);
while v_ack_cmd_idx /= v_local_cmd_idx loop
wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now);
v_ack_cmd_idx := protected_acknowledge_index.get_index;
if not (global_vvc_ack'event) then
tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", C_SCOPE);
-- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- release the semaphore as no VVC can do this
release_semaphore(protected_semaphore);
return;
end if;
end loop;
if (v_was_multicast = true) then
release_semaphore(protected_multicast_semaphore);
end if;
log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), C_SCOPE);
-- clean up and prepare for next
wait for 0 ns; -- wait for executor to stop driving global_vvc_ack
end procedure;
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
) is
begin
-- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously.
while(protected_acknowledge_index.set_index(command_idx) = false) loop
-- if it can't set the acknowledge_index wait for one delta cycle and try again
wait for 0 ns;
end loop;
vvc_ack <= '1';
wait until vvc_ack = '1';
vvc_ack <= 'Z';
wait for 0 ns;
protected_acknowledge_index.release_index;
end procedure;
end package body td_target_support_pkg;
|
CONFIGURATION Decode_ROM_Behavior_config OF Decode_ROM IS
FOR Behavior
END FOR;
END Decode_ROM_Behavior_config; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DDR_Blink is
Port (
DDR_blinker : OUT std_logic;
DDR_Write : IN std_logic;
DDR_Read : IN std_logic;
DDR_Both : IN std_logic;
ddr_Clock : IN std_logic;
DDr_Rst_n : IN std_logic
);
end entity DDR_Blink;
architecture Behavioral of DDR_Blink is
-- Blinking -_-_-_-_
Constant C_BLINKER_MSB : integer := 15; -- 4; -- 15;
Constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11;
signal DDR_blinker_i : std_logic;
signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0);
signal Fast_blinker_MSB_r1 : std_logic;
signal Blink_Pulse : std_logic;
signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0);
signal DDR_write_extension : std_logic;
signal DDR_write_extension_Cnt: std_logic_vector(1 downto 0);
signal DDR_read_extension : std_logic;
signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0);
begin
--
Syn_DDR_Fast_blinker:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
Fast_blinker <= (OTHERS=>'0');
Fast_blinker_MSB_r1 <= '0';
Blink_Pulse <= '0';
Slow_blinker <= (OTHERS=>'0');
elsif ddr_Clock'event and ddr_Clock = '1' then
Fast_blinker <= Fast_blinker + '1';
Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
Slow_blinker <= Slow_blinker + Blink_Pulse;
end if;
end process;
--
Syn_DDR_Write_Extenstion:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_write_extension_Cnt <= (OTHERS=>'0');
DDR_write_extension <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_write_extension_Cnt is
when "00" =>
if DDR_Write='1' then
DDR_write_extension_Cnt <= "01";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_write_extension_Cnt <= "11";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
DDR_write_extension_Cnt <= "10";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when Others =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_write_extension_Cnt <= "00";
DDR_write_extension <= '0';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Read_Extenstion:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_read_extension_Cnt <= (OTHERS=>'0');
DDR_read_extension <= '1';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_read_extension_Cnt is
when "00" =>
if DDR_Read='1' then
DDR_read_extension_Cnt <= "01";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_read_extension_Cnt <= "11";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
DDR_read_extension_Cnt <= "10";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when Others =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_read_extension_Cnt <= "00";
DDR_read_extension <= '1';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Working_blinker:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_Blinker_i <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
-- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2);
end if;
end process;
DDR_blinker <= DDR_blinker_i;
end architecture Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package sim is
procedure hexread(L : inout line; value:out bit_vector);
procedure hexread(L : inout line; value:out std_logic_vector);
function ishex(c : character) return boolean;
end package;
package body sim is
procedure char2hex(C: character; result: out bit_vector(3 downto 0);
good: out boolean; report_error: in boolean) is
begin
good := true;
case C is
when '0' => result := x"0";
when '1' => result := x"1";
when '2' => result := X"2";
when '3' => result := X"3";
when '4' => result := X"4";
when '5' => result := X"5";
when '6' => result := X"6";
when '7' => result := X"7";
when '8' => result := X"8";
when '9' => result := X"9";
when 'A' => result := X"A";
when 'B' => result := X"B";
when 'C' => result := X"C";
when 'D' => result := X"D";
when 'E' => result := X"E";
when 'F' => result := X"F";
when 'a' => result := X"A";
when 'b' => result := X"B";
when 'c' => result := X"C";
when 'd' => result := X"D";
when 'e' => result := X"E";
when 'f' => result := X"F";
when others =>
if report_error then
assert false report
"hexread error: read a '" & C & "', expected a hex character (0-F).";
end if;
good := false;
end case;
end;
procedure hexread(L:inout line; value:out bit_vector) is
variable OK: boolean;
variable C: character;
constant NE: integer := value'length/4; --'
variable BV: bit_vector(0 to value'length-1); --'
variable S: string(1 to NE-1);
begin
if value'length mod 4 /= 0 then --'
assert false report
"hexread Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(L,C);
exit when ((C /= ' ') and (C /= CR) and (C /= HT));
end loop;
char2hex(C, BV(0 to 3), OK, false);
if not OK then
return;
end if;
read(L, S, OK);
-- if not OK then
-- assert false report "hexread Error: Failed to read the STRING";
-- return;
-- end if;
for I in 1 to NE-1 loop
char2hex(S(I), BV(4*I to 4*I+3), OK, false);
if not OK then
return;
end if;
end loop;
value := BV;
end hexread;
procedure hexread(L:inout line; value:out std_ulogic_vector) is
variable tmp: bit_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := TO_X01(tmp);
end hexread;
procedure hexread(L:inout line; value:out std_logic_vector) is
variable tmp: std_ulogic_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := std_logic_vector(tmp);
end hexread;
function ishex(c:character) return boolean is
variable tmp : bit_vector(3 downto 0);
variable OK : boolean;
begin
char2hex(C, tmp, OK, false);
return OK;
end ishex;
end ; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0';
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
driveundriven : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.dqs_gate <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto sdbits) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block driveundriven;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2731.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02731ent IS
END c13s05b00x00p01n01i02731ent;
ARCHITECTURE c13s05b00x00p01n01i02731arch OF c13s05b00x00p01n01i02731ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02731 - ^A can not be used as a character literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02731arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2731.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02731ent IS
END c13s05b00x00p01n01i02731ent;
ARCHITECTURE c13s05b00x00p01n01i02731arch OF c13s05b00x00p01n01i02731ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02731 - ^A can not be used as a character literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02731arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2731.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02731ent IS
END c13s05b00x00p01n01i02731ent;
ARCHITECTURE c13s05b00x00p01n01i02731arch OF c13s05b00x00p01n01i02731ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02731 - ^A can not be used as a character literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02731arch;
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______102.845_____87.180
-- CLK_OUT2___100.000______0.000______50.0______115.831_____87.180
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "c48,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 12,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______102.845_____87.180
-- CLK_OUT2___100.000______0.000______50.0______115.831_____87.180
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "c48,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 12,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______102.845_____87.180
-- CLK_OUT2___100.000______0.000______50.0______115.831_____87.180
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "c48,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 12,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_ut130hbd
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
ut130r : if tech = ut130 generate
ut130rx : ringosc_ut130hbd port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc and tech /= ut130 generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2174.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02174ent IS
END c07s02b05x00p01n01i02174ent;
ARCHITECTURE c07s02b05x00p01n01i02174arch OF c07s02b05x00p01n01i02174ent IS
BEGIN
TESTING: PROCESS
constant x1: real := - 10.0;
BEGIN
assert NOT(x1=-10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02174"
severity NOTE;
assert (x1=-10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02174 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02174arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2174.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02174ent IS
END c07s02b05x00p01n01i02174ent;
ARCHITECTURE c07s02b05x00p01n01i02174arch OF c07s02b05x00p01n01i02174ent IS
BEGIN
TESTING: PROCESS
constant x1: real := - 10.0;
BEGIN
assert NOT(x1=-10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02174"
severity NOTE;
assert (x1=-10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02174 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02174arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2174.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02174ent IS
END c07s02b05x00p01n01i02174ent;
ARCHITECTURE c07s02b05x00p01n01i02174arch OF c07s02b05x00p01n01i02174ent IS
BEGIN
TESTING: PROCESS
constant x1: real := - 10.0;
BEGIN
assert NOT(x1=-10.0)
report "***PASSED TEST: c07s02b05x00p01n01i02174"
severity NOTE;
assert (x1=-10.0)
report "***FAILED TEST: c07s02b05x00p01n01i02174 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02174arch;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural;
type wishbone16_bus is
record
address : std_logic_vector(15 downto 0);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
cycle: std_logic;
write : std_logic;
strobe : std_logic;
ack : std_logic;
end record;
type array_of_addr is array(NATURAL range <>) of std_logic_vector(15 downto 0);
type array_of_slv16 is array(NATURAL range <>) of std_logic_vector(15 downto 0);
component gpmc_wishbone_wrapper is
generic(sync : boolean := false ; burst : boolean := false );
port
(
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component gpmc_wishbone_wrapper_aad is
generic(
sync : boolean := true;
burst : boolean := false;
addr_width : natural := 28
);
port (
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone master interface signals
wbm_address : out std_logic_vector(ADDR_WIDTH-1 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component spi_wishbone_wrapper is
generic(BIG_ENDIAN : boolean := true);
port
(
-- SPI SIGNALS
mosi, ss, sck : in std_logic;
miso : out std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end component;
end logi_wishbone_pack;
package body logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural is
begin
for i in slv'range loop
if slv(i) ='X' then
return i+1 ;
end if;
end loop;
return 0;
end function find_X;
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return natural is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(data, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '1' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return 1;
--end function sim_wishbone_write;
--
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return std_logic_vector(15 downto 0) is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(0, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '0' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return wish_bus.readdata;
--end function sim_wishbone_write;
end logi_wishbone_pack;
|
-- $Id: rbd_timer.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rbd_timer - syn
-- Description: rbus dev: usec precision timer
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 time r/w/- Timer register
-- w: if > 0 timer is running
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
entity rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv16 := (others=>'0'));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end entity rbd_timer;
architecture syn of rbd_timer is
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
timer : slv16; -- timer value
timer_act : slbit; -- timer active flag
timer_end : slbit; -- timer done flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- timer
'0','0' -- timer_act,timer_end
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, RB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_dout := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr=RB_ADDR then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
n.timer := RB_MREQ.din;
n.timer_act := '1';
end if;
if RB_MREQ.re = '1' then
irb_dout := r.timer;
end if;
end if;
-- timer logic
-- count down when active and 'on-the-usec'
n.timer_end := '0'; -- ensure end is 1 cycle pulse
if CE_USEC = '1' then -- if at usec
if r.timer_act = '1' then -- if timer active
if unsigned(r.timer) = 0 then -- if timer at end
n.timer_act := '0'; -- mark unactive
n.timer_end := '1'; -- send end marker
else -- else: timer not at end
n.timer := slv(unsigned(r.timer) - 1); -- decrement
end if;
end if;
end if;
N_REGS <= n;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= '0';
DONE <= r.timer_end;
BUSY <= r.timer_act;
end process proc_next;
end syn;
|
package directmap2_pack is
type rec is record
x : integer;
y : bit;
z : bit_vector(1 to 3);
end record;
end package;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity bot1 is
port ( r : in rec );
end entity;
architecture test of bot1 is
begin
p1: process is
begin
wait for 1 ns;
assert r = ( 5, '1', "101" );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity bot2 is
port ( r : in rec );
end entity;
architecture test of bot2 is
begin
p1: process is
begin
wait for 1 ns;
assert r = ( 6, '1', "101" );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity record24 is
end entity;
architecture test of record24 is
signal p : bit;
signal q : bit_vector(1 to 3);
signal i : integer;
begin
uut1: entity work.bot1
port map (
r.x => 5,
r.y => p,
r.z => q );
uut2: entity work.bot2
port map (
r.x => i,
r.y => p,
r.z => q );
main: process is
begin
i <= 6;
p <= '1';
q <= "101";
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1273.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p02n01i01273ent IS
END c08s04b00x00p02n01i01273ent;
ARCHITECTURE c08s04b00x00p02n01i01273arch OF c08s04b00x00p02n01i01273ent IS
signal T1 : integer;
BEGIN
TESTING: PROCESS
BEGIN
unk <= transport 1 after 10 ns ;
assert FALSE
report "***FAILED TEST: c08s04b00x00p02n01i01273 - Signal name not found."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p02n01i01273arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1273.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p02n01i01273ent IS
END c08s04b00x00p02n01i01273ent;
ARCHITECTURE c08s04b00x00p02n01i01273arch OF c08s04b00x00p02n01i01273ent IS
signal T1 : integer;
BEGIN
TESTING: PROCESS
BEGIN
unk <= transport 1 after 10 ns ;
assert FALSE
report "***FAILED TEST: c08s04b00x00p02n01i01273 - Signal name not found."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p02n01i01273arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1273.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p02n01i01273ent IS
END c08s04b00x00p02n01i01273ent;
ARCHITECTURE c08s04b00x00p02n01i01273arch OF c08s04b00x00p02n01i01273ent IS
signal T1 : integer;
BEGIN
TESTING: PROCESS
BEGIN
unk <= transport 1 after 10 ns ;
assert FALSE
report "***FAILED TEST: c08s04b00x00p02n01i01273 - Signal name not found."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p02n01i01273arch;
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This contains the counter logic
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity cntr is
port (
clk_i : in std_logic;
reset_i : in std_logic;
cntrup_i : in std_logic; -- counting up
cntrdown_i : in std_logic; -- counting down
cntrreset_i : in std_logic; -- count reset 1 .. reset counting
cntrhold_i : in std_logic; -- count hold 1 .. hold counting
digits_o : out std_logic_vector(13 downto 0));
end cntr;
|
-- NEED RESULT: ARCH00167.P1: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00167.P2: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00167.P3: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00167: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00167: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00167: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00167
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00167)
-- ENT00167_Test_Bench(ARCH00167_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00167 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00167" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00167 ;
--
entity ENT00167_Test_Bench is
end ENT00167_Test_Bench ;
--
architecture ARCH00167_Test_Bench of ENT00167_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00167 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00167_Test_Bench ;
|
-- Component declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
use work.AuxPkg.all;
package ComponentsPkg is
component ZUnit
generic (
IFWIDTH : integer;
DATAWIDTH : integer;
CCNTWIDTH : integer;
FIFODEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
AddrxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDO : out std_logic_vector(IFWIDTH-1 downto 0));
end component;
component Scheduler is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
SchedulerSelectxSI : in std_logic;
SchedContextSequencerxDI : in EngineScheduleControlType;
SchedTemporalPartitioningxDI : in EngineScheduleControlType;
EngineScheduleControlxEO : out EngineScheduleControlType
);
end component;
component SchedulerTemporalPartitioning is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
--
ScheduleStartxEI : in std_logic;
ScheduleDonexSO : out std_logic;
-- number of temporal contexts used in temporal partition
NoTpContextsxSI : in unsigned(CNTXTWIDTH-1 downto 0);
-- number of user clock-cycles to run
NoTpUserCyclesxSI : in unsigned(CCNTWIDTH-1 downto 0);
-- signals to engine
CExEO : out std_logic;
ClrContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEO : out std_logic;
ContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0)
);
end component;
component ScheduleStore
generic (
WRDWIDTH : integer;
CONWIDTH : integer;
CYCWIDTH : integer;
ADRWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
IAddrxDI : in std_logic_vector(ADRWIDTH-1 downto 0);
IWordxDI : in std_logic_vector(WRDWIDTH-1 downto 0);
SPCclrxEI : in std_logic;
SPCloadxEI : in std_logic;
ContextxDO : out std_logic_vector(CONWIDTH-1 downto 0);
CyclesxDO : out std_logic_vector(CYCWIDTH-1 downto 0);
LastxSO : out std_logic);
end component;
component ScheduleCtrl
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
StartxEI : in std_logic;
RunningxSI : in std_logic;
LastxSI : in std_logic;
SwitchxEO : out std_logic;
BusyxSO : out std_logic);
end component;
component ConfigMem
generic (
CFGWIDTH : integer;
PTRWIDTH : integer;
SLCWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
CfgSlicexDI : in std_logic_vector(SLCWIDTH-1 downto 0);
LoadSlicePtrxEI : in std_logic;
SlicePtrxDI : in std_logic_vector(PTRWIDTH-1 downto 0);
ConfigWordxDO : out std_logic_vector(CFGWIDTH-1 downto 0));
end component;
component ContextMux
generic (
NINP : integer);
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InpxI : in contextArray;
OutxDO : out contextType);
end component;
component ContextSelCtrl
port (
DecEnxEI : in std_logic;
SchedEnxEI : in std_logic;
SchedBusyxSI : in std_logic;
CSREnxEO : out std_logic;
CSRMuxSO : out std_logic);
end component;
component Decoder
generic (
REGWIDTH : integer);
port (
RstxRB : in std_logic;
WrReqxEI : in std_logic;
RdReqxEI : in std_logic;
RegNrxDI : in std_logic_vector(REGWIDTH-1 downto 0);
SystRstxRBO : out std_logic;
CCloadxEO : out std_logic;
VirtContextNoxEO : out std_logic;
ContextSchedulerSelectxEO : out std_logic;
Fifo0WExEO : out std_logic;
Fifo0RExEO : out std_logic;
Fifo1WExEO : out std_logic;
Fifo1RExEO : out std_logic;
CMWExEO : out std_logic_vector(N_CONTEXTS-1 downto 0);
CMLoadPtrxEO : out std_logic_vector(N_CONTEXTS-1 downto 0);
CSRxEO : out std_logic;
EngClrCntxtxEO : out std_logic;
SSWExEO : out std_logic;
SSIAddrxDO : out std_logic_vector(SIW_ADRWIDTH-1 downto 0);
ScheduleStartxE : out std_logic;
DoutMuxSO : out std_logic_vector(2 downto 0));
end component;
component FifoCtrl
port (
RunningxSI : in std_logic;
EngInPortxEI : in std_logic;
EngOutPortxEI : in std_logic;
DecFifoWExEI : in std_logic;
DecFifoRExEI : in std_logic;
FifoMuxSO : out std_logic;
FifoWExEO : out std_logic;
FifoRExEO : out std_logic);
end component;
component CycleDnCntr
generic (
CNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CinxDI : in std_logic_vector(CNTWIDTH-1 downto 0);
OnxSO : out std_logic;
CoutxDO : out std_logic_vector(CNTWIDTH-1 downto 0));
end component;
component CycleCntCtrl
port (
DecLoadxEI : in std_logic;
SchedLoadxEI : in std_logic;
SchedBusyxSI : in std_logic;
CCLoadxEO : out std_logic;
CCMuxSO : out std_logic);
end component;
component Engine -- computation engine
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in engineConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
InPortxDI : in engineInoutDataType;
OutPortxDO : out engineInoutDataType;
InPortxEO : out std_logic_vector(N_IOP-1 downto 0);
OutPortxEO : out std_logic_vector(N_IOP-1 downto 0));
end component;
component EngClearCtrl
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
DecEngClrxEI : in std_logic;
SchedStartxEI : in std_logic;
SchedSwitchxEI : in std_logic;
SchedBusyxSI : in std_logic;
SchedEngClrxSI : in std_logic;
EngClrxEO : out std_logic);
end component;
component IOPortCtrl -- I/O port controller
generic (
CCNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in ioportConfigRec;
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
PortxEO : out std_logic);
end component;
component Row -- row of cells
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in rowConfigArray;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
InpxI : in rowInputArray;
OutxO : out rowOutputArray;
MemDataxDI : in data_vector(N_COLS-1 downto 0);
MemAddrxDO : out data_vector(N_COLS-1 downto 0);
MemDataxDO : out data_vector(N_COLS-1 downto 0);
MemCtrlxSO : out data_vector(N_COLS-1 downto 0)
);
end component;
component Cell -- cell (routing + proc. element)
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in cellConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- data io signals
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
-- memory signals
MemDataxDI : in data_word;
MemAddrxDO : out data_word;
MemDataxDO : out data_word;
MemCtrlxSO : out data_word
);
end component;
component ProcEl -- processing element
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in procConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- data io signals
InxDI : in procelInputArray;
OutxDO : out data_word;
-- memory signals
MemDataxDI : in data_word;
MemAddrxDO : out data_word;
MemDataxDO : out data_word;
MemCtrlxSO : out data_word
);
end component;
component RoutEl -- routing element
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in routConfigRec;
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
ProcElInxDO : out procelInputArray;
ProcElOutxDI : in data_word
);
end component;
component CClkGating
port (
EnxEI : in std_logic;
MClockxCI : in std_logic;
CClockxCO : out std_logic);
end component;
component Fifo
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0);
EmptyxSO : out std_logic;
FullxSO : out std_logic;
FillLevelxDO : out std_logic_vector(log2(DEPTH) downto 0));
end component;
component UpDownCounter
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
ModexSI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component FlipFlop
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end component;
component FlipFlop_Clr
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end component;
component Reg_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Reg_Clr_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Reg_AClr_En
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxABI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Rom is
generic (
DEPTH : integer
);
port (
ConfigxI : in data_vector(DEPTH-1 downto 0);
RdAddrxDI : in data_word;
RdDataxDO : out data_word
);
end component Rom;
component ContextRegFile
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
EnxEI : in std_logic;
DinxDI : in data_word;
DoutxDO : out data_word);
end component;
component Mux2to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic;
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux4to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(1 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux8to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(2 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Mux16to1
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(3 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
In8xDI : in std_logic_vector(WIDTH-1 downto 0);
In9xDI : in std_logic_vector(WIDTH-1 downto 0);
InAxDI : in std_logic_vector(WIDTH-1 downto 0);
InBxDI : in std_logic_vector(WIDTH-1 downto 0);
InCxDI : in std_logic_vector(WIDTH-1 downto 0);
InDxDI : in std_logic_vector(WIDTH-1 downto 0);
InExDI : in std_logic_vector(WIDTH-1 downto 0);
InFxDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component TristateBuf
generic (
WIDTH : integer);
port (
InxDI : in std_logic_vector(WIDTH-1 downto 0);
OExEI : in std_logic;
OutxZO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component PullBus
generic (
WIDTH : integer);
port (
ModexSI : in std_logic;
BusxZO : out std_logic_vector(WIDTH-1 downto 0));
end component;
component Pull
port (
ModexSI : in std_logic;
WirexZO : out std_logic);
end component;
end ComponentsPkg;
|
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_2
-- Module Name: Controller_Solving_Key_Equation_2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_2.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- This controls a pipeline circuit.
-- Another version each spends more area with two pipelines and two state machines
-- called solving_key_equation_4 was made.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_2 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
reg_new_value_FB_ce : out STD_LOGIC;
reg_new_value_FB_rst : out STD_LOGIC;
sel_reg_new_value_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
reg_new_value_GC_ce : out STD_LOGIC;
reg_new_value_GC_rst : out STD_LOGIC;
sel_reg_new_value_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_load_address_FB_ce : out STD_LOGIC;
ctr_load_address_FB_load : out STD_LOGIC;
ctr_load_address_FB_rst : out STD_LOGIC;
ctr_load_address_GC_ce : out STD_LOGIC;
ctr_load_address_GC_load : out STD_LOGIC;
ctr_load_address_GC_rst : out STD_LOGIC;
reg_bus_address_FB_ce : out STD_LOGIC;
reg_bus_address_GC_ce : out STD_LOGIC;
reg_calc_address_FB_ce : out STD_LOGIC;
reg_calc_address_GC_ce : out STD_LOGIC;
reg_store_address_FB_ce : out STD_LOGIC;
reg_store_address_GC_ce : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_solving_key_equation_2;
architecture Behavioral of controller_solving_key_equation_2 is
type State is (reset, load_counter, load_counter_2, load_counter_3, load_first_inv, send_first_inv_store_G2t, load_F_store_G, last_store_G, prepare_store_B_C, prepare_store_B_C_2, store_B_C, last_store_B_C, swap_F_G_B_C, no_swap_F_G_B_C, prepare_load_j, load_j, load_first_G_first_F, load_h, prepare_load_F_G, load_store_F_G, prepare_degree_B, finalize_i, prepare_i, prepare_load_B_C, load_store_B_C, prepare_final_swap, preparel_swap_address, prepare_load_sigma, prepare_load_sigma_2, load_sigma, load_store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '1';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '1';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter_3 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_first_inv =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when send_first_inv_store_G2t =>
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_F_store_G =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '1';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '1';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when last_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_store_B_C_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when store_B_C =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when last_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '1';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when no_swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_rst <= '0';
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '1';
reg_j_ce <= '1';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '1';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_F_G =>
if(i_minus_j_less_than_zero = '1') then
if(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
if(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
end if;
when prepare_degree_B =>
if(degree_B_equal_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '1';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
end if;
when prepare_i =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_load_new_value_FB <= '0';
sel_reg_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when finalize_i =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_B_C =>
if(i_minus_j_less_than_zero = '1') then
if(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when preparel_swap_address =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_sigma_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '0';
end case;
end process;
New_State : process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_counter_2;
when load_counter_2 =>
next_state <= load_counter_3;
when load_counter_3 =>
next_state <= load_first_inv;
when load_first_inv =>
next_state <= send_first_inv_store_G2t;
when send_first_inv_store_G2t =>
next_state <= load_F_store_G;
when load_F_store_G =>
if(i_equal_zero = '1') then
next_state <= last_store_G;
else
next_state <= load_F_store_G;
end if;
when last_store_G =>
next_state <= prepare_store_B_C;
when prepare_store_B_C =>
next_state <= prepare_store_B_C_2;
when prepare_store_B_C_2 =>
next_state <= store_B_C;
when store_B_C =>
if(i_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= prepare_load_j;
when no_swap_F_G_B_C =>
next_state <= prepare_load_j;
when prepare_load_j =>
next_state <= load_j;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= load_h;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
next_state <= load_store_F_G;
when load_store_F_G =>
if(i_equal_zero = '1') then
next_state <= prepare_degree_B;
else
next_state <= load_store_F_G;
end if;
when prepare_degree_B =>
next_state <= prepare_i;
when prepare_i =>
next_state <= finalize_i;
when finalize_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
next_state <= load_store_B_C;
when load_store_B_C =>
if(i_equal_zero = '1') then
if(degree_F_less_than_degree_G = '1') then
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
else
next_state <= swap_F_G_B_C;
end if;
else
next_state <= no_swap_F_G_B_C;
end if;
else
next_state <= load_store_B_C;
end if;
when prepare_final_swap =>
next_state <= preparel_swap_address;
when preparel_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= prepare_load_sigma_2;
when prepare_load_sigma_2 =>
next_state <= load_sigma;
when load_sigma =>
next_state <= load_store_sigma;
when load_store_sigma =>
if(i_equal_zero = '1') then
next_state <= final;
else
next_state <= load_store_sigma;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter is
Generic ( Tlen : integer;
Ilen : integer;
measureinterval : integer );
Port ( timer : in STD_LOGIC;
input : in STD_LOGIC;
tcount : out UNSIGNED (Tlen-1 downto 0);
icount : out UNSIGNED (Ilen-1 downto 0);
-- overflow : out STD_LOGIC;
enable : in STD_LOGIC;
strobe : out STD_LOGIC;
rst : in STD_LOGIC);
end counter;
architecture Behavioral of counter is
type states is (ST_WAIT, ST_COUNTING, ST_FINISHING, ST_OVERFLOW);
-- *** input-based signals ***
signal input_en, input_en_next : std_logic;
signal M : unsigned (icount'range);
signal icount_int, icount_next : unsigned (icount'range); -- Main counter
signal iover, iover_next : std_logic; -- Overflow of the 'input' counter
signal istate, istate_next : states;
-- *** timer-based signals ***
signal timer_en, timer_en_next : std_logic;
signal N : unsigned (tcount'range);
signal tcount_int, tcount_next : unsigned (tcount'range); -- Main counter
signal sync_ien : std_logic_vector(1 downto 0); -- Synchronizer for 'input_en'
signal tover, tover_next: std_logic; -- Overflow of the 'timer' counter
signal tstate, tstate_next : states;
signal done, done_next : std_logic;
signal strobe_next : std_logic;
-- For synchronizing the 'done' signal into the 'input' clock domain
-- Introduces a significant delay when the frequency of 'input' is
-- low, possibly enough to cause the 'timer' counter to overflow.
-- It prevents metastability problems, however, and increasing the
-- measurement time will help accuracy.
signal sync_done : std_logic_vector(1 downto 0);
-- Likewise for the 'timer_en' signal
signal sync_ten : std_logic_vector(1 downto 0);
begin
icount <= icount_int;
tcount <= tcount_int;
-- overflow <= tover or iover;
-- 'input_en' needs to be available in the 'timer' domain so that
-- the 'timer' counter knows when to start and stop counting
process(rst,timer)
begin
if rst = '1' then
sync_ien <= (others => '0');
elsif rising_edge(timer) then
sync_ien <= sync_ien(0) & input_en;
end if;
end process;
-- Main FSM-type programming of the counter
comb : process(enable, input_en, sync_ien, icount_int, timer_en, sync_ten, tcount_int, done, sync_done, M, N, tover, iover, istate, tstate)
variable input_en_new, timer_en_new, done_new : std_logic;
variable tover_new, iover_new : std_logic;
variable istate_new, tstate_new : states;
begin
input_en_new := input_en;
timer_en_new := timer_en;
done_new := done;
tcount_next <= tcount_int;
icount_next <= icount_int;
tover_new := tover;
iover_new := iover;
strobe_next <= '0';
istate_new := istate;
tstate_new := tstate;
case istate is
when ST_WAIT =>
-- DANGER: crosses clock domain
-- 'timer_en' and 'done' is in the 'timer' domain
if sync_ten(1) = '0' and sync_done(1) = '0' then
istate_new := ST_COUNTING;
-- 'input' couter is started on rising edge of 'input'
input_en_new := '1';
end if;
when ST_COUNTING =>
-- On overflow, turn off counter and wait for timer to stop
if M + "1" = "0" then
istate_new := ST_OVERFLOW;
end if;
-- DANGER: crosses clock domain
-- input done is in the 'timer' domain
if sync_done(1) = '1' then
istate_new := ST_WAIT;
input_en_new := '0'; -- Disable the counter
icount_next <= M + "1"; -- Latch out the counter result
iover_new := '0'; -- Clear any overflow
end if;
when ST_OVERFLOW =>
iover_new := '1';
input_en_new := '0'; -- Disable the counter
istate_new := ST_WAIT;
when others =>
end case;
case tstate is
when ST_WAIT =>
done_new := '0';
if sync_ien(1) = '1' then
tstate_new := ST_COUNTING;
-- 'timer' couter is started on rising edge of 'timer'
timer_en_new := '1';
end if;
when ST_COUNTING =>
if N + "1" = "0" then
tstate_new := ST_OVERFLOW;
end if;
-- Indicate when the minimum measurement interval has been reached
if N = to_unsigned(measureinterval, N'length) then
tstate_new := ST_FINISHING;
done_new := '1';
end if;
when ST_FINISHING =>
if N + "1" = "0" then
tstate_new := ST_OVERFLOW;
end if;
-- If the timer's off, signal done and valid output
if timer_en = '0' then
-- done_new := '0';
strobe_next <= '1';
tstate_new := ST_WAIT;
-- Otherwise, turn off the timer when the input counter is off
elsif sync_ien(1) = '0' then
timer_en_new := '0'; -- Disable the counter
tcount_next <= N + "1"; -- Latch out the counter result
tover_new := '0'; -- Clear any overflow
end if;
when ST_OVERFLOW =>
timer_en_new := '0'; -- Disable the counter
tover_new := '1';
done_new := '1';
if sync_ien(1) = '0' then
strobe_next <= '1';
tstate_new := ST_WAIT;
end if;
when others =>
end case;
input_en_next <= input_en_new;
timer_en_next <= timer_en_new;
done_next <= done_new;
tover_next <= tover_new;
iover_next <= iover_new;
istate_next <= istate_new;
tstate_next <= tstate_new;
end process;
-- Processes synchronous to the 'timer' clock
tmem : process(rst, timer)
begin
if rst = '1' then
timer_en <= '0';
done <= '0';
N <= (others => '0');
tcount_int <= (others => '1'); -- Nonzero, avoids 1/0 fault
tover <= '0';
strobe <= '0';
tstate <= ST_WAIT;
elsif rising_edge(timer) then
if timer_en = '1' then
N <= N + "1";
else
N <= (others => '0');
end if;
timer_en <= timer_en_next;
done <= done_next;
tcount_int <= tcount_next;
tover <= tover_next;
strobe <= strobe_next;
tstate <= tstate_next;
end if;
end process;
-- Processes synchronous to the 'input' clock
imem : process(rst, input)
begin
if rst = '1' then
input_en <= '0';
M <= (others => '0');
icount_int <= (others => '0');
iover <= '0';
istate <= ST_WAIT;
sync_done <= (others => '0');
sync_ten <= (others => '0');
elsif rising_edge(input) then
if input_en = '1' then
M <= M + "1";
else
M <= (others => '0');
end if;
input_en <= input_en_next;
icount_int <= icount_next;
iover <= iover_next;
istate <= istate_next;
sync_done <= sync_done(0) & done;
sync_ten <= sync_ten(0) & timer_en;
end if;
end process;
end Behavioral;
|
-- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert s = patterns(i).s
report "bad sum value" severity error;
assert co = patterns(i).co
report "bad carray out value" severity error;
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: main_design - Behavioral
--
-- Description: Top level of the IP processing design.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_checksum : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end main_design;
architecture Behavioral of main_design is
constant our_broadcast : std_logic_vector(31 downto 0) := our_ip or (not our_netmask);
component detect_speed_and_reassemble_bytes is
Port ( clk125Mhz : in STD_LOGIC;
-- Interface to input FIFO
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
link_10mb : out STD_LOGIC;
link_100mb : out STD_LOGIC;
link_1000mb : out STD_LOGIC;
link_full_duplex : out STD_LOGIC;
output_data_enable : out STD_LOGIC;
output_data : out STD_LOGIC_VECTOR (7 downto 0);
output_data_present : out STD_LOGIC;
output_data_error : out STD_LOGIC);
end component;
signal spaced_out_data_enable : STD_LOGIC;
signal spaced_out_data : STD_LOGIC_VECTOR (7 downto 0);
signal spaced_out_data_present : STD_LOGIC;
signal spaced_out_data_error : STD_LOGIC;
signal link_10mb : STD_LOGIC;
signal link_100mb : STD_LOGIC;
signal link_1000mb : STD_LOGIC;
signal link_full_duplex : STD_LOGIC;
component defragment_and_check_crc is
Port (
clk : in STD_LOGIC;
input_data_enable : in STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
packet_data_valid : out STD_LOGIC;
packet_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal packet_data_valid : STD_LOGIC;
signal packet_data : STD_LOGIC_VECTOR (7 downto 0);
-------------------------------------------
-- Protocol handlers
-------------------------------------------
component arp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0);
-- For the wider design to send any ARP on the wire
queue_request : in std_logic;
queue_request_ip : in std_logic_vector(31 downto 0);
-- to enable IP->MAC lookup for outbound packets
update_valid : out std_logic;
update_ip : out std_logic_vector(31 downto 0);
update_mac : out std_logic_vector(47 downto 0));
end component;
signal packet_arp_request : std_logic;
signal packet_arp_granted : std_logic;
signal packet_arp_valid : std_logic;
signal packet_arp_data : std_logic_vector(7 downto 0);
signal arp_queue_request : std_logic := '0';
signal arp_queue_request_ip : std_logic_vector(31 downto 0) := (others => '0');
signal arp_update_valid : std_logic := '0';
signal arp_update_ip : std_logic_vector(31 downto 0) := (others => '0');
signal arp_update_mac : std_logic_vector(47 downto 0) := (others => '0');
component icmp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0));
end component;
signal packet_icmp_request : std_logic;
signal packet_icmp_granted : std_logic;
signal packet_icmp_valid : std_logic;
signal packet_icmp_data : std_logic_vector(7 downto 0);
component udp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '0';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal packet_udp_request : std_logic;
signal packet_udp_granted : std_logic;
signal packet_udp_valid : std_logic;
signal packet_udp_data : std_logic_vector(7 downto 0);
component tcp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal packet_tcp_request : std_logic;
signal packet_tcp_granted : std_logic;
signal packet_tcp_valid : std_logic;
signal packet_tcp_data : std_logic_vector(7 downto 0);
-------------------------------------------
-- TX Interface
-------------------------------------------
component tx_interface is
Port ( clk125MHz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
--
phy_ready : in STD_LOGIC;
link_10mb : in STD_LOGIC;
link_100mb : in STD_LOGIC;
link_1000mb : in STD_LOGIC;
---
arp_request : in STD_LOGIC;
arp_granted : out STD_LOGIC;
arp_valid : in STD_LOGIC;
arp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
icmp_request : in STD_LOGIC;
icmp_granted : out STD_LOGIC;
icmp_valid : in STD_LOGIC;
icmp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
tcp_request : in STD_LOGIC;
tcp_granted : out STD_LOGIC;
tcp_valid : in STD_LOGIC;
tcp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
udp_request : in STD_LOGIC;
udp_granted : out STD_LOGIC;
udp_valid : in STD_LOGIC;
udp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
status <= link_full_duplex & link_1000mb & link_100mb & link_10mb;
----------------------------------------------------------------------
-- As well as converting nibbles to bytes (for the slowe speeds)
-- this also strips out the preamble and start of frame symbols
----------------------------------------------------------------------
i_detect_speed_and_reassemble_bytes: detect_speed_and_reassemble_bytes port map (
clk125Mhz => clk125Mhz,
-- Interface to input FIFO
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
link_10mb => link_10mb,
link_100mb => link_100mb,
link_1000mb => link_1000mb,
link_full_duplex => link_full_duplex,
output_data_enable => spaced_out_data_enable,
output_data => spaced_out_data,
output_data_present => spaced_out_data_present,
output_data_error => spaced_out_data_error);
----------------------------------------------------------------------
-- Even at gigabit speeds the stream of bytes might include
-- gaps due to differences between the source and destination clocks.
-- This module packs all the bytes in a packet close togeather, so
-- they can be streamed though the rest of the design without using
-- a Data Enable line.
--
-- It also provides a handy place to check the FCS, allowing pacckets
-- with errors or corruption to be dropped early.
----------------------------------------------------------------------
i_defragment_and_check_crc: defragment_and_check_crc port map (
clk => clk125Mhz,
input_data_enable => spaced_out_data_enable,
input_data => spaced_out_data,
input_data_present => spaced_out_data_present,
input_data_error => spaced_out_data_error,
packet_data_valid => packet_data_valid,
packet_data => packet_data);
i_arp_handler:arp_handler generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip)
port map (
clk => clk125MHz,
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- For Sending data to the PHY
packet_out_request => packet_arp_request,
packet_out_granted => packet_arp_granted,
packet_out_valid => packet_arp_valid,
packet_out_data => packet_arp_data,
-- to enable the wider design to send ARP requests
queue_request => arp_queue_request,
queue_request_ip => arp_queue_request_ip,
-- to enable IP->MAC lookup for outbound packets
update_valid => arp_update_valid,
update_ip => arp_update_ip,
update_mac => arp_update_mac);
i_icmp_handler: icmp_handler generic map (
our_mac => our_mac,
our_ip => our_ip)
port map (
clk => clk125MHz,
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- For Sending data to the PHY
packet_out_request => packet_icmp_request,
packet_out_granted => packet_icmp_granted,
packet_out_valid => packet_icmp_valid,
packet_out_data => packet_icmp_data);
i_udp_handler: udp_handler
generic map (
our_mac => our_mac,
our_ip => our_ip,
our_broadcast => our_broadcast)
port map (
clk => clk125MHz,
-- For receiving data from the PHY
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- data received over UDP. Note IP address and port numbers
-- are only valid for the first cycle of a packet each
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
-- data to be sent over UDP
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
-- For sending data to the PHY
packet_out_request => packet_udp_request,
packet_out_granted => packet_udp_granted,
packet_out_valid => packet_udp_valid,
packet_out_data => packet_udp_data);
i_tcp_handler: tcp_handler
generic map (
our_mac => our_mac,
our_ip => our_ip)
port map (
clk => clk125MHz,
-- For receiving data from the PHY
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- data received over TCP/IP
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_mac => x"EF_F9_4C_CC_B3_A0",
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
-- For sending data to the PHY
packet_out_request => packet_tcp_request,
packet_out_granted => packet_tcp_granted,
packet_out_valid => packet_tcp_valid,
packet_out_data => packet_tcp_data);
i_tx_interface: tx_interface port map (
clk125MHz => clk125MHz,
clk125Mhz90 => clk125Mhz90,
--- Link status
phy_ready => phy_ready,
link_10mb => link_10mb,
link_100mb => link_100mb,
link_1000mb => link_1000mb,
--- ARP channel
arp_request => packet_arp_request,
arp_granted => packet_arp_granted,
arp_valid => packet_arp_valid,
arp_data => packet_arp_data,
--- TCP channel
tcp_request => packet_tcp_request,
tcp_granted => packet_tcp_granted,
tcp_valid => packet_tcp_valid,
tcp_data => packet_tcp_data,
--- ICMP channel
icmp_request => packet_icmp_request,
icmp_granted => packet_icmp_granted,
icmp_valid => packet_icmp_valid,
icmp_data => packet_icmp_data,
--- UDP channel
udp_request => packet_udp_request,
udp_granted => packet_udp_granted,
udp_valid => packet_udp_valid,
udp_data => packet_udp_data,
---
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
end Behavioral; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
|
-------------------------------------------------------------------------------------
-- FILE NAME : packer_128.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - packer_128
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : Jan 10, 2015
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- 16-bits as 8 samples =128-bits
-- 12-bits as 8 samples =96-bits
-- 12-bits * 8 samples * 4 cycles = 384-bits
-- 16-bits * 8 samples * 3 cycles = 384-bits
-- When val_in = '1', this entity will accept 4 chuncks of 128-bits unpacked and output
-- 3 chucks of 128-bits packed.
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity packer_128 is
port (
clk_in : in std_logic;
rst_in : in std_logic;
val_in : in std_logic;
data_in : in std_logic_vector(127 downto 0);
val_out : out std_logic;
data_out : out std_logic_vector(127 downto 0);
test_mode : in std_logic
);
end packer_128;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of packer_128 is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_machine is (state0, state1, state2, state3);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal sm_reg : state_machine;
signal reg0 : std_logic_vector(127 downto 0);
signal sample0 : std_logic_vector(11 downto 0);
signal sample1 : std_logic_vector(11 downto 0);
signal sample2 : std_logic_vector(11 downto 0);
signal sample3 : std_logic_vector(11 downto 0);
signal sample4 : std_logic_vector(11 downto 0);
signal sample5 : std_logic_vector(11 downto 0);
signal sample6 : std_logic_vector(11 downto 0);
signal sample7 : std_logic_vector(11 downto 0);
signal sample0_cnt : std_logic_vector(11 downto 0);
signal sample1_cnt : std_logic_vector(11 downto 0);
signal sample2_cnt : std_logic_vector(11 downto 0);
signal sample3_cnt : std_logic_vector(11 downto 0);
signal sample4_cnt : std_logic_vector(11 downto 0);
signal sample5_cnt : std_logic_vector(11 downto 0);
signal sample6_cnt : std_logic_vector(11 downto 0);
signal sample7_cnt : std_logic_vector(11 downto 0);
signal counter : std_logic_vector(11 downto 0);
signal valid_reg : std_logic;
signal zero_32 : std_logic_vector(31 downto 0);
signal zero_64 : std_logic_vector(63 downto 0);
signal zero_96 : std_logic_vector(95 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
zero_96 <= (others=>'0');
zero_64 <= (others=>'0');
zero_32 <= (others=>'0');
-- Genereate a counting test pattern
process(clk_in, rst_in)
begin
if rst_in = '1' then
counter <= (others=>'0');
elsif rising_edge(clk_in) then
if val_in = '1' then
counter <= counter + 8;
end if;
end if;
end process;
sample0_cnt <= counter + 0;
sample1_cnt <= counter + 1;
sample2_cnt <= counter + 2;
sample3_cnt <= counter + 3;
sample4_cnt <= counter + 4;
sample5_cnt <= counter + 5;
sample6_cnt <= counter + 6;
sample7_cnt <= counter + 7;
-- select between test pattern or input data
process(clk_in)
begin
if rising_edge(clk_in) then
valid_reg <= val_in;
if test_mode = '0' then
sample0 <= data_in(11 downto 0);
sample1 <= data_in(27 downto 16);
sample2 <= data_in(43 downto 32);
sample3 <= data_in(59 downto 48);
sample4 <= data_in(75 downto 64);
sample5 <= data_in(91 downto 80);
sample6 <= data_in(107 downto 96);
sample7 <= data_in(123 downto 112);
else
sample0 <= sample0_cnt;
sample1 <= sample1_cnt;
sample2 <= sample2_cnt;
sample3 <= sample3_cnt;
sample4 <= sample4_cnt;
sample5 <= sample5_cnt;
sample6 <= sample6_cnt;
sample7 <= sample7_cnt;
end if;
end if;
end process;
-- packing state machine
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
data_out <= (others=>'0');
val_out <= '0';
reg0 <= (others=>'0');
sm_reg <= state0;
else
--default
val_out <= '0';
case sm_reg is
when state0 =>
if valid_reg = '1' then
sm_reg <= state1;
reg0 <= zero_32 & sample7 & sample6 & sample5 &
sample4 & sample3 & sample2 & sample1 & sample0;
end if;
when state1 =>
sm_reg <= state2;
val_out <= '1';
data_out <= sample2(7 downto 0) & sample1 & sample0 & reg0(95 downto 0);
reg0 <= zero_64 & sample7 & sample6 & sample5 &
sample4 & sample3 & sample2(11 downto 8);
when state2 =>
sm_reg <= state3;
val_out <= '1';
data_out <= sample5(3 downto 0) & sample4 & sample3 & sample2 &
sample1 & sample0 & reg0(63 downto 0);
reg0 <= zero_96 & sample7 & sample6 & sample5(11 downto 4);
when state3 =>
sm_reg <= state0;
val_out <= '1';
data_out <= sample7 & sample6 & sample5 & sample4 & sample3 &
sample2 & sample1 & sample0 & reg0(31 downto 0);
when others =>
sm_reg <= state0;
end case;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
library ieee;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_1164.all;
use ieee.Numeric_std.all;
entity x_registers is
port(
clk : in std_logic;
w_en : in std_logic;
r_en : in std_logic;
d_in : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(7 downto 0);
rst_n : in std_logic;
d_out : out std_logic_vector(31 downto 0)
);
type reg_mux_out is array(31 downto 0) of std_logic_vector(31 downto 0);
end x_registers;
architecture desc of x_registers is
component reg_x
port(
clk, rst_n : in std_logic;
sel : in std_logic;
w_enable : in std_logic;
r_enable : in std_logic;
d_in : in std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0)
);
end component;
signal reg_sel : std_logic_vector(31 downto 0);
signal reg_mux : reg_mux_out;
begin
GEN_R: for i in 0 to 31 generate
reg_x_i: reg_x port map(clk, rst_n, reg_sel(i), w_en, r_en, d_in, reg_mux(i));
end generate;
d_out <= reg_mux(to_integer(unsigned(addr)));
end desc; |
-- -------------------------------------------------------------
--
-- Entity Declaration for di_tnr_ctrl
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Version: Revision: 1.3 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity di_tnr_ctrl
--
entity di_tnr_ctrl is
-- Generics:
-- No Generated Generics for Entity di_tnr_ctrl
-- Generated Port Declaration:
port(
-- Generated Port for Entity di_tnr_ctrl
af_c0_o : out std_ulogic ;
af_c1_o : out std_ulogic;
af_p0_i : in std_ulogic;
al_c0_o : out std_ulogic;
al_c1_o : out std_ulogic;
al_c2_o : out std_ulogic;
al_p0_i : in std_ulogic;
ap_c0_o : out std_ulogic;
ap_c1_o : out std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
clkin : in std_ulogic;
field_p0_i : in std_ulogic;
fieldc_c1_o : out std_ulogic;
fieldy0_c1_o : out std_ulogic;
fieldy1_c1_o : out std_ulogic;
frafiesel_iic_i : in std_ulogic;
hsync_c1_o : out std_ulogic;
hsync_p0_i : in std_ulogic;
hsync_p0_o : out std_ulogic;
req_p1_o : out std_ulogic;
tnrmdnr4c_iic_i : in std_ulogic;
tnrnr4y_iic_i : in std_ulogic;
uen_c1_o : out std_ulogic;
uen_p0_i : in std_ulogic;
vsync_c1_o : out std_ulogic;
vsync_p0_i : in std_ulogic
-- End of Generated Port for Entity di_tnr_ctrl
);
end di_tnr_ctrl;
--
-- End of Generated Entity di_tnr_ctrl
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 3);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0);
in2 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNHQFFAUXQ is
signal data_muxin : std_logic_vector(74 downto 0);
Begin
data_muxin <= in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 3,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 3);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0);
in2 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNHQFFAUXQ is
signal data_muxin : std_logic_vector(74 downto 0);
Begin
data_muxin <= in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 3,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 3);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0);
in2 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNHQFFAUXQ is
signal data_muxin : std_logic_vector(74 downto 0);
Begin
data_muxin <= in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 3,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 3);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0);
in2 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNHQFFAUXQ is
signal data_muxin : std_logic_vector(74 downto 0);
Begin
data_muxin <= in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 3,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity write_file is
port (clock: in std_logic;
message: in std_logic_vector(14 downto 0)
);
end write_file;
architecture behavioral of write_file is
signal counter_write: std_logic_vector(2 downto 0)
:= "000";
begin
process(clock)
file file_pointer : text;
variable line_content : string(1 to 15);
variable line_num : line;
variable i,j : integer := 0;
variable char : character:='0';
begin
if (clock'event and clock='1') then
counter_write <= counter_write + 1;
if(i = 0 and counter_write = "111") then
file_open(file_pointer,"write.txt",write_mode);
end if;
if (counter_write = "111") then
for j in 0 to 14 loop
if(message(j) = '0') then
line_content(15-j) := '0';
else
line_content(15-j) := '1';
end if;
end loop;
write(line_num,line_content);
writeline (file_pointer,line_num);
i := 1;
counter_write <= "001";
end if;
end if;
end process;
end behavioral;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity registered_comp_add is
port (clk: in std_logic;
a, b: in integer range 0 to 7;
reg_comp: out std_logic;
reg_sum: out integer range 0 to 15;);
end entity;
------------------------------
architecture circuit of registered_comp_add is
signal comp: std_logic;
signal sum: integer range 0 to 15;
begin
comp <= '1' when a > b else '0';
sum <= a + b;
process (clk, rst)
begin
if (clk'event and clk = '1') then
reg_comp <= comp;
reg_sum <= sum;
end if;
end process
end architecture;
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is
(idle, write, read, done);
type state_machine is
(idle, write, read, done);
begin
end architecture RTL;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
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|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity test_data is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(6 downto 0)
);
end test_data;
architecture augh of test_data is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity test_data is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(6 downto 0)
);
end test_data;
architecture augh of test_data is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity test_data is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(6 downto 0)
);
end test_data;
architecture augh of test_data is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
write_ff00 : in std_logic := '0';
-- io interface for local cpu
io_req : in t_io_req; -- we get an 8K range
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture gideon of command_interface is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal io_ram_en : std_logic;
signal io_ram_rdata : std_logic_vector(7 downto 0);
signal io_ram_ack : std_logic;
signal b_address : unsigned(10 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0);
signal b_en : std_logic;
signal b_we : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
process(clock)
begin
if rising_edge(clock) then
io_ram_ack <= io_ram_en;
end if;
end process;
io_ram_en <= io_req_ram.read or io_req_ram.write;
io_resp_ram.data <= X"00" when io_ram_ack='0' else io_ram_rdata;
io_resp_ram.ack <= io_ram_ack;
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(10 downto 0),
a_rdata => io_ram_rdata,
a_wdata => io_req_ram.data,
a_en => io_ram_en,
a_we => io_req_ram.write,
b_clock => clock,
b_address => b_address,
b_rdata => b_rdata,
b_wdata => b_wdata,
b_en => b_en,
b_we => b_we );
i_protocol: entity work.command_protocol
port map (
clock => clock,
reset => reset,
-- Local CPU side
io_req => io_req_regs,
io_resp => io_resp_regs,
io_irq => io_irq,
-- slot
slot_req => slot_req,
slot_resp => slot_resp,
freeze => freeze,
write_ff00 => write_ff00,
-- memory
address => b_address,
rdata => b_rdata,
wdata => b_wdata,
en => b_en,
we => b_we );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_tlb_v2_01_a;
use osif_tlb_v2_01_a.all;
entity osif_tlb is
generic
(
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
-- tlb interface
o_tlb_rdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_wdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_tag : in std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
o_tlb_match : out std_logic;
i_tlb_we : in std_logic;
o_tlb_busy : out std_logic;
--o_tlb_wdone : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH - 1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end entity;
architecture imp of osif_tlb is
signal tlb_invalidate : std_logic;
begin
i_tlb : entity osif_tlb_v2_01_a.tlb
port map
(
clk => sys_clk,
rst => sys_reset,
i_tag => i_tlb_tag,
i_data => i_tlb_wdata,
o_data => o_tlb_rdata,
i_we => i_tlb_we,
o_busy => o_tlb_busy,
--o_wdone => o_tlb_wdone,
o_match => o_tlb_match,
i_invalidate => tlb_invalidate
);
i_tlb_dcr : entity osif_tlb_v2_01_a.tlb_dcr
generic map
(
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH
)
port map
(
clk => sys_clk,
rst => sys_reset,
o_invalidate => tlb_invalidate,
-- dcr bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite
);
end architecture;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned.conv_integer;
use work.amba.all;
use work.target.all;
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
entity dcache is
port (
rst : in std_logic;
clk : in clk_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of dcache is
constant TAG_HIGH : integer := DTAG_HIGH;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
type rdatatype is (dtag, ddata, icache, memory); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
signed : std_logic; -- signed/unsigned read
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_logic;
flush : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(3 downto 0);
icenable : std_logic; -- icache diag access
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic; -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
end record;
type snoop_hit_reg_type is record
hit : std_logic_vector(2**DOFFSET_BITS-1 downto 0);-- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);-- saved tag address
end record;
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
begin
dctrl : process(rst, r, rs, rh, dci, mcdo, ico, dcramo, ahbsi, fpuholdn)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((DLINE_SIZE -1) downto 0);
variable vmaskdbl : std_logic_vector((DLINE_SIZE/2 -1) downto 0);
variable enable : std_logic;
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable signed : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr : std_logic;
variable dparerr : std_logic;
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo;
mds := '1'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn;
tparerr := '0'; dparerr := '0';
vs.snoop := '0'; vs.writebp := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
enable := '1';
rdatasel := ddata; -- read data from cache as default
-- AHB snoop handling
if DSNOOP then
-- snoop only in cacheable areas
for i in PROC_CACHETABLE'range loop --'
if (ahbsi.haddr(31 downto 32-PROC_CACHE_ADDR_MSB) >= PROC_CACHETABLE(i).firstaddr) and
(ahbsi.haddr(31 downto 32-PROC_CACHE_ADDR_MSB) <= PROC_CACHETABLE(i).lastaddr)
then hcache := '1'; end if;
end loop;
-- save snoop tag
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := mcdo.dsnoop and hcache;
end if;
-- clear valid bits on snoop hit (or set hit bits)
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and (dcramov.dtramoutsn.tag = rs.addr(TAG_HIGH downto TAG_LOW))
then
if DSNOOP_FAST then
-- pragma translate_off
if not is_x(rs.addr(OFFSET_HIGH downto OFFSET_LOW)) then
-- pragma translate_on
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW))) := '1';
-- pragma translate_off
end if;
-- pragma translate_on
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); snoopwe := '1';
end if;
end if;
-- bypass tag data on read/write contention
if (not DSNOOP_FAST) and (rs.writebp = '1') then
dcramov.dtramout.tag := (others => '0');
dcramov.dtramout.valid := (others => '0');
end if;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or (DEBUG_UNIT and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0); signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
-- generate cache hit and valid bits
forcemiss := not dci.asi(3);
if (dcramov.dtramout.tag = dci.maddress(TAG_HIGH downto TAG_LOW)) then
hit := (not r.flush) and not tparerr;
else
hit := '0';
end if;
-- force miss on snoop hit
if DSNOOP and DSNOOP_FAST then
-- pragma translate_off
if not is_x(rh.taddr) then
-- pragma translate_on
hit := hit and not rh.hit(conv_integer(rh.taddr));
-- pragma translate_off
end if;
-- pragma translate_on
end if;
validraw := genmux(dci.maddress(LINE_HIGH downto LINE_LOW),
dcramov.dtramout.valid);
valid := validraw and not dparerr;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(3 downto 0);
v.signed := dci.signed;
end if;
-- Store buffer
wdata := r.wb.data1;
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn; v.valid := dcramov.dtramout.valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
if dci.asi(3 downto 0) = ASI_DTAG then rdatasel := dtag; end if;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
if dci.read = '1' then -- read access
if (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
end if;
else -- write access
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
if r.stpend = '0' then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then
v.hit := mcdo.cache and r.hit; twrite := v.hit;
elsif (mcdo.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or not r.asi(2)); twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.req) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000"; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.req) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
dsudata := (others => '0');
if DEBUG_UNIT and dci.dsuen = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
v.icenable := not ico.diagrdy;
dsudata := ico.diagdata;
when ASI_DTAG =>
if dci.write = '1' then
twrite := not dci.eenaddr; tdiagwrite := '1';
end if;
dsudata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout.tag;
dsudata(DLINE_SIZE -1 downto 0) := dcramov.dtramout.valid;
when ASI_DDATA =>
if dci.write = '1' then dwrite := '1'; ddiagwrite := '1'; end if;
dsudata := dcramov.ddramout.data;
when others =>
end case;
end if;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0');
align_data := (others => '0');
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout.tag;
rdata(DLINE_SIZE -1 downto 0) := dcramov.dtramout.valid;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if rdatasel = ddata then align_data := dcramov.ddramout.data;
else align_data := mcdo.data; end if;
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if maddress(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
end case;
-- select which data to update the data cache with
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatain := edata(7 downto 0) & dcramov.ddramout.data(23 downto 0);
when "01" =>
ddatain := dcramov.ddramout.data(31 downto 24) & edata(7 downto 0) &
dcramov.ddramout.data(15 downto 0);
when "10" =>
ddatain := dcramov.ddramout.data(31 downto 16) & edata(7 downto 0) &
dcramov.ddramout.data(7 downto 0);
when others =>
ddatain := dcramov.ddramout.data(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatain := edata(15 downto 0) & dcramov.ddramout.data(15 downto 0);
else
ddatain := dcramov.ddramout.data(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatain := edata;
end case;
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdata := r.wb.data2; mexc := r.mexc;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := vmaskraw;
if r.hit = '1' then vmask := r.valid or vmaskraw; end if;
if r.dstate = "000" then
vmask := dcramov.dtramout.valid or vmaskraw;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then v.valid := vmask; end if;
if tdiagwrite = '1' then -- diagnostic tag write
if DEBUG_UNIT and (dci.dsuen = '1') then
vmask := dci.maddress(DLINE_SIZE - 1 downto 0);
else
vmask := dci.edata(DLINE_SIZE - 1 downto 0);
end if;
end if;
-- cache flush
if (dci.flush or flush or mcdo.dflush) = '1' then
v.flush := '1'; v.faddr := (others => '0');
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP then
if DSNOOP_FAST then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if twrite = '1' then
-- pragma translate_off
if not is_x(taddr(OFFSET_HIGH downto OFFSET_LOW)) then
-- pragma translate_on
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := '0';
-- pragma translate_off
end if;
-- pragma translate_on
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
r.xaddress(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then vs.writebp := '1'; end if;
else
if snoopwe = '1' then twrite := '0'; end if; -- avoid write/write contention
end if;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then ddatain := mcdo.data; end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0';
end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
-- tag ram inputs
dcrami.dtramin.valid <= vmask;
dcrami.dtramin.tag <= newtag(TAG_HIGH downto TAG_LOW);
dcrami.dtramin.enable <= enable;
dcrami.dtramin.write <= twrite;
dcrami.dtraminsn.enable <= vs.snoop or snoopwe;
dcrami.dtraminsn.write <= snoopwe;
dcrami.dtraminsn.address<= snoopaddr;
-- data ram inputs
dcrami.ddramin.enable <= enable;
dcrami.ddramin.address <= taddr;
dcrami.ddramin.data <= ddatain;
dcrami.ddramin.write <= dwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock or dci.lock;
mcdi.req <= r.req;
mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush or mcdo.iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.dsudata <= dsudata; -- debug unit
-- IU data cache inputs
dco.data <= rdata;
dco.mexc <= mexc;
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
sn2 : if DSNOOP generate
reg2 : process(clk)
begin if rising_edge(clk) then rs <= cs; end if; end process;
end generate;
sn3 : if DSNOOP_FAST generate
reg3 : process(clk)
begin if rising_edge(clk) then rh <= ch; end if; end process;
end generate;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_SUB is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_SUB is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_SUB : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
begin
OP1 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) );
OP2 := SIGNED( INPUT_2(15) & INPUT_2(15 downto 0) );
OP3 := OP1 - OP2;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
|
-------------------------------------------------------------------------------
-- address_gen.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : address_gen.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI bus address generation
-- logic
-- Structure : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.conv_integer;
library axi_epc_v2_0;
use axi_epc_v2_0.ld_arith_reg;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals
-- NO_PRH_DWIDTH_MATCH - Indication that no device is employing data width
-- matching
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- NO_PRH_ASYNC - Indicates all devices are configured for
-- synchronous interface
-- ADDRCNT_WIDTH - Width of counter generating address suffix in case
-- of data width matching
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Rst - IPIC reset
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Rest for peripheral interface
-- Bus2IP_Addr - Address bus from IPIC interface
-- Dev_fifo_access - Indicates if the current access is to a FIFO like
-- - structure within the external peripheral device
-- Dev_sync - Indicates if the current device being accessed
-- is synchronous device
-- Dev_dwidth_match - Indicates if the current device employs data
-- width matching
-- Dev_dbus_width - Indicates decoded value for the data bus width
-- Async_addr_cnt_ld - Load signal for the address suffix counter for
-- asynchronous interface
-- Async_addr_cnt_ce - Enable for address suffix counter for asynchronous
-- interface
-- Sync_addr_cnt_ld - Load signal for the address suffix counter for
-- synchronous interface
-- Sync_addr_cnt_ce - Enable for address suffix counter for synchronous
-- interface
-- Addr_Int - Internal address bus for peripheral interface
-- Addr_suffix - Address suffix (lower bits of address bus) generated
-- within this module when data width matching is
-- enabled
-------------------------------------------------------------------------------
entity address_gen is
generic (
C_PRH_MAX_AWIDTH : integer;
NO_PRH_DWIDTH_MATCH : integer;
NO_PRH_SYNC : integer;
NO_PRH_ASYNC : integer;
ADDRCNT_WIDTH : integer
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
Local_Clk : in std_logic;
Local_Rst : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Dev_fifo_access : in std_logic;
Dev_sync : in std_logic;
Dev_dwidth_match : in std_logic;
Dev_dbus_width : in std_logic_vector(0 to 2);
Async_addr_cnt_ld : in std_logic;
Async_addr_cnt_ce : in std_logic;
Sync_addr_cnt_ld : in std_logic;
Sync_addr_cnt_ce : in std_logic;
Addr_Int : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Addr_suffix : out std_logic_vector(0 to ADDRCNT_WIDTH-1)
);
end entity address_gen;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of address_gen is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ADDRCNT_RST : std_logic_vector(0 to ADDRCNT_WIDTH-1)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal async_addr_cnt_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal async_addr_ld_cnt_val : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_cnt_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_ld_cnt_val : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal async_addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal addr_suffix_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: NO_DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: If no device employs data width matching, then generate
-- default values
-------------------------------------------------------------------------------
NO_DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 1 generate
Addr_suffix <= (others => '0');
Addr_Int <= Bus2IP_Addr;
end generate NO_DEV_DWIDTH_MATCH_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: If any device employs data width matching, then generate
-- address suffix, peripheral address bus, async and sync cycle
-- indications
-------------------------------------------------------------------------------
DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 0 generate
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as synchronous devices
-----------------------------------------------------------------------------
SOME_DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
---------------------------------------------------------------------------
-- Counter for address suffix generation for synchronous peripheral
-- interface
---------------------------------------------------------------------------
I_SYNC_ADDRCNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => true,
C_REG_WIDTH => ADDRCNT_WIDTH,
C_RESET_VALUE => ADDRCNT_RST,
C_LD_WIDTH => ADDRCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Local_Clk,
RST => Local_Rst,
Q => sync_addr_cnt_i,
LD => sync_addr_ld_cnt_val,
AD => "1",
LOAD => Sync_addr_cnt_ld,
OP => Sync_addr_cnt_ce
);
---------------------------------------------------------------------------
-- NAME : SYNC_ADDR_LD_VAL_PROCESS
---------------------------------------------------------------------------
-- Description: Initial load value for the address suffix counter
---------------------------------------------------------------------------
SYNC_ADDR_LD_VAL_PROCESS: process(Dev_dbus_width, Bus2IP_Addr)
begin
sync_addr_ld_cnt_val <= (others => '0');
case Dev_dbus_width is
when "001" =>
sync_addr_ld_cnt_val <=
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 1);
when "010" =>
sync_addr_ld_cnt_val <= '0' &
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 2);
when "100" =>
sync_addr_ld_cnt_val <= (others => '0');
when others =>
sync_addr_ld_cnt_val <= (others => '0');
end case;
end process SYNC_ADDR_LD_VAL_PROCESS;
---------------------------------------------------------------------------
-- NAME : SYNC_ADDR_SUFFIX_PROCESS
---------------------------------------------------------------------------
-- Description: Address suffix generation for synchronous interface
---------------------------------------------------------------------------
SYNC_ADDR_SUFFIX_PROCESS: process(Dev_dbus_width, sync_addr_cnt_i)
begin
sync_addr_suffix <= (others => '0');
case Dev_dbus_width is
when "001" =>
sync_addr_suffix <= sync_addr_cnt_i;
when "010" =>
sync_addr_suffix <= sync_addr_cnt_i(1 to ADDRCNT_WIDTH-1) & '0';
when "100" =>
sync_addr_suffix <= (others => '0');
when others =>
sync_addr_suffix <= (others => '0');
end case;
end process SYNC_ADDR_SUFFIX_PROCESS;
end generate SOME_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as asynchronous devices
-----------------------------------------------------------------------------
SOME_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 0 generate
---------------------------------------------------------------------------
-- Counter for address suffix generation for asynchronous peripheral
-- interface
---------------------------------------------------------------------------
I_ASYNC_ADDRCNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => true,
C_REG_WIDTH => ADDRCNT_WIDTH,
C_RESET_VALUE => ADDRCNT_RST,
C_LD_WIDTH => ADDRCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => Bus2IP_Rst,
Q => async_addr_cnt_i,
LD => async_addr_ld_cnt_val,
AD => "1",
LOAD => Async_addr_cnt_ld,
OP => Async_addr_cnt_ce
);
---------------------------------------------------------------------------
-- NAME : ASYNC_ADDR_LD_VAL_PROCESS
---------------------------------------------------------------------------
-- Description: Initial load value for the address suffix counter
---------------------------------------------------------------------------
ASYNC_ADDR_LD_VAL_PROCESS: process(Dev_dbus_width, Bus2IP_Addr)
begin
async_addr_ld_cnt_val <= (others => '0');
case Dev_dbus_width is
when "001" =>
async_addr_ld_cnt_val <=
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 1);
when "010" =>
async_addr_ld_cnt_val <= '0' &
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 2);
when "100" =>
async_addr_ld_cnt_val <= (others => '0');
when others =>
async_addr_ld_cnt_val <= (others => '0');
end case;
end process ASYNC_ADDR_LD_VAL_PROCESS;
---------------------------------------------------------------------------
-- NAME : ASYNC_ADDR_SUFFIX_PROCESS
---------------------------------------------------------------------------
-- Description: Address suffix generation for asynchronous interface
---------------------------------------------------------------------------
ASYNC_ADDR_SUFFIX_PROCESS: process(Dev_dbus_width, async_addr_cnt_i)
begin
async_addr_suffix <= (others => '0');
case Dev_dbus_width is
when "001" =>
async_addr_suffix <= async_addr_cnt_i;
when "010" =>
async_addr_suffix <= async_addr_cnt_i(1 to ADDRCNT_WIDTH-1) & '0';
when "100" =>
async_addr_suffix <= (others => '0');
when others =>
async_addr_suffix <= (others => '0');
end case;
end process ASYNC_ADDR_SUFFIX_PROCESS;
end generate SOME_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-----------------------------------------------------------------------------
ALL_DEV_SYNC_GEN: if NO_PRH_ASYNC = 1 generate
addr_suffix_i <= sync_addr_suffix;
end generate ALL_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-----------------------------------------------------------------------------
ALL_DEV_ASYNC_GEN: if NO_PRH_SYNC = 1 generate
addr_suffix_i <= async_addr_suffix;
end generate ALL_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: DEV_SYNC_AND_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous and some
-- asynchronous
-----------------------------------------------------------------------------
DEV_SYNC_AND_ASYNC_GEN: if NO_PRH_SYNC = 0 and NO_PRH_ASYNC = 0 generate
addr_suffix_i <= async_addr_suffix when dev_sync = '0'
else sync_addr_suffix;
end generate DEV_SYNC_AND_ASYNC_GEN;
Addr_suffix <= addr_suffix_i;
Addr_Int <= Bus2IP_Addr when (Dev_dwidth_match = '0' or Dev_fifo_access = '1')
else Bus2IP_Addr(0 to C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH-1)
& addr_suffix_i;
end generate DEV_DWIDTH_MATCH_GEN;
end architecture imp;
--------------------------------end of file------------------------------------
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package ch_20_03_a is
-- code from book:
attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
-- end of code from book
end package ch_20_03_a;
entity ch_20_03 is
end entity ch_20_03;
----------------------------------------------------------------
architecture std_cell of ch_20_03 is
use work.ch_20_03_a.all;
signal enable, clk : bit;
type state_type is (idle_state, other_state);
-- code from book:
attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- end of code from book
begin
the_fpu : block is
begin
end block the_fpu;
process is
use std.textio.all;
variable L : line;
begin
write(L, std_cell'cell_name);
writeline(output, L);
write(L, enable'pin_number);
writeline(output, L);
write(L, clk'max_wire_delay);
writeline(output, L);
write(L, idle_state[return state_type]'encoding);
writeline(output, L);
write(L, length'image(the_fpu'cell_position.x));
write(L, ' ');
write(L, length'image(the_fpu'cell_position.y));
writeline(output, L);
wait;
end process;
end architecture std_cell;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package ch_20_03_a is
-- code from book:
attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
-- end of code from book
end package ch_20_03_a;
entity ch_20_03 is
end entity ch_20_03;
----------------------------------------------------------------
architecture std_cell of ch_20_03 is
use work.ch_20_03_a.all;
signal enable, clk : bit;
type state_type is (idle_state, other_state);
-- code from book:
attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- end of code from book
begin
the_fpu : block is
begin
end block the_fpu;
process is
use std.textio.all;
variable L : line;
begin
write(L, std_cell'cell_name);
writeline(output, L);
write(L, enable'pin_number);
writeline(output, L);
write(L, clk'max_wire_delay);
writeline(output, L);
write(L, idle_state[return state_type]'encoding);
writeline(output, L);
write(L, length'image(the_fpu'cell_position.x));
write(L, ' ');
write(L, length'image(the_fpu'cell_position.y));
writeline(output, L);
wait;
end process;
end architecture std_cell;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package ch_20_03_a is
-- code from book:
attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
-- end of code from book
end package ch_20_03_a;
entity ch_20_03 is
end entity ch_20_03;
----------------------------------------------------------------
architecture std_cell of ch_20_03 is
use work.ch_20_03_a.all;
signal enable, clk : bit;
type state_type is (idle_state, other_state);
-- code from book:
attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- end of code from book
begin
the_fpu : block is
begin
end block the_fpu;
process is
use std.textio.all;
variable L : line;
begin
write(L, std_cell'cell_name);
writeline(output, L);
write(L, enable'pin_number);
writeline(output, L);
write(L, clk'max_wire_delay);
writeline(output, L);
write(L, idle_state[return state_type]'encoding);
writeline(output, L);
write(L, length'image(the_fpu'cell_position.x));
write(L, ' ');
write(L, length'image(the_fpu'cell_position.y));
writeline(output, L);
wait;
end process;
end architecture std_cell;
|
-- file: modules/output_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package output is
-- Draw game images from current game state (player position and current
-- obstacles) using vgacon.
component draw_frame
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- Input data
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
-- VGA output
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic ;
-- Control signals
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
-- Sweeps through each bit of a VGA screen.
component pixel_counter
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
lin : out integer range 0 to V_RES - 1 ;
col : out integer range 0 to H_RES - 1 ;
clock : in std_logic ;
reset : in std_logic ;
enable : in std_logic
) ;
end component ;
-- Generate a frame from the current game state.
component frame_builder
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 ; -- Number of obstacles
P_POS : natural := 20 -- Player Horizontal position
) ;
port (
-- Game state data.
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1 ;
obst_id : out integer range 0 to N_OBST - 1 ;
lin : in integer range 0 to V_RES - 1 ;
col : in integer range 0 to H_RES - 1 ;
enable : in std_logic ;
colour : out std_logic_vector(2 downto 0)
) ;
end component ;
-- Leds and 7seg display controller -- converts internal signals to led
-- outputs.
component ledcon
port (
obst_count : in integer range -2 to 255 ;
pause : in std_logic ;
game_over : in std_logic ;
hex0 : out std_logic_vector(0 to 6) ;
hex1 : out std_logic_vector(0 to 6) ;
hex2 : out std_logic_vector(0 to 6) ;
hex3 : out std_logic_vector(0 to 6) ;
ledr : out std_logic_vector(0 to 9) ;
ledg : out std_logic_vector(0 to 7)
) ;
end component ;
component hex2disp
port ( num : in std_logic_vector(3 downto 0) ; -- Input value
led : out std_logic_vector(0 to 6) -- 7seg led display signal
) ;
end component ;
-- VGA controller
component vgacon
generic (
-- When changing this, remember to keep 4:3 aspect ratio
-- Must also keep in mind that our native resolution is 640x480, and
-- you can't cross these bounds (although you will seldom have enough
-- on-chip memory to instantiate this module with higher res).
NUM_HORZ_PIXELS : natural := 128 ; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96 -- Number of vertical pixels
) ;
port (
clk27M : in std_logic ;
rstn : in std_logic ;
write_enable : in std_logic ;
write_clk : in std_logic ;
write_addr : in integer range 0 to
NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1 ;
data_in : in std_logic_vector(2 downto 0) ;
vga_clk : buffer std_logic ; -- Ideally 25.175 MHz
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic
) ;
end component ;
end output ;
|
-- *****************************************
-- * Banco de prueba para Flip Flop tipo D *
-- *****************************************
library ieee; use ieee.std_logic_1164.all;
entity ff_d_bp is
end ff_d_bp;
architecture arq_bp of ff_d_bp is
constant T: time := 20 ns; -- Período del reloj
signal clk, prueba_e: std_logic; -- Entradas
signal prueba_s: std_logic; -- Salida
begin
-- Instanciar la unidad bajo prueba
ubp: entity work.ff_d(arq)
port map(
clk => clk,
d => prueba_e,
q => prueba_s
);
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Otros estímulos
process begin
for i in 1 to 10 loop -- Esperar 10 transisiones del Flip Flop tipo D
prueba_e <= '0';
wait until falling_edge(clk);
prueba_e <= '1';
wait until falling_edge(clk);
end loop;
-- Terminar la simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_5x5Dig_TEST IS
END MultBcd_5x5Dig_TEST;
ARCHITECTURE behavior OF MultBcd_5x5Dig_TEST IS
COMPONENT MultBcd_5x5Dig
PORT(
EntradaA : IN unsigned(19 downto 0);
EntradaB : IN unsigned(19 downto 0);
SaidaZ : OUT unsigned(39 downto 0)
);
END COMPONENT;
--Inputs
signal A : unsigned(19 downto 0);
signal B : unsigned(19 downto 0);
--Outputs
signal SaidaZ : unsigned(39 downto 0) := (others => '0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MultBcd_5x5Dig PORT MAP (
EntradaA => A,
EntradaB => B,
SaidaZ => SaidaZ
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- Entrada 1 = 16
--------------------------------- MSB
A(19 downto 16) <= "0000";
A(15 downto 12) <= "0000";
A(11 downto 8) <= "0000";
A(7 downto 4) <= "0001";
A(3 downto 0) <= "0110";
--------------------------------- LSB
-- Entrada 2 = 16
--------------------------------- MSB
B(19 downto 16) <= "0000";
B(15 downto 12) <= "0000";
B(11 downto 8) <= "0000";
B(7 downto 4) <= "0001";
B(3 downto 0) <= "0110";
--------------------------------- LSB
wait for 100 ns;
-- Entrada 1 = 18
--------------------------------- MSB
A(19 downto 16) <= "0000";
A(15 downto 12) <= "0000";
A(11 downto 8) <= "0000";
A(7 downto 4) <= "0001";
A(3 downto 0) <= "1000";
--------------------------------- LSB
-- Entrada 2 = 18
--------------------------------- MSB
B(19 downto 16) <= "0000";
B(15 downto 12) <= "0000";
B(11 downto 8) <= "0000";
B(7 downto 4) <= "0001";
B(3 downto 0) <= "1000";
--------------------------------- LSB
wait;
end process;
END;
|
entity bounds20 is
end entity;
architecture test of bounds20 is
type rec1 is record
x : bit;
y : bit_vector(1 to 3);
z : integer;
end record;
signal a : bit;
signal b : bit_vector(1 to 2);
signal c : integer;
begin
p1: process is
variable r1 : rec1;
begin
r1 := ('1', "010", 42);
(a, b, c) <= r1;
wait;
end process;
end architecture;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of encoder is
begin
encoder : entity work.encoder_inferred(rtl)
generic map (
input_bits => input_bits
)
port map (
datain => datain,
dataout => dataout
);
end;
|
entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
|
entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
|
entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
|
entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
|
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