content stringlengths 1 1.04M ⌀ |
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entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:37:36 11/11/2017
-- Design Name:
-- Module Name: Writeback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Writeback is
Port ( datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
datatoreg : out STD_LOGIC_VECTOR (31 downto 0));
end Writeback;
architecture Behavioral of Writeback is
COMPONENT MuxDM
PORT(
DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a999: std_logic_vector(31 downto 0);
begin ints_muxdatamemory: MuxDM PORT MAP(
DataMem => datatomenin,
AluResult => aluresultin,
PC => pc,
RFSC => rfsourcein,
DWR => a999
);
datatoreg<=a999;
end Behavioral;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net4
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
use work.txt_utils.all;
entity regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end regFile;
architecture behav of regFile is
type regfile_t is array (31 downto 0) of word_t;
signal reg : regfile_t := (0 => ZERO, others => ZERO);
signal reg1, reg2, reg3, reg4 : word_t; -- for debug purposes only
begin process(clk, rst, readreg1, readreg2)
begin
readdata1 <= reg(vtou(readreg1));
readdata2 <= reg(vtou(readreg2));
if rst = '1' then
for i in 0 to 31 loop reg(i) <= ZERO; end loop;
elsif rising_edge(clk) then
if regWrite = '1' and writereg /= R0 then
printf(ANSI_GREEN & "R%s=%s\n", writereg, writedata);
reg(vtou(writereg)) <= writedata;
end if;
end if;
end process;
reg1 <= reg(1);
reg2 <= reg(2);
reg3 <= reg(3);
reg4 <= reg(4);
end behav;
|
library IEEE;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity instruction_memory is
generic (filename : string := "unknown.prg");
port ( I_addr : in STD_LOGIC_VECTOR (5 downto 0);
O_instr : out STD_LOGIC_VECTOR (31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
begin
process is
file progFile: TEXT;
variable l: line;
variable ch: character;
variable i, index, result: integer;
type memtype is array (0 to 15) of STD_LOGIC_VECTOR (31 downto 0);
variable ROM: memtype;
begin
-- Set all instructions to NOP
for i in 0 to 15 loop
ROM(i) := X"0000";
end loop;
index := 0;
FILE_OPEN(progFile, filename, READ_MODE);
while (not endfile(progFile)) loop
-- Read a single line (1 instruction)
readline(progFile, l);
-- Build the instruction code from the individual characters.
result := 0;
-- Translate each character to its value
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else
report "Format error on line " & integer'image(index) severity error;
end if;
ROM(index)(35 - i*4 downto 32-i*4) := std_logic_vector(to_unsigned(result, 4));
end loop;
index := index + 1;
end loop;
-- Read memory
loop
O_instr <= ROM(to_integer(unsigned(I_addr)));
wait on I_addr;
end loop;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_stratixiii
-- File: serdes_stratixiii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_stratixiii is
component altera_tse_lvds_reset_sequencer is
port (
clk : in std_logic;
reset : in std_logic;
rx_locked : in std_logic;
rx_channel_data_align : out std_logic;
pll_areset : out std_logic; -- can be ignored
rx_reset : out std_logic;
rx_cda_reset : out std_logic;
rx_reset_sequence_done : out std_logic
);
end component;
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal r3 : std_logic_vector(5 downto 0);
signal r4 : std_logic_vector(1 downto 0);
begin
bitslip_int(0) <= bitslip;
rx_in_int(0) <= rx_in;
tx_in_int <= tx_in;
rx_out <= rx_out_int;
tx_out <= tx_out_int(0);
-- output clocks
rx_clk <= rx_clk_int;
rx_pll_clk <= rx_pll_clk_int;
tx_pll_clk <= tx_pll_clk_int;
-- output synchronized resets
rx_rstn <= rx_clk_rstn_int;
rx_pll_rstn <= rx_pll_rstn_int;
tx_pll_rstn <= tx_pll_rstn_int;
--rx_cda_reset_int(0) <= rx_cda_reset_int_0;
rx_rst_int(0) <= not rx_rstn_int_0;
rx_clk_int <= rx_divfwdclk_int(0);
-- reset synchronizers
rst0 : process (rx_clk_int, rst_125) begin
if rising_edge(rx_clk_int) then
r0 <= r0(3 downto 0) & rx_locked_int;
rx_clk_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(rx_pll_clk_int) then
r1 <= r1(3 downto 0) & rx_locked_int;
rx_pll_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(tx_pll_clk_int) then
r2 <= r2(3 downto 0) & tx_locked_int;
tx_pll_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if;
end process;
-- 6 stages reset synchronizer
rst3 : process (clk_125, rst_125) begin
if rising_edge(clk_125) then
r3 <= r3(4 downto 0) & rx_locked_int;
rx_rstn_int_0 <= r3(5) and r3(4) and r3(3);
end if;
if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if;
end process;
lvds_rx0: altlvds_rx
generic map (
buffer_implementation => "RAM",
cds_mode => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
data_align_rollover => 10,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
dpa_initial_phase_value => 0,
dpll_lock_count => 0,
dpll_lock_window => 0,
--enable_clock_pin_mode => "UNUSED",
enable_dpa_align_to_rising_edge_only => "OFF",
enable_dpa_calibration => "ON",
enable_dpa_fifo => "UNUSED",
enable_dpa_initial_phase_selection => "OFF",
enable_dpa_mode => "ON",
enable_dpa_pll_calibration => "OFF",
enable_soft_cdr_mode => "ON",
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
input_data_rate => 1250,
intended_device_family => "Stratix IV",
lose_lock_on_one_change => "UNUSED",
lpm_hint => "UNUSED",
lpm_type => "altlvds_rx",
number_of_channels => 1,
outclock_resource => "AUTO",
pll_operation_mode => "UNUSED",
pll_self_reset_on_loss_lock => "UNUSED",
port_rx_channel_data_align => "PORT_USED",
port_rx_data_align => "PORT_UNUSED",
--refclk_frequency => "125.000000 MHz",
registered_data_align_input => "UNUSED",
registered_output => "ON",
reset_fifo_at_first_lock => "UNUSED",
rx_align_data_reg => "UNUSED",
sim_dpa_is_negative_ppm_drift => "OFF",
sim_dpa_net_ppm_variation => 0,
sim_dpa_output_clock_phase_shift => 0,
use_coreclock_input => "OFF",
use_dpll_rawperror => "OFF",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
x_on_bitslip => "ON"
)
port map (
pll_areset => rst_125, --pll_areset_int,
rx_channel_data_align => bitslip_int,
rx_in => rx_in_int,
rx_inclock => clk_125,
rx_reset => rx_rst_int,
rx_divfwdclk => rx_divfwdclk_int,
rx_locked => rx_locked_int,
rx_out => rx_out_int,
rx_outclock => rx_pll_clk_int,
dpa_pll_cal_busy => open,
dpa_pll_recal => '0',
pll_phasecounterselect => open,
pll_phasedone => '1',
pll_phasestep => open,
pll_phaseupdown => open,
pll_scanclk => open,
rx_cda_max => open,
rx_cda_reset => (others => '0'),
rx_coreclk => (others => '1'),
rx_data_align => '0',
rx_data_align_reset => '0',
--rx_data_reset => '0',
rx_deskew => '0',
rx_dpa_lock_reset => (others => '0'),
rx_dpa_locked => open,
--rx_dpaclock => '0',
rx_dpll_enable => (others => '1'),
rx_dpll_hold => (others => '0'),
rx_dpll_reset => (others => '0'),
rx_enable => '1',
rx_fifo_reset => (others => '0'),
rx_pll_enable => '1',
rx_readclock => '0',
rx_syncclock => '0'
);
lvds_tx0: altlvds_tx
generic map (
center_align_msb => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
coreclock_divide_by => 1,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
differential_drive => 0,
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
intended_device_family => "Stratix IV",
lpm_hint => "UNUSED",
lpm_type => "altlvds_tx",
multi_clock => "OFF",
number_of_channels => 1,
outclock_alignment => "EDGE_ALIGNED",
outclock_divide_by => 10,
outclock_duty_cycle => 50,
outclock_multiply_by => 1,
outclock_phase_shift => 0,
outclock_resource => "AUTO",
output_data_rate => 1250,
pll_self_reset_on_loss_lock => "OFF",
preemphasis_setting => 0,
--refclk_frequency => "125.00 MHz",
registered_input => "TX_CORECLK",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
vod_setting => 0
)
port map (
pll_areset => rst_125, --pll_areset_int,
tx_in => tx_in_int,
tx_inclock => clk_125,
tx_out => tx_out_int,
tx_locked => tx_locked_int,
tx_coreclock => tx_pll_clk_int,
sync_inclock => '0',
--tx_data_reset => '0',
tx_enable => '1',
tx_outclock => open,
tx_pll_enable => '1',
tx_syncclock => '0'
);
end architecture ; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity bottom is
port ( terminal Tb : electrical; -- ... );
-- not in book
terminal Tz : electrical );
-- end not in book
end entity bottom;
-- end code from book
architecture bottom_arch of bottom is
-- code from book
quantity -- ...
i_b1 through Tb to Tz; -- ...;
quantity -- ...
i_b2 through Tb to Tz; -- ...;
quantity -- ...
i_b3 through Tz to Tb; -- ... to Tb;
quantity -- ...
i_b4 through Tz to Tb; -- ... to Tb;
-- end code from book
begin
assert
-- code from book
Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
-- end code from book
;
end architecture bottom_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity other_ent is
port ( terminal Tx, Tz : electrical );
end entity other_ent;
architecture other_arch of other_ent is
begin
end architecture other_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_03a is
end entity inline_03a;
architecture test of inline_03a is
terminal Ty, Tb, Tx : electrical;
-- code from book
terminal T : electrical;
quantity -- ...
i_t1, i_t2 through T to Ty; -- ...;
quantity -- ...
i_t3 through Ty to T; -- ... to T;
-- ...
-- end code from book
begin
-- code from book
comp1 : entity work.bottom(bottom_arch)
port map ( Tb => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
comp2 : entity work.other_ent(other_arch)
port map ( Tx => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
-- end code from book
assert
-- code from book
T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
-- end code from book
;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity bottom is
port ( terminal Tb : electrical; -- ... );
-- not in book
terminal Tz : electrical );
-- end not in book
end entity bottom;
-- end code from book
architecture bottom_arch of bottom is
-- code from book
quantity -- ...
i_b1 through Tb to Tz; -- ...;
quantity -- ...
i_b2 through Tb to Tz; -- ...;
quantity -- ...
i_b3 through Tz to Tb; -- ... to Tb;
quantity -- ...
i_b4 through Tz to Tb; -- ... to Tb;
-- end code from book
begin
assert
-- code from book
Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
-- end code from book
;
end architecture bottom_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity other_ent is
port ( terminal Tx, Tz : electrical );
end entity other_ent;
architecture other_arch of other_ent is
begin
end architecture other_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_03a is
end entity inline_03a;
architecture test of inline_03a is
terminal Ty, Tb, Tx : electrical;
-- code from book
terminal T : electrical;
quantity -- ...
i_t1, i_t2 through T to Ty; -- ...;
quantity -- ...
i_t3 through Ty to T; -- ... to T;
-- ...
-- end code from book
begin
-- code from book
comp1 : entity work.bottom(bottom_arch)
port map ( Tb => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
comp2 : entity work.other_ent(other_arch)
port map ( Tx => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
-- end code from book
assert
-- code from book
T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
-- end code from book
;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity bottom is
port ( terminal Tb : electrical; -- ... );
-- not in book
terminal Tz : electrical );
-- end not in book
end entity bottom;
-- end code from book
architecture bottom_arch of bottom is
-- code from book
quantity -- ...
i_b1 through Tb to Tz; -- ...;
quantity -- ...
i_b2 through Tb to Tz; -- ...;
quantity -- ...
i_b3 through Tz to Tb; -- ... to Tb;
quantity -- ...
i_b4 through Tz to Tb; -- ... to Tb;
-- end code from book
begin
assert
-- code from book
Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
-- end code from book
;
end architecture bottom_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity other_ent is
port ( terminal Tx, Tz : electrical );
end entity other_ent;
architecture other_arch of other_ent is
begin
end architecture other_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_03a is
end entity inline_03a;
architecture test of inline_03a is
terminal Ty, Tb, Tx : electrical;
-- code from book
terminal T : electrical;
quantity -- ...
i_t1, i_t2 through T to Ty; -- ...;
quantity -- ...
i_t3 through Ty to T; -- ... to T;
-- ...
-- end code from book
begin
-- code from book
comp1 : entity work.bottom(bottom_arch)
port map ( Tb => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
comp2 : entity work.other_ent(other_arch)
port map ( Tx => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
-- end code from book
assert
-- code from book
T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
-- end code from book
;
end architecture test;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
entity array15 is
end entity;
architecture test of array15 is
function get_bits (n : natural) return bit_vector is
begin
return (1 to n => '0');
end function;
type bvv is array (natural range <>) of bit_vector;
procedure do_test (a, b : in natural) is
constant k : bvv := ( 1 => get_bits(a),
2 => get_bits(b) );
begin
report to_string(k(1)'length);
report to_string(k(2)'length);
assert a = b report "should have failed" severity failure;
end procedure;
begin
p1: process is
begin
do_test(2, 2); -- OK
do_test(3, 5); -- Error
wait;
end process;
end architecture;
|
entity t87io is
end;
use std.textio.all;
architecture behav of t87io is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
--
-- Title : second_level_CLA
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\second_level_CLA.vhd
-- Generated : Sun Nov 20 16:59:32 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {second_level_CLA} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity second_level_CLA is
port(
c0: in std_logic;
Pi: in std_logic_vector (3 downto 0);
Gi: in std_logic_vector (3 downto 0);
Ci: out std_logic_vector (4 downto 1);
P64bit: out std_logic;
G64bit: out std_logic
);
end second_level_CLA;
--}} End of automatically maintained section
architecture structural of second_level_CLA is
begin
Ci(1) <= Gi(0) or (Pi(0) and c0); --C1 = c4
Ci(2) <= Gi(1) or (Pi(1) and Gi(0)) or (Pi(1) and Pi(0) and c0); --C2 = c8
Ci(3) <= Gi(2) or (Pi(2) and Gi(1)) or (Pi(2) and Pi(1) and Gi(0)) or (Pi(2) and Pi(1) and Pi(0) and c0); --C3 == c12
Ci(4) <= Gi(3) or (Pi(3) and Gi(2)) or (Pi(3) and Pi(2) and Gi(1)) or (Pi(3) and Pi(2) and Pi(1) and Gi(0)) or (Pi(3) and Pi(2) and Pi(1) and Pi(0) and c0); --C4 ==c16
P64bit <= Pi(3) and Pi(2) and Pi(1) and Pi(0);
G64bit <= Gi(3) and Gi(2) and Gi(1) and Gi(0);
end structural;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(10 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 2000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 11
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "2000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "2000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFVAL "q[10..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 11 0 @q 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 77
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_BeebAdapter.vhd
-- /___/ /\ Timestamp : 21/04/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_BeebAdapter
--Device: Spartan6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity AtomFpga_BeebAdapter is
port (
-- System oscillator
clk50 : in std_logic;
-- BBC 1MHZ Bus
clke : in std_logic;
rnw : in std_logic;
rst_n : in std_logic;
pgfc_n : in std_logic;
pgfd_n : in std_logic;
bus_addr : in std_logic_vector (7 downto 0);
bus_data : inout std_logic_vector (7 downto 0);
bus_data_dir : out std_logic;
bus_data_oel : out std_logic;
nmi : out std_logic;
irq : out std_logic;
-- SPI DAC
dac_cs_n : out std_logic;
dac_sck : out std_logic;
dac_sdi : out std_logic;
dac_ldac_n : out std_logic;
-- RAM
ram_addr : out std_logic_vector(18 downto 0);
ram_data : inout std_logic_vector(7 downto 0);
ram_cel : out std_logic;
ram_oel : out std_logic;
ram_wel : out std_logic;
-- UART
uart_rxd : in std_logic;
uart_txd : out std_logic;
-- Flash
flash_cs : out std_logic;
flash_ck : out std_logic;
flash_si : out std_logic;
flash_so : in std_logic;
-- Misc
pmod0 : out std_logic_vector(7 downto 0);
pmod1 : inout std_logic_vector(7 downto 0);
pmod2 : inout std_logic_vector(3 downto 0);
sw1 : in std_logic;
sw2 : in std_logic;
led : out std_logic
);
end AtomFpga_BeebAdapter;
architecture behavioral of AtomFpga_BeebAdapter is
-- Clock generation
signal clk0 : std_logic;
signal clk1 : std_logic;
-- signal clk2 : std_logic;
signal clkfb : std_logic;
signal clkfb_buf : std_logic;
signal clkin_buf : std_logic;
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal phi2 : std_logic;
signal ext_A : std_logic_vector(18 downto 0);
signal ext_Din : std_logic_vector(7 downto 0);
signal ext_Dout : std_logic_vector(7 downto 0);
signal ext_nWE : std_logic;
signal ext_nOE : std_logic;
signal ext_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
-- Audio mixer and DAC
constant dacwidth : integer := 16; -- this needs to match the MCP4822 frame size
signal atom_audio : std_logic;
signal sid_audio : std_logic_vector(17 downto 0);
signal cycle : std_logic_vector(6 downto 0);
signal audio_l : std_logic_vector(dacwidth - 1 downto 0);
signal audio_r : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_l : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_r : std_logic_vector(dacwidth - 1 downto 0);
signal mmc_clk : std_logic;
signal mmc_ss : std_logic;
signal mmc_mosi : std_logic;
signal mmc_miso : std_logic;
signal ps2_kbd_clk : std_logic;
signal ps2_kbd_data : std_logic;
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 128KB (32x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"020000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
------------------------------------------------
-- Clock generation
--
-- from the on-board 50MHz Oscillator
-- using a PLL for the 16/32 MHz
-- using a DCM for the 25.175 MHz (approx)
------------------------------------------------
inst_clkin_buf : IBUFG
port map (
I => clk50,
O => clkin_buf
);
inst_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16, -- 50 * 16 = 800
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50, -- 800 / 50 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 25, -- 800 / 25 = 32MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 32, -- 800 / 32 = 25MHz
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010
)
port map (
-- Output clocks
CLKFBOUT => clkfb,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
-- CLKOUT2 => clk2,
RST => '0',
-- Input clock control
CLKFBIN => clkfb_buf,
CLKIN => clkin_buf
);
inst_clkfb_buf : BUFG
port map (
I => clkfb,
O => clkfb_buf
);
inst_clk0_buf : BUFG
port map (
I => clk0,
O => clock_16
);
inst_clk1_buf : BUFG
port map (
I => clk1,
O => clock_32
);
-- inst_clk2_buf : BUFG
-- port map (
-- I => clk2,
-- O => clock_25
-- );
inst_DCM : DCM
generic map (
CLKFX_MULTIPLY => 11,
CLKFX_DIVIDE => 14,
CLKIN_PERIOD => 31.250,
CLK_FEEDBACK => "NONE"
)
port map (
CLKIN => clock_32,
CLKFB => '0',
RST => '0',
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
CLKFX => clock_25
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- The external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= (not SW1) and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Atom Fpga Core
--------------------------------------------------------
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => false,
CImplAtoMMC2 => true,
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
CImplRamRomNone => false,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => true,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clk_vga => clock_25,
clk_main => clock_32,
clk_avr => clock_32,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_kbd_clk,
ps2_data => ps2_kbd_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
phi2 => phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => open,
sid_audio_d => sid_audio,
atom_audio => atom_audio,
SDMISO => mmc_miso,
SDSS => mmc_ss,
SDCLK => mmc_clk,
SDMOSI => mmc_mosi,
uart_RxD => uart_rxd,
uart_TxD => uart_txd,
avr_RxD => '1',
avr_TxD => open,
LED1 => led, -- Green LED
LED2 => open, -- Red LED
charSet => '1',
Joystick1 => (others => '1'),
Joystick2 => (others => '1')
);
------------------------------------------------
-- Audio mixer
------------------------------------------------
process(atom_audio, sid_audio)
variable l : std_logic_vector(dacwidth - 1 downto 0);
variable r : std_logic_vector(dacwidth - 1 downto 0);
begin
-- Atom Audio is a single bit
if (atom_audio = '1') then
l := x"1000";
r := x"1000";
else
l := x"EFFF";
r := x"EFFF";
end if;
-- SID output is 18-bit unsigned
l := l + sid_audio(17 downto 2);
r := r + sid_audio(17 downto 2);
-- Currently the left and right channels are identical
audio_l <= l;
audio_r <= r;
end process;
------------------------------------------------
-- MCP4822 SPI 12-bit DAC
--
-- note: this actually takes 16-bit samples
------------------------------------------------
process(clock_16)
begin
if rising_edge(clock_16) then
cycle <= cycle + 1;
if (unsigned(cycle(5 downto 0)) < 33) then
dac_cs_n <= '0';
dac_sck <= cycle(0);
else
dac_cs_n <= '1';
dac_sck <= '0';
end if;
if (cycle(0) = '0') then
if (unsigned(cycle(5 downto 1)) = 0) then
if (cycle(6) = '0') then
dac_shift_reg_l <= audio_l;
dac_shift_reg_r <= audio_r;
end if;
dac_sdi <= cycle(6);
elsif (unsigned(cycle(5 downto 1)) < 4) then
dac_sdi <= '1';
elsif (unsigned(cycle(5 downto 1)) < 16) then
if (cycle(6) = '0') then
dac_sdi <= dac_shift_reg_l(dacwidth - 1);
dac_shift_reg_l <= dac_shift_reg_l(dacwidth - 2 downto 0) & '0';
else
dac_sdi <= dac_shift_reg_r(dacwidth - 1);
dac_shift_reg_r <= dac_shift_reg_r(dacwidth - 2 downto 0) & '0';
end if;
else
dac_sdi <= '0';
end if;
if (unsigned(cycle(6 downto 1)) = 60) then
dac_ldac_n <= '0';
else
dac_ldac_n <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_length => user_length
)
port map(
clock => clock_32,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => ext_nOE,
RAM_nWE => ext_nWE,
RAM_nCS => ext_nCS,
RAM_A => ext_A,
RAM_Din => ext_Din,
RAM_Dout => ext_Dout,
SRAM_nOE => ram_oel,
SRAM_nWE => ram_wel,
SRAM_nCS => ram_cel,
SRAM_A(20 downto 19) => open,
SRAM_A(18 downto 0) => ram_addr,
SRAM_D => ram_data,
FLASH_CS => flash_cs,
FLASH_SI => flash_si,
FLASH_CK => flash_ck,
FLASH_SO => flash_so
);
MemProcess : process (clock_32)
begin
if rising_edge(clock_32) then
ext_A <= ExternA;
ext_nCS <= not ExternCE;
ext_nOE <= not ((not ExternWE) and ExternCE and phi2);
ext_nWE <= not (ExternWE and ExternCE and phi2);
ext_Din <= ExternDin;
end if;
end process;
ExternDout <= ext_Dout;
bus_data <= (others => 'Z');
bus_data_dir <= '1';
bus_data_oel <= '1';
nmi <= '0';
irq <= '0';
pmod0 <= blue & "0" & red & "0";
pmod1 <= "ZZ" & vsync & hsync & green & "0";
pmod2 <= "Z" & mmc_clk & mmc_mosi & mmc_ss;
ps2_kbd_clk <= pmod1(6);
ps2_kbd_data <= pmod1(7);
mmc_miso <= pmod2(3);
end behavioral;
|
package pkg is
constant a : integer := 5; -- Strange but valid character: é
-- Invalid ascii character
end pkg;
|
package pkg is
constant a : integer := 5; -- Strange but valid character: é
-- Invalid ascii character
end pkg;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm5 is
port ( CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm5;
architecture BEHAVIORAL of dcm5 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF, O=>CLK0_OUT);
DCM_INST : DCM
-- DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.00 = 32 * 8 / 16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm5 is
port ( CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm5;
architecture BEHAVIORAL of dcm5 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF, O=>CLK0_OUT);
DCM_INST : DCM
-- DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.00 = 32 * 8 / 16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
entity test is
end entity test;
architecture test of test is
-- next line should fail to compile because it's not legal to assign a default value to a signal parameter
procedure proc(signal a : integer := 1) is
begin
end procedure proc;
begin
end architecture test;
architecture test2 of test is
procedure proc(signal a : integer) is
begin
end procedure proc;
begin
-- next line should also fail to compile because it's not legal to have no actual or an OPEN actual
proc(a => open);
end architecture test2;
architecture test3 of test is
procedure proc(
variable a : in integer := 1;
variable a : out integer := 1
) is
begin
end procedure proc;
begin
end architecture test3;
architecture test4 of test is
procedure proc(
variable a : in integer := 1;
variable a : inout integer := 1
) is
begin
end procedure proc;
begin
end architecture test4;
|
-----------------------------------------------------------------------------
-- Title : FF Synchronizer with Reset
-- Project : 10 Gigabit Ethernet PCS/PMA Core
-- File : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd
-- Author : Xilinx Inc.
-- Description: This module provides a parameterizable multi stage
-- FF Synchronizer with appropriate synth attributes
-- to mark ASYNC_REG and prevent SRL inference
-- An active reset is included with a paramterized
-- reset value
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic := '0'
);
end ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2;
architecture rtl of ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
signal sync1_r : std_logic_vector(C_NUM_SYNC_REGS-1 downto 0) := (others => C_RVAL);
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of sync1_r : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync1_r : signal is "true";
begin
-----------------------------------------------------------------------------
-- Synchronizer
-----------------------------------------------------------------------------
syncrst_proc : process(clk, rst)
begin
if(rst = '1') then
sync1_r <= (others => C_RVAL);
elsif(clk'event and clk = '1') then
sync1_r <= sync1_r(C_NUM_SYNC_REGS-2 downto 0) & data_in;
end if;
end process syncrst_proc;
outreg_proc : process(clk)
begin
if(clk'event and clk = '1') then
data_out <= sync1_r(C_NUM_SYNC_REGS-1);
end if;
end process outreg_proc;
end rtl;
|
-----------------------------------------------------------------------------
-- Title : FF Synchronizer with Reset
-- Project : 10 Gigabit Ethernet PCS/PMA Core
-- File : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd
-- Author : Xilinx Inc.
-- Description: This module provides a parameterizable multi stage
-- FF Synchronizer with appropriate synth attributes
-- to mark ASYNC_REG and prevent SRL inference
-- An active reset is included with a paramterized
-- reset value
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic := '0'
);
end ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2;
architecture rtl of ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
signal sync1_r : std_logic_vector(C_NUM_SYNC_REGS-1 downto 0) := (others => C_RVAL);
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of sync1_r : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync1_r : signal is "true";
begin
-----------------------------------------------------------------------------
-- Synchronizer
-----------------------------------------------------------------------------
syncrst_proc : process(clk, rst)
begin
if(rst = '1') then
sync1_r <= (others => C_RVAL);
elsif(clk'event and clk = '1') then
sync1_r <= sync1_r(C_NUM_SYNC_REGS-2 downto 0) & data_in;
end if;
end process syncrst_proc;
outreg_proc : process(clk)
begin
if(clk'event and clk = '1') then
data_out <= sync1_r(C_NUM_SYNC_REGS-1);
end if;
end process outreg_proc;
end rtl;
|
-----------------------------------------------------------------------------
-- Title : FF Synchronizer with Reset
-- Project : 10 Gigabit Ethernet PCS/PMA Core
-- File : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd
-- Author : Xilinx Inc.
-- Description: This module provides a parameterizable multi stage
-- FF Synchronizer with appropriate synth attributes
-- to mark ASYNC_REG and prevent SRL inference
-- An active reset is included with a paramterized
-- reset value
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic := '0'
);
end ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2;
architecture rtl of ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
signal sync1_r : std_logic_vector(C_NUM_SYNC_REGS-1 downto 0) := (others => C_RVAL);
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of sync1_r : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync1_r : signal is "true";
begin
-----------------------------------------------------------------------------
-- Synchronizer
-----------------------------------------------------------------------------
syncrst_proc : process(clk, rst)
begin
if(rst = '1') then
sync1_r <= (others => C_RVAL);
elsif(clk'event and clk = '1') then
sync1_r <= sync1_r(C_NUM_SYNC_REGS-2 downto 0) & data_in;
end if;
end process syncrst_proc;
outreg_proc : process(clk)
begin
if(clk'event and clk = '1') then
data_out <= sync1_r(C_NUM_SYNC_REGS-1);
end if;
end process outreg_proc;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2434.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02434ent IS
END c07s03b02x02p01n01i02434ent;
ARCHITECTURE c07s03b02x02p01n01i02434arch OF c07s03b02x02p01n01i02434ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (natural range <>, positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(0 to 1) := ( ('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0') );
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02434 - The elements of the aggregate of the one-dimensional array type do not specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02434arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2434.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02434ent IS
END c07s03b02x02p01n01i02434ent;
ARCHITECTURE c07s03b02x02p01n01i02434arch OF c07s03b02x02p01n01i02434ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (natural range <>, positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(0 to 1) := ( ('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0') );
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02434 - The elements of the aggregate of the one-dimensional array type do not specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02434arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2434.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02434ent IS
END c07s03b02x02p01n01i02434ent;
ARCHITECTURE c07s03b02x02p01n01i02434arch OF c07s03b02x02p01n01i02434ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (natural range <>, positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(0 to 1) := ( ('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0') );
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02434 - The elements of the aggregate of the one-dimensional array type do not specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02434arch;
|
architecture RTL of FIFO is
begin
with buttons select
tmp <= "000" when x"1",
"001" when x"2",
"010" when x"4",
"011" when x"8",
"100" when others;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MB_MUXCY
generic map (
C_TARGET => C_TARGET)
port map (
LO => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MB_MUXCY
generic map (
C_TARGET => C_TARGET)
port map (
LO => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MB_MUXCY
generic map (
C_TARGET => C_TARGET)
port map (
LO => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MB_MUXCY
generic map (
C_TARGET => C_TARGET)
port map (
LO => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
library ieee;
use ieee.std_logic_1164.all;
entity symmetric_pwm_tb is
end symmetric_pwm_tb;
use work.symmetric_pwm_pkg.all;
architecture behavior of symmetric_pwm_tb is
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal pwm : std_logic;
signal underflow : std_logic; -- Center of the 'on'-periode
signal overflow : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 us;
value <= x"01";
wait for 100 us;
value <= x"FE";
wait for 100 us;
value <= x"00";
wait for 100 us;
value <= x"FF";
wait for 100 us;
end process;
uut : symmetric_pwm
generic map (
WIDTH => 8)
port map (
clk_en_p => clk_en,
value_p => value,
pwm_p => pwm,
underflow_p => underflow,
overflow_p => overflow,
reset => reset,
clk => clk);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity symmetric_pwm_tb is
end symmetric_pwm_tb;
use work.symmetric_pwm_pkg.all;
architecture behavior of symmetric_pwm_tb is
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal pwm : std_logic;
signal underflow : std_logic; -- Center of the 'on'-periode
signal overflow : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 us;
value <= x"01";
wait for 100 us;
value <= x"FE";
wait for 100 us;
value <= x"00";
wait for 100 us;
value <= x"FF";
wait for 100 us;
end process;
uut : symmetric_pwm
generic map (
WIDTH => 8)
port map (
clk_en_p => clk_en,
value_p => value,
pwm_p => pwm,
underflow_p => underflow,
overflow_p => overflow,
reset => reset,
clk => clk);
end;
|
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
-- entity
entity pic_mem is
port ( clk : in std_logic;
we : in std_logic;
data_in : in std_logic_vector(0 downto 0);
tile_x : in std_logic_vector(7 downto 0);
tile_y : in std_logic_vector(6 downto 0);
player_x : in integer;
player_y : in integer;
out_pixel : out std_logic_vector(7 downto 0);
pixel_x : in unsigned(10 downto 0);
pixel_y : in unsigned(9 downto 0);
collision : out std_logic;
offset : in integer;
gap : in integer;
height : in integer;
terrain_change : out std_logic);
end pic_mem;
-- architecture
architecture Behavioral of pic_mem is
signal sprite_x_mod : integer;
signal sprite_y_mod : integer;
signal tile_pixel : std_logic_vector(7 downto 0);
signal sprite_pixel : std_logic_vector(7 downto 0);
signal background_pixel : std_logic_vector(7 downto 0) := "00000001";
constant GRID_HEIGHT : integer := 60;
constant GRID_WIDTH : integer := 128;
constant SCREEN_HEIGHT : integer := 480;
constant SCREEN_WIDTH : integer := 640;
constant TILE_SIZE : integer := 8;
constant SPRITE_SIZE : integer := 32;
-- The grid which makes up the terrain of the game
-- 8x8 Tile grid (1024 / 8) * (480 / 8) = 128 * 60 = 4800 => 4096
type grid_ram is array (0 to 7679) of std_logic_vector(0 downto 0);
signal grid_mem : grid_ram := ("0", others => "0");
-- 16x16 Sprite memory 16*16 = 256 (This is the copter design)
type sprite_ram is array (0 to 255) of std_logic_vector(7 downto 0);
signal sprite_mem : sprite_ram := (x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",
x"FF",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"1F",x"1F",x"1F",x"FF",x"FF",x"00",x"00",x"00",
x"E0",x"FF",x"00",x"00",x"00",x"00",x"FF",x"FF",x"1F",x"1F",x"1F",x"1F",x"FF",x"00",x"00",x"00",
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"1F",x"1F",x"FF",x"00",x"00",
x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"03",x"03",x"03",x"FF",x"FF",x"FF",x"FF",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"FF",x"00",x"00",x"FF",x"00",
x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00");
signal tile_addr : std_logic_vector(0 downto 0);
signal grid_coord_x : unsigned(7 downto 0); -- x tile coordinate
signal grid_coord_y : unsigned(6 downto 0); -- y tile coordinate
signal tile_sub_x : unsigned(2 downto 0); -- x pixel in the tile
signal tile_sub_y : unsigned(2 downto 0); -- y pixel in the tile
signal tmp_tile_addr : integer;
signal offset_x : unsigned (10 downto 0);
-- after this many pixels have scrolled by the terrain will change
constant TERRAIN_CHANGE_LATENCY : integer := 8;
-- Grid building signals
signal new_col, new_col_start, q, q_plus : std_logic;
signal current_row : integer := 0;
-- Tile_memory type
type tile_ram is array (0 to 127) of std_logic_vector(7 downto 0);
signal tile_mem : tile_ram :=
( x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- Transparent
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
x"49",x"49",x"92",x"92",x"92",x"92",x"92",x"92", -- BlockOfRock
x"49",x"92",x"25",x"25",x"25",x"92",x"92",x"92",
x"92",x"25",x"24",x"49",x"25",x"92",x"92",x"92",
x"92",x"92",x"25",x"24",x"49",x"25",x"92",x"49",
x"92",x"92",x"25",x"49",x"25",x"92",x"92",x"49",
x"92",x"92",x"92",x"25",x"92",x"92",x"92",x"92",
x"92",x"92",x"92",x"49",x"49",x"92",x"92",x"92",
x"92",x"92",x"49",x"49",x"49",x"92",x"92",x"92");
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92", -- One color
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92",
--x"92",x"92",x"92",x"92",x"92",x"92",x"92",x"92");
begin
-- The offset is how long into our tile grid we've traveller
-- The grid loos every 1024 tiles
--Offset
offset_x <= (pixel_x + offset) mod 1024;
--Grid coord
grid_coord_x <= offset_x(10 downto 3);
grid_coord_y <= pixel_y(9 downto 3);
--Sub pixel
tile_sub_x <= offset_x(2 downto 0);
tile_sub_y <= pixel_y(2 downto 0);
tmp_tile_addr <= (conv_integer(tile_addr) * TILE_SIZE * TILE_SIZE) + (to_integer(tile_sub_y) * TILE_SIZE) + to_integer(tile_sub_x);
--grid memory
process(clk)
begin
if rising_edge(clk) then
if (we = '1') then
grid_mem(conv_integer(tile_y) * SCREEN_WIDTH +
conv_integer(tile_x)) <= data_in;
end if;
tile_addr <= grid_mem((to_integer(grid_coord_y) * GRID_WIDTH) + to_integer(grid_coord_x));
end if;
end process;
--tile memory
process(clk)
begin
if rising_edge(clk) then
tile_pixel <= tile_mem(tmp_tile_addr);
end if;
end process;
--modulus sprite_size
sprite_x_mod <= (to_integer(pixel_x) - player_x) /2; -- mod 16
sprite_y_mod <= (to_integer(pixel_y) - player_y) /2; -- mod 16
--sprite memory
process(clk)
begin
if rising_edge(clk) then
if (pixel_x >= player_x) and (pixel_y >= player_y) then
if (pixel_x < (player_x + SPRITE_SIZE)) and (pixel_y < (player_y + SPRITE_SIZE)) then
sprite_pixel <= sprite_mem(((sprite_y_mod * (SPRITE_SIZE/2)) + sprite_x_mod) mod 256);
else
sprite_pixel <= x"00";
end if;
else
sprite_pixel <= x"00";
end if;
end if;
end process;
--pixel chooser
-- Sends the right pixel to out_pixel and sends collision signal
-- when the player overlaps with a non-transparent pixel in tile_grid
process (clk)
begin
if rising_edge(clk) then
if sprite_pixel /= x"00" then
out_pixel <= sprite_pixel;
if tile_addr /= "0" then
collision <= '1';
else
collision <= '0';
end if;
elsif tile_pixel /= x"00" then
out_pixel <= tile_pixel;
collision <= '0';
else
out_pixel <= background_pixel;
collision <= '0';
end if;
end if;
end process;
-- Sends a signal when the terrain should be updated
terrain_change <= '1' when (offset mod TERRAIN_CHANGE_LATENCY) = 1 else
'0';
process(clk)
begin
if rising_edge(clk) then
q <= q_plus;
end if;
end process;
q_plus <= '1' when (offset mod TERRAIN_CHANGE_LATENCY) = 0 else
'0';
new_col_start <= not q and q_plus;
-- Grid builder
process(clk)
begin
if rising_edge(clk) then
-- Check if it's time to start building a new column
if new_col_start = '1' then
new_col <= '1';
current_row <= 0;
-- When at the last row (60) then disable grid building, reset row counter
elsif current_row = 60 then
current_row <= 0;
new_col <= '0';
-- While grid building is enabled, place the correct tile type at the
-- current spot in the grid, depending on current height and gap
elsif new_col = '1' then
if current_row < height or current_row > (height + gap) then
grid_mem((((127 + (offset mod 1024)/8)) mod 128) + (128*current_row)) <= "1";
else
grid_mem((((127 + (offset mod 1024)/8)) mod 128) + (128*current_row)) <= "0";
end if;
current_row <= current_row + 1;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_iic.vhd
-- Version: v1.01.b
-- Description:
-- This file is the top level file that contains the IIC AXI
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf in iic_control to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282 and CR#613486
-- - Release of v1.01.b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- IIC Signals
-- sda_i -- IIC serial data input
-- sda_o -- IIC serial data output
-- sda_t -- IIC seral data output enable
-- scl_i -- IIC serial clock input
-- scl_o -- IIC serial clock output
-- scl_t -- IIC serial clock output enable
-- gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_iic is
generic (
-- FPGA Family Type specification
C_FAMILY : string := "virtex7";
-- Select the target architecture type
-- AXI Parameters
--C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9
C_S_AXI_ADDR_WIDTH : integer := 9; --9
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-- AXI IIC Feature generics
C_IIC_FREQ : integer := 100E3;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 1;
C_S_AXI_ACLK_FREQ_HZ : integer := 25E6;
C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_LEVEL : integer := 1; -- delay in nanoseconds
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port (
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
iic2intc_irpt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
--((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- IIC interface signals
sda_i : in std_logic;
sda_o : out std_logic;
sda_t : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_t : out std_logic;
gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0)
);
end entity axi_iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant C_NUM_IIC_REGS : integer := 18;
begin
X_IIC: entity axi_iic_v2_0.iic
generic map (
-- System Generics
C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers
--iic Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz
C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer]
C_GPO_WIDTH => C_GPO_WIDTH, -- [integer]
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
-- Transmit FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_TX_FIFO_EXIST => TRUE, -- [boolean]
-- Recieve FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_RC_FIFO_EXIST => TRUE, -- [boolean]
-- AXI interface generics
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9]
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32]
-- Width of the AXI Data Bus (in bits)
C_FAMILY => C_FAMILY, -- [string]
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map
(
-- System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
IIC2INTC_IRPT => iic2intc_iRPT,
-- AXI Interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IIC Bus Signals
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
GPO => gpo
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- axi_iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_iic.vhd
-- Version: v1.01.b
-- Description:
-- This file is the top level file that contains the IIC AXI
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf in iic_control to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282 and CR#613486
-- - Release of v1.01.b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- IIC Signals
-- sda_i -- IIC serial data input
-- sda_o -- IIC serial data output
-- sda_t -- IIC seral data output enable
-- scl_i -- IIC serial clock input
-- scl_o -- IIC serial clock output
-- scl_t -- IIC serial clock output enable
-- gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_iic is
generic (
-- FPGA Family Type specification
C_FAMILY : string := "virtex7";
-- Select the target architecture type
-- AXI Parameters
--C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9
C_S_AXI_ADDR_WIDTH : integer := 9; --9
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-- AXI IIC Feature generics
C_IIC_FREQ : integer := 100E3;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 1;
C_S_AXI_ACLK_FREQ_HZ : integer := 25E6;
C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_LEVEL : integer := 1; -- delay in nanoseconds
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port (
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
iic2intc_irpt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
--((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- IIC interface signals
sda_i : in std_logic;
sda_o : out std_logic;
sda_t : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_t : out std_logic;
gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0)
);
end entity axi_iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant C_NUM_IIC_REGS : integer := 18;
begin
X_IIC: entity axi_iic_v2_0.iic
generic map (
-- System Generics
C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers
--iic Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz
C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer]
C_GPO_WIDTH => C_GPO_WIDTH, -- [integer]
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
-- Transmit FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_TX_FIFO_EXIST => TRUE, -- [boolean]
-- Recieve FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_RC_FIFO_EXIST => TRUE, -- [boolean]
-- AXI interface generics
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9]
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32]
-- Width of the AXI Data Bus (in bits)
C_FAMILY => C_FAMILY, -- [string]
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map
(
-- System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
IIC2INTC_IRPT => iic2intc_iRPT,
-- AXI Interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IIC Bus Signals
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
GPO => gpo
);
end architecture RTL;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
--phy_txer : out std_ulogic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
--phy_txclk : in std_ulogic;
--phy_rxer : in std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_gtxclk => phy_gtxclk,
--phy_txer => phy_txer,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
--phy_txclk => phy_txclk,
--phy_rxer => phy_rxer,
phy_rxd => phy_rxd(3 downto 0)'delayed(2 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(2 ns),
phy_rxclk => phy_rxclk,
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => phy_int
);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 22, fname => promfile)
port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
use sys.sys_config_pkg.all;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_mmu_data_types_pkg.all;
architecture rtl of cpu_l1mem_data_pass is
type state_index_type is (
state_index_idle,
state_index_mmu_access,
state_index_bus_access
);
type state_type is array (state_index_type range state_index_type'high downto state_index_type'low) of std_ulogic;
constant state_idle : state_type := "001";
constant state_mmu_access : state_type := "010";
constant state_bus_access : state_type := "100";
type paddr_sel_index_type is (
paddr_sel_index_reg,
paddr_sel_index_incoming,
paddr_sel_index_mmu
);
type paddr_sel_type is array (paddr_sel_index_type range paddr_sel_index_type'high downto paddr_sel_index_type'low) of std_ulogic;
constant paddr_sel_reg : paddr_sel_type := "001";
constant paddr_sel_incoming : paddr_sel_type := "010";
constant paddr_sel_mmu : paddr_sel_type := "100";
type comb_type is record
state_next : state_type;
mmu_request : std_ulogic;
bus_request : std_ulogic;
bus_requested_next : std_ulogic;
incoming_request : std_ulogic;
use_incoming_request : std_ulogic;
write : std_ulogic;
incoming_size : sys_transfer_size_type;
be : std_ulogic;
size : sys_transfer_size_type;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
store_data : cpu_word_type;
incoming_paddr : cpu_paddr_type;
mmu_paddr : cpu_paddr_type;
bus_paddr_sel : paddr_sel_type;
bus_paddr : cpu_paddr_type;
paddr_next : cpu_paddr_type;
end record;
type reg_type is record
state : state_type;
bus_requested : std_ulogic;
write : std_ulogic;
be : std_ulogic;
size : sys_transfer_size_type;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
store_data : cpu_word_type;
paddr : cpu_paddr_type;
end record;
constant reg_x : reg_type := (
state => (others => 'X'),
bus_requested => 'X',
write => 'X',
be => 'X',
size => (others => 'X'),
mmuen => 'X',
cacheen => 'X',
priv => 'X',
store_data => (others => 'X'),
paddr => (others => 'X')
);
constant reg_init : reg_type := (
state => state_idle,
bus_requested => 'X',
write => 'X',
be => 'X',
size => (others => 'X'),
mmuen => 'X',
cacheen => 'X',
priv => 'X',
store_data => (others => 'X'),
paddr => (others => 'X')
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.incoming_request <= (cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_load) or
cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_store));
with r.state select
c.state_next <= (state_index_idle => not c.incoming_request,
state_index_mmu_access => c.incoming_request and cpu_l1mem_data_pass_ctrl_in.mmuen,
state_index_bus_access => c.incoming_request and not cpu_l1mem_data_pass_ctrl_in.mmuen
) when state_idle,
(state_index_idle => (cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid) and
not c.incoming_request
),
state_index_mmu_access => (not cpu_mmu_data_ctrl_out.ready or
(not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid) and
c.incoming_request)
),
state_index_bus_access => (cpu_mmu_data_ctrl_out.ready and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)
)
) when state_mmu_access,
(state_index_idle => (r.bus_requested and
sys_slave_ctrl_out.ready and
not c.incoming_request
),
state_index_mmu_access => (r.bus_requested and
sys_slave_ctrl_out.ready and
c.incoming_request and
cpu_l1mem_data_pass_ctrl_in.mmuen
),
state_index_bus_access => ((sys_slave_ctrl_out.ready and
c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen
) or
not r.bus_requested or
not sys_slave_ctrl_out.ready
)
) when state_bus_access,
(others => 'X') when others;
c.mmu_request <= r.state(state_index_idle) and c.incoming_request;
with r.state select
c.bus_request <= (c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen) when state_idle,
cpu_mmu_data_ctrl_out.ready when state_mmu_access,
(not r.bus_requested or
(c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen)) when state_bus_access,
'X' when others;
c.use_incoming_request <= (r.state(state_index_idle) or
(r.state(state_index_mmu_access) and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)) or
(r.state(state_index_bus_access) and sys_slave_ctrl_out.ready)
);
with r.state select
c.bus_requested_next <= not cpu_l1mem_data_pass_ctrl_in.mmuen and sys_slave_ctrl_out.ready when state_idle,
cpu_mmu_data_ctrl_out.ready and sys_slave_ctrl_out.ready when state_mmu_access,
r.bus_requested or sys_slave_ctrl_out.ready when state_bus_access,
'X' when others;
with c.use_incoming_request select
c.write <= cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_store) when '1',
r.write when '0',
'X' when others;
c.incoming_size(cpu_data_size_bits-1 downto 0) <= cpu_l1mem_data_pass_dp_in.size;
incoming_size_high_bits : if sys_transfer_size_bits > cpu_data_size_bits generate
c.incoming_size(sys_transfer_size_bits downto cpu_data_size_bits) <= (others => '0');
end generate;
with c.use_incoming_request select
c.size <= c.incoming_size when '1',
r.size when '0',
(others => 'X') when others;
with c.use_incoming_request select
c.mmuen <= cpu_l1mem_data_pass_ctrl_in.mmuen when '1',
r.mmuen when '0',
'X' when others;
with c.use_incoming_request select
c.cacheen <= cpu_l1mem_data_pass_ctrl_in.cacheen when '1',
r.cacheen when '0',
'X' when others;
with c.use_incoming_request select
c.priv <= cpu_l1mem_data_pass_ctrl_in.priv when '1',
r.priv when '0',
'X' when others;
with c.use_incoming_request select
c.be <= cpu_l1mem_data_pass_ctrl_in.be when '1',
r.be when '0',
'X' when others;
with c.use_incoming_request select
c.store_data <= cpu_l1mem_data_pass_dp_in.data when '1',
r.store_data when '0',
(others => 'X') when others;
incoming_paddr_vaddr_bigger : if cpu_vaddr_bits >= cpu_paddr_bits generate
c.incoming_paddr <= cpu_l1mem_data_pass_dp_in.vaddr(cpu_paddr_bits-1 downto 0);
end generate;
incoming_paddr_vaddr_smaller : if cpu_vaddr_bits < cpu_paddr_bits generate
c.incoming_paddr(cpu_paddr_bits-1 downto cpu_vaddr_bits) <= (others => '0');
c.incoming_paddr(cpu_vaddr_bits-1 downto 0) <= cpu_l1mem_data_pass_dp_in.vaddr;
end generate;
mmu_paddr_gen_0 : if cpu_ppn_bits = 0 generate
c.mmu_paddr <= r.paddr;
end generate;
mmu_paddr_gen_n : if cpu_ppn_bits > 0 generate
c.mmu_paddr <= cpu_mmu_data_dp_out.ppn & r.paddr(cpu_poffset_bits-1 downto 0);
end generate;
with r.state select
c.bus_paddr_sel <= paddr_sel_incoming when state_idle,
paddr_sel_mmu when state_mmu_access,
(paddr_sel_index_reg => not r.bus_requested or not sys_slave_ctrl_out.ready,
paddr_sel_index_incoming => r.bus_requested and sys_slave_ctrl_out.ready,
paddr_sel_index_mmu => '0'
) when state_bus_access,
(others => 'X') when others;
with c.bus_paddr_sel select
c.bus_paddr <= r.paddr when paddr_sel_reg,
c.incoming_paddr when paddr_sel_incoming,
c.mmu_paddr when paddr_sel_mmu,
(others => 'X') when others;
c.paddr_next <= c.bus_paddr;
cpu_l1mem_data_pass_ctrl_out <= (
ready => (sys_slave_ctrl_out.ready and
not r.state(state_index_mmu_access)
),
result => (
cpu_l1mem_data_result_code_index_valid => (
not ((r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
)
),
cpu_l1mem_data_result_code_index_error => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_error)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
),
cpu_l1mem_data_result_code_index_tlbmiss => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_tlbmiss))
),
cpu_l1mem_data_result_code_index_pf => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_pf))
)
)
);
cpu_l1mem_data_pass_dp_out <= (
paddr => r.paddr,
data => sys_slave_dp_out.data(cpu_word_bits-1 downto 0)
);
cpu_mmu_data_ctrl_in <= (
request => c.mmu_request,
mmuen => c.mmuen
);
sys_master_ctrl_out <= (
request => c.bus_request,
be => c.be,
write => c.write,
cacheable => c.cacheen,
priv => c.priv,
inst => '0',
burst => '0',
bwrap => 'X',
bcycles => (others => 'X')
);
sys_master_dp_out <= (
size => c.size,
paddr => (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.bus_paddr,
data => c.store_data
);
r_next <= (
state => c.state_next,
bus_requested => c.bus_requested_next,
write => c.write,
size => c.size,
mmuen => c.mmuen,
cacheen => c.cacheen,
be => c.be,
priv => c.priv,
paddr => c.paddr_next,
store_data => c.store_data
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
end;
|
package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2);
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2);
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9);
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4);
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2);
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
end package body;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_streeOg_DSP48_3 is
port (
in0: in std_logic_vector(9 - 1 downto 0);
in1: in std_logic_vector(23 - 1 downto 0);
in2: in std_logic_vector(31 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_streeOg_DSP48_3 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_streeOg is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_streeOg is
component hls_contrast_streeOg_DSP48_3 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_streeOg_DSP48_3_U : component hls_contrast_streeOg_DSP48_3
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 19/10/2008
-- File : xilinx_one_port_ram_async.vhd
--
-- Abstract : Xilinx behavioural template for ram
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- For bram
Library UNISIM;
use UNISIM.vcomponents.all;
---------------------------------------------------------------------------
Entity xilinx_one_port_ram_async is
---------------------------------------------------------------------------
generic
(
ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 16
);
port
(
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector( ADDR_WIDTH - 1 downto 0);
din : in std_logic_vector( DATA_WIDTH - 1 downto 0);
dout : out std_logic_vector( DATA_WIDTH - 1 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture xilinx_one_port_ram_async_1 of xilinx_one_port_ram_async is
---------------------------------------------------------------------------
-- type ram_type is array (2**ADDR_WIDTH-1 downto 0)
-- of std_logic_vector( DATA_WIDTH-1 downto 0);
-- signal ram: ram_type;
-- signal addr_reg : std_logic_vector( ADDR_WIDTH-1 downto 0);
begin
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (we='1') then
-- ram(to_integer(unsigned(addr)))<= din;
-- end if;
-- addr_reg <= addr;
-- end if;
-- end process;
-- dout <= ram(to_integer(unsigned(addr_reg)));
-- RAMB16_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Single-Port RAM
-- Xilinx HDL Language Template, version 10.1.3
RAMB16_S18_inst : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => dout, -- 16-bit Data Output
DOP => open, -- 2-bit parity Output
ADDR => addr, -- 10-bit Address Input
CLK => clk, -- Clock
DI => din, -- 16-bit Data Input
DIP => "00", -- 2-bit parity Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => we -- Write Enable Input
);
end architecture xilinx_one_port_ram_async_1;
|
entity issue354 is
end issue354;
architecture behav of issue354 is
signal byte : bit_vector(7 downto 0);
signal byte_too : bit_vector(7 downto 0);
begin
-- nvc doesn't like the byte_too(1) in the next line
byte(1 downto 0) <= (1 => byte_too(1), 0 => '0') when true else (others => '0');
process
begin
byte_too(0) <= '0';
byte_too(1) <= '1';
wait for 100ns;
assert byte(0) = '0';
assert byte(1) = '1';
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
entity issue354 is
end issue354;
architecture behav of issue354 is
signal byte : bit_vector(7 downto 0);
signal byte_too : bit_vector(7 downto 0);
begin
-- nvc doesn't like the byte_too(1) in the next line
byte(1 downto 0) <= (1 => byte_too(1), 0 => '0') when true else (others => '0');
process
begin
byte_too(0) <= '0';
byte_too(1) <= '1';
wait for 100ns;
assert byte(0) = '0';
assert byte(1) = '1';
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Nov 19 18:26:09 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT clk_prescaler
PORT(
in_clk : IN std_logic;
rst : in STD_LOGIC;
prescaler_value : IN std_logic_vector(4 downto 0);
out_clk : OUT std_logic
);
END COMPONENT;
COMPONENT pwm
PORT(
clk : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
top : IN std_logic_vector(31 downto 0);
duty_cycle : IN std_logic_vector(31 downto 0);
output : OUT std_logic
);
END COMPONENT;
--USER signal declarations added here, as needed for user logic
signal clk_sig : std_logic;
signal rst_sig : std_logic;
signal enable_sig : std_logic;
signal prescaler_value_sig : std_logic_vector(4 downto 0);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal control_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal top_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
-- Instantiate the Unit Under Test (UUT)
prescaler: clk_prescaler PORT MAP (
in_clk => Bus2IP_Clk,
rst => rst_sig,
prescaler_value => prescaler_value_sig,
out_clk => clk_sig
);
pwm0: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_0,
output => led0
);
pwm1: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_1,
output => led1
);
pwm2: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_2,
output => led2
);
pwm3: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_3,
output => led3
);
pwm4: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_4,
output => led4
);
pwm5: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_5,
output => led5
);
pwm6: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_6,
output => led6
);
pwm7: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_7,
output => led7
);
pwm8: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_8,
output => led8
);
pwm9: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_9,
output => led9
);
pwm10: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_10,
output => led10
);
pwm11: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_11,
output => led11
);
pwm12: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_12,
output => led12
);
pwm13: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_13,
output => led13
);
pwm14: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_14,
output => led14
);
pwm15: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_15,
output => led15
);
pwm16: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_16,
output => led16
);
pwm17: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_17,
output => led17
);
pwm18: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_18,
output => led18
);
pwm19: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_19,
output => led19
);
pwm20: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_20,
output => led20
);
pwm21: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_21,
output => led21
);
pwm22: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_22,
output => led22
);
pwm23: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_23,
output => led23
);
pwm24: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_24,
output => led24
);
pwm25: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_25,
output => led25
);
pwm26: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_26,
output => led26
);
pwm27: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_27,
output => led27
);
pwm28: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_28,
output => led28
);
pwm29: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_29,
output => led29
);
enable_sig <= control_reg(0);
rst_sig <= control_reg(1) or not Bus2IP_Resetn;
prescaler_value_sig <= control_reg(6 downto 2);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
control_reg <= (others => '0');
top_reg <= (others => '0');
duty_cycle_reg_0 <= (others => '0');
duty_cycle_reg_1 <= (others => '0');
duty_cycle_reg_2 <= (others => '0');
duty_cycle_reg_3 <= (others => '0');
duty_cycle_reg_4 <= (others => '0');
duty_cycle_reg_5 <= (others => '0');
duty_cycle_reg_6 <= (others => '0');
duty_cycle_reg_7 <= (others => '0');
duty_cycle_reg_8 <= (others => '0');
duty_cycle_reg_9 <= (others => '0');
duty_cycle_reg_10 <= (others => '0');
duty_cycle_reg_11 <= (others => '0');
duty_cycle_reg_12 <= (others => '0');
duty_cycle_reg_13 <= (others => '0');
duty_cycle_reg_14 <= (others => '0');
duty_cycle_reg_15 <= (others => '0');
duty_cycle_reg_16 <= (others => '0');
duty_cycle_reg_17 <= (others => '0');
duty_cycle_reg_18 <= (others => '0');
duty_cycle_reg_19 <= (others => '0');
duty_cycle_reg_20 <= (others => '0');
duty_cycle_reg_21 <= (others => '0');
duty_cycle_reg_22 <= (others => '0');
duty_cycle_reg_23 <= (others => '0');
duty_cycle_reg_24 <= (others => '0');
duty_cycle_reg_25 <= (others => '0');
duty_cycle_reg_26 <= (others => '0');
duty_cycle_reg_27 <= (others => '0');
duty_cycle_reg_28 <= (others => '0');
duty_cycle_reg_29 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
control_reg(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
top_reg(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, control_reg, top_reg, duty_cycle_reg_0, duty_cycle_reg_1, duty_cycle_reg_2, duty_cycle_reg_3, duty_cycle_reg_4, duty_cycle_reg_5, duty_cycle_reg_6, duty_cycle_reg_7, duty_cycle_reg_8, duty_cycle_reg_9, duty_cycle_reg_10, duty_cycle_reg_11, duty_cycle_reg_12, duty_cycle_reg_13, duty_cycle_reg_14, duty_cycle_reg_15, duty_cycle_reg_16, duty_cycle_reg_17, duty_cycle_reg_18, duty_cycle_reg_19, duty_cycle_reg_20, duty_cycle_reg_21, duty_cycle_reg_22, duty_cycle_reg_23, duty_cycle_reg_24, duty_cycle_reg_25, duty_cycle_reg_26, duty_cycle_reg_27, duty_cycle_reg_28, duty_cycle_reg_29 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= control_reg;
when "01000000000000000000000000000000" => slv_ip2bus_data <= top_reg;
when "00100000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_0;
when "00010000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_1;
when "00001000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_2;
when "00000100000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_3;
when "00000010000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_4;
when "00000001000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_5;
when "00000000100000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_6;
when "00000000010000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_7;
when "00000000001000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_8;
when "00000000000100000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_9;
when "00000000000010000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_10;
when "00000000000001000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_11;
when "00000000000000100000000000000000" => slv_ip2bus_data <= duty_cycle_reg_12;
when "00000000000000010000000000000000" => slv_ip2bus_data <= duty_cycle_reg_13;
when "00000000000000001000000000000000" => slv_ip2bus_data <= duty_cycle_reg_14;
when "00000000000000000100000000000000" => slv_ip2bus_data <= duty_cycle_reg_15;
when "00000000000000000010000000000000" => slv_ip2bus_data <= duty_cycle_reg_16;
when "00000000000000000001000000000000" => slv_ip2bus_data <= duty_cycle_reg_17;
when "00000000000000000000100000000000" => slv_ip2bus_data <= duty_cycle_reg_18;
when "00000000000000000000010000000000" => slv_ip2bus_data <= duty_cycle_reg_19;
when "00000000000000000000001000000000" => slv_ip2bus_data <= duty_cycle_reg_20;
when "00000000000000000000000100000000" => slv_ip2bus_data <= duty_cycle_reg_21;
when "00000000000000000000000010000000" => slv_ip2bus_data <= duty_cycle_reg_22;
when "00000000000000000000000001000000" => slv_ip2bus_data <= duty_cycle_reg_23;
when "00000000000000000000000000100000" => slv_ip2bus_data <= duty_cycle_reg_24;
when "00000000000000000000000000010000" => slv_ip2bus_data <= duty_cycle_reg_25;
when "00000000000000000000000000001000" => slv_ip2bus_data <= duty_cycle_reg_26;
when "00000000000000000000000000000100" => slv_ip2bus_data <= duty_cycle_reg_27;
when "00000000000000000000000000000010" => slv_ip2bus_data <= duty_cycle_reg_28;
when "00000000000000000000000000000001" => slv_ip2bus_data <= duty_cycle_reg_29;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SETUP is
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end;
architecture control of SETUP is
component address_transcode
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ROW : OUT STD_LOGIC_VECTOR (9 downto 0);
COL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component create_opcode
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
component FLOW
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end component;
signal COL_A : std_logic_vector (2 downto 0);
signal COL_B : std_logic_vector (2 downto 0);
signal COL_C : std_logic_vector (2 downto 0);
signal COL_D : std_logic_vector (2 downto 0);
signal COL_E : std_logic_vector (2 downto 0);
signal COL_W : std_logic_vector (2 downto 0);
signal ROW_A : std_logic_vector (9 downto 0);
signal ROW_B : std_logic_vector (9 downto 0);
signal ROW_C : std_logic_vector (9 downto 0);
signal ROW_D : std_logic_vector (9 downto 0);
signal ROW_E : std_logic_vector (9 downto 0);
signal ROW_W : std_logic_vector (9 downto 0);
signal OPCODE_0 : std_logic_vector (5 downto 0);
signal OPCODE_1 : std_logic_vector (5 downto 0);
signal OPCODE_2 : std_logic_vector (5 downto 0);
signal OPCODE_3 : std_logic_vector (5 downto 0);
signal OPCODE_4 : std_logic_vector (5 downto 0);
signal OPCODE_5 : std_logic_vector (5 downto 0);
signal OPCODE_6 : std_logic_vector (5 downto 0);
signal OPCODE_7 : std_logic_vector (5 downto 0);
signal equality_0 : std_logic;
signal equality_1 : std_logic;
signal equality_2 : std_logic;
signal equality_3 : std_logic;
signal equality_4 : std_logic;
signal equality_5 : std_logic;
signal equality_6 : std_logic;
signal equality_7 : std_logic;
begin
transcode_a : address_transcode PORT MAP (
ADDRESS => ADDRESS_A,
ROW => ROW_A,
COL => COL_A
);
transcode_b : address_transcode PORT MAP (
ADDRESS => ADDRESS_B,
ROW => ROW_B,
COL => COL_B
);
transcode_c : address_transcode PORT MAP (
ADDRESS => ADDRESS_C,
ROW => ROW_C,
COL => COL_C
);
transcode_d : address_transcode PORT MAP (
ADDRESS => ADDRESS_0,
ROW => ROW_D,
COL => COL_D
);
transcode_e : address_transcode PORT MAP (
ADDRESS => ADDRESS_1,
ROW => ROW_E,
COL => COL_E
);
transcode_w : address_transcode PORT MAP (
ADDRESS => ADDRESS_W,
ROW => ROW_W,
COL => COL_W
);
opcodery : create_opcode PORT MAP (
COL_A => COL_A,
COL_B => COL_B,
COL_C => COL_C,
COL_D => COL_D,
COL_E => COL_E,
COL_W => COL_W,
W_EN => W_EN,
OPCODE_0 => OPCODE_0,
OPCODE_1 => OPCODE_1,
OPCODE_2 => OPCODE_2,
OPCODE_3 => OPCODE_3,
OPCODE_4 => OPCODE_4,
OPCODE_5 => OPCODE_5,
OPCODE_6 => OPCODE_6,
OPCODE_7 => OPCODE_7
);
RAM_0_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_0,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_0,
ADDRESS_A => ram_0_port_a,
ADDRESS_B => ram_0_port_b,
SEL_VECTOR => ram_0_sel_vector,
WREN_A => ram_0_wren_a,
WREN_B => ram_0_wren_b
);
RAM_1_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_1,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_1,
ADDRESS_A => ram_1_port_a,
ADDRESS_B => ram_1_port_b,
SEL_VECTOR => ram_1_sel_vector,
WREN_A => ram_1_wren_a,
WREN_B => ram_1_wren_b
);
RAM_2_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_2,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_2,
ADDRESS_A => ram_2_port_a,
ADDRESS_B => ram_2_port_b,
SEL_VECTOR => ram_2_sel_vector,
WREN_A => ram_2_wren_a,
WREN_B => ram_2_wren_b
);
RAM_3_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_3,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_3,
ADDRESS_A => ram_3_port_a,
ADDRESS_B => ram_3_port_b,
SEL_VECTOR => ram_3_sel_vector,
WREN_A => ram_3_wren_a,
WREN_B => ram_3_wren_b
);
RAM_4_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_4,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_4,
ADDRESS_A => ram_4_port_a,
ADDRESS_B => ram_4_port_b,
SEL_VECTOR => ram_4_sel_vector,
WREN_A => ram_4_wren_a,
WREN_B => ram_4_wren_b
);
RAM_5_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_5,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_5,
ADDRESS_A => ram_5_port_a,
ADDRESS_B => ram_5_port_b,
SEL_VECTOR => ram_5_sel_vector,
WREN_A => ram_5_wren_a,
WREN_B => ram_5_wren_b
);
RAM_6_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_6,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_6,
ADDRESS_A => ram_6_port_a,
ADDRESS_B => ram_6_port_b,
SEL_VECTOR => ram_6_sel_vector,
WREN_A => ram_6_wren_a,
WREN_B => ram_6_wren_b
);
RAM_7_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_7,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_7,
ADDRESS_A => ram_7_port_a,
ADDRESS_B => ram_7_port_b,
SEL_VECTOR => ram_7_sel_vector,
WREN_A => ram_7_wren_a,
WREN_B => ram_7_wren_b
);
STALL <= not (equality_0 and equality_1 and equality_2 and equality_3 and equality_4 and equality_5 and equality_6 and equality_7);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SETUP is
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end;
architecture control of SETUP is
component address_transcode
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ROW : OUT STD_LOGIC_VECTOR (9 downto 0);
COL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component create_opcode
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
component FLOW
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end component;
signal COL_A : std_logic_vector (2 downto 0);
signal COL_B : std_logic_vector (2 downto 0);
signal COL_C : std_logic_vector (2 downto 0);
signal COL_D : std_logic_vector (2 downto 0);
signal COL_E : std_logic_vector (2 downto 0);
signal COL_W : std_logic_vector (2 downto 0);
signal ROW_A : std_logic_vector (9 downto 0);
signal ROW_B : std_logic_vector (9 downto 0);
signal ROW_C : std_logic_vector (9 downto 0);
signal ROW_D : std_logic_vector (9 downto 0);
signal ROW_E : std_logic_vector (9 downto 0);
signal ROW_W : std_logic_vector (9 downto 0);
signal OPCODE_0 : std_logic_vector (5 downto 0);
signal OPCODE_1 : std_logic_vector (5 downto 0);
signal OPCODE_2 : std_logic_vector (5 downto 0);
signal OPCODE_3 : std_logic_vector (5 downto 0);
signal OPCODE_4 : std_logic_vector (5 downto 0);
signal OPCODE_5 : std_logic_vector (5 downto 0);
signal OPCODE_6 : std_logic_vector (5 downto 0);
signal OPCODE_7 : std_logic_vector (5 downto 0);
signal equality_0 : std_logic;
signal equality_1 : std_logic;
signal equality_2 : std_logic;
signal equality_3 : std_logic;
signal equality_4 : std_logic;
signal equality_5 : std_logic;
signal equality_6 : std_logic;
signal equality_7 : std_logic;
begin
transcode_a : address_transcode PORT MAP (
ADDRESS => ADDRESS_A,
ROW => ROW_A,
COL => COL_A
);
transcode_b : address_transcode PORT MAP (
ADDRESS => ADDRESS_B,
ROW => ROW_B,
COL => COL_B
);
transcode_c : address_transcode PORT MAP (
ADDRESS => ADDRESS_C,
ROW => ROW_C,
COL => COL_C
);
transcode_d : address_transcode PORT MAP (
ADDRESS => ADDRESS_0,
ROW => ROW_D,
COL => COL_D
);
transcode_e : address_transcode PORT MAP (
ADDRESS => ADDRESS_1,
ROW => ROW_E,
COL => COL_E
);
transcode_w : address_transcode PORT MAP (
ADDRESS => ADDRESS_W,
ROW => ROW_W,
COL => COL_W
);
opcodery : create_opcode PORT MAP (
COL_A => COL_A,
COL_B => COL_B,
COL_C => COL_C,
COL_D => COL_D,
COL_E => COL_E,
COL_W => COL_W,
W_EN => W_EN,
OPCODE_0 => OPCODE_0,
OPCODE_1 => OPCODE_1,
OPCODE_2 => OPCODE_2,
OPCODE_3 => OPCODE_3,
OPCODE_4 => OPCODE_4,
OPCODE_5 => OPCODE_5,
OPCODE_6 => OPCODE_6,
OPCODE_7 => OPCODE_7
);
RAM_0_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_0,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_0,
ADDRESS_A => ram_0_port_a,
ADDRESS_B => ram_0_port_b,
SEL_VECTOR => ram_0_sel_vector,
WREN_A => ram_0_wren_a,
WREN_B => ram_0_wren_b
);
RAM_1_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_1,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_1,
ADDRESS_A => ram_1_port_a,
ADDRESS_B => ram_1_port_b,
SEL_VECTOR => ram_1_sel_vector,
WREN_A => ram_1_wren_a,
WREN_B => ram_1_wren_b
);
RAM_2_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_2,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_2,
ADDRESS_A => ram_2_port_a,
ADDRESS_B => ram_2_port_b,
SEL_VECTOR => ram_2_sel_vector,
WREN_A => ram_2_wren_a,
WREN_B => ram_2_wren_b
);
RAM_3_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_3,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_3,
ADDRESS_A => ram_3_port_a,
ADDRESS_B => ram_3_port_b,
SEL_VECTOR => ram_3_sel_vector,
WREN_A => ram_3_wren_a,
WREN_B => ram_3_wren_b
);
RAM_4_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_4,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_4,
ADDRESS_A => ram_4_port_a,
ADDRESS_B => ram_4_port_b,
SEL_VECTOR => ram_4_sel_vector,
WREN_A => ram_4_wren_a,
WREN_B => ram_4_wren_b
);
RAM_5_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_5,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_5,
ADDRESS_A => ram_5_port_a,
ADDRESS_B => ram_5_port_b,
SEL_VECTOR => ram_5_sel_vector,
WREN_A => ram_5_wren_a,
WREN_B => ram_5_wren_b
);
RAM_6_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_6,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_6,
ADDRESS_A => ram_6_port_a,
ADDRESS_B => ram_6_port_b,
SEL_VECTOR => ram_6_sel_vector,
WREN_A => ram_6_wren_a,
WREN_B => ram_6_wren_b
);
RAM_7_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_7,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_7,
ADDRESS_A => ram_7_port_a,
ADDRESS_B => ram_7_port_b,
SEL_VECTOR => ram_7_sel_vector,
WREN_A => ram_7_wren_a,
WREN_B => ram_7_wren_b
);
STALL <= not (equality_0 and equality_1 and equality_2 and equality_3 and equality_4 and equality_5 and equality_6 and equality_7);
end;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package max_atom_pack is
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
end max_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body max_atom_pack is
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 35 loop
if ((list(i) = '0') or (list(i) = 'L')) then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
end max_atom_pack;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for MAX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- MAX7K_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_io is
generic ( operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
weak_pull_up : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01);
port ( datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
padio : inout STD_LOGIC;
dataout : out STD_LOGIC);
attribute VITAL_LEVEL0 of max_asynch_io : entity is TRUE;
end max_asynch_io;
architecture behave of max_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable tmp_dataout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
tmp_dataout := padio_ipd;
if ( padio_ipd = 'Z') then
if (prev_value = '1') then
tmp_dataout := 'H';
elsif (prev_value = '0') then
tmp_dataout := 'L';
end if;
end if;
prev_value := padio_ipd;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
if (prev_value = 'L') then
prev_value := 'L';
elsif (prev_value = 'H') then
prev_value := 'H';
else
prev_value := 'W';
end if;
end if;
tmp_padio := prev_value;
else
if (now <= 1 ps) then
tmp_padio := '0';
prev_value := 'L';
else
tmp_padio := 'X';
prev_value := 'W';
end if;
end if; -- end oe_in
if ( operation_mode = "bidir") then
if ((padio_ipd /= '1') and (padio_ipd /= '0')and (padio_ipd /= 'X')) then
tmp_dataout := prev_value;
else
tmp_dataout := to_x01z(padio_ipd);
end if;
else
tmp_dataout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_dataout := padio_ipd;
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_dataout := padio_ipd;
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
else
tmp_dataout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
else
tmp_padio := datain_ipd;
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- MAX_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_io;
entity max_io is
generic ( operation_mode : string := "input";
open_drain_output :string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in std_logic := '0';
oe : in std_logic := '1';
devoe : in std_logic := '0';
dataout : out std_logic;
padio : inout std_logic);
end max_io;
architecture structure of max_io is
signal data_out : std_logic;
component max_asynch_io
generic ( operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
padio : inout STD_LOGIC;
dataout: out STD_LOGIC);
end component;
begin
asynch_inst: max_asynch_io
generic map ( operation_mode => operation_mode,
bus_hold => bus_hold,
open_drain_output => open_drain_output,
weak_pull_up => weak_pull_up)
port map ( datain => datain,
oe => oe,
padio => padio,
dataout => data_out);
dataout <= data_out;
end structure;
--
-- MAX MCELL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_mcell is
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pterm0_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pxor_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_combout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_fpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pxor_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_pexpout : VitalDelayType01 := DefPropDelay01;
tipd_pterm0 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm1 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm2 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm3 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm4 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm5 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pxor : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_fpin : VitalDelayType01 := DefPropDelay01;
tipd_pexpin : VitalDelayType01 := DefPropDelay01);
port ( pterm0 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm1 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm2 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm3 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm4 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm5 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
fpin : in std_logic := '1';
pxor : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pexpin : in std_logic := '0';
fbkin : in std_logic;
combout : out std_logic;
regin : out std_logic;
pexpout : out std_logic );
attribute VITAL_LEVEL0 of max_asynch_mcell : entity is TRUE;
end max_asynch_mcell;
architecture vital_mcell of max_asynch_mcell is
attribute VITAL_LEVEL0 of vital_mcell : architecture is TRUE;
signal pterm0_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm1_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm2_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm3_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm4_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm5_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal fpin_ipd :std_ulogic := 'U';
signal pxor_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pexpin_ipd :std_ulogic := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (pterm0_ipd(0), pterm0(0), tipd_pterm0(0));
VitalWireDelay (pterm0_ipd(1), pterm0(1), tipd_pterm0(1));
VitalWireDelay (pterm0_ipd(2), pterm0(2), tipd_pterm0(2));
VitalWireDelay (pterm0_ipd(3), pterm0(3), tipd_pterm0(3));
VitalWireDelay (pterm0_ipd(4), pterm0(4), tipd_pterm0(4));
VitalWireDelay (pterm0_ipd(5), pterm0(5), tipd_pterm0(5));
VitalWireDelay (pterm0_ipd(6), pterm0(6), tipd_pterm0(6));
VitalWireDelay (pterm0_ipd(7), pterm0(7), tipd_pterm0(7));
VitalWireDelay (pterm0_ipd(8), pterm0(8), tipd_pterm0(8));
VitalWireDelay (pterm0_ipd(9), pterm0(9), tipd_pterm0(9));
VitalWireDelay (pterm0_ipd(10), pterm0(10), tipd_pterm0(10));
VitalWireDelay (pterm0_ipd(11), pterm0(11), tipd_pterm0(11));
VitalWireDelay (pterm0_ipd(12), pterm0(12), tipd_pterm0(12));
VitalWireDelay (pterm0_ipd(13), pterm0(13), tipd_pterm0(13));
VitalWireDelay (pterm0_ipd(14), pterm0(14), tipd_pterm0(14));
VitalWireDelay (pterm0_ipd(15), pterm0(15), tipd_pterm0(15));
VitalWireDelay (pterm0_ipd(16), pterm0(16), tipd_pterm0(16));
VitalWireDelay (pterm0_ipd(17), pterm0(17), tipd_pterm0(17));
VitalWireDelay (pterm0_ipd(18), pterm0(18), tipd_pterm0(18));
VitalWireDelay (pterm0_ipd(19), pterm0(19), tipd_pterm0(19));
VitalWireDelay (pterm0_ipd(20), pterm0(20), tipd_pterm0(20));
VitalWireDelay (pterm0_ipd(21), pterm0(21), tipd_pterm0(21));
VitalWireDelay (pterm0_ipd(22), pterm0(22), tipd_pterm0(22));
VitalWireDelay (pterm0_ipd(23), pterm0(23), tipd_pterm0(23));
VitalWireDelay (pterm0_ipd(24), pterm0(24), tipd_pterm0(24));
VitalWireDelay (pterm0_ipd(25), pterm0(25), tipd_pterm0(25));
VitalWireDelay (pterm0_ipd(26), pterm0(26), tipd_pterm0(26));
VitalWireDelay (pterm0_ipd(27), pterm0(27), tipd_pterm0(27));
VitalWireDelay (pterm0_ipd(28), pterm0(28), tipd_pterm0(28));
VitalWireDelay (pterm0_ipd(29), pterm0(29), tipd_pterm0(29));
VitalWireDelay (pterm0_ipd(30), pterm0(30), tipd_pterm0(30));
VitalWireDelay (pterm0_ipd(31), pterm0(31), tipd_pterm0(31));
VitalWireDelay (pterm0_ipd(32), pterm0(32), tipd_pterm0(32));
VitalWireDelay (pterm0_ipd(33), pterm0(33), tipd_pterm0(33));
VitalWireDelay (pterm0_ipd(34), pterm0(34), tipd_pterm0(34));
VitalWireDelay (pterm0_ipd(35), pterm0(35), tipd_pterm0(35));
VitalWireDelay (pterm0_ipd(36), pterm0(36), tipd_pterm0(36));
VitalWireDelay (pterm0_ipd(37), pterm0(37), tipd_pterm0(37));
VitalWireDelay (pterm0_ipd(38), pterm0(38), tipd_pterm0(38));
VitalWireDelay (pterm0_ipd(39), pterm0(39), tipd_pterm0(39));
VitalWireDelay (pterm0_ipd(40), pterm0(40), tipd_pterm0(40));
VitalWireDelay (pterm0_ipd(41), pterm0(41), tipd_pterm0(41));
VitalWireDelay (pterm0_ipd(42), pterm0(42), tipd_pterm0(42));
VitalWireDelay (pterm0_ipd(43), pterm0(43), tipd_pterm0(43));
VitalWireDelay (pterm0_ipd(44), pterm0(44), tipd_pterm0(44));
VitalWireDelay (pterm0_ipd(45), pterm0(45), tipd_pterm0(45));
VitalWireDelay (pterm0_ipd(46), pterm0(46), tipd_pterm0(46));
VitalWireDelay (pterm0_ipd(47), pterm0(47), tipd_pterm0(47));
VitalWireDelay (pterm0_ipd(48), pterm0(48), tipd_pterm0(48));
VitalWireDelay (pterm0_ipd(49), pterm0(49), tipd_pterm0(49));
VitalWireDelay (pterm0_ipd(50), pterm0(50), tipd_pterm0(50));
VitalWireDelay (pterm0_ipd(51), pterm0(51), tipd_pterm0(51));
VitalWireDelay (pterm1_ipd(0), pterm1(0), tipd_pterm1(0));
VitalWireDelay (pterm1_ipd(1), pterm1(1), tipd_pterm1(1));
VitalWireDelay (pterm1_ipd(2), pterm1(2), tipd_pterm1(2));
VitalWireDelay (pterm1_ipd(3), pterm1(3), tipd_pterm1(3));
VitalWireDelay (pterm1_ipd(4), pterm1(4), tipd_pterm1(4));
VitalWireDelay (pterm1_ipd(5), pterm1(5), tipd_pterm1(5));
VitalWireDelay (pterm1_ipd(6), pterm1(6), tipd_pterm1(6));
VitalWireDelay (pterm1_ipd(7), pterm1(7), tipd_pterm1(7));
VitalWireDelay (pterm1_ipd(8), pterm1(8), tipd_pterm1(8));
VitalWireDelay (pterm1_ipd(9), pterm1(9), tipd_pterm1(9));
VitalWireDelay (pterm1_ipd(10), pterm1(10), tipd_pterm1(10));
VitalWireDelay (pterm1_ipd(11), pterm1(11), tipd_pterm1(11));
VitalWireDelay (pterm1_ipd(12), pterm1(12), tipd_pterm1(12));
VitalWireDelay (pterm1_ipd(13), pterm1(13), tipd_pterm1(13));
VitalWireDelay (pterm1_ipd(14), pterm1(14), tipd_pterm1(14));
VitalWireDelay (pterm1_ipd(15), pterm1(15), tipd_pterm1(15));
VitalWireDelay (pterm1_ipd(16), pterm1(16), tipd_pterm1(16));
VitalWireDelay (pterm1_ipd(17), pterm1(17), tipd_pterm1(17));
VitalWireDelay (pterm1_ipd(18), pterm1(18), tipd_pterm1(18));
VitalWireDelay (pterm1_ipd(19), pterm1(19), tipd_pterm1(19));
VitalWireDelay (pterm1_ipd(20), pterm1(20), tipd_pterm1(20));
VitalWireDelay (pterm1_ipd(21), pterm1(21), tipd_pterm1(21));
VitalWireDelay (pterm1_ipd(22), pterm1(22), tipd_pterm1(22));
VitalWireDelay (pterm1_ipd(23), pterm1(23), tipd_pterm1(23));
VitalWireDelay (pterm1_ipd(24), pterm1(24), tipd_pterm1(24));
VitalWireDelay (pterm1_ipd(25), pterm1(25), tipd_pterm1(25));
VitalWireDelay (pterm1_ipd(26), pterm1(26), tipd_pterm1(26));
VitalWireDelay (pterm1_ipd(27), pterm1(27), tipd_pterm1(27));
VitalWireDelay (pterm1_ipd(28), pterm1(28), tipd_pterm1(28));
VitalWireDelay (pterm1_ipd(29), pterm1(29), tipd_pterm1(29));
VitalWireDelay (pterm1_ipd(30), pterm1(30), tipd_pterm1(30));
VitalWireDelay (pterm1_ipd(31), pterm1(31), tipd_pterm1(31));
VitalWireDelay (pterm1_ipd(32), pterm1(32), tipd_pterm1(32));
VitalWireDelay (pterm1_ipd(33), pterm1(33), tipd_pterm1(33));
VitalWireDelay (pterm1_ipd(34), pterm1(34), tipd_pterm1(34));
VitalWireDelay (pterm1_ipd(35), pterm1(35), tipd_pterm1(35));
VitalWireDelay (pterm1_ipd(36), pterm1(36), tipd_pterm1(36));
VitalWireDelay (pterm1_ipd(37), pterm1(37), tipd_pterm1(37));
VitalWireDelay (pterm1_ipd(38), pterm1(38), tipd_pterm1(38));
VitalWireDelay (pterm1_ipd(39), pterm1(39), tipd_pterm1(39));
VitalWireDelay (pterm1_ipd(40), pterm1(40), tipd_pterm1(40));
VitalWireDelay (pterm1_ipd(41), pterm1(41), tipd_pterm1(41));
VitalWireDelay (pterm1_ipd(42), pterm1(42), tipd_pterm1(42));
VitalWireDelay (pterm1_ipd(43), pterm1(43), tipd_pterm1(43));
VitalWireDelay (pterm1_ipd(44), pterm1(44), tipd_pterm1(44));
VitalWireDelay (pterm1_ipd(45), pterm1(45), tipd_pterm1(45));
VitalWireDelay (pterm1_ipd(46), pterm1(46), tipd_pterm1(46));
VitalWireDelay (pterm1_ipd(47), pterm1(47), tipd_pterm1(47));
VitalWireDelay (pterm1_ipd(48), pterm1(48), tipd_pterm1(48));
VitalWireDelay (pterm1_ipd(49), pterm1(49), tipd_pterm1(49));
VitalWireDelay (pterm1_ipd(50), pterm1(50), tipd_pterm1(50));
VitalWireDelay (pterm1_ipd(51), pterm1(51), tipd_pterm1(51));
VitalWireDelay (pterm2_ipd(0), pterm2(0), tipd_pterm2(0));
VitalWireDelay (pterm2_ipd(1), pterm2(1), tipd_pterm2(1));
VitalWireDelay (pterm2_ipd(2), pterm2(2), tipd_pterm2(2));
VitalWireDelay (pterm2_ipd(3), pterm2(3), tipd_pterm2(3));
VitalWireDelay (pterm2_ipd(4), pterm2(4), tipd_pterm2(4));
VitalWireDelay (pterm2_ipd(5), pterm2(5), tipd_pterm2(5));
VitalWireDelay (pterm2_ipd(6), pterm2(6), tipd_pterm2(6));
VitalWireDelay (pterm2_ipd(7), pterm2(7), tipd_pterm2(7));
VitalWireDelay (pterm2_ipd(8), pterm2(8), tipd_pterm2(8));
VitalWireDelay (pterm2_ipd(9), pterm2(9), tipd_pterm2(9));
VitalWireDelay (pterm2_ipd(10), pterm2(10), tipd_pterm2(10));
VitalWireDelay (pterm2_ipd(11), pterm2(11), tipd_pterm2(11));
VitalWireDelay (pterm2_ipd(12), pterm2(12), tipd_pterm2(12));
VitalWireDelay (pterm2_ipd(13), pterm2(13), tipd_pterm2(13));
VitalWireDelay (pterm2_ipd(14), pterm2(14), tipd_pterm2(14));
VitalWireDelay (pterm2_ipd(15), pterm2(15), tipd_pterm2(15));
VitalWireDelay (pterm2_ipd(16), pterm2(16), tipd_pterm2(16));
VitalWireDelay (pterm2_ipd(17), pterm2(17), tipd_pterm2(17));
VitalWireDelay (pterm2_ipd(18), pterm2(18), tipd_pterm2(18));
VitalWireDelay (pterm2_ipd(19), pterm2(19), tipd_pterm2(19));
VitalWireDelay (pterm2_ipd(20), pterm2(20), tipd_pterm2(20));
VitalWireDelay (pterm2_ipd(21), pterm2(21), tipd_pterm2(21));
VitalWireDelay (pterm2_ipd(22), pterm2(22), tipd_pterm2(22));
VitalWireDelay (pterm2_ipd(23), pterm2(23), tipd_pterm2(23));
VitalWireDelay (pterm2_ipd(24), pterm2(24), tipd_pterm2(24));
VitalWireDelay (pterm2_ipd(25), pterm2(25), tipd_pterm2(25));
VitalWireDelay (pterm2_ipd(26), pterm2(26), tipd_pterm2(26));
VitalWireDelay (pterm2_ipd(27), pterm2(27), tipd_pterm2(27));
VitalWireDelay (pterm2_ipd(28), pterm2(28), tipd_pterm2(28));
VitalWireDelay (pterm2_ipd(29), pterm2(29), tipd_pterm2(29));
VitalWireDelay (pterm2_ipd(30), pterm2(30), tipd_pterm2(30));
VitalWireDelay (pterm2_ipd(31), pterm2(31), tipd_pterm2(31));
VitalWireDelay (pterm2_ipd(32), pterm2(32), tipd_pterm2(32));
VitalWireDelay (pterm2_ipd(33), pterm2(33), tipd_pterm2(33));
VitalWireDelay (pterm2_ipd(34), pterm2(34), tipd_pterm2(34));
VitalWireDelay (pterm2_ipd(35), pterm2(35), tipd_pterm2(35));
VitalWireDelay (pterm2_ipd(36), pterm2(36), tipd_pterm2(36));
VitalWireDelay (pterm2_ipd(37), pterm2(37), tipd_pterm2(37));
VitalWireDelay (pterm2_ipd(38), pterm2(38), tipd_pterm2(38));
VitalWireDelay (pterm2_ipd(39), pterm2(39), tipd_pterm2(39));
VitalWireDelay (pterm2_ipd(40), pterm2(40), tipd_pterm2(40));
VitalWireDelay (pterm2_ipd(41), pterm2(41), tipd_pterm2(41));
VitalWireDelay (pterm2_ipd(42), pterm2(42), tipd_pterm2(42));
VitalWireDelay (pterm2_ipd(43), pterm2(43), tipd_pterm2(43));
VitalWireDelay (pterm2_ipd(44), pterm2(44), tipd_pterm2(44));
VitalWireDelay (pterm2_ipd(45), pterm2(45), tipd_pterm2(45));
VitalWireDelay (pterm2_ipd(46), pterm2(46), tipd_pterm2(46));
VitalWireDelay (pterm2_ipd(47), pterm2(47), tipd_pterm2(47));
VitalWireDelay (pterm2_ipd(48), pterm2(48), tipd_pterm2(48));
VitalWireDelay (pterm2_ipd(49), pterm2(49), tipd_pterm2(49));
VitalWireDelay (pterm2_ipd(50), pterm2(50), tipd_pterm2(50));
VitalWireDelay (pterm2_ipd(51), pterm2(51), tipd_pterm2(51));
VitalWireDelay (pterm3_ipd(0), pterm3(0), tipd_pterm3(0));
VitalWireDelay (pterm3_ipd(1), pterm3(1), tipd_pterm3(1));
VitalWireDelay (pterm3_ipd(2), pterm3(2), tipd_pterm3(2));
VitalWireDelay (pterm3_ipd(3), pterm3(3), tipd_pterm3(3));
VitalWireDelay (pterm3_ipd(4), pterm3(4), tipd_pterm3(4));
VitalWireDelay (pterm3_ipd(5), pterm3(5), tipd_pterm3(5));
VitalWireDelay (pterm3_ipd(6), pterm3(6), tipd_pterm3(6));
VitalWireDelay (pterm3_ipd(7), pterm3(7), tipd_pterm3(7));
VitalWireDelay (pterm3_ipd(8), pterm3(8), tipd_pterm3(8));
VitalWireDelay (pterm3_ipd(9), pterm3(9), tipd_pterm3(9));
VitalWireDelay (pterm3_ipd(10), pterm3(10), tipd_pterm3(10));
VitalWireDelay (pterm3_ipd(11), pterm3(11), tipd_pterm3(11));
VitalWireDelay (pterm3_ipd(12), pterm3(12), tipd_pterm3(12));
VitalWireDelay (pterm3_ipd(13), pterm3(13), tipd_pterm3(13));
VitalWireDelay (pterm3_ipd(14), pterm3(14), tipd_pterm3(14));
VitalWireDelay (pterm3_ipd(15), pterm3(15), tipd_pterm3(15));
VitalWireDelay (pterm3_ipd(16), pterm3(16), tipd_pterm3(16));
VitalWireDelay (pterm3_ipd(17), pterm3(17), tipd_pterm3(17));
VitalWireDelay (pterm3_ipd(18), pterm3(18), tipd_pterm3(18));
VitalWireDelay (pterm3_ipd(19), pterm3(19), tipd_pterm3(19));
VitalWireDelay (pterm3_ipd(20), pterm3(20), tipd_pterm3(20));
VitalWireDelay (pterm3_ipd(21), pterm3(21), tipd_pterm3(21));
VitalWireDelay (pterm3_ipd(22), pterm3(22), tipd_pterm3(22));
VitalWireDelay (pterm3_ipd(23), pterm3(23), tipd_pterm3(23));
VitalWireDelay (pterm3_ipd(24), pterm3(24), tipd_pterm3(24));
VitalWireDelay (pterm3_ipd(25), pterm3(25), tipd_pterm3(25));
VitalWireDelay (pterm3_ipd(26), pterm3(26), tipd_pterm3(26));
VitalWireDelay (pterm3_ipd(27), pterm3(27), tipd_pterm3(27));
VitalWireDelay (pterm3_ipd(28), pterm3(28), tipd_pterm3(28));
VitalWireDelay (pterm3_ipd(29), pterm3(29), tipd_pterm3(29));
VitalWireDelay (pterm3_ipd(30), pterm3(30), tipd_pterm3(30));
VitalWireDelay (pterm3_ipd(31), pterm3(31), tipd_pterm3(31));
VitalWireDelay (pterm3_ipd(32), pterm3(32), tipd_pterm3(32));
VitalWireDelay (pterm3_ipd(33), pterm3(33), tipd_pterm3(33));
VitalWireDelay (pterm3_ipd(34), pterm3(34), tipd_pterm3(34));
VitalWireDelay (pterm3_ipd(35), pterm3(35), tipd_pterm3(35));
VitalWireDelay (pterm3_ipd(36), pterm3(36), tipd_pterm3(36));
VitalWireDelay (pterm3_ipd(37), pterm3(37), tipd_pterm3(37));
VitalWireDelay (pterm3_ipd(38), pterm3(38), tipd_pterm3(38));
VitalWireDelay (pterm3_ipd(39), pterm3(39), tipd_pterm3(39));
VitalWireDelay (pterm3_ipd(40), pterm3(40), tipd_pterm3(40));
VitalWireDelay (pterm3_ipd(41), pterm3(41), tipd_pterm3(41));
VitalWireDelay (pterm3_ipd(42), pterm3(42), tipd_pterm3(42));
VitalWireDelay (pterm3_ipd(43), pterm3(43), tipd_pterm3(43));
VitalWireDelay (pterm3_ipd(44), pterm3(44), tipd_pterm3(44));
VitalWireDelay (pterm3_ipd(45), pterm3(45), tipd_pterm3(45));
VitalWireDelay (pterm3_ipd(46), pterm3(46), tipd_pterm3(46));
VitalWireDelay (pterm3_ipd(47), pterm3(47), tipd_pterm3(47));
VitalWireDelay (pterm3_ipd(48), pterm3(48), tipd_pterm3(48));
VitalWireDelay (pterm3_ipd(49), pterm3(49), tipd_pterm3(49));
VitalWireDelay (pterm3_ipd(50), pterm3(50), tipd_pterm3(50));
VitalWireDelay (pterm3_ipd(51), pterm3(51), tipd_pterm3(51));
VitalWireDelay (pterm4_ipd(0), pterm4(0), tipd_pterm4(0));
VitalWireDelay (pterm4_ipd(1), pterm4(1), tipd_pterm4(1));
VitalWireDelay (pterm4_ipd(2), pterm4(2), tipd_pterm4(2));
VitalWireDelay (pterm4_ipd(3), pterm4(3), tipd_pterm4(3));
VitalWireDelay (pterm4_ipd(4), pterm4(4), tipd_pterm4(4));
VitalWireDelay (pterm4_ipd(5), pterm4(5), tipd_pterm4(5));
VitalWireDelay (pterm4_ipd(6), pterm4(6), tipd_pterm4(6));
VitalWireDelay (pterm4_ipd(7), pterm4(7), tipd_pterm4(7));
VitalWireDelay (pterm4_ipd(8), pterm4(8), tipd_pterm4(8));
VitalWireDelay (pterm4_ipd(9), pterm4(9), tipd_pterm4(9));
VitalWireDelay (pterm4_ipd(10), pterm4(10), tipd_pterm4(10));
VitalWireDelay (pterm4_ipd(11), pterm4(11), tipd_pterm4(11));
VitalWireDelay (pterm4_ipd(12), pterm4(12), tipd_pterm4(12));
VitalWireDelay (pterm4_ipd(13), pterm4(13), tipd_pterm4(13));
VitalWireDelay (pterm4_ipd(14), pterm4(14), tipd_pterm4(14));
VitalWireDelay (pterm4_ipd(15), pterm4(15), tipd_pterm4(15));
VitalWireDelay (pterm4_ipd(16), pterm4(16), tipd_pterm4(16));
VitalWireDelay (pterm4_ipd(17), pterm4(17), tipd_pterm4(17));
VitalWireDelay (pterm4_ipd(18), pterm4(18), tipd_pterm4(18));
VitalWireDelay (pterm4_ipd(19), pterm4(19), tipd_pterm4(19));
VitalWireDelay (pterm4_ipd(20), pterm4(20), tipd_pterm4(20));
VitalWireDelay (pterm4_ipd(21), pterm4(21), tipd_pterm4(21));
VitalWireDelay (pterm4_ipd(22), pterm4(22), tipd_pterm4(22));
VitalWireDelay (pterm4_ipd(23), pterm4(23), tipd_pterm4(23));
VitalWireDelay (pterm4_ipd(24), pterm4(24), tipd_pterm4(24));
VitalWireDelay (pterm4_ipd(25), pterm4(25), tipd_pterm4(25));
VitalWireDelay (pterm4_ipd(26), pterm4(26), tipd_pterm4(26));
VitalWireDelay (pterm4_ipd(27), pterm4(27), tipd_pterm4(27));
VitalWireDelay (pterm4_ipd(28), pterm4(28), tipd_pterm4(28));
VitalWireDelay (pterm4_ipd(29), pterm4(29), tipd_pterm4(29));
VitalWireDelay (pterm4_ipd(30), pterm4(30), tipd_pterm4(30));
VitalWireDelay (pterm4_ipd(31), pterm4(31), tipd_pterm4(31));
VitalWireDelay (pterm4_ipd(32), pterm4(32), tipd_pterm4(32));
VitalWireDelay (pterm4_ipd(33), pterm4(33), tipd_pterm4(33));
VitalWireDelay (pterm4_ipd(34), pterm4(34), tipd_pterm4(34));
VitalWireDelay (pterm4_ipd(35), pterm4(35), tipd_pterm4(35));
VitalWireDelay (pterm4_ipd(36), pterm4(36), tipd_pterm4(36));
VitalWireDelay (pterm4_ipd(37), pterm4(37), tipd_pterm4(37));
VitalWireDelay (pterm4_ipd(38), pterm4(38), tipd_pterm4(38));
VitalWireDelay (pterm4_ipd(39), pterm4(39), tipd_pterm4(39));
VitalWireDelay (pterm4_ipd(40), pterm4(40), tipd_pterm4(40));
VitalWireDelay (pterm4_ipd(41), pterm4(41), tipd_pterm4(41));
VitalWireDelay (pterm4_ipd(42), pterm4(42), tipd_pterm4(42));
VitalWireDelay (pterm4_ipd(43), pterm4(43), tipd_pterm4(43));
VitalWireDelay (pterm4_ipd(44), pterm4(44), tipd_pterm4(44));
VitalWireDelay (pterm4_ipd(45), pterm4(45), tipd_pterm4(45));
VitalWireDelay (pterm4_ipd(46), pterm4(46), tipd_pterm4(46));
VitalWireDelay (pterm4_ipd(47), pterm4(47), tipd_pterm4(47));
VitalWireDelay (pterm4_ipd(48), pterm4(48), tipd_pterm4(48));
VitalWireDelay (pterm4_ipd(49), pterm4(49), tipd_pterm4(49));
VitalWireDelay (pterm4_ipd(50), pterm4(50), tipd_pterm4(50));
VitalWireDelay (pterm4_ipd(51), pterm4(51), tipd_pterm4(51));
VitalWireDelay (pterm5_ipd(0), pterm5(0), tipd_pterm5(0));
VitalWireDelay (pterm5_ipd(1), pterm5(1), tipd_pterm5(1));
VitalWireDelay (pterm5_ipd(2), pterm5(2), tipd_pterm5(2));
VitalWireDelay (pterm5_ipd(3), pterm5(3), tipd_pterm5(3));
VitalWireDelay (pterm5_ipd(4), pterm5(4), tipd_pterm5(4));
VitalWireDelay (pterm5_ipd(5), pterm5(5), tipd_pterm5(5));
VitalWireDelay (pterm5_ipd(6), pterm5(6), tipd_pterm5(6));
VitalWireDelay (pterm5_ipd(7), pterm5(7), tipd_pterm5(7));
VitalWireDelay (pterm5_ipd(8), pterm5(8), tipd_pterm5(8));
VitalWireDelay (pterm5_ipd(9), pterm5(9), tipd_pterm5(9));
VitalWireDelay (pterm5_ipd(10), pterm5(10), tipd_pterm5(10));
VitalWireDelay (pterm5_ipd(11), pterm5(11), tipd_pterm5(11));
VitalWireDelay (pterm5_ipd(12), pterm5(12), tipd_pterm5(12));
VitalWireDelay (pterm5_ipd(13), pterm5(13), tipd_pterm5(13));
VitalWireDelay (pterm5_ipd(14), pterm5(14), tipd_pterm5(14));
VitalWireDelay (pterm5_ipd(15), pterm5(15), tipd_pterm5(15));
VitalWireDelay (pterm5_ipd(16), pterm5(16), tipd_pterm5(16));
VitalWireDelay (pterm5_ipd(17), pterm5(17), tipd_pterm5(17));
VitalWireDelay (pterm5_ipd(18), pterm5(18), tipd_pterm5(18));
VitalWireDelay (pterm5_ipd(19), pterm5(19), tipd_pterm5(19));
VitalWireDelay (pterm5_ipd(20), pterm5(20), tipd_pterm5(20));
VitalWireDelay (pterm5_ipd(21), pterm5(21), tipd_pterm5(21));
VitalWireDelay (pterm5_ipd(22), pterm5(22), tipd_pterm5(22));
VitalWireDelay (pterm5_ipd(23), pterm5(23), tipd_pterm5(23));
VitalWireDelay (pterm5_ipd(24), pterm5(24), tipd_pterm5(24));
VitalWireDelay (pterm5_ipd(25), pterm5(25), tipd_pterm5(25));
VitalWireDelay (pterm5_ipd(26), pterm5(26), tipd_pterm5(26));
VitalWireDelay (pterm5_ipd(27), pterm5(27), tipd_pterm5(27));
VitalWireDelay (pterm5_ipd(28), pterm5(28), tipd_pterm5(28));
VitalWireDelay (pterm5_ipd(29), pterm5(29), tipd_pterm5(29));
VitalWireDelay (pterm5_ipd(30), pterm5(30), tipd_pterm5(30));
VitalWireDelay (pterm5_ipd(31), pterm5(31), tipd_pterm5(31));
VitalWireDelay (pterm5_ipd(32), pterm5(32), tipd_pterm5(32));
VitalWireDelay (pterm5_ipd(33), pterm5(33), tipd_pterm5(33));
VitalWireDelay (pterm5_ipd(34), pterm5(34), tipd_pterm5(34));
VitalWireDelay (pterm5_ipd(35), pterm5(35), tipd_pterm5(35));
VitalWireDelay (pterm5_ipd(36), pterm5(36), tipd_pterm5(36));
VitalWireDelay (pterm5_ipd(37), pterm5(37), tipd_pterm5(37));
VitalWireDelay (pterm5_ipd(38), pterm5(38), tipd_pterm5(38));
VitalWireDelay (pterm5_ipd(39), pterm5(39), tipd_pterm5(39));
VitalWireDelay (pterm5_ipd(40), pterm5(40), tipd_pterm5(40));
VitalWireDelay (pterm5_ipd(41), pterm5(41), tipd_pterm5(41));
VitalWireDelay (pterm5_ipd(42), pterm5(42), tipd_pterm5(42));
VitalWireDelay (pterm5_ipd(43), pterm5(43), tipd_pterm5(43));
VitalWireDelay (pterm5_ipd(44), pterm5(44), tipd_pterm5(44));
VitalWireDelay (pterm5_ipd(45), pterm5(45), tipd_pterm5(45));
VitalWireDelay (pterm5_ipd(46), pterm5(46), tipd_pterm5(46));
VitalWireDelay (pterm5_ipd(47), pterm5(47), tipd_pterm5(47));
VitalWireDelay (pterm5_ipd(48), pterm5(48), tipd_pterm5(48));
VitalWireDelay (pterm5_ipd(49), pterm5(49), tipd_pterm5(49));
VitalWireDelay (pterm5_ipd(50), pterm5(50), tipd_pterm5(50));
VitalWireDelay (pterm5_ipd(51), pterm5(51), tipd_pterm5(51));
VitalWireDelay (pxor_ipd(0), pxor(0), tipd_pxor(0));
VitalWireDelay (pxor_ipd(1), pxor(1), tipd_pxor(1));
VitalWireDelay (pxor_ipd(2), pxor(2), tipd_pxor(2));
VitalWireDelay (pxor_ipd(3), pxor(3), tipd_pxor(3));
VitalWireDelay (pxor_ipd(4), pxor(4), tipd_pxor(4));
VitalWireDelay (pxor_ipd(5), pxor(5), tipd_pxor(5));
VitalWireDelay (pxor_ipd(6), pxor(6), tipd_pxor(6));
VitalWireDelay (pxor_ipd(7), pxor(7), tipd_pxor(7));
VitalWireDelay (pxor_ipd(8), pxor(8), tipd_pxor(8));
VitalWireDelay (pxor_ipd(9), pxor(9), tipd_pxor(9));
VitalWireDelay (pxor_ipd(10), pxor(10), tipd_pxor(10));
VitalWireDelay (pxor_ipd(11), pxor(11), tipd_pxor(11));
VitalWireDelay (pxor_ipd(12), pxor(12), tipd_pxor(12));
VitalWireDelay (pxor_ipd(13), pxor(13), tipd_pxor(13));
VitalWireDelay (pxor_ipd(14), pxor(14), tipd_pxor(14));
VitalWireDelay (pxor_ipd(15), pxor(15), tipd_pxor(15));
VitalWireDelay (pxor_ipd(16), pxor(16), tipd_pxor(16));
VitalWireDelay (pxor_ipd(17), pxor(17), tipd_pxor(17));
VitalWireDelay (pxor_ipd(18), pxor(18), tipd_pxor(18));
VitalWireDelay (pxor_ipd(19), pxor(19), tipd_pxor(19));
VitalWireDelay (pxor_ipd(20), pxor(20), tipd_pxor(20));
VitalWireDelay (pxor_ipd(21), pxor(21), tipd_pxor(21));
VitalWireDelay (pxor_ipd(22), pxor(22), tipd_pxor(22));
VitalWireDelay (pxor_ipd(23), pxor(23), tipd_pxor(23));
VitalWireDelay (pxor_ipd(24), pxor(24), tipd_pxor(24));
VitalWireDelay (pxor_ipd(25), pxor(25), tipd_pxor(25));
VitalWireDelay (pxor_ipd(26), pxor(26), tipd_pxor(26));
VitalWireDelay (pxor_ipd(27), pxor(27), tipd_pxor(27));
VitalWireDelay (pxor_ipd(28), pxor(28), tipd_pxor(28));
VitalWireDelay (pxor_ipd(29), pxor(29), tipd_pxor(29));
VitalWireDelay (pxor_ipd(30), pxor(30), tipd_pxor(30));
VitalWireDelay (pxor_ipd(31), pxor(31), tipd_pxor(31));
VitalWireDelay (pxor_ipd(32), pxor(32), tipd_pxor(32));
VitalWireDelay (pxor_ipd(33), pxor(33), tipd_pxor(33));
VitalWireDelay (pxor_ipd(34), pxor(34), tipd_pxor(34));
VitalWireDelay (pxor_ipd(35), pxor(35), tipd_pxor(35));
VitalWireDelay (pxor_ipd(36), pxor(36), tipd_pxor(36));
VitalWireDelay (pxor_ipd(37), pxor(37), tipd_pxor(37));
VitalWireDelay (pxor_ipd(38), pxor(38), tipd_pxor(38));
VitalWireDelay (pxor_ipd(39), pxor(39), tipd_pxor(39));
VitalWireDelay (pxor_ipd(40), pxor(40), tipd_pxor(40));
VitalWireDelay (pxor_ipd(41), pxor(41), tipd_pxor(41));
VitalWireDelay (pxor_ipd(42), pxor(42), tipd_pxor(42));
VitalWireDelay (pxor_ipd(43), pxor(43), tipd_pxor(43));
VitalWireDelay (pxor_ipd(44), pxor(44), tipd_pxor(44));
VitalWireDelay (pxor_ipd(45), pxor(45), tipd_pxor(45));
VitalWireDelay (pxor_ipd(46), pxor(46), tipd_pxor(46));
VitalWireDelay (pxor_ipd(47), pxor(47), tipd_pxor(47));
VitalWireDelay (pxor_ipd(48), pxor(48), tipd_pxor(48));
VitalWireDelay (pxor_ipd(49), pxor(49), tipd_pxor(49));
VitalWireDelay (pxor_ipd(50), pxor(50), tipd_pxor(50));
VitalWireDelay (pxor_ipd(51), pxor(51), tipd_pxor(51));
VitalWireDelay (pexpin_ipd, pexpin, tipd_pexpin);
VitalWireDelay (fpin_ipd, fpin, tipd_fpin);
end block;
VITALtiming : process(pterm0_ipd, pterm1_ipd, pterm2_ipd, pterm3_ipd, pterm4_ipd, pterm5_ipd, pxor_ipd, pexpin_ipd, fbkin, fpin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable pexpout_VitalGlitchData : VitalGlitchDataType;
variable tmp_comb, tmp_pexpout : std_logic;
begin
if (pexp_mode = "off") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor fbkin;
else
tmp_comb := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
end if;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd)) xor (not(fbkin));
else
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor '1';
end if;
elsif (operation_mode = "xor") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor product(pxor_ipd);
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
elsif (pexp_mode = "on") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := (product (pterm5_ipd)) xor fbkin;
else
tmp_comb := product (pterm5_ipd);
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (product(pterm5_ipd)) xor (not(fbkin));
else
tmp_comb := (product(pterm5_ipd)) xor '1';
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "xor") then
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
tmp_comb := (product(pterm5_ipd)) xor (product(pxor_ipd));
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
tmp_pexpout := (product(pterm0) or product(pterm1) or product(pterm2) or product(pterm3) or product(pterm4)) or pexpin_ipd;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_combout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_combout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_combout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_combout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_combout(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_combout(0), TRUE),
7 => (pxor_ipd'last_event, tpd_pxor_combout(0), TRUE),
8 => (pexpin_ipd'last_event, tpd_pexpin_combout, TRUE),
9 => (fbkin'last_event, tpd_fbkin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => pexpout,
OutSignalName => "PEXPOUT",
OutTemp => tmp_pexpout,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_pexpout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_pexpout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_pexpout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_pexpout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_pexpout(0), TRUE),
6 => (pexpin_ipd'last_event, tpd_pexpin_pexpout, TRUE),
7 => (fbkin'last_event, tpd_fbkin_pexpout, TRUE)),
GlitchData => pexpout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_regin(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_regin(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_regin(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_regin(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_regin(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_regin(0), TRUE),
7 => (fpin_ipd'last_event, tpd_fpin_regin, TRUE),
8 => (pxor_ipd'last_event, tpd_pxor_regin(0), TRUE),
9 => (pexpin_ipd'last_event, tpd_pexpin_regin, TRUE),
10 => (fbkin'last_event, tpd_fbkin_regin, TRUE)),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_mcell;
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_mcell_register is
generic ( operation_mode : string := "normal";
power_up : string := "low";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pclk_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pclk_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tipd_pclk : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pena : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_paclr : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_papre : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01);
port ( datain : in std_logic;
clk : in std_logic;
aclr : in std_logic := '0';
pclk : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
papre : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
regout : out std_logic;
fbkout : out std_logic);
attribute VITAL_LEVEL0 of max_mcell_register : entity is TRUE;
end max_mcell_register;
architecture vital_mcell_reg of max_mcell_register is
attribute VITAL_LEVEL0 of vital_mcell_reg : architecture is TRUE;
signal pclk_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pena_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal paclr_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal papre_ipd :std_logic_vector(51 downto 0) := (OTHERS => '0');
signal clk_ipd :std_ulogic := 'U';
signal aclr_ipd :std_ulogic := 'U';
signal ena_ipd :std_ulogic := '1';
signal ptermclk :std_ulogic := '0';
signal penable :std_ulogic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (pclk_ipd(0), pclk(0), tipd_pclk(0));
VitalWireDelay (pclk_ipd(1), pclk(1), tipd_pclk(1));
VitalWireDelay (pclk_ipd(2), pclk(2), tipd_pclk(2));
VitalWireDelay (pclk_ipd(3), pclk(3), tipd_pclk(3));
VitalWireDelay (pclk_ipd(4), pclk(4), tipd_pclk(4));
VitalWireDelay (pclk_ipd(5), pclk(5), tipd_pclk(5));
VitalWireDelay (pclk_ipd(6), pclk(6), tipd_pclk(6));
VitalWireDelay (pclk_ipd(7), pclk(7), tipd_pclk(7));
VitalWireDelay (pclk_ipd(8), pclk(8), tipd_pclk(8));
VitalWireDelay (pclk_ipd(9), pclk(9), tipd_pclk(9));
VitalWireDelay (pclk_ipd(10), pclk(10), tipd_pclk(10));
VitalWireDelay (pclk_ipd(11), pclk(11), tipd_pclk(11));
VitalWireDelay (pclk_ipd(12), pclk(12), tipd_pclk(12));
VitalWireDelay (pclk_ipd(13), pclk(13), tipd_pclk(13));
VitalWireDelay (pclk_ipd(14), pclk(14), tipd_pclk(14));
VitalWireDelay (pclk_ipd(15), pclk(15), tipd_pclk(15));
VitalWireDelay (pclk_ipd(16), pclk(16), tipd_pclk(16));
VitalWireDelay (pclk_ipd(17), pclk(17), tipd_pclk(17));
VitalWireDelay (pclk_ipd(18), pclk(18), tipd_pclk(18));
VitalWireDelay (pclk_ipd(19), pclk(19), tipd_pclk(19));
VitalWireDelay (pclk_ipd(20), pclk(20), tipd_pclk(20));
VitalWireDelay (pclk_ipd(21), pclk(21), tipd_pclk(21));
VitalWireDelay (pclk_ipd(22), pclk(22), tipd_pclk(22));
VitalWireDelay (pclk_ipd(23), pclk(23), tipd_pclk(23));
VitalWireDelay (pclk_ipd(24), pclk(24), tipd_pclk(24));
VitalWireDelay (pclk_ipd(25), pclk(25), tipd_pclk(25));
VitalWireDelay (pclk_ipd(26), pclk(26), tipd_pclk(26));
VitalWireDelay (pclk_ipd(27), pclk(27), tipd_pclk(27));
VitalWireDelay (pclk_ipd(28), pclk(28), tipd_pclk(28));
VitalWireDelay (pclk_ipd(29), pclk(29), tipd_pclk(29));
VitalWireDelay (pclk_ipd(30), pclk(30), tipd_pclk(30));
VitalWireDelay (pclk_ipd(31), pclk(31), tipd_pclk(31));
VitalWireDelay (pclk_ipd(32), pclk(32), tipd_pclk(32));
VitalWireDelay (pclk_ipd(33), pclk(33), tipd_pclk(33));
VitalWireDelay (pclk_ipd(34), pclk(34), tipd_pclk(34));
VitalWireDelay (pclk_ipd(35), pclk(35), tipd_pclk(35));
VitalWireDelay (pclk_ipd(36), pclk(36), tipd_pclk(36));
VitalWireDelay (pclk_ipd(37), pclk(37), tipd_pclk(37));
VitalWireDelay (pclk_ipd(38), pclk(38), tipd_pclk(38));
VitalWireDelay (pclk_ipd(39), pclk(39), tipd_pclk(39));
VitalWireDelay (pclk_ipd(40), pclk(40), tipd_pclk(40));
VitalWireDelay (pclk_ipd(41), pclk(41), tipd_pclk(41));
VitalWireDelay (pclk_ipd(42), pclk(42), tipd_pclk(42));
VitalWireDelay (pclk_ipd(43), pclk(43), tipd_pclk(43));
VitalWireDelay (pclk_ipd(44), pclk(44), tipd_pclk(44));
VitalWireDelay (pclk_ipd(45), pclk(45), tipd_pclk(45));
VitalWireDelay (pclk_ipd(46), pclk(46), tipd_pclk(46));
VitalWireDelay (pclk_ipd(47), pclk(47), tipd_pclk(47));
VitalWireDelay (pclk_ipd(48), pclk(48), tipd_pclk(48));
VitalWireDelay (pclk_ipd(49), pclk(49), tipd_pclk(49));
VitalWireDelay (pclk_ipd(50), pclk(50), tipd_pclk(50));
VitalWireDelay (pclk_ipd(51), pclk(51), tipd_pclk(51));
VitalWireDelay (pena_ipd(0), pena(0), tipd_pena(0));
VitalWireDelay (pena_ipd(1), pena(1), tipd_pena(1));
VitalWireDelay (pena_ipd(2), pena(2), tipd_pena(2));
VitalWireDelay (pena_ipd(3), pena(3), tipd_pena(3));
VitalWireDelay (pena_ipd(4), pena(4), tipd_pena(4));
VitalWireDelay (pena_ipd(5), pena(5), tipd_pena(5));
VitalWireDelay (pena_ipd(6), pena(6), tipd_pena(6));
VitalWireDelay (pena_ipd(7), pena(7), tipd_pena(7));
VitalWireDelay (pena_ipd(8), pena(8), tipd_pena(8));
VitalWireDelay (pena_ipd(9), pena(9), tipd_pena(9));
VitalWireDelay (pena_ipd(10), pena(10), tipd_pena(10));
VitalWireDelay (pena_ipd(11), pena(11), tipd_pena(11));
VitalWireDelay (pena_ipd(12), pena(12), tipd_pena(12));
VitalWireDelay (pena_ipd(13), pena(13), tipd_pena(13));
VitalWireDelay (pena_ipd(14), pena(14), tipd_pena(14));
VitalWireDelay (pena_ipd(15), pena(15), tipd_pena(15));
VitalWireDelay (pena_ipd(16), pena(16), tipd_pena(16));
VitalWireDelay (pena_ipd(17), pena(17), tipd_pena(17));
VitalWireDelay (pena_ipd(18), pena(18), tipd_pena(18));
VitalWireDelay (pena_ipd(19), pena(19), tipd_pena(19));
VitalWireDelay (pena_ipd(20), pena(20), tipd_pena(20));
VitalWireDelay (pena_ipd(21), pena(21), tipd_pena(21));
VitalWireDelay (pena_ipd(22), pena(22), tipd_pena(22));
VitalWireDelay (pena_ipd(23), pena(23), tipd_pena(23));
VitalWireDelay (pena_ipd(24), pena(24), tipd_pena(24));
VitalWireDelay (pena_ipd(25), pena(25), tipd_pena(25));
VitalWireDelay (pena_ipd(26), pena(26), tipd_pena(26));
VitalWireDelay (pena_ipd(27), pena(27), tipd_pena(27));
VitalWireDelay (pena_ipd(28), pena(28), tipd_pena(28));
VitalWireDelay (pena_ipd(29), pena(29), tipd_pena(29));
VitalWireDelay (pena_ipd(30), pena(30), tipd_pena(30));
VitalWireDelay (pena_ipd(31), pena(31), tipd_pena(31));
VitalWireDelay (pena_ipd(32), pena(32), tipd_pena(32));
VitalWireDelay (pena_ipd(33), pena(33), tipd_pena(33));
VitalWireDelay (pena_ipd(34), pena(34), tipd_pena(34));
VitalWireDelay (pena_ipd(35), pena(35), tipd_pena(35));
VitalWireDelay (pena_ipd(36), pena(36), tipd_pena(36));
VitalWireDelay (pena_ipd(37), pena(37), tipd_pena(37));
VitalWireDelay (pena_ipd(38), pena(38), tipd_pena(38));
VitalWireDelay (pena_ipd(39), pena(39), tipd_pena(39));
VitalWireDelay (pena_ipd(40), pena(40), tipd_pena(40));
VitalWireDelay (pena_ipd(41), pena(41), tipd_pena(41));
VitalWireDelay (pena_ipd(42), pena(42), tipd_pena(42));
VitalWireDelay (pena_ipd(43), pena(43), tipd_pena(43));
VitalWireDelay (pena_ipd(44), pena(44), tipd_pena(44));
VitalWireDelay (pena_ipd(45), pena(45), tipd_pena(45));
VitalWireDelay (pena_ipd(46), pena(46), tipd_pena(46));
VitalWireDelay (pena_ipd(47), pena(47), tipd_pena(47));
VitalWireDelay (pena_ipd(48), pena(48), tipd_pena(48));
VitalWireDelay (pena_ipd(49), pena(49), tipd_pena(49));
VitalWireDelay (pena_ipd(50), pena(50), tipd_pena(50));
VitalWireDelay (pena_ipd(51), pena(51), tipd_pena(51));
VitalWireDelay (paclr_ipd(0), paclr(0), tipd_paclr(0));
VitalWireDelay (paclr_ipd(1), paclr(1), tipd_paclr(1));
VitalWireDelay (paclr_ipd(2), paclr(2), tipd_paclr(2));
VitalWireDelay (paclr_ipd(3), paclr(3), tipd_paclr(3));
VitalWireDelay (paclr_ipd(4), paclr(4), tipd_paclr(4));
VitalWireDelay (paclr_ipd(5), paclr(5), tipd_paclr(5));
VitalWireDelay (paclr_ipd(6), paclr(6), tipd_paclr(6));
VitalWireDelay (paclr_ipd(7), paclr(7), tipd_paclr(7));
VitalWireDelay (paclr_ipd(8), paclr(8), tipd_paclr(8));
VitalWireDelay (paclr_ipd(9), paclr(9), tipd_paclr(9));
VitalWireDelay (paclr_ipd(10), paclr(10), tipd_paclr(10));
VitalWireDelay (paclr_ipd(11), paclr(11), tipd_paclr(11));
VitalWireDelay (paclr_ipd(12), paclr(12), tipd_paclr(12));
VitalWireDelay (paclr_ipd(13), paclr(13), tipd_paclr(13));
VitalWireDelay (paclr_ipd(14), paclr(14), tipd_paclr(14));
VitalWireDelay (paclr_ipd(15), paclr(15), tipd_paclr(15));
VitalWireDelay (paclr_ipd(16), paclr(16), tipd_paclr(16));
VitalWireDelay (paclr_ipd(17), paclr(17), tipd_paclr(17));
VitalWireDelay (paclr_ipd(18), paclr(18), tipd_paclr(18));
VitalWireDelay (paclr_ipd(19), paclr(19), tipd_paclr(19));
VitalWireDelay (paclr_ipd(20), paclr(20), tipd_paclr(20));
VitalWireDelay (paclr_ipd(21), paclr(21), tipd_paclr(21));
VitalWireDelay (paclr_ipd(22), paclr(22), tipd_paclr(22));
VitalWireDelay (paclr_ipd(23), paclr(23), tipd_paclr(23));
VitalWireDelay (paclr_ipd(24), paclr(24), tipd_paclr(24));
VitalWireDelay (paclr_ipd(25), paclr(25), tipd_paclr(25));
VitalWireDelay (paclr_ipd(26), paclr(26), tipd_paclr(26));
VitalWireDelay (paclr_ipd(27), paclr(27), tipd_paclr(27));
VitalWireDelay (paclr_ipd(28), paclr(28), tipd_paclr(28));
VitalWireDelay (paclr_ipd(29), paclr(29), tipd_paclr(29));
VitalWireDelay (paclr_ipd(30), paclr(30), tipd_paclr(30));
VitalWireDelay (paclr_ipd(31), paclr(31), tipd_paclr(31));
VitalWireDelay (paclr_ipd(32), paclr(32), tipd_paclr(32));
VitalWireDelay (paclr_ipd(33), paclr(33), tipd_paclr(33));
VitalWireDelay (paclr_ipd(34), paclr(34), tipd_paclr(34));
VitalWireDelay (paclr_ipd(35), paclr(35), tipd_paclr(35));
VitalWireDelay (paclr_ipd(36), paclr(36), tipd_paclr(36));
VitalWireDelay (paclr_ipd(37), paclr(37), tipd_paclr(37));
VitalWireDelay (paclr_ipd(38), paclr(38), tipd_paclr(38));
VitalWireDelay (paclr_ipd(39), paclr(39), tipd_paclr(39));
VitalWireDelay (paclr_ipd(40), paclr(40), tipd_paclr(40));
VitalWireDelay (paclr_ipd(41), paclr(41), tipd_paclr(41));
VitalWireDelay (paclr_ipd(42), paclr(42), tipd_paclr(42));
VitalWireDelay (paclr_ipd(43), paclr(43), tipd_paclr(43));
VitalWireDelay (paclr_ipd(44), paclr(44), tipd_paclr(44));
VitalWireDelay (paclr_ipd(45), paclr(45), tipd_paclr(45));
VitalWireDelay (paclr_ipd(46), paclr(46), tipd_paclr(46));
VitalWireDelay (paclr_ipd(47), paclr(47), tipd_paclr(47));
VitalWireDelay (paclr_ipd(48), paclr(48), tipd_paclr(48));
VitalWireDelay (paclr_ipd(49), paclr(49), tipd_paclr(49));
VitalWireDelay (paclr_ipd(50), paclr(50), tipd_paclr(50));
VitalWireDelay (paclr_ipd(51), paclr(51), tipd_paclr(51));
VitalWireDelay (papre_ipd(0), papre(0), tipd_papre(0));
VitalWireDelay (papre_ipd(1), papre(1), tipd_papre(1));
VitalWireDelay (papre_ipd(2), papre(2), tipd_papre(2));
VitalWireDelay (papre_ipd(3), papre(3), tipd_papre(3));
VitalWireDelay (papre_ipd(4), papre(4), tipd_papre(4));
VitalWireDelay (papre_ipd(5), papre(5), tipd_papre(5));
VitalWireDelay (papre_ipd(6), papre(6), tipd_papre(6));
VitalWireDelay (papre_ipd(7), papre(7), tipd_papre(7));
VitalWireDelay (papre_ipd(8), papre(8), tipd_papre(8));
VitalWireDelay (papre_ipd(9), papre(9), tipd_papre(9));
VitalWireDelay (papre_ipd(10), papre(10), tipd_papre(10));
VitalWireDelay (papre_ipd(11), papre(11), tipd_papre(11));
VitalWireDelay (papre_ipd(12), papre(12), tipd_papre(12));
VitalWireDelay (papre_ipd(13), papre(13), tipd_papre(13));
VitalWireDelay (papre_ipd(14), papre(14), tipd_papre(14));
VitalWireDelay (papre_ipd(15), papre(15), tipd_papre(15));
VitalWireDelay (papre_ipd(16), papre(16), tipd_papre(16));
VitalWireDelay (papre_ipd(17), papre(17), tipd_papre(17));
VitalWireDelay (papre_ipd(18), papre(18), tipd_papre(18));
VitalWireDelay (papre_ipd(19), papre(19), tipd_papre(19));
VitalWireDelay (papre_ipd(20), papre(20), tipd_papre(20));
VitalWireDelay (papre_ipd(21), papre(21), tipd_papre(21));
VitalWireDelay (papre_ipd(22), papre(22), tipd_papre(22));
VitalWireDelay (papre_ipd(23), papre(23), tipd_papre(23));
VitalWireDelay (papre_ipd(24), papre(24), tipd_papre(24));
VitalWireDelay (papre_ipd(25), papre(25), tipd_papre(25));
VitalWireDelay (papre_ipd(26), papre(26), tipd_papre(26));
VitalWireDelay (papre_ipd(27), papre(27), tipd_papre(27));
VitalWireDelay (papre_ipd(28), papre(28), tipd_papre(28));
VitalWireDelay (papre_ipd(29), papre(29), tipd_papre(29));
VitalWireDelay (papre_ipd(30), papre(30), tipd_papre(30));
VitalWireDelay (papre_ipd(31), papre(31), tipd_papre(31));
VitalWireDelay (papre_ipd(32), papre(32), tipd_papre(32));
VitalWireDelay (papre_ipd(33), papre(33), tipd_papre(33));
VitalWireDelay (papre_ipd(34), papre(34), tipd_papre(34));
VitalWireDelay (papre_ipd(35), papre(35), tipd_papre(35));
VitalWireDelay (papre_ipd(36), papre(36), tipd_papre(36));
VitalWireDelay (papre_ipd(37), papre(37), tipd_papre(37));
VitalWireDelay (papre_ipd(38), papre(38), tipd_papre(38));
VitalWireDelay (papre_ipd(39), papre(39), tipd_papre(39));
VitalWireDelay (papre_ipd(40), papre(40), tipd_papre(40));
VitalWireDelay (papre_ipd(41), papre(41), tipd_papre(41));
VitalWireDelay (papre_ipd(42), papre(42), tipd_papre(42));
VitalWireDelay (papre_ipd(43), papre(43), tipd_papre(43));
VitalWireDelay (papre_ipd(44), papre(44), tipd_papre(44));
VitalWireDelay (papre_ipd(45), papre(45), tipd_papre(45));
VitalWireDelay (papre_ipd(46), papre(46), tipd_papre(46));
VitalWireDelay (papre_ipd(47), papre(47), tipd_papre(47));
VitalWireDelay (papre_ipd(48), papre(48), tipd_papre(48));
VitalWireDelay (papre_ipd(49), papre(49), tipd_papre(49));
VitalWireDelay (papre_ipd(50), papre(50), tipd_papre(50));
VitalWireDelay (papre_ipd(51), papre(51), tipd_papre(51));
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
end block;
VITALtiming : process(datain, ptermclk, pclk_ipd, pena_ipd, paclr_ipd,
papre_ipd, clk_ipd, aclr_ipd, ena_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_penable_clk : std_ulogic := '0';
variable Tviol_clk : std_ulogic := '0';
variable Tviol_datain_ptermclk : std_ulogic := '0';
variable Tviol_ptermclk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_pena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datain_pclk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable fbkout_VitalGlitchData : VitalGlitchDataType;
variable tmp_regout : std_logic;
variable oldclk : std_logic;
variable pterm_aclr : std_logic;
variable pterm_preset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
penable <= product(pena_ipd);
pterm_aclr := product(paclr_ipd);
pterm_preset := product(papre_ipd);
ptermclk <= product(pclk_ipd);
for N in 0 to 51 loop
if (papre_ipd(N) = 'U') then
pterm_preset := '0';
end if;
exit when pterm_preset = '0';
end loop;
for N in 0 to 51 loop
if (paclr_ipd(N) = 'U') then
pterm_aclr := '0';
end if;
exit when pterm_aclr = '0';
end loop;
for N in 0 to 51 loop
if (pclk_ipd(N) = 'U') then
ptermclk <= '0';
end if;
exit when ptermclk = '0';
end loop;
if (now <= 0 ns) then
if (power_up = "low") then
tmp_regout := '0';
elsif (power_up = "high") then
tmp_regout := '1';
end if;
ptermclk <= '0';
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_penable_clk,
TimingData => TimingData_pena_clk,
TestSignal => pena_ipd,
TestSignalName => "PENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_pena_clk_noedge_posedge(0),
SetupLow => tsetup_pena_clk_noedge_posedge(0),
HoldHigh => thold_pena_clk_noedge_posedge(0),
HoldLow => thold_pena_clk_noedge_posedge(0),
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datain_ptermclk,
TimingData => TimingData_datain_pclk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => ptermclk,
RefSignalName => "PCLK",
SetupHigh => tsetup_datain_pclk_noedge_posedge(0),
SetupLow => tsetup_datain_pclk_noedge_posedge(0),
HoldHigh => thold_datain_pclk_noedge_posedge(0),
HoldLow => thold_datain_pclk_noedge_posedge(0),
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := (Tviol_datain_clk or Tviol_datain_ptermclk or Tviol_penable_clk);
if ((aclr_ipd = '1') or (pterm_aclr = '1')) then
tmp_regout := '0';
elsif (pterm_preset = '1') then
tmp_regout := '1';
elsif (violation = 'X') then
tmp_regout := 'X';
elsif (penable = '1') then
if ((clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') or ((ptermclk'event) and (oldclk = '0') and (ptermclk = '1'))) then
tmp_regout := datain;
end if;
end if;
oldclk := ptermclk;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE),
2 => (pclk_ipd'last_event, tpd_pclk_regout_posedge(0), TRUE),
3 => (pena_ipd'last_event, tpd_pena_regout_posedge(0), TRUE),
4 => (paclr_ipd'last_event, tpd_paclr_regout_posedge(0), TRUE),
5 => (papre_ipd'last_event, tpd_papre_regout_posedge(0), TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => fbkout,
OutSignalName => "FBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE),
2 => (pclk_ipd'last_event, tpd_pclk_regout_posedge(0), TRUE),
3 => (pena_ipd'last_event, tpd_pena_regout_posedge(0), TRUE),
4 => (paclr_ipd'last_event, tpd_paclr_regout_posedge(0), TRUE),
5 => (papre_ipd'last_event, tpd_papre_regout_posedge(0), TRUE)),
GlitchData => fbkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_mcell_reg;
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_mcell;
use work.max_mcell_register;
entity max_mcell is
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
output_mode : string := "comb";
register_mode : string := "false";
power_up : string := "low" );
port ( pterm0 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm1 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm2 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm3 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm4 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm5 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pclk : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
papre : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pxor : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pexpin : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
fpin : in std_logic := '1';
dataout : out std_logic;
pexpout : out std_logic );
attribute VITAL_LEVEL0 of max_mcell : entity is TRUE;
end max_mcell;
architecture vital_mcell_atom of max_mcell is
attribute VITAL_LEVEL0 of vital_mcell_atom : architecture is TRUE;
component max_asynch_mcell
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pterm0_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pxor_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_combout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fpin_regin : VitalDelayType01 := DefPropDelay01;
tipd_pterm0 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm1 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm2 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm3 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm4 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm5 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_fpin : VitalDelayType01 := DefPropDelay01;
tipd_pxor : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pexpin : VitalDelayType01 := DefPropDelay01);
port ( pterm0 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm1 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm2 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm3 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm4 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm5 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
fpin : in std_logic := '1';
pxor : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pexpin : in std_logic := '0';
fbkin : in std_logic;
combout : out std_logic;
regin : out std_logic;
pexpout : out std_logic );
end component;
component max_mcell_register
generic ( operation_mode : string := "normal";
power_up : string := "low";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pclk_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pclk_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tipd_pclk : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pena : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_paclr : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_papre : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
port ( datain : in std_logic;
clk : in std_logic;
aclr : in std_logic;
pclk : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
papre : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
regout : out std_logic;
fbkout : out std_logic);
end component;
signal fbk, dffin, combo, dffo :std_ulogic ;
begin
pcom: max_asynch_mcell
generic map ( operation_mode => operation_mode,
pexp_mode => pexp_mode, register_mode => register_mode)
port map ( pterm0 => pterm0,
pterm1 => pterm1,
pterm2 => pterm2,
pterm3 => pterm3,
pterm4 => pterm4,
pterm5 => pterm5,
fpin => fpin,
pxor => pxor,
pexpin => pexpin,
fbkin => fbk,
regin => dffin,
combout => combo,
pexpout => pexpout);
preg: max_mcell_register
generic map ( operation_mode => operation_mode,
power_up => power_up,
register_mode => register_mode)
port map ( datain => dffin,
clk => clk,
aclr => aclr,
pclk => pclk,
pena => pena,
paclr => paclr,
papre => papre,
regout => dffo,
fbkout => fbk);
dataout <= combo when output_mode = "comb" else dffo;
end vital_mcell_atom;
--
--
-- MAX7K_SEXP Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_sexp is
generic ( TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_datain_dataout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_datain : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01));
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout : out STD_LOGIC);
attribute VITAL_LEVEL0 of max_asynch_sexp : entity is TRUE;
end max_asynch_sexp;
architecture behave of max_asynch_sexp is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic_vector(51 downto 0) := (OTHERS => 'U');
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd(0), datain(0), tipd_datain(0));
VitalWireDelay (datain_ipd(1), datain(1), tipd_datain(1));
VitalWireDelay (datain_ipd(2), datain(2), tipd_datain(2));
VitalWireDelay (datain_ipd(3), datain(3), tipd_datain(3));
VitalWireDelay (datain_ipd(4), datain(4), tipd_datain(4));
VitalWireDelay (datain_ipd(5), datain(5), tipd_datain(5));
VitalWireDelay (datain_ipd(6), datain(6), tipd_datain(6));
VitalWireDelay (datain_ipd(7), datain(7), tipd_datain(7));
VitalWireDelay (datain_ipd(8), datain(8), tipd_datain(8));
VitalWireDelay (datain_ipd(9), datain(9), tipd_datain(9));
VitalWireDelay (datain_ipd(10), datain(10), tipd_datain(10));
VitalWireDelay (datain_ipd(11), datain(11), tipd_datain(11));
VitalWireDelay (datain_ipd(12), datain(12), tipd_datain(12));
VitalWireDelay (datain_ipd(13), datain(13), tipd_datain(13));
VitalWireDelay (datain_ipd(14), datain(14), tipd_datain(14));
VitalWireDelay (datain_ipd(15), datain(15), tipd_datain(15));
VitalWireDelay (datain_ipd(16), datain(16), tipd_datain(16));
VitalWireDelay (datain_ipd(17), datain(17), tipd_datain(17));
VitalWireDelay (datain_ipd(18), datain(18), tipd_datain(18));
VitalWireDelay (datain_ipd(19), datain(19), tipd_datain(19));
VitalWireDelay (datain_ipd(20), datain(20), tipd_datain(20));
VitalWireDelay (datain_ipd(21), datain(21), tipd_datain(21));
VitalWireDelay (datain_ipd(22), datain(22), tipd_datain(22));
VitalWireDelay (datain_ipd(23), datain(23), tipd_datain(23));
VitalWireDelay (datain_ipd(24), datain(24), tipd_datain(24));
VitalWireDelay (datain_ipd(25), datain(25), tipd_datain(25));
VitalWireDelay (datain_ipd(26), datain(26), tipd_datain(26));
VitalWireDelay (datain_ipd(27), datain(27), tipd_datain(27));
VitalWireDelay (datain_ipd(28), datain(28), tipd_datain(28));
VitalWireDelay (datain_ipd(29), datain(29), tipd_datain(29));
VitalWireDelay (datain_ipd(30), datain(30), tipd_datain(30));
VitalWireDelay (datain_ipd(31), datain(31), tipd_datain(31));
VitalWireDelay (datain_ipd(32), datain(32), tipd_datain(32));
VitalWireDelay (datain_ipd(33), datain(33), tipd_datain(33));
VitalWireDelay (datain_ipd(34), datain(34), tipd_datain(34));
VitalWireDelay (datain_ipd(35), datain(35), tipd_datain(35));
VitalWireDelay (datain_ipd(36), datain(36), tipd_datain(36));
VitalWireDelay (datain_ipd(37), datain(37), tipd_datain(37));
VitalWireDelay (datain_ipd(38), datain(38), tipd_datain(38));
VitalWireDelay (datain_ipd(39), datain(39), tipd_datain(39));
VitalWireDelay (datain_ipd(40), datain(40), tipd_datain(40));
VitalWireDelay (datain_ipd(41), datain(41), tipd_datain(41));
VitalWireDelay (datain_ipd(42), datain(42), tipd_datain(42));
VitalWireDelay (datain_ipd(43), datain(43), tipd_datain(43));
VitalWireDelay (datain_ipd(44), datain(44), tipd_datain(44));
VitalWireDelay (datain_ipd(45), datain(45), tipd_datain(45));
VitalWireDelay (datain_ipd(46), datain(46), tipd_datain(46));
VitalWireDelay (datain_ipd(47), datain(47), tipd_datain(47));
VitalWireDelay (datain_ipd(48), datain(48), tipd_datain(48));
VitalWireDelay (datain_ipd(49), datain(49), tipd_datain(49));
VitalWireDelay (datain_ipd(50), datain(50), tipd_datain(50));
VitalWireDelay (datain_ipd(51), datain(51), tipd_datain(51));
end block;
VITAL: process(datain_ipd)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable tmp_dataout : std_logic;
begin
tmp_dataout := not (product(datain_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout(0), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- MAX_SEXP
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_sexp;
entity max_sexp is
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout : out std_logic);
end max_sexp;
architecture structure of max_sexp is
signal data_out : std_logic;
component max_asynch_sexp
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout: out STD_LOGIC);
end component;
begin
pcom: max_asynch_sexp
port map ( datain => datain,
dataout => data_out);
dataout <= data_out;
end structure;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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7wUKes/G3A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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ATruKUzAJXwuE8GFWg0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
--
-- Testbench for MICROBUS evaluation.
--
-- $Id: tb_microbus.vhd,v 1.1 2006-06-05 21:04:52 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_microbus is
end tb_microbus;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.all;
use work.t400_opt_pack.all;
architecture behav of tb_microbus is
-- 5 MHz clock
constant period_c : time := 200 ns;
signal ck_s : std_logic;
signal en_ck_s : std_logic := '0';
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
signal tb_io_l_s : std_logic_vector(7 downto 0);
begin
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_microbus_g => t400_opt_microbus_c
)
port map (
ck_i => ck_s,
ck_en_i => en_ck_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => tb_io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Generates the en_ck_s signal from the high frequency clock.
--
ck_div: process (ck_s)
variable cnt_v : natural := 0;
begin
if ck_s'event and ck_s = '1' then
en_ck_s <= '0';
if cnt_v = 25 then
cnt_v := 0;
en_ck_s <= '1';
else
cnt_v := cnt_v + 1;
end if;
end if;
end process ck_div;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process microbus
--
-- Purpose:
-- Implements the microbus testbench element.
-- a) sends twelve bytes of data to the DUT
-- HELLO WORLD!
-- b) reads twelve bytes from the DUT and compares them against
-- the original sequence
--
microbus: process
procedure tb_pass_fail(pass : in boolean) is
begin
tb_io_l_s <= "00000000";
wait for 1 us;
tb_io_l_s <= "10100000";
wait for 1 us;
tb_io_l_s <= "01010000";
wait for 1 us;
if pass then
tb_io_l_s <= "00000000";
else
tb_io_l_s <= "11110000";
end if;
wait for 1 us;
end;
constant msg_c : string := string'("HELLO WORLD!");
begin
-- default settings
cs_n_s <= '1';
rd_n_s <= '1';
wr_n_s <= '1';
io_l_s <= (others => 'H');
tb_io_l_s <= (others => '0');
--
-- send the message string
--
for idx in msg_c'range loop
wait until io_g_s(0)'event and io_g_s(0) = '1';
if idx mod 2 = 0 then
-- short wait for even positions
wait for 1 us;
else
-- long wait for odd positions
wait for 1 ms;
end if;
io_l_s <= std_logic_vector(to_unsigned(character'pos(msg_c(idx)), 8));
wait for 10 ns;
cs_n_s <= '0';
wr_n_s <= '0';
wait for 400 ns;
cs_n_s <= '1';
wr_n_s <= '1';
wait for 10 ns;
io_l_s <= (others => 'H');
end loop;
--
-- and receive it again
--
for idx in msg_c'range loop
wait until io_g_s(0)'event and io_g_s(0) = '1';
if idx mod 2 = 0 then
-- short wait for even positions
wait for 1 us;
else
-- long wait for odd positions
wait for 1 ms;
end if;
cs_n_s <= '0';
rd_n_s <= '0';
wait for 400 ns;
if character'pos(msg_c(idx)) /= to_integer(unsigned(io_l_s)) then
tb_pass_fail(pass => false);
end if;
cs_n_s <= '1';
rd_n_s <= '1';
-- ack with dummy write
wait for 1 us;
cs_n_s <= '0';
wr_n_s <= '0';
wait for 400 ns;
cs_n_s <= '1';
wr_n_s <= '1';
end loop;
tb_pass_fail(pass => true);
wait;
end process microbus;
--
io_in_s(1) <= rd_n_s;
io_in_s(2) <= cs_n_s;
io_in_s(3) <= wr_n_s;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity test_file_RAM is
end test_file_RAM;
architecture behavioural of test_file_RAM is
component file_RAM is
generic (
filename: string
);
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end component file_RAM;
signal write_enable : std_logic;
signal address : std_logic_vector(9 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal period: time := 10 ns;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
begin
clock <= not clock after period/2 when finished='0';
memory : file_RAM generic map (filename => "ram_1024.mif")
port map (clock, write_enable, address, data_in, data_out);
process
begin
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
wait for period;
assert data_out = "00000000"
report "file_RAM should start at zero" severity error;
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
wait for period;
assert data_out = "01010101"
report "file_RAM should store values" severity error;
address <= "0000000001";
wait for period;
assert data_out = "00000001"
report "data should be sequential in ram" severity error;
address <= "0000000010";
wait for period;
assert data_out = "00000010"
report "data should be sequential in ram" severity error;
address <= "0000010010";
wait for period;
assert data_out = "00010010"
report "data should be sequential in ram" severity error;
finished <= '1';
wait;
end process;
end behavioural;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_v2_prac4 IS
END test_fsm_v2_prac4;
ARCHITECTURE behavior OF test_fsm_v2_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic;
DEBUG_CHECK : OUT std_logic_vector (3 downto 0);
DEBUG_OUT : OUT std_logic_vector (3 downto 0)
);
END COMPONENT;
signal X : std_logic := '0';
signal RESET : std_logic := '0';
signal clk100mhz : std_logic := '0';
signal Z : std_logic;
signal DEBUG_CHECK : std_logic_vector(3 downto 0) := (others => '0');
signal DEBUG_OUT : std_logic_vector(3 downto 0) := (others => '0');
signal check_data_line : std_logic_vector (15 downto 0) := "0101110110011010";
signal check_data_match : std_logic_vector (15 downto 0) := "0000000000000000";
signal check_state_trans : std_logic_vector (19 downto 0) := "11010011101100011010";
constant clk100mhz_period : time := 10 ns;
signal full_check_state : std_logic_vector(31 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
BEGIN
full_check_state(31 downto 16) <= check_data_line;
full_check_state(15 downto 0) <= check_data_match;
uut: fsm_prac4 PORT MAP (
X => X,
RESET => RESET,
clk100mhz => clk100mhz,
Z => Z,
DEBUG_CHECK => DEBUG_CHECK,
DEBUG_OUT => DEBUG_OUT
);
-- Clock process definitions
clk100mhz_process :process
begin
clk100mhz <= '0';
wait for clk100mhz_period/2;
clk100mhz <= '1';
wait for clk100mhz_period/2;
end process;
RESET <= '1';
-- Stimulus process
-- stim_proc: process
-- begin
-- RESET <= '0' ;
-- wait for clk100mhz_period*10;
-- RESET <= '1' ;
-- wait for clk100mhz_period*10;
--
-- FOR I in 19 downto 0 loop
-- wait until clk100mhz'event;
-- if clk100mhz = '1' then
-- X <= check_state_trans(I);
-- end if;
-- --assert ( Z = check_data_match(I) ) report "MATCH ERROR" severity error;
-- END loop;
-- wait until clk100mhz'event and clk100mhz = '1';
--
-- wait for clk100mhz_period*10;
-- wait;
-- end process;
tester : process (clk100mHz)
variable counter : counter_bit_int := 0;
begin
--wait until submitButton'event and submitButton = '1' ;
if (clk100mhz'event and clk100mhz = '1') then
if (counter >= 0) then
X <= full_check_state(counter);
counter := counter - 1;
else
counter := 31;
end if;
end if;
end process;
END;
|
--
-- File Name: RandomBasePkg.vhd
-- Design Unit Name: RandomBasePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Defines Base randomization, seed definition, seed generation,
-- and seed IO functionality for RandomPkg.vhd
-- Defines:
-- Procedure Uniform - baseline randomization
-- Type RandomSeedType - the seed as a single object
-- function GenRandSeed from integer_vector, integer, or string
-- IO function to_string, & procedures write, read
--
-- In revision 2.0 these types and functions are included by package reference.
-- Long term these will be passed as generics to RandomGenericPkg
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference
-- to ieee_proposed.standard_additions.all ;
-- 03/01/2011 2.0 STANDARD VERSION
-- Fixed abstraction by moving RandomParmType to RandomPkg.vhd
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No Changes
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 6/2015 2015.06 Changed GenRandSeed to impure
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.math_real.all ;
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package RandomBasePkg is
-- RandomSeedType and Uniform can be replaced by any procedure that
-- produces a uniform distribution with 0 <= Value < 1 or 0 < Value < 1
-- and maintains the same call interface
type RandomSeedType is array (1 to 2) of integer ;
procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- Translate from integer_vector, integer, or string to RandomSeedType
-- Required by RandomPkg.InitSeed
-- GenRandSeed makes sure all values are in a valid range
impure function GenRandSeed(IV : integer_vector) return RandomSeedType ;
impure function GenRandSeed(I : integer) return RandomSeedType ;
impure function GenRandSeed(S : string) return RandomSeedType ;
-- IO for RandomSeedType. If use subtype, then create aliases here
-- in a similar fashion VHDL-2008 std_logic_textio.
-- Not required by RandomPkg
function to_string(A : RandomSeedType) return string ;
procedure write(variable L: inout line ; A : RandomSeedType ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ; good : out boolean ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ) ;
end RandomBasePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomBasePkg is
-----------------------------------------------------------------
-- Uniform
-- Generate a random number with a Uniform distribution
-- Required by RandomPkg. All randomization is derived from here.
-- Value produced must be either:
-- 0 <= Value < 1 or 0 < Value < 1
--
-- Current version uses ieee.math_real.Uniform
-- This abstraction allows higher precision version
-- of a uniform distribution to be used provided
--
procedure Uniform (
Result : out real ;
Seed : inout RandomSeedType
) is
begin
ieee.math_real.Uniform (Seed(Seed'left), Seed(Seed'right), Result) ;
end procedure Uniform ;
-----------------------------------------------------------------
-- GenRandSeed
-- Convert integer_vector to RandomSeedType
-- Uniform requires two seed values of the form:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
--
-- if 2 seed values are passed to GenRandSeed and they are
-- in the above range, then they must remain unmodified.
--
impure function GenRandSeed(IV : integer_vector) return RandomSeedType is
alias iIV : integer_vector(1 to IV'length) is IV ;
variable Seed1 : integer ;
variable Seed2 : integer ;
constant SEED1_MAX : integer := 2147483562 ;
constant SEED2_MAX : integer := 2147483398 ;
begin
if iIV'Length <= 0 then -- no seed
Alert(OSVVM_ALERTLOG_ID, "RandomBasePkg.GenRandSeed received NULL integer_vector", FAILURE) ;
return (3, 17) ; -- if continue seed = (3, 17)
elsif iIV'Length = 1 then -- one seed value
-- inefficient handling, but condition is unlikely
return GenRandSeed(iIV(1)) ; -- generate a seed
else -- only use the left two values
-- 1 <= SEED1 <= 2147483562
-- mod returns 0 to MAX-1, the -1 adjusts legal values, +1 adjusts them back
Seed1 := ((iIV(1)-1) mod SEED1_MAX) + 1 ;
-- 1 <= SEED2 <= 2147483398
Seed2 := ((iIV(2)-1) mod SEED2_MAX) + 1 ;
return (Seed1, Seed2) ;
end if ;
end function GenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed
-- transform a single integer into the internal seed
--
impure function GenRandSeed(I : integer) return RandomSeedType is
variable result : integer_vector(1 to 2) ;
begin
result(1) := I ;
result(2) := I/3 + 1 ;
return GenRandSeed(result) ; -- make value ranges legal
end function GenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed
-- transform a string value into the internal seed
-- usage: RV.GenRandSeed(RV'instance_path));
--
impure function GenRandSeed(S : string) return RandomSeedType is
constant LEN : integer := S'length ;
constant HALF_LEN : integer := LEN/2 ;
alias revS : string(LEN downto 1) is S ;
variable result : integer_vector(1 to 2) ;
variable temp : integer := 0 ;
begin
for i in 1 to HALF_LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(1) := temp ;
for i in HALF_LEN + 1 to LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(2) := temp ;
return GenRandSeed(result) ; -- make value ranges legal
end function GenRandSeed ;
-----------------------------------------------------------------
function to_string(A : RandomSeedType) return string is
begin
return to_string(A(A'left)) & " " & to_string(A(A'right)) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L: inout line ; A : RandomSeedType ) is
begin
write(L, to_string(A)) ;
end procedure ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ; good : out boolean ) is
variable iReadValid : boolean ;
begin
for i in A'range loop
read(L, A(i), iReadValid) ;
exit when not iReadValid ;
end loop ;
good := iReadValid ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot(ReadValid, OSVVM_ALERTLOG_ID, "RandomBasePkg.read[line, RandomSeedType] failed", FAILURE) ;
end procedure read ;
end RandomBasePkg ; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "Mux4x1_10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux4x1_10_0_0_arch : ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux4x1_10,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "Mux4x1_10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux4x1_10_0_0_arch : ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux4x1_10,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
|
package logicbricks is
-- START COMPONENT
component logicvc is
generic (
-- Version generics
C_IP_LICENSE_TYPE : integer := 0; -- IP encryption type: 0 = source, 1 = evaluation, 2 = release, 3 = university evaluation
C_IP_MAJOR_REVISION : integer := 0; -- IP major revision: 0 - 31; vXX_yy_z
C_IP_MINOR_REVISION : integer := 0; -- IP minor revision: 0 - 31; vxx_YY_z
C_IP_PATCH_LEVEL : integer := 0; -- IP patch level: 0 - 25; vxx_yy_Z
C_IP_LICENSE_CHECK : integer := 0; -- IP license check: 0 = no, 1 = yes
C_IP_TIME_BEFORE_BREAK : integer := 0; -- IP time before break: 0 = infinite, 1 = 1h, 2 = 12h, 3 = 24h
C_FAMILY : string := "spartan6";
-- Video memory generics
C_VMEM_INTERFACE : integer := 0; -- Use PLB, XMB or AXI to access video memory: 0 - PLB, 1 - XMB, 2 - AXI
C_VMEM_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_VMEM_HIGHADDR : std_logic_vector := x"00000000";
C_MEM_BURST : integer := 4; -- Memory burst width; 4, 5 or 6. (4 means burst lasts 16 transfers), Used for XMB and AXI
C_MEM_BYTE_SWAP : integer := 0; -- Memory access byte swap: 0 - Do not swap, 1 - Swap
C_MEM_LITTLE_ENDIAN : integer := 1; -- Memory access endianness: 0 - Big endian, 1 - Little endian
C_INCREASE_FIFO : integer := 1; -- FIFO size multiplication factor: 1=1x, 2=2x, 4=4x, 8=8x
-- Master PLB generics
C_MPLB_NUM_MASTERS : integer := 8;
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 64;
C_MPLB_PRIORITY : integer := 3;
C_MPLB_SMALLEST_SLAVE : integer := 32;
-- XMB generics
C_XMB_DATA_BUS_WIDTH : integer := 64; -- XMB Memory interface data bus width
-- Master AXI generics
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_M_AXI_DATA_WIDTH : integer := 64;
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Registers generics
C_REGS_INTERFACE : integer := 0; -- Use OPB, PLB or AXI interface for registers: 0 - OPB, 1 - PLB, 2 - AXI
C_READABLE_REGS : integer := 1; -- Are logiCVC registers readable?: 0 - no, 1 - yes
C_REG_BYTE_SWAP : integer := 0; -- Registers access byte swap: 0 - Do not swap, 1 - Swap
-- OPB generics
C_REGS_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_REGS_HIGHADDR : std_logic_vector := x"00000000";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
-- Slave PLB generics
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 1;
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
-- AXI4-Lite Slave generics
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
-- Output format
C_PIXEL_DATA_WIDTH : integer := 24; -- Output data width: 12, 15, 16, 18 or 24
C_USE_VCLK2 : integer := 1; -- pix_clk rising edge will be in the middle of the DDR RGB data eye or synchronous if not used
C_ROW_STRIDE : integer := 1024; -- Row stride in number of pixels
C_XCOLOR : integer := 0;
C_USE_SIZE_POSITION : integer := 0; -- Use layer size, position and offset functionality: 0 - no, 1 - yes
C_DISPLAY_INTERFACE : integer := 0; -- Select output interface type: 0 - parallel only, 1 - ITU656, 2 - LVDS 4bit, 3 - camera link, 4 - LVDS 3bit, 5 - DVI
C_DISPLAY_COLOR_SPACE : integer := 0; -- Select output interface color space: 0 - RGB, 1 - YCbCr 4:2:2, 2 - YCbCr 4:4:4
C_LVDS_DATA_WIDTH : integer := 4; -- 3 or 4
C_VCLK_PERIOD : integer := 25000; -- vclk clock period in ps
-- Multilayer generics
C_NUM_OF_LAYERS : positive := 3; -- Number of logiCVC layers: 1, 2, 3, 4 or 5
C_LAYER_0_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_1_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha
C_LAYER_2_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_3_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha
C_LAYER_4_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_0_DATA_WIDTH : positive := 16; -- Layer 0 data width: 8, 16, 24 bit
C_LAYER_1_DATA_WIDTH : positive := 16; -- Layer 1 data width: 8, 16, 24 bit
C_LAYER_2_DATA_WIDTH : positive := 16; -- Layer 2 data width: 8, 16, 24 bit
C_LAYER_3_DATA_WIDTH : positive := 16; -- Layer 3 data width: 8, 16, 24 bit
C_LAYER_4_DATA_WIDTH : positive := 16; -- Layer 4 data width: 8, 16, 24 bit
C_LAYER_0_ALPHA_MODE : integer := 0; -- Layer 0 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_1_ALPHA_MODE : integer := 0; -- Layer 1 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_2_ALPHA_MODE : integer := 0; -- Layer 2 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_3_ALPHA_MODE : integer := 0; -- Layer 3 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_4_ALPHA_MODE : integer := 0; -- Layer 4 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_USE_BACKGROUND : integer := 0; -- configure last layer as background: 0 - no, 1 - yes
C_USE_XTREME_DSP : integer := 2; -- enable or disable use of DSP resources: 0 - no, 1 - yes, 2 - auto
C_USE_MULTIPLIER : integer := 2; -- control way in which multipliers in blender are implemented: 0 - lut, 1 - block, 2 - auto
C_LAYER_0_OFFSET : natural := 0; -- address offset for layer 0 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_1_OFFSET : natural := 2048; -- address offset for layer 1 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_2_OFFSET : natural := 4096; -- address offset for layer 2 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_3_OFFSET : natural := 6144; -- address offset for layer 3 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_4_OFFSET : natural := 8192; -- address offset for layer 4 in 2k steps for 16bpp and 1k steps for 8bpp
C_BUFFER_0_OFFSET : natural := 1024; -- address offset for layer 0 double buffer relative to LAYER_0_OFFSET
C_BUFFER_1_OFFSET : natural := 1024; -- address offset for layer 1 double buffer relative to LAYER_1_OFFSET
C_BUFFER_2_OFFSET : natural := 1024; -- address offset for layer 2 double buffer relative to LAYER_2_OFFSET
C_BUFFER_3_OFFSET : natural := 1024; -- address offset for layer 3 double buffer relative to LAYER_3_OFFSET
C_BUFFER_4_OFFSET : natural := 1024; -- address offset for layer 4 double buffer relative to LAYER_4_OFFSET
-- Extern parallel input generics
C_USE_E_PARALLEL_INPUT : integer := 0; -- Syncronize logiCVC to external parallel input and use data as one layer: 0 - no, 1 - yes
C_USE_E_VCLK_BUFGMUX : integer := 1; -- Use BUFGMUX for switching video clock to e_vclk, else use vclk
C_E_LAYER : integer := 0; -- External parallel input layer: 0, 1, 2, 3, 4
C_E_DATA_WIDTH : integer := 24 -- External parallel input data width: 8, 16, 24 bit
);
port(
rst : in std_logic; -- Global reset
mclk : in std_logic; -- Memory clock
vclk : in std_logic; -- Video clock
vclk2 : in std_logic; -- Video clock x2
itu_clk_in : in std_logic; -- It has to be 27 MHz and synchronous to vclk
lvds_clk : in std_logic; -- lvds clock is 3.5x video clock
lvds_clkn : in std_logic; -- Inverted lvds_clk
-- Xylon Memory Bus (XMB)
mem_req : out std_logic;
mem_wr : out std_logic;
mem_ack : in std_logic := '0';
mem_addr : out std_logic_vector(31 downto 0);
mem_data : out std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0);
mem_data_be : out std_logic_vector(C_XMB_DATA_BUS_WIDTH / 8 - 1 downto 0);
mem_wrack : in std_logic := '0';
mem_burst : out std_logic_vector(C_MEM_BURST - 1 downto 0);
mem_data_valid : in std_logic := '0';
mem_data_in : in std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0) := (others => '0');
-- PLB --------------
-- Master
mplb_rst : in std_logic;
plb_maddrack : in std_logic;
plb_mrearbitrate : in std_logic;
plb_mssize : in std_logic_vector(0 to 1);
plb_mbusy : in std_logic;
plb_mrderr : in std_logic;
plb_mwrerr : in std_logic;
plb_mtimeout : in std_logic;
plb_mirq : in std_logic;
m_request : out std_logic;
m_priority : out std_logic_vector(0 to 1);
m_buslock : out std_logic;
m_rnw : out std_logic;
m_be : out std_logic_vector(0 to (C_MPLB_DWIDTH / 8) - 1);
m_size : out std_logic_vector(0 to 3);
m_type : out std_logic_vector(0 to 2);
m_msize : out std_logic_vector(0 to 1);
m_tattribute : out std_logic_vector(0 to 15);
m_lockerr : out std_logic;
m_abort : out std_logic;
m_abus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1));
m_uabus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1));
plb_mwrdack : in std_logic;
plb_mwrbterm : in std_logic;
m_wrburst : out std_logic;
m_wrdbus : out std_logic_vector(0 to (C_MPLB_DWIDTH - 1));
plb_mrddack : in std_logic;
plb_mrdbterm : in std_logic;
plb_mrdwdaddr : in std_logic_vector(0 to 3);
plb_mrddbus : in std_logic_vector(0 to (C_MPLB_DWIDTH - 1));
m_rdburst : out std_logic;
-- AXI --------------
-- Master
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH / 8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
----------------------
-- OPB --------------
-- Slave
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH / 8 - 1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1);
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
----------------------
-- PLB --------------
-- Slave
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH - 1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH / 8 - 1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_tattribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH - 1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH - 1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
----------------------
-- AXI4-Lite --------
-- Slave
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
----------------------
-- Video Outputs --------------
pix_clk_i : in std_logic; -- Pixel clock
pix_clk_o : out std_logic; -- Pixel clock
pix_clk_t : out std_logic; -- Pixel clock
pix_clk_n_i : in std_logic; -- Pixel clock inverted
pix_clk_n_o : out std_logic; -- Pixel clock inverted
pix_clk_n_t : out std_logic; -- Pixel clock inverted
d_pix_i : in std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus
d_pix_o : out std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus
d_pix_t : out std_logic; -- Pixel data bus
hsync_i : in std_logic; -- Hsync
hsync_o : out std_logic; -- Hsync
hsync_t : out std_logic; -- Hsync
vsync_i : in std_logic; -- Vsync
vsync_o : out std_logic; -- Vsync
vsync_t : out std_logic; -- Vsync
blank_i : in std_logic; -- Blank
blank_o : out std_logic; -- Blank
blank_t : out std_logic; -- Blank
itu656_clk_o : out std_logic; -- ITU656 clock output
itu656_data_o : out std_logic_vector(7 downto 0); -- ITU656 data output
lvds_data_out_p : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, positive
lvds_data_out_n : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, negative
lvds_clk_out_p : out std_logic; -- lvds clk, positive
lvds_clk_out_n : out std_logic; -- lvds clk, negative
pllvclk_locked : in std_logic; -- PLL_BASE LOCKED (spartan6, LVDS clk gen)
dvi_clk_p : out std_logic; -- DVI clock, positive
dvi_clk_n : out std_logic; -- DVI clock, negative
dvi_data_p : out std_logic_vector(2 downto 0); -- DVI data, positive
dvi_data_n : out std_logic_vector(2 downto 0); -- DVI data, negative
----------------------
-- External parallel input --------------
e_vclk : in std_logic; -- External video clock
e_vsync : in std_logic; -- External vsync
e_hsync : in std_logic; -- External hsync
e_blank : in std_logic; -- External blank
e_data : in std_logic_vector(C_E_DATA_WIDTH - 1 downto 0); -- External data
e_video_present : in std_logic; -- External video present flag
----------------------
-- Other --------------
e_curr_vbuff : in std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Current external stream vbuffer
e_next_vbuff : out std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Next external stream vbuffer to write to
e_sw_vbuff : in std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Switch video buffers from external source
e_sw_grant : out std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Video buffers switch req granted
vcdivsel : out std_logic_vector(1 downto 0); -- vclk div select bits
vclksel : out std_logic_vector(2 downto 0); -- vclk select bits
en_vdd : out std_logic; -- vdd enable
en_blight : out std_logic; -- backlight enable
v_en : out std_logic; -- Enable display control/data signals
en_vee : out std_logic; -- vee enable
interrupt : out std_logic -- logiCVC interrupt signal, level sensitive, high active
);
end component;
end logicbricks;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the pulse generator.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PulseGenerator_Tester is
end entity;
architecture stdarch of PulseGenerator_Tester is
--------------------
-- Constants
--------------------
constant counter_width: natural := 32;
constant clk_period: time := 5ns;
constant test_high_duration: unsigned(counter_width-1 downto 0) := to_unsigned(16, counter_width);
constant test_low_duration: unsigned(counter_width-1 downto 0) := to_unsigned(8, counter_width);
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal high_duration: unsigned(counter_width-1 downto 0) := test_high_duration;
signal low_duration: unsigned(counter_width-1 downto 0) := test_low_duration;
--------------------
-- Outputs
--------------------
signal pulse_signal: std_logic;
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
begin
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.PulseGenerator
generic map
(
counter_width => counter_width
)
port map
(
clk => clk,
high_duration => high_duration,
low_duration => low_duration,
pulse_signal => pulse_signal
);
--------------------------------------------------------------------------------
-- UUT stimulation.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
begin
-- Do the tests for the specified duration.
wait for 5 * (to_integer(test_high_duration) + to_integer(test_low_duration)) * clk_period;
-- Stop the tests.
run_test <= false;
wait;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper frequency signal generation.
must_create_correct_pulse_signal: process is
variable startup: boolean := true;
begin
-- Wait for the pulse generator to settle down after powered up.
if startup then
wait until rising_edge(pulse_signal);
wait until falling_edge(pulse_signal);
startup := false;
end if;
-- Verify the correct duration of high and the low phase.
for i in 1 to to_integer(test_low_duration) loop
wait until falling_edge(clk);
assert (pulse_signal = '0') report "Signal not set or held to '0'." severity error;
end loop;
for i in 1 to to_integer(test_high_duration) loop
wait until falling_edge(clk);
assert (pulse_signal = '1') report "Signal not set or held to '1'." severity error;
end loop;
end process;
end architecture;
|
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer;
variable y : my_int;
begin
assert integer'left = -2147483648;
x := integer'right;
wait for 1 ns;
assert x = 2147483647;
assert positive'left = 1;
assert natural'high = integer'high;
assert integer'ascending;
assert not my_int'ascending;
x := 0;
wait for 1 ns;
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
x := 1;
y := 1;
wait for 1 ns;
assert integer'leftof(x) = 0;
assert integer'rightof(x) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
assert my_int'base'left = 10;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity main_file is
Port (
--JA_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JB_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JC_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JD_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
slide_switch : in STD_LOGIC_VECTOR (7 downto 0);
--push_button : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_kath : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_an : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
usb_db : inout std_logic_vector(7 downto 0);
usb_write : in std_logic;
usb_astb : in std_logic;
usb_dstb : in std_logic;
usb_wait : out std_logic
);
end main_file;
architecture Behavioral of main_file is
constant address_map : addr_range_and_mapping_array := (
address_range_and_map(
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(3, bus_address_type'length))
),
address_range_and_map(
low => std_logic_vector(to_unsigned(4, bus_address_type'length))
));
signal rst : STD_LOGIC;
signal depp2demux : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal demux2depp : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2ss : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2mem : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal mem2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
rst <= '0';
concurrent : process(slide_switch)
begin
led <= slide_switch;
end process;
depp_slave_controller : entity work.depp_slave_controller
port map (
rst => rst,
clk => clk,
mst2slv => depp2demux,
slv2mst => demux2depp,
USB_DB => usb_db,
USB_WRITE => usb_write,
USB_ASTB => usb_astb,
USB_DSTB => usb_dstb,
USB_WAIT => usb_wait
);
demux : entity work.bus_demux
generic map (
ADDRESS_MAP => address_map
)
port map (
rst => rst,
mst2demux => depp2demux,
demux2mst => demux2depp,
demux2slv(0) => demux2ss,
demux2slv(1) => demux2mem,
slv2demux(0) => ss2demux,
slv2demux(1) => mem2demux
);
ss : entity work.seven_seg_controller
generic map (
hold_count => 200000,
digit_count => 4
)
port map (
clk => clk,
rst => rst,
mst2slv => demux2ss,
slv2mst => ss2demux,
digit_anodes => seven_seg_an,
kathode => seven_seg_kath
);
mem : entity work.bus_singleport_ram
generic map (
DEPTH_LOG2B => 11
)
port map (
rst => rst,
clk => clk,
mst2mem => demux2mem,
mem2mst => mem2demux
);
end Behavioral;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register8 is
Port (
d : in STD_LOGIC_VECTOR(7 downto 0) := X"00"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(7 downto 0) := X"00" --Output
);
end Register8;
architecture Behavioral of Register8 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "00000000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_RL_Test IS
END gpib_RL_Test;
ARCHITECTURE behavior OF gpib_RL_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, att => att_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
assert isLocal_1 = '1';
assert isLocal_2 = '1';
assert REN = '0';
sre_1 <= '1';
wait until REN = '1';
assert isLocal_1 = '1';
assert isLocal_2 = '1';
assert REN = '1';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_1 = '1';
assert isLocal_2 = '0';
assert REN = '1';
rtl_2 <= '1';
wait until isLocal_2 = '1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send LLO (local lockout)
w_write_buffer(0) <= "10010001";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send GTL (go to local)
w_write_buffer(0) <= "00000001";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '0';
sre_1 <= '0';
wait until REN = '0';
wait for clk_period*5;
assert isLocal_2 = '1';
report "$$$ END OF TEST - remote / local $$$";
wait;
end process;
END;
|
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end RECORD t_record;
type t_record is record
a : std_logic;
b : std_logic;
end RECORD t_record;
begin
end architecture rtl;
|
--Copyright (C) 2017 Siavoosh Payandeh Azad
-- DPU has one fixed input which is coming directly from Register-File
-- The other input is selectable between Rfile, Memory, Control
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port (
rst: in std_logic;
clk: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_1: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_2: in std_logic_vector (BitWidth-1 downto 0);
Data_in_control_2: in std_logic_vector (BitWidth-1 downto 0);
ALUCommand: in ALU_COMMAND;
Mux_Cont_2: in DPU_IN_MUX;
DPU_OV : out std_logic;
Result : out std_logic_vector (2*BitWidth-1 downto 0);
Result_ACC : out std_logic_vector (2*BitWidth-1 downto 0)
);
end DPU;
--Architecture of the DPU
architecture RTL of DPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal ACC_in, ACC_out: std_logic_vector (2*BitWidth-1 downto 0);
signal Mux_Out_1, Mux_Out_2: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
---------------------------------------------
-- Flags
---------------------------------------------
signal OV_Flag_Value, Cout :std_logic := '0';
begin
ALU_comp: ALU
generic map (BitWidth => BitWidth)
port map (Mux_Out_1, Mux_Out_2, ALUCommand, OV_Flag_Value, Cout, ACC_in);
---------------------------------------------
-- Registers and Flags
---------------------------------------------
CLOCK_PROCESS:process (clk,rst)
begin
if rst = '1' then
ACC_out<=(others =>'0');
elsif clk'event and clk= '1' then
if ALUCommand = ALU_MULT or ALUCommand = ALU_MULTU or ALUCommand = ALU_MTHI or
ALUCommand = ALU_MTLO or ALUCommand = ALU_DIV or ALUCommand = ALU_DIVU then
ACC_out <= ACC_in;
elsif ALUCommand = ALU_MADD then
ACC_out <= std_logic_vector(signed(ACC_in) + signed(ACC_out));
elsif ALUCommand = ALU_MADDU then
ACC_out <= std_logic_vector(unsigned(ACC_in) + unsigned(ACC_out));
elsif ALUCommand = ALU_MSUB then
ACC_out <= std_logic_vector(signed(ACC_in) - signed(ACC_out));
elsif ALUCommand = ALU_MSUBU then
ACC_out <= std_logic_vector(unsigned(ACC_in) - unsigned(ACC_out));
end if;
end if;
end process;
---------------------------------------------
-- ALU Input multiplexer
---------------------------------------------
Mux_Out_1 <= Data_in_RegFile_1;
INPUT_MUX_2:process (Data_in_mem, Data_in_control_2, Data_in_RegFile_2, Mux_Cont_2)
begin
case Mux_Cont_2 is
when MEM => Mux_Out_2 <= Data_in_mem;
when CONT => Mux_Out_2 <= Data_in_control_2;
when RFILE => Mux_Out_2 <= Data_in_RegFile_2;
when ONE => Mux_Out_2 <= std_logic_vector(to_unsigned(1, BitWidth));
when others => Mux_Out_2 <= std_logic_vector(to_unsigned(0, BitWidth));
end case;
end process;
Result <= ACC_in;
Result_ACC <= ACC_out;
DPU_OV <= OV_Flag_Value;
end RTL;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: rgb_conv.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: albertomg994@gmail.com
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity rgb_conv is
Port ( r : in STD_LOGIC;
g : in STD_LOGIC;
b : in STD_LOGIC;
pos_h : in std_logic_vector(9 downto 0);
pos_v : in std_logic_vector(9 downto 0);
r_out : out STD_LOGIC_VECTOR (2 downto 0);
g_out : out STD_LOGIC_VECTOR (2 downto 0);
b_out : out STD_LOGIC_VECTOR (1 downto 0));
end rgb_conv;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of rgb_conv is
begin
-- Proceso de conversion de rgb de 3 bits a rgb de 8 bits:
-----------------------------------------------------------
p_outputs: process(r, g, b, pos_h, pos_v)
begin
-- Si estamos fuera del rango del tablero pintaremos negro.
if pos_h >= "0010000000" and pos_h < "0100000000" and pos_v >= "0010000000" and pos_v < "0100000000" then
if r = '1' then
r_out <= "111";
else
r_out <= "000";
end if;
if g = '1' then
g_out <= "111";
else
g_out <= "000";
end if;
if b = '1' then
b_out <= "11";
else
b_out <= "00";
end if;
else
r_out <= (others => '0');
g_out <= (others => '0');
b_out <= (others => '0');
end if;
end process p_outputs;
end arq;
|
entity foo is end;
architecture bar of foo is
constant xA : std.standard.TIME;
--constant xB : TIME := 10 ns;
constant yA: std.standard.DELAY_LENGTH;
constant zA: std.standard.TIME_VECTOR;
begin end;
|
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
ATTRIBUTE COORDINATE of comp_1:component IS (0.0, 17.5);
begin
end architecture RTL;
|
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
begin
--nvc doesn't like the to_bitvector() below, fails in analysis.
case to_bitvector(mode) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
begin
--nvc doesn't like the to_bitvector() below, fails in analysis.
case to_bitvector(mode) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
use work.cst.all;
package pkg is
type rec is record
s : string;
a : integer;
end record;
constant cfour : natural := work.cst.four;
subtype rec_4 is rec (s(1 to 4));
subtype rec_4bis is rec (s(1 to 4));
subtype rec_4dyn is rec (s(1 to cfour));
end pkg;
|
use work.cst.all;
package pkg is
type rec is record
s : string;
a : integer;
end record;
constant cfour : natural := work.cst.four;
subtype rec_4 is rec (s(1 to 4));
subtype rec_4bis is rec (s(1 to 4));
subtype rec_4dyn is rec (s(1 to cfour));
end pkg;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jul 6 07:18:32 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao3_go : out std_ulogic;
s_ai14 : in std_ulogic_vector(7 downto 0);
s_ai16 : out std_ulogic_vector(7 downto 0);
s_ai6 : in std_ulogic;
s_ai8 : out std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao1 : out std_ulogic;
s_ao12 : out std_ulogic_vector(7 downto 0);
s_ao13 : out std_ulogic_vector(7 downto 0);
s_ao4 : out std_ulogic;
s_ao5 : out std_ulogic;
s_ao9 : in std_ulogic_vector(7 downto 0);
s_outname : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_e_e
-- No Generated Generics
-- Generated Generics for Entity inst_e_e
-- End of Generated Generics for Entity inst_e_e
port (
-- Generated Port for Entity inst_e_e
p_mix_s_eo3_go : out std_ulogic;
s_eo1 : out std_ulogic;
s_eo2 : out std_ulogic;
s_eo4 : out std_ulogic;
s_eo5 : out std_ulogic;
s_outname : in std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
-- __I_OUT_OPEN signal s_ao1 : std_ulogic;
-- __I_OUT_OPEN signal s_ao12 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_ao4 : std_ulogic;
-- __I_NODRV_I signal s_ao9 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_eo1 : std_ulogic;
-- __I_OUT_OPEN signal s_eo2 : std_ulogic;
-- __I_OUT_OPEN signal s_eo4 : std_ulogic;
signal s_outname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_s_aio17_gc => s_aio17,
p_mix_s_ao11_go => s_ao11,
p_mix_s_ao3_go => s_ao3,
s_ai14 => s_ai14,
s_ai16 => s_ai16,
s_ai6 => s_ai6,
s_ai8 => s_ai8,
s_aio18 => s_aio18,
s_aio19 => s_aio19,
s_ao1 => open, -- __I_OUT_OPEN
s_ao12 => open, -- __I_OUT_OPEN
s_ao13 => s_ao13,
s_ao4 => open, -- __I_OUT_OPEN
s_ao5 => s_ao5,
-- __I_NODRV_I s_ao9 => __nodrv__/s_ao9,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_s_eo3_go => s_eo3,
s_eo1 => open, -- __I_OUT_OPEN
s_eo2 => open, -- __I_OUT_OPEN
s_eo4 => open, -- __I_OUT_OPEN
s_eo5 => s_eo5,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_Core_v1_1_S01_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
PPM_INPUT : in std_logic;
SAMPLE_CLOCK : in std_logic;
INTR_SINGLE : out std_logic;
INTR_COMPLETE: out std_logic;
-- Debugging:
-- ppm_sample_dbg : inout std_logic_vector (1 downto 0) := "00";
-- counter_dbg : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr_dbg : inout unsigned (3 downto 0) := "0000";
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Syma_Ctrl_Core_v1_1_S01_AXI;
architecture arch_imp of Syma_Ctrl_Core_v1_1_S01_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal ppm_out_cnt_1 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_2 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_3 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_4 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_5 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_6 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_7 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_8 : STD_LOGIC_VECTOR (31 downto 0);
component ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0);
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end component;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (ppm_out_cnt_1, ppm_out_cnt_2, ppm_out_cnt_3, ppm_out_cnt_4, ppm_out_cnt_5, ppm_out_cnt_6, ppm_out_cnt_7, ppm_out_cnt_8, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= ppm_out_cnt_1;
when b"001" =>
reg_data_out <= ppm_out_cnt_2;
when b"010" =>
reg_data_out <= ppm_out_cnt_3;
when b"011" =>
reg_data_out <= ppm_out_cnt_4;
when b"100" =>
reg_data_out <= ppm_out_cnt_5;
when b"101" =>
reg_data_out <= ppm_out_cnt_6;
when b"110" =>
reg_data_out <= ppm_out_cnt_7;
when b"111" =>
reg_data_out <= ppm_out_cnt_8;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
ppm_decoder_0 : ppm_decoder
port map (
clk => SAMPLE_CLOCK,
ppm_in => PPM_INPUT,
ppm_out_1 => ppm_out_cnt_1,
ppm_out_2 => ppm_out_cnt_2,
ppm_out_3 => ppm_out_cnt_3,
ppm_out_4 => ppm_out_cnt_4,
ppm_out_5 => ppm_out_cnt_5,
ppm_out_6 => ppm_out_cnt_6,
ppm_out_7 => ppm_out_cnt_7,
ppm_out_8 => ppm_out_cnt_8,
intr_1 => INTR_SINGLE,
intr_comp => INTR_COMPLETE);
--ppm_sample => ppm_sample_dbg,
--counter => counter_dbg,
--reg_nr => reg_nr_dbg);
-- User logic ends
end arch_imp; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_Core_v1_1_S01_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
PPM_INPUT : in std_logic;
SAMPLE_CLOCK : in std_logic;
INTR_SINGLE : out std_logic;
INTR_COMPLETE: out std_logic;
-- Debugging:
-- ppm_sample_dbg : inout std_logic_vector (1 downto 0) := "00";
-- counter_dbg : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr_dbg : inout unsigned (3 downto 0) := "0000";
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Syma_Ctrl_Core_v1_1_S01_AXI;
architecture arch_imp of Syma_Ctrl_Core_v1_1_S01_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal ppm_out_cnt_1 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_2 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_3 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_4 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_5 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_6 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_7 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_8 : STD_LOGIC_VECTOR (31 downto 0);
component ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0);
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end component;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (ppm_out_cnt_1, ppm_out_cnt_2, ppm_out_cnt_3, ppm_out_cnt_4, ppm_out_cnt_5, ppm_out_cnt_6, ppm_out_cnt_7, ppm_out_cnt_8, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= ppm_out_cnt_1;
when b"001" =>
reg_data_out <= ppm_out_cnt_2;
when b"010" =>
reg_data_out <= ppm_out_cnt_3;
when b"011" =>
reg_data_out <= ppm_out_cnt_4;
when b"100" =>
reg_data_out <= ppm_out_cnt_5;
when b"101" =>
reg_data_out <= ppm_out_cnt_6;
when b"110" =>
reg_data_out <= ppm_out_cnt_7;
when b"111" =>
reg_data_out <= ppm_out_cnt_8;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
ppm_decoder_0 : ppm_decoder
port map (
clk => SAMPLE_CLOCK,
ppm_in => PPM_INPUT,
ppm_out_1 => ppm_out_cnt_1,
ppm_out_2 => ppm_out_cnt_2,
ppm_out_3 => ppm_out_cnt_3,
ppm_out_4 => ppm_out_cnt_4,
ppm_out_5 => ppm_out_cnt_5,
ppm_out_6 => ppm_out_cnt_6,
ppm_out_7 => ppm_out_cnt_7,
ppm_out_8 => ppm_out_cnt_8,
intr_1 => INTR_SINGLE,
intr_comp => INTR_COMPLETE);
--ppm_sample => ppm_sample_dbg,
--counter => counter_dbg,
--reg_nr => reg_nr_dbg);
-- User logic ends
end arch_imp; |
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