content stringlengths 1 1.04M ⌀ |
|---|
package foo is
alias bar is baz;
alias bar is baz [];
alias bar is baz [a,b,c];
alias bar is baz [return d];
alias bar is baz [a,b,c return d];
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Keyboard is
port (
datain, clkin : in std_logic ; -- PS2 clk and data
fclk, rst : in std_logic ; -- filter clock
-- fok : out std_logic ; -- data output enable signal
scancode : out std_logic_vector(7 downto 0) -- scan code signal output
) ;
end Keyboard ;
architecture rtl of Keyboard is
type state_type is (delay, start, d0, d1, d2, d3, d4, d5, d6, d7, parity, stop, finish) ;
signal data, clk, clk1, clk2, odd, fok : std_logic ; -- ë´Ì´¦ÀíÄÚ²¿ÐźÅ, oddΪÆæżУÑé
signal code : std_logic_vector(7 downto 0) ;
signal state : state_type ;
begin
clk1 <= clkin when rising_edge(fclk) ;
clk2 <= clk1 when rising_edge(fclk) ;
clk <= (not clk1) and clk2 ;
data <= datain when rising_edge(fclk) ;
odd <= code(0) xor code(1) xor code(2) xor code(3)
xor code(4) xor code(5) xor code(6) xor code(7) ;
scancode <= code when fok = '1' ;
process(rst, fclk)
begin
if rst = '1' then
state <= delay ;
code <= (others => '0') ;
fok <= '0' ;
elsif rising_edge(fclk) then
fok <= '0' ;
case state is
when delay =>
state <= start ;
when start =>
if clk = '1' then
if data = '0' then
state <= d0 ;
else
state <= delay ;
end if ;
end if ;
when d0 =>
if clk = '1' then
code(0) <= data ;
state <= d1 ;
end if ;
when d1 =>
if clk = '1' then
code(1) <= data ;
state <= d2 ;
end if ;
when d2 =>
if clk = '1' then
code(2) <= data ;
state <= d3 ;
end if ;
when d3 =>
if clk = '1' then
code(3) <= data ;
state <= d4 ;
end if ;
when d4 =>
if clk = '1' then
code(4) <= data ;
state <= d5 ;
end if ;
when d5 =>
if clk = '1' then
code(5) <= data ;
state <= d6 ;
end if ;
when d6 =>
if clk = '1' then
code(6) <= data ;
state <= d7 ;
end if ;
when d7 =>
if clk = '1' then
code(7) <= data ;
state <= parity ;
end if ;
WHEN parity =>
IF clk = '1' then
if (data xor odd) = '1' then
state <= stop ;
else
state <= delay ;
end if;
END IF;
WHEN stop =>
IF clk = '1' then
if data = '1' then
state <= finish;
else
state <= delay;
end if;
END IF;
WHEN finish =>
state <= delay ;
fok <= '1' ;
when others =>
state <= delay ;
end case ;
end if ;
end process ;
end rtl ;
|
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
-- Misc
assert ("1011" sll 1) = "0110";
assert ("1011" srl 1) = "0101";
assert ("1011" sla 1) = "0111";
assert ("1011" sra 1) = "1101";
assert ("1011" srl -1) = "0110";
assert ("1011" sll -1) = "0101";
assert ("1011" sra -1) = "0111";
assert ("1011" sla -1) = "1101";
end architecture;
|
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
-- Misc
assert ("1011" sll 1) = "0110";
assert ("1011" srl 1) = "0101";
assert ("1011" sla 1) = "0111";
assert ("1011" sra 1) = "1101";
assert ("1011" srl -1) = "0110";
assert ("1011" sll -1) = "0101";
assert ("1011" sra -1) = "0111";
assert ("1011" sla -1) = "1101";
end architecture;
|
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
entity Debounce is
port (clock: in STD_LOGIC;
input_h: in STD_LOGIC;
output_h: out STD_LOGIC;
--internal structure
input_temp1_h: out STD_LOGIC;
input_temp2_h: out STD_LOGIC;
count_h: out STD_LOGIC_VECTOR(19 downto 0));
end Debounce;
architecture Behavioral of Debounce is
constant delay : INTEGER := 500000;
signal count : INTEGER := 0;
signal input_temp1, input_temp2 : STD_LOGIC :='0';
signal output_temp : STD_LOGIC;
begin
contar: process (input_h, clock, input_temp1)
begin
if input_h /= input_temp1 then
count <= 0;
input_temp1 <= input_h;
elsif clock'event and clock = '1' then
input_temp1 <= input_h;
input_temp2 <= input_temp1;
count <= count +1;
else
count <= count;
end if;
end process;
avaliar: process (clock, input_temp1, input_temp2, count)
begin
if clock'event and clock='1' then
if count >= delay and input_temp1 = input_temp2 then
output_temp <= input_h;
else
output_temp <= output_temp;
end if;
else
output_temp <= output_temp;
end if;
end process;
output_h <= output_temp;
count_h <= conv_std_logic_vector(count, 20);
input_temp1_h <= input_temp1;
input_temp2_h <= input_temp2;
end Behavioral;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_utilities.all;
--! @brief Simple memory module for use in Wishbone-based systems.
entity pp_soc_memory is
generic(
MEMORY_SIZE : natural := 4096 --! Memory size in bytes.
);
port(
clk : in std_logic;
reset : in std_logic;
-- Wishbone interface:
wb_adr_in : in std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
wb_dat_in : in std_logic_vector(31 downto 0);
wb_dat_out : out std_logic_vector(31 downto 0);
wb_cyc_in : in std_logic;
wb_stb_in : in std_logic;
wb_sel_in : in std_logic_vector( 3 downto 0);
wb_we_in : in std_logic;
wb_ack_out : out std_logic
);
end entity pp_soc_memory;
architecture behaviour of pp_soc_memory is
type memory_array is array(0 to (MEMORY_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
signal memory : memory_array := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of memory : signal is "block";
type state_type is (IDLE, ACK);
signal state : state_type;
signal read_ack : std_logic;
begin
wb_ack_out <= read_ack and wb_stb_in;
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
read_ack <= '0';
state <= IDLE;
else
if wb_cyc_in = '1' then
case state is
when IDLE =>
if wb_stb_in = '1' and wb_we_in = '1' then
for i in 0 to 3 loop
if wb_sel_in(i) = '1' then
memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 2))))(((i + 1) * 8) - 1 downto i * 8)
<= wb_dat_in(((i + 1) * 8) - 1 downto i * 8);
end if;
end loop;
read_ack <= '1';
state <= ACK;
elsif wb_stb_in = '1' then
wb_dat_out <= memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 2))));
read_ack <= '1';
state <= ACK;
end if;
when ACK =>
if wb_stb_in = '0' then
read_ack <= '0';
state <= IDLE;
end if;
end case;
else
state <= IDLE;
read_ack <= '0';
end if;
end if;
end if;
end process;
end architecture behaviour;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis VIP AXISTREAM Library : axistream_bfm_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s).
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package axistream_bfm_pkg is
--========================================================================================================================
-- Types and constants for AXISTREAM_BFM
--========================================================================================================================
constant C_SCOPE : string := "AXISTREAM_BFM";
--========================================================================================================================
-- C_MAX_*_BITS : Maximum number of bits per data word supported by the BFM.
-- These constant can be increased as needed.
constant C_MAX_TUSER_BITS : positive := 8;
constant C_MAX_TSTRB_BITS : positive := 32; -- Must be large enough for number of data bytes per transfer, C_MAX_TSTRB_BITS >= tdata/8
constant C_MAX_TID_BITS : positive := 8; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_MAX_TDEST_BITS : positive := 4; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_RANDOM : integer := -1;
constant C_MULTIPLE_RANDOM : integer := -2;
type t_user_array is array(natural range <>) of std_logic_vector(C_MAX_TUSER_BITS-1 downto 0);
type t_strb_array is array(natural range <>) of std_logic_vector(C_MAX_TSTRB_BITS-1 downto 0);
type t_id_array is array(natural range <>) of std_logic_vector(C_MAX_TID_BITS-1 downto 0);
type t_dest_array is array(natural range <>) of std_logic_vector(C_MAX_TDEST_BITS-1 downto 0);
--========================================================================================================================
-- Interface record for BFM signals
type t_axistream_if is record
tdata : std_logic_vector; -- Data. Width is constrained when the procedure is called
tkeep : std_logic_vector; -- One valid-bit per data byte
tuser : std_logic_vector; -- User sideband data
tvalid : std_logic; -- Data valid
tlast : std_logic; -- Active high during last data word in packet.
tready : std_logic; -- Backpressure
tstrb : std_logic_vector; -- Treated as sideband data by BFM: tstrb does not affect tdata
tid : std_logic_vector; -- Treated as sideband data by BFM
tdest : std_logic_vector; -- Treated as sideband data by BFM
end record;
-- Configuration record to be assigned in the test harness.
type t_axistream_bfm_config is
record
-- Common
max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready or valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
byte_endianness : t_byte_endianness; -- Byte ordering from left (big-endian) or right (little-endian)
-- config for axistream_transmit()
valid_low_at_word_num : integer; -- Word index where the Source BFM shall deassert valid
valid_low_duration : integer; -- Number of clock cycles to deassert valid
-- config for axistream_receive()
check_packet_length : boolean; -- When true, receive() will check that last is set at data_array'high
protocol_error_severity : t_alert_level; -- severity if protocol errors are detected by axistream_receive()
ready_low_at_word_num : integer; -- Word index where the Sink BFM shall deassert ready
ready_low_duration : integer; -- Number of clock cycles to deassert ready
ready_default_value : std_logic; -- Which value the BFM shall set ready to between accesses.
-- Common
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the BFM
end record;
-- Define the default value for the BFM config
constant C_AXISTREAM_BFM_CONFIG_DEFAULT : t_axistream_bfm_config := (
max_wait_cycles => 100,
max_wait_cycles_severity => ERROR,
clock_period => 0 ns, -- Make sure we notice if we forget to set clock period.
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 0 ns,
hold_time => 0 ns,
byte_endianness => FIRST_BYTE_LEFT,
valid_low_at_word_num => 0,
valid_low_duration => 0,
check_packet_length => false,
protocol_error_severity => ERROR,
ready_low_at_word_num => 0,
ready_low_duration => 0,
ready_default_value => '0',
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--========================================================================================================================
-- BFM procedures
--========================================================================================================================
-- - This function returns an AXI Stream interface with initialized signals.
-- - All input signals are initialized to 0
-- - All output signals are initialized to Z
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
--
-- Source: BFM
-- Sink: DUT
--¨
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
--
-- Source: DUT
-- Sink: BFM
--
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
-- Overloaded version without records
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
end package axistream_bfm_pkg;
--========================================================================================================================
--========================================================================================================================
package body axistream_bfm_pkg is
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if is
variable init_if : t_axistream_if(tdata(data_width-1 downto 0),
tkeep(data_width/8-1 downto 0),
tuser(user_width-1 downto 0),
tstrb(data_width/8-1 downto 0),
tid (id_width-1 downto 0),
tdest(dest_width-1 downto 0)
);
begin
if is_master then
-- from slave to master
init_if.tready := 'Z';
-- from master to slave
init_if.tvalid := '0';
init_if.tdata := (init_if.tdata'range => '0');
init_if.tkeep := (init_if.tkeep'range => '0');
init_if.tuser := (init_if.tuser'range => '0');
init_if.tstrb := (init_if.tstrb'range => '0');
init_if.tid := (init_if.tid'range => '0');
init_if.tdest := (init_if.tdest'range => '0');
init_if.tlast := '0';
else
-- from slave to master
init_if.tready := config.ready_default_value;
--init_if.tready := '0';
-- from master to slave
init_if.tvalid := 'Z';
init_if.tdata := (init_if.tdata'range => 'Z');
init_if.tkeep := (init_if.tkeep'range => 'Z');
init_if.tuser := (init_if.tuser'range => 'Z');
init_if.tstrb := (init_if.tstrb'range => 'Z');
init_if.tid := (init_if.tid'range => 'Z');
init_if.tdest := (init_if.tdest'range => 'Z');
init_if.tlast := 'Z';
end if;
return init_if;
end function;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
-- Send a packet on the AXI interface.
-- Packet length and data is defined by data_array
-- tuser is set based on user_array,
-- tstrb is set based on strb_array, etc
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_transmit";
constant proc_call : string := "axistream_transmit(" & to_string(data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current byte within the data word
variable v_clk_cycles_waited : natural := 0;
variable v_wait_for_next_transfer_cycle : boolean; -- When set, the BFM shall wait for at least one clock cycle, until tready='1' before continuing
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_valid_low_duration : natural := 0;
variable v_next_deassert_byte : natural := c_num_bytes_per_word; -- C_MULTIPLE_RANDOM always deasserts on second word the first time
-- Sampled tready for the current clock cycle
variable v_tready : std_logic;
begin
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(proc_name, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.clock_period /= 0 ns, TB_ERROR, "Sanity check: Check that bfm_config.clock_period is set", scope, ID_NEVER, msg_id_panel, proc_call);
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length);
-- Check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_call & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
log(ID_PACKET_INITIATE, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Send byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
for byte in 0 to data_array'high loop
log(ID_PACKET_DATA, proc_call & "=> Tx " & to_string(data_array(byte), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
", byte# " & to_string(byte) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
-------------------------------------------------------------------
-- Set tvalid low (once per transmission or multiple random times)
-------------------------------------------------------------------
if v_byte_in_word = 0 and (config.valid_low_duration > 0 or config.valid_low_duration = C_RANDOM) then
-- Check if pulse duration is defined or random
if config.valid_low_duration > 0 then
v_valid_low_duration := config.valid_low_duration;
elsif config.valid_low_duration = C_RANDOM then
v_valid_low_duration := random(1,5);
end if;
-- Deassert tvalid once per transmission on a specific word
if config.valid_low_at_word_num = byte/c_num_bytes_per_word then
wait for v_valid_low_duration * config.clock_period;
v_last_rising_edge := -1 ns; -- clear the time stamp since it will be longer than one period
-- Deassert tvalid multiple random times per transmission
elsif config.valid_low_at_word_num = C_MULTIPLE_RANDOM and v_next_deassert_byte = byte then
wait for v_valid_low_duration * config.clock_period;
v_next_deassert_byte := byte + (1+random(1,5))*c_num_bytes_per_word; -- avoid deasserting on the next word
v_last_rising_edge := -1 ns; -- clear the time stamp since it will be longer than one period
end if;
end if;
axistream_if.tvalid <= '1';
-- Byte locations within the data word is described in chapter 2.3 in "ARM IHI0051A"
axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word) <= data_array(byte);
-- Set sideband data for this transfer (i.e. this word)
if v_byte_in_word = 0 then
axistream_if.tuser(c_num_user_bits_per_word-1 downto 0) <= user_array(byte/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0);
axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0) <= strb_array(byte/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0);
axistream_if.tid(c_num_id_bits_per_word-1 downto 0) <= id_array(byte/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0);
axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0) <= dest_array(byte/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0);
end if;
-- TKEEP[x] is associated with TDATA[(7+8*v_byte_in_word) : 8*v_byte_in_word].
axistream_if.tkeep(v_byte_in_word) <= '1';
-- Default: Go to next 'byte' iteration in zero time (when tdata is not completely filled with bytes).
v_wait_for_next_transfer_cycle := false;
if byte = data_array'high then
-- Packet done.
axistream_if.tlast <= '1';
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
axistream_if.tlast <= '0';
end if;
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Next byte is in the next clk cycle
v_byte_in_word := 0;
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
-- Next byte is in the same clk cycle
v_byte_in_word := v_byte_in_word + 1;
end if;
--
-- If no more bytes to fill in tdata, wait until the transfer takes place (tvalid=1 and tready=1)
--
if v_wait_for_next_transfer_cycle then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
v_tready := axistream_if.tready; -- Will this cycle be a transfer? (tvalid=1 and tready=1)
-- Wait hold time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
-- reset wait cycles error counter
v_clk_cycles_waited := 0;
while v_tready = '0' loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
v_tready := axistream_if.tready; -- Will this cycle be a transfer? (tvalid=1 and tready=1)
-- Wait hold time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for tready " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
-- Default values for the next clk cycle
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length
);
end if;
end loop;
-- Done.
log(ID_PACKET_COMPLETE, proc_call & "=> Tx DONE" &
". " & add_msg_delimiter(msg),
scope, msg_id_panel);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array(data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_data_array := convert_slv_array_to_byte_array(data_array, true, v_byte_endianness); -- data_array is ascending
-- call t_byte_array overloaded procedure
axistream_transmit_bytes(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_check_ok : boolean := false;
variable v_data_array : t_slv_array(0 to 0)(data_array'length-1 downto 0);
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
v_data_array(0) := data_array;
-- call t_slv_array overloaded procedure
axistream_transmit(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-- Overload that doesn't use records for the AXI interface:
-- (In turn calls the record version)
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading procedure
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another overload that fills in strb_array, id_array, dest_array
axistream_transmit_bytes(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another t_slv_array overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another slv overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
-- Receive a packet, store it in data_array
-- data_array'length can be longer than the actual packet, so that you can call receive() without knowing the length to be expected.
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
constant local_proc_name : string := "axistream_receive"; -- Internal proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()"; -- Internal proc_call; used if called from sequncer or VVC
-- Helper variables
variable v_proc_call : line; -- Current proc_call, external or local
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current Byte within the data word
variable v_byte_cnt : integer := 0; -- # bytes received
variable v_timeout : boolean := false;
variable v_done : boolean := false;
variable v_invalid_count : integer := 0; -- # cycles without valid being asserted
variable v_sample_on_next_cycle : boolean := false;
variable v_byte_idx : integer;
variable v_word_idx : integer;
variable v_ready_low_duration : natural := 0;
variable v_next_deassert_byte : natural := 0;
begin
-- If called from sequencer/VVC, show 'axistream_receive()...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure like axistream_expect, log 'axistream_expect() while executing axistream_receive()...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(local_proc_call, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(config.clock_period /= 0 ns, TB_ERROR, "Sanity check: Check that bfm_config.clock_period is set", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for knowing which byte is sent first", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- Avoid driving inputs
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
-- Check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, v_proc_call.all & ": timeout waiting for clk low period for setup_time.");
end if;
-- This will ensure the procedure always starts at the same time before the rising edge.
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
log(ID_PACKET_INITIATE, v_proc_call.all & "=> Receive packet. " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Sample byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
while not v_done loop
v_sample_on_next_cycle := false;
--------------------------------------------------------------------------------------
-- Set tready low before given byte (once per transmission or multiple random times)
--------------------------------------------------------------------------------------
if v_byte_in_word = 0 and (config.ready_low_duration > 0 or config.ready_low_duration = C_RANDOM) then
-- Check if pulse duration is defined or random
if config.ready_low_duration > 0 then
v_ready_low_duration := config.ready_low_duration;
elsif config.ready_low_duration = C_RANDOM then
v_ready_low_duration := random(1,5);
end if;
-- Deassert tready once per transmission on a specific word
if config.ready_low_at_word_num = v_byte_cnt/c_num_bytes_per_word then
-- Wait until tvalid goes high before deasserting tready so it has an effect
if axistream_if.tvalid = '0' then
wait until axistream_if.tvalid = '1' for (config.max_wait_cycles * config.clock_period);
if axistream_if.tvalid = '1' then
-- Wait until the setup time before the next rising edge to lower tready
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
else
-- TValid timed out
v_timeout := true;
v_done := true;
v_ready_low_duration := 0;
end if;
end if;
-- If config.ready_low_at_word_num = 0 and tvalid was already high then
-- tready will be deasserted right away.
-- If config.ready_low_at_word_num > 0 then tready will be deasserted before the
-- rising edge (previous iteration in the loop will wait for period-setup_time).
axistream_if.tready <= '0';
wait for v_ready_low_duration * config.clock_period;
axistream_if.tready <= '1';
wait for config.setup_time;
-- Deassert tready multiple random times per transmission
elsif config.ready_low_at_word_num = C_MULTIPLE_RANDOM and v_next_deassert_byte = v_byte_cnt then
axistream_if.tready <= '0';
wait for v_ready_low_duration * config.clock_period;
axistream_if.tready <= '1';
wait for config.setup_time;
v_next_deassert_byte := v_byte_cnt + (1+random(1,5))*c_num_bytes_per_word; -- avoid deasserting on the next word
end if;
end if;
------------------------------------------------------------
-- Set tready high (after tvalid is high)
------------------------------------------------------------
if v_byte_in_word = 0 then
-- To receive the first byte wait until tvalid goes high before asserting tready
if v_byte_cnt = 0 and axistream_if.tvalid = '0' and not(v_timeout) then
wait until axistream_if.tvalid = '1' for (config.max_wait_cycles * config.clock_period);
if axistream_if.tvalid = '1' then
axistream_if.tready <= '1';
if clk = '0' then
-- Align sampling of the data with the rising edge of the clock
wait until clk = '1';
else
-- TValid and TReady are high but it's already past the rising edge of the
-- clock so the data must be sampled on the next cycle
v_sample_on_next_cycle := true;
end if;
else
-- TValid timed out
v_timeout := true;
v_done := true;
end if;
-- TValid was already high, assert ready right away
else
axistream_if.tready <= '1';
-- Align sampling of the data with the rising edge of the clock
wait until clk = '1';
end if;
end if;
------------------------------------------------------------
-- Sample the data
------------------------------------------------------------
if axistream_if.tvalid = '1' and axistream_if.tready = '1' and not(v_sample_on_next_cycle) then
v_invalid_count := 0;
-- Sample data.
data_array(v_byte_cnt) := axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word);
-- Sample tuser for this transfer (this word): There is one user_array entry per word
if v_byte_in_word = 0 then
v_word_idx := v_byte_cnt/c_num_bytes_per_word;
if (v_word_idx <= user_array'high) then -- Include this 'if' to allow a shorter user_array if the caller doesn't care what tuser is
user_array(v_byte_cnt/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0) := axistream_if.tuser(c_num_user_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= strb_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tstrb is
strb_array(v_byte_cnt/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0) := axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= id_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tid is
id_array(v_byte_cnt/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0) := axistream_if.tid(c_num_id_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= dest_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tdest is
dest_array(v_byte_cnt/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0) := axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0);
end if;
end if;
log(ID_PACKET_DATA, v_proc_call.all & "=> Rx " & to_string(data_array(v_byte_cnt), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
" (byte# " & to_string(v_byte_cnt) & "). " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Check tlast='1' at expected last byte
if v_byte_cnt = data_array'high then
check_value(axistream_if.tlast, '1', config.protocol_error_severity, "Check tlast at expected last byte = " & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope);
v_done := true; -- Stop sampling data when we have filled the data_array
end if;
-- Allow that tlast arrives sooner than indicated by data_array'high
-- if receive() is called without knowing the length to be expected.
if axistream_if.tlast = '1' then
if axistream_if.tkeep(v_byte_in_word) = '1' then
if v_byte_in_word = c_num_bytes_per_word-1 then
-- it's the last byte in word and tlast='1', thus the last in packet.
v_done := true;
else
if axistream_if.tkeep(v_byte_in_word+1) = '0' then
-- Next byte in word is invalid, so this is the last byte
v_done := true;
-- Check that tkeep for the remaining bytes in the last word are also '0'. (Only continous stream supported)
v_byte_idx := v_byte_in_word+1;
l_check_remaining_TKEEP: loop
check_value(axistream_if.tkeep(v_byte_idx), '0', ERROR, "Check that tkeep doesn't go from '1' to '0' to '1' again within this last word. (The BFM supports only continuous stream)", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if v_byte_idx < (axistream_if.tkeep'length-1) then
v_byte_idx := v_byte_idx + 1;
else
exit l_check_remaining_TKEEP;
end if;
end loop;
else
-- Next byte in word is valid but the data_array has finished
if v_done then
alert(ERROR, v_proc_call.all & "=> Failed. data_array too small for received bytes. " & add_msg_delimiter(msg), scope);
end if;
end if;
end if;
end if;
else -- tlast = 0
if (v_byte_cnt = data_array'high) then
alert(config.protocol_error_severity, v_proc_call.all & "=> Failed. tlast not received, expected at or before byte#" & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope);
end if;
-- Check that all tkeep bits are '1'. (Only continous stream supported)
check_value(axistream_if.tkeep(v_byte_in_word), '1', ERROR, "When tlast='0', check that all tkeep bits are '1'. (The BFM supports only continuous stream)" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
-- Next byte is in the next clk cycle
if v_byte_in_word = c_num_bytes_per_word-1 then
if axistream_if.tlast = '0' then
-- Next byte will have tready deasserted so it needs to happen before
-- the rising edge of the clock
if (config.ready_low_duration > 0 or config.ready_low_duration = C_RANDOM) and
(config.ready_low_at_word_num = v_byte_cnt/c_num_bytes_per_word + 1 or
(config.ready_low_at_word_num = C_MULTIPLE_RANDOM and v_next_deassert_byte = v_byte_cnt + 1))
then
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
else
-- No tready deassertion, wait a full period
wait for config.clock_period;
end if;
end if;
v_byte_in_word := 0;
-- Next byte is in the same clk cycle
else
v_byte_in_word := v_byte_in_word + 1;
end if;
-- Next byte
v_byte_cnt := v_byte_cnt + 1;
------------------------------------------------------------
-- Data couldn't be sampled, wait until next cycle
------------------------------------------------------------
elsif not(v_timeout) then
-- Check for timeout (also when max_wait_cycles_severity = NO_ALERT,
-- or else the VVC will wait forever, until the UVVM cmd times out)
if (v_invalid_count >= config.max_wait_cycles-1) then
v_timeout := true;
v_done := true;
else
v_invalid_count := v_invalid_count + 1;
end if;
wait for config.clock_period;
end if;
end loop; -- while not v_done
-- Set the number of bytes received
data_length := v_byte_cnt;
-- Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " & add_msg_delimiter(msg), scope);
else
log(ID_PACKET_COMPLETE, v_proc_call.all & "=> Rx DONE (" & to_string(v_byte_cnt) & "B)" & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
-- Done, set axistream back to default
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
end procedure axistream_receive_bytes;
-- Overloaded t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is -- helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array_as_byte : t_byte_array(0 to v_num_bytes-1);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- call overloaded t_byte_array procedure
axistream_receive_bytes ( v_data_array_as_byte,
data_length, user_array, strb_array, id_array, dest_array, msg,
clk, axistream_if, scope, msg_id_panel, config, ext_proc_call );
data_array := convert_byte_array_to_slv_array(v_data_array_as_byte, v_bytes_in_word, v_byte_endianness);
end procedure axistream_receive;
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is
begin
-- Simply call the record version
axistream_receive_bytes(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive_bytes;
-- Overloading t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is
begin
-- Simply call the record version
axistream_receive(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive;
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- Receive data, then compare the received data against exp_data_array
-- - If the received data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_expect";
constant proc_call : string := "axistream_expect(" & to_string(exp_data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_config : t_axistream_bfm_config := config;
variable v_rx_data_array : t_byte_array(exp_data_array'range); -- received data
variable v_rx_user_array : t_user_array(exp_user_array'range); -- received tuser
variable v_rx_strb_array : t_strb_array(exp_strb_array'range);
variable v_rx_id_array : t_id_array(exp_id_array'range);
variable v_rx_dest_array : t_dest_array(exp_dest_array'range);
variable v_rx_data_length : natural;
variable v_data_error_cnt : natural := 0;
variable v_user_error_cnt : natural := 0;
variable v_strb_error_cnt : natural := 0;
variable v_id_error_cnt : natural := 0;
variable v_dest_error_cnt : natural := 0;
variable v_first_errored_byte : natural;
begin
-- Make the receive() procedure check tlast position is as expected
v_config.check_packet_length := true;
-- Receive and store data
axistream_receive_bytes(data_array => v_rx_data_array,
data_length => v_rx_data_length,
user_array => v_rx_user_array,
strb_array => v_rx_strb_array,
id_array => v_rx_id_array,
dest_array => v_rx_dest_array,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => v_config,
ext_proc_call => proc_call);
-- Check if each received bit matches the expected
-- Find and report the first errored byte
for byte in v_rx_data_array'high downto 0 loop
for i in v_rx_data_array(byte)'range loop
if (exp_data_array(byte)(i) = '-') or -- Expected set to don't care, or
(v_rx_data_array(byte)(i) = exp_data_array(byte)(i)) then -- received value matches expected
-- Check is OK
else
-- Received byte does not match the expected byte
--log(config.id_for_bfm, proc_call & "=> NOK, checked " & to_string(v_rx_data_array(byte), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_data_array(byte), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
v_data_error_cnt := v_data_error_cnt + 1;
v_first_errored_byte := byte;
end if;
end loop;
end loop;
-- Check tuser matches exp_user_array
-- Check all bits the exp_user_array. If the caller (Test Sequencer or VVC) don't care, the length of exp_user_array input shall be only one
for word in exp_user_array'high downto 0 loop
for i in c_num_user_bits_per_word-1 downto 0 loop -- i = bit
if (exp_user_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_user_array(word)(i) = exp_user_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tuser word does not match the expected word
v_user_error_cnt := v_user_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_strb_array matches received tstrb
for word in exp_strb_array'high downto 0 loop
for i in c_num_strb_bits_per_word-1 downto 0 loop -- i = bit
if (exp_strb_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_strb_array(word)(i) = exp_strb_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tstrb word does not match the expected word
v_strb_error_cnt := v_strb_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_id_array matches received tid
for word in exp_id_array'high downto 0 loop
for i in c_num_id_bits_per_word-1 downto 0 loop -- i = bit
if (exp_id_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_id_array(word)(i) = exp_id_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tid word does not match the expected word
v_id_error_cnt := v_id_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_dest_array matches received tdest
for word in exp_dest_array'high downto 0 loop
for i in c_num_dest_bits_per_word-1 downto 0 loop -- i = bit
if (exp_dest_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_dest_array(word)(i) = exp_dest_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tdest word does not match the expected word
v_dest_error_cnt := v_dest_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- No more than one alert per packet
if v_data_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_data_array(v_first_errored_byte), HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_data_array(v_first_errored_byte), HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_user_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_user_error_cnt) & " tuser bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_strb_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_strb_error_cnt) & " tstrb bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_id_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_id_error_cnt) & " tid bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_dest_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_dest_error_cnt) & " tdest bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & "B. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_expect_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_bytes_in_word : integer := (exp_data_array(exp_data_array'low)'length/8);
variable v_num_bytes : integer := (exp_data_array'length) * v_bytes_in_word;
variable v_exp_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_exp_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_dummy : t_slv_array(0 to 0)(31 downto 0);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array(exp_data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array is N*byte");
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_exp_data_array := convert_slv_array_to_byte_array(exp_data_array, true, v_byte_endianness); -- exp_data_array is ascending
-- call t_byte_array overloaded procedure
axistream_expect_bytes(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_exp_data_array : t_slv_array(0 to 0)(exp_data_array'length-1 downto 0);
variable v_check_ok : boolean := false;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array word is N*byte");
if v_check_ok then
v_exp_data_array(0) := exp_data_array;
-- call t_slv_array overloaded procedure
axistream_expect(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the record version
axistream_expect_bytes(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the t_slv_array record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the slv record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-- Overload without exp_strb_array, exp_id_array, exp_dest_array arguments' argument
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-- Overload without arguments exp_user_array, exp_strb_array, exp_id_array, exp_dest_array arguments
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
end package body axistream_bfm_pkg;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:54:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-e.vhd,v 1.2 2006/09/25 10:00:31 wig Exp $
-- $Date: 2006/09/25 10:00:31 $
-- $Log: ent_a-e.vhd,v $
-- Revision 1.2 2006/09/25 10:00:31 wig
-- Updated testcase file ent_a-e.vhd (comment).
--
-- Revision 1.1 2004/04/06 11:07:27 wig
-- Adding result/highlow
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_a
--
entity ent_a is
-- Generics:
-- No Generated Generics for Entity ent_a
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_a
low_bit_a : in std_ulogic -- Ground bit port
-- End of Generated Port for Entity ent_a
);
end ent_a;
--
-- End of Generated Entity ent_a
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3171.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p22n01i03171ent IS
END c14s01b00x00p22n01i03171ent;
ARCHITECTURE c14s01b00x00p22n01i03171arch OF c14s01b00x00p22n01i03171ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'high = 15 and
roufbit'high = 15 )
report "***PASSED TEST: c14s01b00x00p22n01i03171"
severity NOTE;
assert ( fourbit'high = 15 and
roufbit'high = 15 )
report "***FAILED TEST: c14s01b00x00p22n01i03171 - Predefined attribute HIGH test for integer subtype failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p22n01i03171arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3171.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p22n01i03171ent IS
END c14s01b00x00p22n01i03171ent;
ARCHITECTURE c14s01b00x00p22n01i03171arch OF c14s01b00x00p22n01i03171ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'high = 15 and
roufbit'high = 15 )
report "***PASSED TEST: c14s01b00x00p22n01i03171"
severity NOTE;
assert ( fourbit'high = 15 and
roufbit'high = 15 )
report "***FAILED TEST: c14s01b00x00p22n01i03171 - Predefined attribute HIGH test for integer subtype failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p22n01i03171arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3171.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p22n01i03171ent IS
END c14s01b00x00p22n01i03171ent;
ARCHITECTURE c14s01b00x00p22n01i03171arch OF c14s01b00x00p22n01i03171ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'high = 15 and
roufbit'high = 15 )
report "***PASSED TEST: c14s01b00x00p22n01i03171"
severity NOTE;
assert ( fourbit'high = 15 and
roufbit'high = 15 )
report "***FAILED TEST: c14s01b00x00p22n01i03171 - Predefined attribute HIGH test for integer subtype failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p22n01i03171arch;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wb_stream_pkg.all;
use work.wb_stream_generic_pkg.all;
use work.fmc_adc_pkg.all;
use work.wr_fabric_pkg.all;
package dbe_wishbone_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component wb_dma_interface
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component xwb_dma_interface
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component wb_fmc150
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Simulation Only ports
-----------------------------
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- ADC output signals
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end component;
component xwb_fmc150
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Simulation Only ports
-----------------------------
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- ADC output signals
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
-- Wishbone Streaming Interface Source
wbs_source_i : in t_wbs_source_in;
wbs_source_o : out t_wbs_source_out
);
end component;
component wb_fmc516
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := dummy_clk_use_chain;
g_use_data_chains : t_data_use_chain := dummy_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch0 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(7 downto 0);
adc_data_ch0_n_i : in std_logic_vector(7 downto 0);
adc_data_ch1_p_i : in std_logic_vector(7 downto 0);
adc_data_ch1_n_i : in std_logic_vector(7 downto 0);
adc_data_ch2_p_i : in std_logic_vector(7 downto 0);
adc_data_ch2_n_i : in std_logic_vector(7 downto 0);
adc_data_ch3_p_i : in std_logic_vector(7 downto 0);
adc_data_ch3_n_i : in std_logic_vector(7 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC.
-- SPI interface?
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable Si571 VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_b : inout std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_adr_o : out std_logic_vector(c_num_adc_channels*c_wbs_adr4_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_num_adc_channels*c_wbs_dat16_width-1 downto 0);
wbs_cyc_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_stb_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_we_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_sel_o : out std_logic_vector(c_num_adc_channels*c_wbs_sel16_width-1 downto 0);
wbs_ack_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_stall_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
component xwb_fmc516
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := dummy_clk_use_chain;
g_use_data_chains : t_data_use_chain := dummy_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC,
-- programmable via Microwire Interface
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_b : inout std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
component wb_fmc130m_4ch
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := default_clk_use_chain;
g_with_bufio_clk_chains : t_clk_use_bufio_chain := default_clk_use_bufio_chain;
g_with_bufr_clk_chains : t_clk_use_bufr_chain := default_clk_use_bufr_chain;
g_use_data_chains : t_data_use_chain := default_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic := '0';
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic := '0';
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic := '0';
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc3_of_i : in std_logic := '0'; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic := '0';
fmc_pg_m2c_i : in std_logic := '0';
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic := '0';
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic := '0';
fmc_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic := '0';
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_pll_status_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_adr_o : out std_logic_vector(c_num_adc_channels*c_wbs_adr4_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_num_adc_channels*c_wbs_dat16_width-1 downto 0);
wbs_cyc_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_stb_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_we_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_sel_o : out std_logic_vector(c_num_adc_channels*c_wbs_sel16_width-1 downto 0);
wbs_ack_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_stall_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
component xwb_fmc130m_4ch
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := default_clk_use_chain;
g_with_bufio_clk_chains : t_clk_use_bufio_chain := default_clk_use_bufio_chain;
g_with_bufr_clk_chains : t_clk_use_bufr_chain := default_clk_use_bufr_chain;
g_use_data_chains : t_data_use_chain := default_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic := '0';
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_pll_status_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
component xwb_ethmac_adapter
port(
clk_i : in std_logic;
rstn_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in;
tx_ram_o : out t_wishbone_master_out;
tx_ram_i : in t_wishbone_master_in;
rx_ram_o : out t_wishbone_master_out;
rx_ram_i : in t_wishbone_master_in;
rx_eb_o : out t_wrf_source_out;
rx_eb_i : in t_wrf_source_in;
tx_eb_o : out t_wrf_sink_out;
tx_eb_i : in t_wrf_sink_in;
irq_tx_done_o : out std_logic;
irq_rx_done_o : out std_logic
);
end component;
component wb_dbe_periph
generic(
-- NOT used!
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_num_buttons : natural := 8
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- LEDs
led_out_o : out std_logic_vector(g_num_leds-1 downto 0);
led_in_i : in std_logic_vector(g_num_leds-1 downto 0);
led_oen_o : out std_logic_vector(g_num_leds-1 downto 0);
-- Buttons
button_out_o : out std_logic_vector(g_num_buttons-1 downto 0);
button_in_i : in std_logic_vector(g_num_buttons-1 downto 0);
button_oen_o : out std_logic_vector(g_num_buttons-1 downto 0);
-- Wishbone
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic
);
end component;
component xwb_dbe_periph
generic(
-- NOT used!
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_num_buttons : natural := 8
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- LEDs
led_out_o : out std_logic_vector(g_num_leds-1 downto 0);
led_in_i : in std_logic_vector(g_num_leds-1 downto 0);
led_oen_o : out std_logic_vector(g_num_leds-1 downto 0);
-- Buttons
button_out_o : out std_logic_vector(g_num_buttons-1 downto 0);
button_in_i : in std_logic_vector(g_num_buttons-1 downto 0);
button_oen_o : out std_logic_vector(g_num_buttons-1 downto 0);
-- Wishbone
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end component;
component wb_rs232_syscon
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
m_wb_sel_o : out std_logic_vector(3 downto 0);
m_wb_we_o : out std_logic;
m_wb_dat_o : out std_logic_vector(31 downto 0);
m_wb_dat_i : in std_logic_vector(31 downto 0);
m_wb_cyc_o : out std_logic;
m_wb_stb_o : out std_logic;
m_wb_ack_i : in std_logic;
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
m_wb_rty_i : in std_logic
);
end component;
component xwb_rs232_syscon
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
wb_master_i : in t_wishbone_master_in;
wb_master_o : out t_wishbone_master_out
);
end component;
--------------------------------------------------------------------
-- SDB Devices Structures
--------------------------------------------------------------------
-- Simple GPIO interface device
constant c_xwb_gpio32_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF", -- Max of 256 pins. Max of 8 32-bit registers
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"35aa6b95",
version => x"00000001",
date => x"20120305",
name => "GSI_GPIO_32 ")));
-- IRQ manager interface device
constant c_xwb_irqmngr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"15ff65e1",
version => x"00000001",
date => x"20120903",
name => "LNLS_IRQMNGR ")));
-- FMC150 Interface
constant c_xwb_fmc150_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"f8c150c1",
version => x"00000001",
date => x"20121010",
name => "LNLS_FMC150 ")));
-- FMC516 Interface
--constant c_xwb_fmc516_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"00",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"0000000000000FFF", -- Too much addresses? Probably...
-- product => (
-- vendor_id => x"1000000000001215", -- LNLS
-- device_id => x"64f2a9ba",
-- version => x"00000001",
-- date => x"20121124",
-- name => "LNLS_FMC516 ")));
-- UART Interface
constant c_xwb_uart_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"1", -- 8-bit port granularity (0001)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"8a5719ae",
version => x"00000001",
date => x"20121011",
name => "CERN_SIMPLE_UART ")));
-- SPI Opencores Interface
constant c_xwb_spi_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"100000004E2C05E5", -- OpenCores
device_id => x"40286417",
version => x"00000001",
date => x"20121124",
name => "OCORES_SPI ")));
-- I2C Opencores Interface
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"100000004E2C05E5", -- OpenCores
device_id => x"97b6323d",
version => x"00000001",
date => x"20121124",
name => "OCORES_I2C_MASTER ")));
-- 1-Wire Opencores Interface
constant c_xwb_1_wire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity (0111)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"100000004E2C05E5", -- OpenCores
device_id => x"525fbb09",
version => x"00000001",
date => x"20121124",
name => "OCORES_1_WIRE ")));
-- Simple TICs counter Interface
constant c_xwb_tics_counter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"FDAFB9DD",
version => x"00000001",
date => x"20130225",
name => "CERN_TICS_COUNTER ")));
constant c_xwb_bpm_swap_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"12897592",
version => x"00000001",
date => x"20130703",
name => "LNLS_BPM_SWAP ")));
constant c_xwb_position_calc_core_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"1bafbf1e",
version => x"00000001",
date => x"20130703",
name => "LNLS_POSITION_CALC ")));
end dbe_wishbone_pkg;
|
-- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_AT_LEAST is
generic(
M : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_AT_LEAST;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_AT_LEAST is
signal value : std_logic_vector(11 downto 0);
signal local_reset : std_logic;
begin
local_reset <= RESET or not SYMBOL;
cnt_symbols: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((value > 0) or (INPUT = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
OUTPUT <= '1' when (value >= M) else '0';
end architecture full;
|
----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----
---- level triggered interrupts.The operating modes available are ----
---- polling fixed priority modes. ---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the pic project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, lalnitt@gmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PIC is
port( CLK_I : in std_logic; --Clock.
RST_I : in std_logic; --Reset
IR : in unsigned(7 downto 0); --Interrupt requests from peripherals.
DataBus : inout unsigned(7 downto 0); --Data bus between processor PIC.
INTR_O : out std_logic; --Interrupt Request pin of processor.
INTA_I : in std_logic --Interrupt ack.
);
end PIC;
architecture Behavioral of PIC is
type state_type is (reset_s,get_commands,jump_int_method,start_polling,tx_int_info_polling,ack_ISR_done,
ack_txinfo_rxd,start_priority_check,tx_int_info_priority,ack_txinfo_rxd_priority,ack_ISR_done_pt);
signal next_s : state_type :=reset_s;
signal int_type : unsigned(1 downto 0):="01";
signal int_index,count_cmd : integer := 0;
type prior_table is array (0 to 7) of unsigned(2 downto 0);
signal pt : prior_table := (others => (others => '0'));
signal int_pt : unsigned(2 downto 0):="000";
signal flag,flag1 : std_logic := '0'; --These flags are used for timing purposes.
begin
process(CLK_I,RST_I)
begin
if( RST_I = '1') then
next_s <= reset_s;
elsif( rising_edge(CLK_I) ) then
flag <= INTA_I;
case next_s is
when reset_s =>
--initialze signals to zero.
flag <= '0';
flag1 <= '0';
int_type <= "00";
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
pt <= (others => (others => '0'));
if( RST_I = '0' ) then
next_s <= get_commands;
else
next_s <= reset_s;
end if;
DataBus <= (others => 'Z');
when get_commands => --Get commands and operating mode from the processor.
if( DataBus(1 downto 0) = "01" ) then
int_type <= "01";
next_s <= jump_int_method;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 0) then
pt(0) <= DataBus(7 downto 5);
pt(1) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 1) then
pt(2) <= DataBus(7 downto 5);
pt(3) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 2) then
pt(4) <= DataBus(7 downto 5);
pt(5) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 3) then
pt(6) <= DataBus(7 downto 5);
pt(7) <= DataBus(4 downto 2);
count_cmd <= 0;
int_type <= "10";
next_s <= jump_int_method;
else
next_s <= get_commands;
end if;
when jump_int_method => --Check which method is used to determine the interrupts.
flag <= '0';
flag1 <= '0';
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
if( int_type = "01" ) then
next_s <= start_polling; --Polling method for checking the interrupts.
elsif( int_type = "10" ) then
next_s <= start_priority_check; --Fixed priority scheme.
else
next_s <= reset_s; --Error if no method is specified.
end if;
DataBus <= (others => 'Z');
when start_polling => --Check for interrupts(one by one) using polling method.
if( IR(int_index) = '1' ) then
INTR_O <= '1';
next_s <= tx_int_info_polling;
else
INTR_O <= '0';
end if;
if( int_index = 7 ) then
int_index <= 0;
else
int_index <= int_index+1;
end if;
DataBus <= (others => 'Z');
when tx_int_info_polling => --Transmit interrupt information if an interrupt is found.
if( INTA_I = '0' ) then
INTR_O <= '0';
end if;
if( flag = '0' ) then
DataBus <= "01011" & to_unsigned( (int_index-1),3); --MSB "01011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if ( flag1 = '1' ) then
next_s <= ack_txinfo_rxd;
if( INTA_I = '0' ) then
DataBus <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd => --ACK send by processor to tell PIC that interrupt info is received correctly.
if( INTA_I <= '0' ) then
next_s <= ack_ISR_done;
DataBus <= (others => 'Z');
end if;
when ack_ISR_done => --Wait for the ISR for the particular interrupt to get over.
if( INTA_I = '0' and DataBus(7 downto 3) = "10100" and DataBus(2 downto 0) = to_unsigned(int_index-1,3) ) then
next_s <= start_polling;
else
next_s <= ack_ISR_done;
end if;
when start_priority_check => --Fixed priority method for interrupt handling.
--Interrupts are checked based on their priority.
if( IR(to_integer(pt(0))) = '1' ) then
int_pt <= pt(0);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(1))) = '1' ) then
int_pt <= pt(1);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(2))) = '1' ) then
int_pt <= pt(2);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(3))) = '1' ) then
int_pt <= pt(3);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(4))) = '1' ) then
int_pt <= pt(4);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(5))) = '1' ) then
int_pt <= pt(5);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(6))) = '1' ) then
int_pt <= pt(6);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(7))) = '1' ) then
int_pt <= pt(7);
INTR_O <= '1';
next_s <= tx_int_info_priority;
else
next_s <= start_priority_check;
end if;
DataBus <= (others => 'Z');
when tx_int_info_priority => --Transmit interrupt information if an interrupt is found.
if( INTA_I = '0' ) then
INTR_O <= '0';
end if;
if( flag = '0' ) then
DataBus <= "10011" & int_pt; --MSB "10011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if ( flag1 = '1' ) then
next_s <= ack_txinfo_rxd_priority;
if( INTA_I = '0' ) then
DataBus <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd_priority => --ACK send by processor to tell PIC that interrupt info is received correctly.
if( INTA_I <= '0' ) then
next_s <= ack_ISR_done_pt;
DataBus <= (others => 'Z');
end if;
when ack_ISR_done_pt => --Wait for the ISR for the particular interrupt to get over.
if( INTA_I = '0' and DataBus(7 downto 3) = "01100" and DataBus(2 downto 0) = int_pt ) then
next_s <= start_priority_check;
elsif( DataBus(7 downto 3) /= "01100" or DataBus(2 downto 0) /= int_pt ) then
next_s <= reset_s; --Error.
else
next_s <= ack_ISR_done_pt;
end if;
when others =>
DataBus <= (others => 'Z');
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all,
work.reg_file_types.all;
entity controller is
generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
debug : dlx_debug_control := none );
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end entity controller;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all,
work.reg_file_types.all;
entity controller is
generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
debug : dlx_debug_control := none );
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end entity controller;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all,
work.reg_file_types.all;
entity controller is
generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
debug : dlx_debug_control := none );
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end entity controller;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for vgca
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: vgca-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- Generated use statements
library analog_hw;
use analog_hw.analog_pack.all;
--
--
-- Start of Generated Entity vgca
--
entity vgca is
-- Generics:
-- No Generated Generics for Entity vgca
-- Generated Port Declaration:
-- No Generated Port for Entity vgca
end vgca;
--
-- End of Generated Entity vgca
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_sender is
port (
send_start: in std_logic;
clock_master: in std_logic; -- clk_500KHz
slave_id: in std_logic_vector(6 downto 0);
rw: in std_logic;
sub_address: in std_logic_vector(7 downto 0);
data: in std_logic_vector(7 downto 0);
ack: out std_logic := '0';
scl: out std_logic := '1';
sda: out std_logic := '1'
);
end i2c_sender;
architecture arch of i2c_sender is
type state_type is (STATE_IDLE, STATE_SENDING);
signal state: state_type;
signal power_on: std_logic := '0';
signal master_count: integer;
begin
process(clock_master)
begin
if (rising_edge(clock_master)) then
if (power_on = '0') then
-- init
power_on <= '1';
state <= STATE_IDLE;
scl <= '1';
sda <= '1';
else
case state is
when STATE_IDLE =>
scl <= '1';
sda <= '1';
if (send_start = '1') then
state <= STATE_SENDING;
master_count <= 0;
end if;
when STATE_SENDING =>
-- scl
if (master_count /= 0 and master_count mod 4 = 0) then
scl <= '1';
elsif (master_count mod 4 = 2) then
scl <= '0';
end if;
if (master_count > 117) then
scl <= '1';
end if;
-- sda
case master_count is
-- start bit
when 1 =>
ack <= '0';
sda <= '0';
-- first byte
when 3 =>
sda <= slave_id(6);
when 7 =>
sda <= slave_id(5);
when 11 =>
sda <= slave_id(4);
when 15 =>
sda <= slave_id(3);
when 19 =>
sda <= slave_id(2);
when 23 =>
sda <= slave_id(1);
when 27 =>
sda <= slave_id(0);
when 31 =>
sda <= rw;
when 35 =>
sda <= 'X';
-- second byte
when 39 =>
sda <= sub_address(7);
when 43 =>
sda <= sub_address(6);
when 47 =>
sda <= sub_address(5);
when 51 =>
sda <= sub_address(4);
when 55 =>
sda <= sub_address(3);
when 59 =>
sda <= sub_address(2);
when 63 =>
sda <= sub_address(1);
when 67 =>
sda <= sub_address(0);
when 71 =>
sda <= 'X';
-- third byte
when 75 =>
sda <= data(7);
when 79 =>
sda <= data(6);
when 83 =>
sda <= data(5);
when 87 =>
sda <= data(4);
when 91 =>
sda <= data(3);
when 95 =>
sda <= data(2);
when 99 =>
sda <= data(1);
when 103 =>
sda <= data(0);
when 107 =>
sda <= 'X';
-- end bit
when 111 =>
sda <= '0';
when 123 =>
sda <= '1';
-- ack
-- when 118 =>
when 258 =>
ack <= '1';
-- when 119 =>
when 259 =>
ack <= '0';
state <= STATE_IDLE;
when others =>
ack <= '0';
-- do nothing
end case; -- master_count
master_count <= master_count + 1;
end case; -- state
end if; -- (power_on = '0')
end if; -- rising_edge(clock_master)
end process; -- (clock_master)
end arch;
|
configuration blah of blah is
end blah;
configuration blah of blah is
for beh
end for beh;
end blah;
configuration blah of blah is
use blah.blah.blah;
end blah;
configuration blah of blah is
attribute attribute_designator of entity_designator : entity is 0;
end blah;
configuration blah of blah is
group identifier : group_template_name ( group_constituent, group_constituent );
end blah;
configuration blah of blah is
use blah.blah.blah;
attribute attribute_designator of entity_designator : entity is 0;
group identifier : group_template_name ( group_constituent, group_constituent );
use blah.blah.blah;
group identifier : group_template_name ( group_constituent, group_constituent );
attribute attribute_designator of entity_designator : entity is 0;
end blah;
configuration blah of blah is
for generate_statement_label ( generate_specification )
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
use my.my.my;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for beh2
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for all : component_name
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for others : component_name
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
use open;
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
use configuration configuration_name;
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
use entity entity_name;
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
use entity entity_name(architecture_name);
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
generic map (
formal_part => actual_part,
actual_part
);
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
port map (
formal_part => actual_part,
actual_part
);
end for;
end for;
end configuration blah;
configuration blah of blah is
for beh
use blah.blah.blah;
for instantiation_label : component_name
use entity entity_name(architecture_name)
generic map (
formal_part => actual_part,
actual_part
)
port map (
formal_part => actual_part,
actual_part
);
for beh2
use blah2.blah2.blah2;
for instantiation_label : component_name
use entity entity_name2(architecture_name2)
generic map (
formal_part2 => actual_part2,
actual_part2
)
port map (
formal_part2 => actual_part2,
actual_part2
);
end for;
end for;
end for;
end for;
end configuration blah;
|
------------------------------------------------------------
-- VGA Simulator projet VHDL
-- The whole system implementation that holds the three modules
-- Elhamer Oussama abdelkhalek
-- Generate a picture, save if on a spesific location on the disk, and generate the corresponding H_Sync and V_Sync
-- the three modules are setted with the 640 * 480 resolution
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VGA_SIMULATOR is
Port ( Reset : in STD_LOGIC;
H_SYNC : inout STD_LOGIC;
V_SYNC : inout STD_LOGIC );
end VGA_SIMULATOR;
architecture Behavioral of VGA_SIMULATOR is
component VGA is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : inout STD_LOGIC;
H_SYNC : inout STD_LOGIC;
V_SYNC : inout STD_LOGIC);
end component;
component MIRE is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (7 downto 0);
G : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component image_file is
generic ( V_SIZE, H_SIZE : integer);
port ( clk, reset : in std_logic;
r,g,b : in std_logic_vector);
end component;
signal Pix_sig : std_logic;
signal R_sig : std_logic_vector(7 downto 0) ;
signal G_sig : std_logic_vector(7 downto 0);
signal B_sig : std_logic_vector(7 downto 0);
begin
VGA_Module : VGA generic map (V_SIZE => 480, H_SIZE => 640) port map (Reset, Pix_sig, H_SYNC, V_SYNC);
MIRE_Module : MIRE generic map (V_SIZE => 480, H_SIZE => 640) port map (Reset, Pix_sig, R_sig, G_sig, B_sig);
SAVE_IMAGE_MODULE : image_file generic map (V_SIZE =>480, H_SIZE => 640) port map (Pix_sig, Reset, R_sig, G_sig, B_sig);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(
-- GLOBAL SIGNALS:
clk : in std_logic;
reset : in std_logic;
-- COMMAND INTERFACE:
data_in_vld : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out_vld : out std_logic;
data_out : out std_logic_vector(7 downto 0);
--REGISTER ACCESS INTERFACE:
rd_ack : in std_logic;
rd_data : in std_logic_vector(31 downto 0);
wr_en : out std_logic;
rd_en : out std_logic;
addr : out std_logic_vector(15 downto 0);
wr_data : out std_logic_vector(31 downto 0));
end entity;
architecture behaviour of fsm is
type state is (IDLE, CMD, RD, WR, RSP, BRK, ADDR_0, ADDR_1, ADDR_2, ADDR_3, DATA_0, DATA_1, DATA_2, DATA_3, READ_DATA, READ_ACK, RSP_SPC, RSP_CMD);
signal fsm_state : state := IDLE;
signal prev_fsm_state : state := IDLE;
signal current_state : state := IDLE;
signal next_state : state := IDLE;
signal state_buffer : state := IDLE;
signal addr_reg : std_logic_vector(31 downto 0) := (others => '0');
signal data_reg : std_logic_vector(31 downto 0) := (others => '0');
signal fsm_sig : std_logic_vector(7 downto 0);
signal prev_fsm_sig : std_logic_vector(7 downto 0);
signal current_sig : std_logic_vector(7 downto 0);
signal next_sig : std_logic_vector(7 downto 0);
signal rd_cntr : integer := 0;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
fsm_state <= IDLE;
current_state <= IDLE;
prev_fsm_state <= IDLE;
else
case fsm_state is
when IDLE =>
if (data_in_vld = '1' and data_in = x"e7") then
fsm_state <= CMD;
end if;
current_state <= IDLE;
when CMD =>
if (data_in_vld = '1') then
case data_in is
when x"13" =>
fsm_state <= RD;
current_state <= ADDR_3;
when x"23" =>
fsm_state <= WR;
current_state <= ADDR_3;
when x"e7" =>
fsm_state <= prev_fsm_state;
current_state <= next_state;
when others =>
fsm_state <= IDLE;
current_state <= IDLE;
end case;
end if;
when others =>
if (data_in_vld = '1' and data_in = x"e7") then
prev_fsm_state <= fsm_state;
fsm_state <= CMD;
current_state <= CMD;
elsif (next_state = BRK) then
if (fsm_state = BRK) then
fsm_state <= IDLE;
current_state <= IDLE;
else
fsm_state <= BRK;
current_state <= RSP_SPC;
end if;
elsif (next_state = READ_DATA) then
if (rd_ack = '1') then
fsm_state <= RSP;
current_state <= READ_ACK;
rd_cntr <= 0;
elsif (rd_cntr >= 3) then
fsm_state <= BRK;
current_state <= RSP_SPC;
rd_cntr <= 0;
else
current_state <= next_state;
rd_cntr <= rd_cntr + 1;
end if;
elsif (next_state = fsm_state) then
fsm_state <= IDLE;
current_state <= next_state;
else
current_state <= next_state;
end if;
end case;
end if;
end if;
end process;
process(current_state)
begin
rd_en <= '0';
wr_en <= '0';
addr <= (others => '0');
wr_data <= (others => '0');
data_out_vld <= '0';
data_out <= (others => '0');
case current_state is
when IDLE =>
next_state <= IDLE;
when ADDR_3 =>
if (data_in_vld = '1') then
addr_reg(31 downto 24) <= data_in;
next_state <= ADDR_2;
end if;
when ADDR_2 =>
if (data_in_vld = '1') then
addr_reg(23 downto 16) <= data_in;
next_state <= ADDR_1;
end if;
when ADDR_1 =>
if (data_in_vld = '1') then
addr_reg(15 downto 8) <= data_in;
next_state <= ADDR_0;
end if;
when ADDR_0 =>
if (data_in_vld = '1') then
addr_reg(7 downto 0) <= data_in;
case fsm_state is
when RD =>
next_state <= READ_DATA;
when WR =>
next_state <= DATA_3;
when others => null;
end case;
end if;
when DATA_3 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(31 downto 24) <= data_in;
next_state <= DATA_2;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(31 downto 24);
if (data_reg(31 downto 24) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_2;
else
next_state <= DATA_2;
end if;
when others => null;
end case;
when DATA_2 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(23 downto 16) <= data_in;
next_state <= DATA_1;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(23 downto 16);
if (data_reg(23 downto 16) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_1;
else
next_state <= DATA_1;
end if;
when others => null;
end case;
when DATA_1 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(15 downto 8) <= data_in;
next_state <= DATA_0;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(15 downto 8);
if (data_reg(15 downto 8) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= DATA_0;
else
next_state <= DATA_0;
end if;
when others => null;
end case;
when DATA_0 =>
case fsm_state is
when WR =>
if (data_in_vld = '1') then
data_reg(7 downto 0) <= data_in;
next_state <= WR;
end if;
when RSP =>
data_out_vld <= '1';
data_out <= data_reg(7 downto 0);
if (data_reg(7 downto 0) = x"e7") then
next_state <= RSP_SPC;
state_buffer <= RSP;
else
next_state <= RSP;
end if;
when others => null;
end case;
when READ_DATA =>
rd_en <= '1';
addr <= addr_reg(15 downto 0);
when READ_ACK =>
data_reg <= rd_data;
next_state <= RSP_SPC;
when WR =>
wr_en <= '1';
addr <= addr_reg(15 downto 0);
wr_data <= data_reg;
next_state <= IDLE;
when RSP_SPC =>
data_out_vld <= '1';
data_out <= x"e7";
if (state_buffer = IDLE) then
next_state <= RSP_CMD;
else
next_state <= state_buffer;
end if;
state_buffer <= IDLE;
when RSP_CMD =>
data_out_vld <= '1';
case fsm_state is
when RSP =>
data_out <= x"03";
next_state <= DATA_3;
when BRK =>
data_out <= x"55";
next_state <= BRK;
when others => null;
end case;
when others => null;
end case;
end process;
end architecture; |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:55:20)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 30);
output1, output2, output3, output4: OUT unsigned(0 TO 31));
END mesaia_random_entity;
ARCHITECTURE mesaia_random_description OF mesaia_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register15: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register16: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register17: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register18: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register19: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register20: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register21: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register22: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register23: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register24: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register25: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register26: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register27: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register28: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register29: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register30: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register31: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register32: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register33: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register34: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register35: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register36: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 * 11;
register12 := input12 + 12;
register13 := input13 * 13;
register14 := input14 + 14;
register15 := input15 * 15;
register16 := input16 + 16;
register17 := input17 * 17;
register18 := input18 * 18;
register19 := input19 + 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
WHEN "00000010" =>
register19 := register20 + register19;
register20 := input25 * 25;
register25 := input26 + 26;
register8 := register8 + register16;
register16 := input27 * 27;
register26 := input28 + 28;
register27 := input29 + 29;
register28 := input30 * 30;
register29 := input31 + 31;
register30 := input32 + 32;
register31 := input33 + 33;
register32 := input34 * 34;
WHEN "00000011" =>
register18 := register18 + register27;
register27 := input35 * 35;
register33 := input36 + 36;
register34 := input37 * 37;
register35 := input38 + 38;
WHEN "00000100" =>
register4 := register4 + register35;
register18 := register28 + register18;
register28 := input39 + 39;
register35 := input40 * 40;
register14 := register32 + register14;
register32 := input41 * 41;
register36 := input42 * 42;
WHEN "00000101" =>
register4 := register6 + register4;
register6 := register36 + register25;
register18 := ((NOT register18) + 1) XOR register18;
register7 := register15 + register7;
register13 := register13 + register23;
WHEN "00000110" =>
register4 := ((NOT register4) + 1) XOR register4;
register14 := register17 + register14;
WHEN "00000111" =>
register14 := ((NOT register14) + 1) XOR register14;
register12 := register34 + register12;
register8 := register35 + register8;
register15 := input43 * 49;
register17 := input44 * 50;
register5 := register5 + register26;
register21 := register21 + register30;
register23 := register27 + register29;
register25 := input45 * 51;
register26 := input46 * 52;
WHEN "00001000" =>
register19 := register26 + register19;
register13 := register15 + register13;
register15 := register32 + register33;
register26 := input47 * 53;
WHEN "00001001" =>
register5 := register26 + register5;
register6 := register22 + register6;
register22 := input48 * 54;
register17 := register17 + register31;
WHEN "00001010" =>
register1 := register22 + register1;
register7 := register25 + register7;
register11 := register11 + register21;
register5 := ((NOT register5) + 1) XOR register5;
register17 := register20 + register17;
WHEN "00001011" =>
register7 := ((NOT register7) + 1) XOR register7;
register3 := register3 + register28;
register13 := ((NOT register13) + 1) XOR register13;
WHEN "00001100" =>
register11 := ((NOT register11) + 1) XOR register11;
register10 := register10 + register12;
register7 := register13 - register7;
WHEN "00001101" =>
register11 := register11 - register14;
register7 := register7 * 64;
register10 := ((NOT register10) + 1) XOR register10;
register2 := register2 + register15;
register1 := register24 + register1;
WHEN "00001110" =>
register11 := register11 * 68;
register9 := register9 + register23;
register3 := register16 + register3;
register6 := ((NOT register6) + 1) XOR register6;
register12 := ((NOT register19) + 1) XOR register19;
register4 := register4 - register10;
WHEN "00001111" =>
register3 := ((NOT register3) + 1) XOR register3;
register7 := register12 + register7;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00010000" =>
register1 := register1 - register5;
register4 := register4 * 78;
WHEN "00010001" =>
register4 := register18 + register4;
register1 := register1 * 80;
register3 := register3 + register11;
output1 <= register7(0 TO 14) & register2(0 TO 15);
WHEN "00010010" =>
output2 <= register3(0 TO 14) & register9(0 TO 15);
output3 <= register4(0 TO 14) & register17(0 TO 15);
register1 := register6 + register1;
WHEN "00010011" =>
output4 <= register1(0 TO 14) & register8(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_random_description; |
--------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 7/23/2010 Scott Larson
-- Initial Public Release
-- Version 1.1 4/11/2013 Scott Larson
-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY spi_master IS
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2); --data bus width
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
END spi_master;
ARCHITECTURE logic OF spi_master IS
TYPE machine IS(ready, execute); --state machine data type
SIGNAL state : machine; --current state
SIGNAL slave : INTEGER; --slave selected for current transaction
SIGNAL clk_ratio : INTEGER; --current clk_div
SIGNAL count : INTEGER; --counter to trigger sclk from system clock
SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
SIGNAL continue : STD_LOGIC; --flag to continue transaction
SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
BEGIN
PROCESS(clock, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset system
busy <= '1'; --set busy signal
ss_n <= (OTHERS => '1'); --deassert all slave select lines
mosi <= '0'; --set master out to high impedance
rx_data <= (OTHERS => '0'); --clear receive data port
state <= ready; --go to ready state when reset is exited
ELSIF(clock'EVENT AND clock = '1') THEN
CASE state IS --state machine
WHEN ready =>
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave select outputs high
mosi <= '0'; --set mosi output high impedance
continue <= '0'; --clear continue flag
--user input to initiate transaction
IF(enable = '1') THEN
busy <= '1'; --set busy signal
IF(addr < slaves) THEN --check for valid slave address
slave <= addr; --clock in current slave selection if valid
ELSE
slave <= 0; --set to first slave if not valid
END IF;
IF(clk_div = 0) THEN --check for valid spi speed
clk_ratio <= 1; --set to maximum speed if zero
count <= 1; --initiate system-to-spi clock counter
ELSE
clk_ratio <= clk_div; --set to input selection if valid
count <= clk_div; --initiate system-to-spi clock counter
END IF;
sclk <= cpol; --set spi clock polarity
assert_data <= NOT cpha; --set spi clock phase
tx_buffer <= tx_data; --clock in data for transmit into buffer
clk_toggles <= 0; --initiate clock toggle counter
last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
state <= execute; --proceed to execute state
ELSE
state <= ready; --remain in ready state
END IF;
WHEN execute =>
busy <= '1'; --set busy signal
ss_n(slave) <= '0'; --set proper slave select output
--system clock to sclk ratio is met
IF(count = clk_ratio) THEN
count <= 1; --reset system-to-spi clock counter
assert_data <= NOT assert_data; --switch transmit/receive indicator
IF(clk_toggles = d_width*2 + 1) THEN
clk_toggles <= 0; --reset spi clock toggles counter
ELSE
clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
END IF;
--spi clock toggle needed
IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
sclk <= NOT sclk; --toggle spi clock
END IF;
--receive spi clock toggle
IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
END IF;
--transmit spi clock toggle
IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
mosi <= tx_buffer(d_width-1); --clock out data bit
tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
END IF;
--last data receive, but continue
IF(clk_toggles = last_bit_rx AND cont = '1') THEN
tx_buffer <= tx_data; --reload transmit buffer
clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
continue <= '1'; --set continue flag
END IF;
--normal end of transaction, but continue
IF(continue = '1') THEN
continue <= '0'; --clear continue flag
busy <= '0'; --clock out signal that first receive data is ready
rx_data <= rx_buffer; --clock out received data to output port
END IF;
--end of transaction
IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave selects high
mosi <= '0'; --set mosi output high impedance
rx_data <= rx_buffer; --clock out received data to output port
state <= ready; --return to ready state
ELSE --not end of transaction
state <= execute; --remain in execute state
END IF;
ELSE --system clock to sclk ratio not met
count <= count + 1; --increment counter
state <= execute; --remain in execute state
END IF;
END CASE;
END IF;
END PROCESS;
END logic;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start : in std_ulogic; -- Start signal
signal clk : in std_ulogic; -- Strobe clock
terminal ain : electrical; -- Analog input terminal
signal eoc : out std_ulogic := '0'; -- End of conversion pin
signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
end entity a2d_nbit;
----------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax : real := 5.0; -- ADC's maximum range
constant delay : time := 10 us; -- ADC's conversion time
type states is (input, convert); -- Two states of A2D Conversion
constant bit_range : integer := 9; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process is
variable thresh : real := Vmax; -- Threshold to test input voltage against
variable Vtmp : real := Vin; -- Snapshot of input voltage
-- when conversion starts
variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
variable status : states := input; -- Begin with "input" case
variable bit_cnt : integer := bit_range;
begin
case status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H';
bit_cnt := bit_range; -- Reset bit_cnt for conversion
thresh := Vmax;
Vtmp := Vin; -- Variable to hold input comparison voltage
eoc <= '0'; -- Reset end of conversion
status := convert; -- Go to convert state
when convert => -- Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh := thresh / 2.0; -- Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
Vtmp := Vtmp - thresh; -- Prepare for next comparison
else
dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := bit_cnt - 1; -- Decrement the bit count
else
dout <= dtmp; -- Put contents of dtmp on output pins
eoc <= '1' after delay; -- Signal end of conversion
status := input; -- Go to input state
end if;
end case;
end process sa_adc;
Iin == 0.0; -- Ideal input draws no current
end architecture sar;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start : in std_ulogic; -- Start signal
signal clk : in std_ulogic; -- Strobe clock
terminal ain : electrical; -- Analog input terminal
signal eoc : out std_ulogic := '0'; -- End of conversion pin
signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
end entity a2d_nbit;
----------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax : real := 5.0; -- ADC's maximum range
constant delay : time := 10 us; -- ADC's conversion time
type states is (input, convert); -- Two states of A2D Conversion
constant bit_range : integer := 9; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process is
variable thresh : real := Vmax; -- Threshold to test input voltage against
variable Vtmp : real := Vin; -- Snapshot of input voltage
-- when conversion starts
variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
variable status : states := input; -- Begin with "input" case
variable bit_cnt : integer := bit_range;
begin
case status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H';
bit_cnt := bit_range; -- Reset bit_cnt for conversion
thresh := Vmax;
Vtmp := Vin; -- Variable to hold input comparison voltage
eoc <= '0'; -- Reset end of conversion
status := convert; -- Go to convert state
when convert => -- Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh := thresh / 2.0; -- Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
Vtmp := Vtmp - thresh; -- Prepare for next comparison
else
dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := bit_cnt - 1; -- Decrement the bit count
else
dout <= dtmp; -- Put contents of dtmp on output pins
eoc <= '1' after delay; -- Signal end of conversion
status := input; -- Go to input state
end if;
end case;
end process sa_adc;
Iin == 0.0; -- Ideal input draws no current
end architecture sar;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start : in std_ulogic; -- Start signal
signal clk : in std_ulogic; -- Strobe clock
terminal ain : electrical; -- Analog input terminal
signal eoc : out std_ulogic := '0'; -- End of conversion pin
signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
end entity a2d_nbit;
----------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax : real := 5.0; -- ADC's maximum range
constant delay : time := 10 us; -- ADC's conversion time
type states is (input, convert); -- Two states of A2D Conversion
constant bit_range : integer := 9; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process is
variable thresh : real := Vmax; -- Threshold to test input voltage against
variable Vtmp : real := Vin; -- Snapshot of input voltage
-- when conversion starts
variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
variable status : states := input; -- Begin with "input" case
variable bit_cnt : integer := bit_range;
begin
case status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H';
bit_cnt := bit_range; -- Reset bit_cnt for conversion
thresh := Vmax;
Vtmp := Vin; -- Variable to hold input comparison voltage
eoc <= '0'; -- Reset end of conversion
status := convert; -- Go to convert state
when convert => -- Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh := thresh / 2.0; -- Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
Vtmp := Vtmp - thresh; -- Prepare for next comparison
else
dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := bit_cnt - 1; -- Decrement the bit count
else
dout <= dtmp; -- Put contents of dtmp on output pins
eoc <= '1' after delay; -- Signal end of conversion
status := input; -- Go to input state
end if;
end case;
end process sa_adc;
Iin == 0.0; -- Ideal input draws no current
end architecture sar;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_A_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_A_e
case_a_p : out std_ulogic
-- End of Generated Port for Entity inst_A_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
case_b_p : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal case : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_case_go <= case; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_A_e
port map (
case_a_p => case
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
case_b_p => case
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
tbi_2p : out tracebuf_2p_in_type;
tbo_2p : in tracebuf_2p_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1; --regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp, npasi, pwrpsr)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, tbo_2p, tbi_2p, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken
);
end;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32 -- Comment should stay
);
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_11 is
end entity ch_03_11;
architecture test of ch_03_11 is
signal sensitivity_list : bit := '0';
begin
-- code from book:
-- make "sensitivity_list" roman italic
control_section : process ( sensitivity_list ) is
begin
null;
end process control_section;
-- end of code from book
stimulus : process is
begin
sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_11 is
end entity ch_03_11;
architecture test of ch_03_11 is
signal sensitivity_list : bit := '0';
begin
-- code from book:
-- make "sensitivity_list" roman italic
control_section : process ( sensitivity_list ) is
begin
null;
end process control_section;
-- end of code from book
stimulus : process is
begin
sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_11 is
end entity ch_03_11;
architecture test of ch_03_11 is
signal sensitivity_list : bit := '0';
begin
-- code from book:
-- make "sensitivity_list" roman italic
control_section : process ( sensitivity_list ) is
begin
null;
end process control_section;
-- end of code from book
stimulus : process is
begin
sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
wait;
end process stimulus;
end architecture test;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block5
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block5 IS
-- Signals
SIGNAL dout_13_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_13_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_13_re_signed <= signed(dout_13_re);
dout_13_im_signed <= signed(dout_13_im);
dout_15_re_signed <= signed(dout_15_re);
dout_15_im_signed <= signed(dout_15_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_13_re_signed, dout_13_im_signed,
dout_15_re_signed, dout_15_im_signed, dout_1_vld, rotate_13)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_13 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_13_re_signed, 18) + resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_13_re_signed, 18) - resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_13_im_signed, 18) + resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_13_im_signed, 18) - resize(dout_15_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_13_re_signed, 18) + resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_13_re_signed, 18) - resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_13_im_signed, 18) + resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_13_im_signed, 18) - resize(dout_15_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
dout_13_re_1 <= std_logic_vector(dout_13_re_tmp);
dout_13_im_1 <= std_logic_vector(dout_13_im_tmp);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg32 is
port(
d : in std_logic_vector(31 downto 0);
rst : in std_logic;
en : in std_logic;
clk : in std_logic; -- clock.
q : out std_logic_vector(31 DOWNTO 0) -- output
);
end reg32;
architecture bhv of reg32 is
begin
process(clk,rst)
begin
if rst = '1' then
q <= (others => '0');
elsif (clk = '1' and clk'event) then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end bhv; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I) -- new
begin
if (rising_edge(CLK_I) and T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I) and T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I) -- new
begin
if (rising_edge(CLK_I) and T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I) and T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity matching is
end matching;
architecture behav of matching is
constant ceq11 : std_logic := '1' ?= '1';
constant ceq1h : std_logic := '1' ?= 'H';
constant ceq1w : std_logic := '1' ?= 'W';
begin
assert ceq11 = '1';
assert ceq1h = '1';
assert ceq1w = 'X';
end behav;
|
constant FONT_ROM : glyph_rom_t = (
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00011000","00111100","00111100","00011000","00011000","00000000","00011000","00000000"),
("01101100","01101100","00000000","00000000","00000000","00000000","00000000","00000000"),
("01101100","01101100","11111110","01101100","11111110","01101100","01101100","00000000"),
("00110000","01111100","11000000","01111000","00001100","11111000","00110000","00000000"),
("00000000","11000110","11001100","00011000","00110000","01100110","11000110","00000000"),
("00111000","01101100","00111000","01110110","11011100","11001100","01110110","00000000"),
("01100000","01100000","11000000","00000000","00000000","00000000","00000000","00000000"),
("00011000","00110000","01100000","01100000","01100000","00110000","00011000","00000000"),
("01100000","00110000","00011000","00011000","00011000","00110000","01100000","00000000"),
("00000000","01100110","00111100","11111111","00111100","01100110","00000000","00000000"),
("00000000","00110000","00110000","11111100","00110000","00110000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00110000","00110000","01100000"),
("00000000","00000000","00000000","11111100","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00110000","00110000","00000000"),
("00000110","00001100","00011000","00110000","01100000","11000000","10000000","00000000"),
("01111100","11000110","11001110","11011110","11110110","11100110","01111100","00000000"),
("00110000","01110000","00110000","00110000","00110000","00110000","11111100","00000000"),
("01111000","11001100","00001100","00111000","01100000","11001100","11111100","00000000"),
("01111000","11001100","00001100","00111000","00001100","11001100","01111000","00000000"),
("00011100","00111100","01101100","11001100","11111110","00001100","00011110","00000000"),
("11111100","11000000","11111000","00001100","00001100","11001100","01111000","00000000"),
("00111000","01100000","11000000","11111000","11001100","11001100","01111000","00000000"),
("11111100","11001100","00001100","00011000","00110000","00110000","00110000","00000000"),
("01111000","11001100","11001100","01111000","11001100","11001100","01111000","00000000"),
("01111000","11001100","11001100","01111100","00001100","00011000","01110000","00000000"),
("00000000","00110000","00110000","00000000","00000000","00110000","00110000","00000000"),
("00000000","00110000","00110000","00000000","00000000","00110000","00110000","01100000"),
("00011000","00110000","01100000","11000000","01100000","00110000","00011000","00000000"),
("00000000","00000000","11111100","00000000","00000000","11111100","00000000","00000000"),
("01100000","00110000","00011000","00001100","00011000","00110000","01100000","00000000"),
("01111000","11001100","00001100","00011000","00110000","00000000","00110000","00000000"),
("01111100","11000110","11011110","11011110","11011110","11000000","01111000","00000000"),
("00110000","01111000","11001100","11001100","11111100","11001100","11001100","00000000"),
("11111100","01100110","01100110","01111100","01100110","01100110","11111100","00000000"),
("00111100","01100110","11000000","11000000","11000000","01100110","00111100","00000000"),
("11111000","01101100","01100110","01100110","01100110","01101100","11111000","00000000"),
("11111110","01100010","01101000","01111000","01101000","01100010","11111110","00000000"),
("11111110","01100010","01101000","01111000","01101000","01100000","11110000","00000000"),
("00111100","01100110","11000000","11000000","11001110","01100110","00111110","00000000"),
("11001100","11001100","11001100","11111100","11001100","11001100","11001100","00000000"),
("01111000","00110000","00110000","00110000","00110000","00110000","01111000","00000000"),
("00011110","00001100","00001100","00001100","11001100","11001100","01111000","00000000"),
("11100110","01100110","01101100","01111000","01101100","01100110","11100110","00000000"),
("11110000","01100000","01100000","01100000","01100010","01100110","11111110","00000000"),
("11000110","11101110","11111110","11111110","11010110","11000110","11000110","00000000"),
("11000110","11100110","11110110","11011110","11001110","11000110","11000110","00000000"),
("00111000","01101100","11000110","11000110","11000110","01101100","00111000","00000000"),
("11111100","01100110","01100110","01111100","01100000","01100000","11110000","00000000"),
("01111000","11001100","11001100","11001100","11011100","01111000","00011100","00000000"),
("11111100","01100110","01100110","01111100","01101100","01100110","11100110","00000000"),
("01111000","11001100","11100000","01110000","00011100","11001100","01111000","00000000"),
("11111100","10110100","00110000","00110000","00110000","00110000","01111000","00000000"),
("11001100","11001100","11001100","11001100","11001100","11001100","11111100","00000000"),
("11001100","11001100","11001100","11001100","11001100","01111000","00110000","00000000"),
("11000110","11000110","11000110","11010110","11111110","11101110","11000110","00000000"),
("11000110","11000110","01101100","00111000","00111000","01101100","11000110","00000000"),
("11001100","11001100","11001100","01111000","00110000","00110000","01111000","00000000"),
("11111110","11000110","10001100","00011000","00110010","01100110","11111110","00000000"),
("01111000","01100000","01100000","01100000","01100000","01100000","01111000","00000000"),
("11000000","01100000","00110000","00011000","00001100","00000110","00000010","00000000"),
("01111000","00011000","00011000","00011000","00011000","00011000","01111000","00000000"),
("00010000","00111000","01101100","11000110","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","11111111"),
("00110000","00110000","00011000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","01111000","00001100","01111100","11001100","01110110","00000000"),
("11100000","01100000","01100000","01111100","01100110","01100110","11011100","00000000"),
("00000000","00000000","01111000","11001100","11000000","11001100","01111000","00000000"),
("00011100","00001100","00001100","01111100","11001100","11001100","01110110","00000000"),
("00000000","00000000","01111000","11001100","11111100","11000000","01111000","00000000"),
("00111000","01101100","01100000","11110000","01100000","01100000","11110000","00000000"),
("00000000","00000000","01110110","11001100","11001100","01111100","00001100","11111000"),
("11100000","01100000","01101100","01110110","01100110","01100110","11100110","00000000"),
("00110000","00000000","01110000","00110000","00110000","00110000","01111000","00000000"),
("00001100","00000000","00001100","00001100","00001100","11001100","11001100","01111000"),
("11100000","01100000","01100110","01101100","01111000","01101100","11100110","00000000"),
("01110000","00110000","00110000","00110000","00110000","00110000","01111000","00000000"),
("00000000","00000000","11001100","11111110","11111110","11010110","11000110","00000000"),
("00000000","00000000","11111000","11001100","11001100","11001100","11001100","00000000"),
("00000000","00000000","01111000","11001100","11001100","11001100","01111000","00000000"),
("00000000","00000000","11011100","01100110","01100110","01111100","01100000","11110000"),
("00000000","00000000","01110110","11001100","11001100","01111100","00001100","00011110"),
("00000000","00000000","11011100","01110110","01100110","01100000","11110000","00000000"),
("00000000","00000000","01111100","11000000","01111000","00001100","11111000","00000000"),
("00010000","00110000","01111100","00110000","00110000","00110100","00011000","00000000"),
("00000000","00000000","11001100","11001100","11001100","11001100","01110110","00000000"),
("00000000","00000000","11001100","11001100","11001100","01111000","00110000","00000000"),
("00000000","00000000","11000110","11010110","11111110","11111110","01101100","00000000"),
("00000000","00000000","11000110","01101100","00111000","01101100","11000110","00000000"),
("00000000","00000000","11001100","11001100","11001100","01111100","00001100","11111000"),
("00000000","00000000","11111100","10011000","00110000","01100100","11111100","00000000"),
("00011100","00110000","00110000","11100000","00110000","00110000","00011100","00000000"),
("00011000","00011000","00011000","00000000","00011000","00011000","00011000","00000000"),
("11100000","00110000","00110000","00011100","00110000","00110000","11100000","00000000"),
("01110110","11011100","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"));
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:28:39 04/11/2017
-- Design Name:
-- Module Name: variable_clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_controller is
Port ( clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_o : out STD_LOGIC);
end clk_controller;
architecture PORTMAP of clk_controller is
COMPONENT prescaler_FSM IS
PORT(
clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_state : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT quad_prescaler IS
PORT(
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
control : in STD_LOGIC_VECTOR(1 downto 0);
reset : in STD_LOGIC);
END COMPONENT;
COMPONENT debounce IS
PORT (
clk : in STD_LOGIC;
button : in STD_LOGIC;
result : out STD_LOGIC);
END COMPONENT;
signal operation : std_logic_vector(1 downto 0);
signal i_c : std_logic;
signal tp: std_logic;
begin
debounceP : debounce PORT MAP(
clk => clk,
button => toggle,
result => tp
);
FSM : prescaler_FSM PORT MAP(
toggle => tp,
reset => reset,
clk => clk,
clk_state => operation
);
clk_div : quad_prescaler PORT MAP(
clk_in => clk,
clk_out => i_c,
reset => reset,
control => operation
);
clk_o <= i_c;
end PORTMAP;
|
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Calculator is
port (clock : in STD_LOGIC;
btn_reset : in STD_LOGIC;
btn_inc : in STD_LOGIC;
btn_dec : in STD_LOGIC;
switch_input : in STD_LOGIC;
switch_operation : in STD_LOGIC;
switch_done : in STD_LOGIC;
display_out : out STD_LOGIC_VECTOR (15 downto 0));
end Calculator;
architecture Behavioral of Calculator is
type STATE is (BOOT,
POLLING,
INPUT_DATA,
RELEASE_BTN_INC,
RELEASE_BTN_DEC,
CALCULATE,
SHOW_RESULTS);
signal current_state : STATE;
signal input_a, input_b : INTEGER range 0 to 255;
signal result : STD_LOGIC_VECTOR (7 downto 0);
signal operation : INTEGER range 0 to 9;
begin
core : process (clock, btn_reset, btn_inc, btn_dec)
begin
if clock'event and clock = '1' then
if btn_reset = '1' then
current_state <= BOOT;
end if;
case current_state is
when BOOT =>
input_a <= 0;
input_b <= 0;
operation <= 0;
current_state <= POLLING;
when POLLING =>
if switch_done = '1' then
current_state <= CALCULATE;
elsif btn_inc = '1' then
current_state <= RELEASE_BTN_INC;
elsif btn_dec = '1' then
current_state <= RELEASE_BTN_DEC;
else
current_state <= POLLING;
end if;
when RELEASE_BTN_INC =>
if btn_inc = '0' then
if switch_operation = '0' then
if switch_input = '0' then
input_a <= input_a + 1;
else
input_b <= input_b + 1;
end if;
else
operation <= operation + 1;
end if;
current_state <= POLLING;
end if;
when RELEASE_BTN_DEC =>
if btn_dec = '0' then
if switch_operation = '0' then
if switch_input = '0' then
input_a <= input_a - 1;
else
input_b <= input_b - 1;
end if;
else
operation <= operation - 1;
end if;
current_state <= POLLING;
end if;
when CALCULATE =>
case operation is
when 1 =>
result <= conv_std_logic_vector((input_a + input_b), 8);
when 2 =>
result <= conv_std_logic_vector((input_a - input_b), 8);
when 3 =>
result <= conv_std_logic_vector((input_a - input_b), 8);
when 4 =>
result <= conv_std_logic_vector((input_a * input_b), 8);
when 5 =>
result <= conv_std_logic_vector(input_a, 8) and conv_std_logic_vector(input_b, 8);
when 6 =>
result <= conv_std_logic_vector(input_a, 8) or conv_std_logic_vector(input_b, 8);
when 7 =>
result <= conv_std_logic_vector(input_a, 8) xor conv_std_logic_vector(input_b, 8);
when 8 =>
result <= not conv_std_logic_vector(input_a, 8);
when 9 =>
result <= conv_std_logic_vector(0, 8);
when others =>
result <= conv_std_logic_vector(0, 8);
end case;
current_state <= BOOT;
when others =>
current_state <= BOOT;
end case;
end if;
end process;
end Behavioral ;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
-- ------------------------------------------------------------------------
entity gigatron_tb_rom is
port (
a : in unsigned(15 downto 0);
q : out unsigned(15 downto 0)
);
end entity;
-- ------------------------------------------------------------------------
architecture rtl of gigatron_tb_rom is
subtype rom_data_elem_t is unsigned(7 downto 0);
type rom_data_t is array(integer range 0 to 65535) of rom_data_elem_t;
signal rom_data_byte0 : rom_data_t := (
X"00",X"18",X"18",X"C1",X"00",X"D6",X"00",X"69",
X"CA",X"C2",X"69",X"EC",X"00",X"69",X"CA",X"61",
X"F0",X"01",X"FC",X"82",X"00",X"C2",X"EC",X"A0",
X"01",X"EC",X"A0",X"00",X"18",X"18",X"00",X"D2",
X"D6",X"01",X"F4",X"8D",X"60",X"C2",X"01",X"F4",
X"81",X"60",X"C2",X"81",X"C2",X"01",X"80",X"EC",
X"D2",X"01",X"80",X"EC",X"D6",X"00",X"18",X"18",
X"00",X"C2",X"90",X"00",X"D6",X"DC",X"DC",X"DC",
X"DC",X"DC",X"DC",X"DC",X"DC",X"DC",X"DC",X"00",
X"C2",X"00",X"C2",X"C2",X"C2",X"C2",X"C2",X"00",
X"18",X"18",X"00",X"C2",X"C2",X"C2",X"00",X"18",
X"18",X"C2",X"C2",X"14",X"E0",X"C2",X"00",X"C2",
X"00",X"C2",X"14",X"CA",X"CA",X"CA",X"C2",X"C2",
X"00",X"C2",X"00",X"C2",X"C2",X"C2",X"00",X"C2",
X"00",X"C2",X"00",X"C2",X"01",X"A0",X"C2",X"14",
X"E0",X"00",X"02",X"02",X"02",X"02",X"02",X"02",
X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",
X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",
X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",
X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",
X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",
X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",
X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",
X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",
X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",
X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",
X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",
X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",X"00",
X"14",X"E0",X"00",X"14",X"E0",X"00",X"14",X"E0",
X"00",X"14",X"E0",X"00",X"14",X"E0",X"15",X"14",
X"E0",X"01",X"02",X"02",X"19",X"02",X"14",X"E0",
X"00",X"C3",X"00",X"C2",X"02",X"14",X"E0",X"00",
X"15",X"E0",X"00",X"00",X"C2",X"00",X"C2",X"00",
X"C2",X"00",X"C2",X"81",X"C2",X"61",X"61",X"81",
X"C2",X"81",X"C2",X"E8",X"FC",X"60",X"60",X"81",
X"C2",X"01",X"F0",X"FC",X"A0",X"01",X"C2",X"F0",
X"FC",X"00",X"00",X"81",X"EC",X"FC",X"00",X"E4",
X"C2",X"80",X"FE",X"FC",X"00",X"C2",X"FC",X"21",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"C2",X"00",X"C2",X"01",X"F0",X"00",X"C2",X"15",
X"E0",X"00",X"14",X"E0",X"14",X"01",X"20",X"C2",
X"01",X"EC",X"FC",X"00",X"00",X"41",X"C2",X"01",
X"F0",X"FC",X"A0",X"00",X"C2",X"19",X"01",X"21",
X"80",X"19",X"D6",X"00",X"29",X"89",X"CA",X"30",
X"05",X"89",X"89",X"CA",X"20",X"69",X"12",X"09",
X"14",X"8D",X"E8",X"FC",X"20",X"00",X"81",X"C2",
X"01",X"14",X"19",X"01",X"F4",X"80",X"C2",X"A0",
X"EC",X"A1",X"00",X"FC",X"C2",X"EC",X"00",X"FC",
X"C2",X"01",X"02",X"60",X"C2",X"01",X"60",X"EC",
X"FC",X"C3",X"C0",X"01",X"20",X"F0",X"01",X"00",
X"C2",X"15",X"E0",X"00",X"FC",X"19",X"40",X"21",
X"C2",X"C0",X"00",X"C2",X"15",X"E0",X"00",X"FC",
X"19",X"E0",X"14",X"01",X"60",X"EC",X"01",X"A0",
X"C2",X"20",X"F0",X"00",X"FC",X"FC",X"00",X"EC",
X"A0",X"02",X"00",X"C2",X"FC",X"02",X"C2",X"00",
X"C2",X"00",X"C2",X"01",X"60",X"EC",X"01",X"E8",
X"01",X"C2",X"01",X"C2",X"FC",X"00",X"00",X"C2",
X"C2",X"02",X"C2",X"00",X"EC",X"A0",X"02",X"C2",
X"FC",X"00",X"01",X"20",X"C2",X"00",X"C2",X"15",
X"E0",X"00",X"14",X"09",X"C2",X"C2",X"EC",X"FC",
X"00",X"00",X"C2",X"01",X"21",X"80",X"14",X"E0",
X"18",X"02",X"02",X"02",X"02",X"02",X"02",X"FC",
X"01",X"00",X"C2",X"14",X"11",X"0D",X"DE",X"C2",
X"0D",X"91",X"15",X"00",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",X"5D",
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X"61",X"72",X"6E",X"47",X"67",X"74",X"6F",X"21",
others => (others => '0'));
signal q0_reg : rom_data_elem_t;
signal q1_reg : rom_data_elem_t;
begin
q(7 downto 0) <= q0_reg;
q(15 downto 8) <= q1_reg;
process(a)
begin
q0_reg <= rom_data_byte0(to_integer(a));
q1_reg <= rom_data_byte1(to_integer(a));
end process;
end architecture;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then b <= '0';
elsif c = '1' then b <= '1';
else
if x = '1' then z <= '0';
elsif x = '0' then z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PISO is
port (
Pattern : in std_logic_vector(7 downto 0);
DataIn : in std_logic;
Load : in std_logic;
Reset : in std_logic;
Clk : in std_logic;
Found : out std_logic
);
end entity; --PISO
architecture synth of piso is
signal content : std_logic_vector(7 downto 0);
signal reg_pattern : std_logic_vector(7 downto 0);
begin
load : process(Clk, Load, DataIn)
begin
if rising_edge(Clk) then
if Reset = '1' then
reg_pattern <= (others => '0')
elsif Load = '1' then
reg_pattern <= Pattern;
end if;
end if;
end process;
input_handle : process(Clk, Pattern)
begin
if rising_edge(Clk) then
content <= content(7 downto 1) & DataIn;
end if;
end process;
Found <= '1' when content = reg_pattern else '0';
end architecture ; -- synth |
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 8x1
entity mux8x1 is
port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7: in std_logic;
REG: out std_logic;
SW: in std_logic_vector(2 downto 0)
);
end mux8x1;
--Definicao Arquitetura
architecture circuito of mux8x1 is
begin
REG <= IN0 when SW = "000" else
IN1 when SW = "001" else
IN2 when SW = "010" else
IN3 when SW = "011" else
IN4 when SW = "100" else
IN5 when SW = "101" else
IN6 when SW = "110" else
IN7;
end circuito; |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity mblite_wrapper is
generic (
g_icache : boolean := true;
g_dcache : boolean := true;
g_tag_i : std_logic_vector(7 downto 0) := X"20";
g_tag_d : std_logic_vector(7 downto 0) := X"21" );
port (
clock : in std_logic;
reset : in std_logic;
mb_reset : in std_logic;
irq_i : in std_logic := '0';
irq_o : out std_logic;
disable_i : in std_logic := '0';
disable_d : in std_logic := '0';
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
io_req : out t_io_req;
io_resp : in t_io_resp;
io_busy : out std_logic;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture arch of mblite_wrapper is
signal reset_i : std_logic;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal imem_o : dmem_out_type;
signal imem_i : dmem_in_type;
signal dmem_req : t_mem_req_32;
signal dmem_resp : t_mem_resp_32;
signal imem_req : t_mem_req_32;
signal imem_resp : t_mem_resp_32;
begin
reset_i <= mb_reset or reset when rising_edge(clock);
i_proc: entity mblite.cached_mblite
generic map (
g_icache => g_icache,
g_dcache => g_dcache )
port map (
clock => clock,
reset => reset_i,
disable_i => disable_i,
disable_d => disable_d,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_o => dmem_o,
dmem_i => dmem_i,
imem_o => imem_o,
imem_i => imem_i,
irq_i => irq_i,
irq_o => irq_o );
i_imem: entity work.dmem_splitter
generic map (
g_tag => g_tag_i,
g_support_io => false )
port map (
clock => clock,
reset => reset_i,
dmem_i => imem_i,
dmem_o => imem_o,
mem_req => imem_req,
mem_resp => imem_resp,
io_req => open,
io_resp => c_io_resp_init );
i_dmem: entity work.dmem_splitter
generic map (
g_tag => g_tag_d,
g_support_io => true )
port map (
clock => clock,
reset => reset_i,
dmem_i => dmem_i,
dmem_o => dmem_o,
mem_req => dmem_req,
mem_resp => dmem_resp,
io_busy => io_busy,
io_req => io_req,
io_resp => io_resp );
i_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_registered => false,
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => imem_req,
reqs(1) => dmem_req,
resps(0) => imem_resp,
resps(1) => dmem_resp,
req => mem_req,
resp => mem_resp );
end arch;
|
----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : With this example it is possible to generate
-- control-commands for the LCD-Display by using
-- switch 0 to 7. The command is send by pressing
-- key 0.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_WAIT_KEY_PRESS, S_SEND_DATA, S_WAIT_KEY_RELEASE);
signal state, state_nxt : state_t;
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state <= S_WAIT_KEY_PRESS;
elsif rising_edge(clock) then
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, lcd_irq_rdy, key, switch)
begin
-- set default values for the internal bus -> zero on all signals means, nothing will happen
lcd_cs <= '0';
lcd_wr <= '0';
lcd_dout <= (others => '0');
lcd_addr <= (others => '0');
lcd_ack_rdy <= '0';
-- hold previous values of all registers
state_nxt <= state;
case state is
-- Wait until KEY0 is triggered
when S_WAIT_KEY_PRESS =>
if key(0) = '1' then
-- next state
state_nxt <= S_SEND_DATA;
end if;
-- Read value from ADC and save it into the led_out-register
when S_SEND_DATA =>
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Enable the Write-Select signal
lcd_wr <= '1';
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Take the new data from the first eight switches (SW0 to SW7)
lcd_dout(7 downto 0) <= switch(7 downto 0);
-- next state
state_nxt <= S_WAIT_KEY_RELEASE;
end if;
-- Wait until KEY0 is released
when S_WAIT_KEY_RELEASE =>
if key(0) = '0' then
-- next state
state_nxt <= S_WAIT_KEY_PRESS;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc617.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00617ent IS
END c03s04b01x00p01n01i00617ent;
ARCHITECTURE c03s04b01x00p01n01i00617arch OF c03s04b01x00p01n01i00617ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open write_mode is "iofile.31";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00617 - The output file will be verified by test s010262.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00617arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc617.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00617ent IS
END c03s04b01x00p01n01i00617ent;
ARCHITECTURE c03s04b01x00p01n01i00617arch OF c03s04b01x00p01n01i00617ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open write_mode is "iofile.31";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00617 - The output file will be verified by test s010262.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00617arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc617.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00617ent IS
END c03s04b01x00p01n01i00617ent;
ARCHITECTURE c03s04b01x00p01n01i00617arch OF c03s04b01x00p01n01i00617ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open write_mode is "iofile.31";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00617 - The output file will be verified by test s010262.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00617arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- -------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- ATTENSION:
-- The parameter 'constant INIT' of some functions is actually the reset
-- value, not the initial value after device programming (e.g. for FPGAs),
-- this value MUST be set via signal declaration!
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
package components is
-- implement an optional register stage
function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean;
-- FlipFlop functions
-- ===========================================================================
-- RS-FlipFlops
function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant rst
function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant set
-- D-FlipFlops (Delay)
function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable
function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable
function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable
-- T-FlipFlops (Toggle)
function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable
function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- T-FlipFlop with set and enable
-- counter
function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned;
function upcounter_equal(cnt : unsigned; value : natural) return std_logic;
function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed;
function downcounter_equal(cnt : signed; value : integer) return std_logic;
function downcounter_neg(cnt : signed) return std_logic;
-- shiftregisters
function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
-- rotate registers
function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
-- compare
function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector;
function comp(value1 : unsigned; value2 : unsigned) return unsigned;
function comp(value1 : signed; value2 : signed) return signed;
function comp_allzero(value : std_logic_vector) return std_logic;
function comp_allzero(value : unsigned) return std_logic;
function comp_allzero(value : signed) return std_logic;
function comp_allone(value : std_logic_vector) return std_logic;
function comp_allone(value : unsigned) return std_logic;
function comp_allone(value : signed) return std_logic;
-- multiplexing
function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic;
function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector;
function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned;
function mux(sel : std_logic; s0 : signed; s1 : signed) return signed;
end package;
package body components is
-- implement an optional register stage
-- ===========================================================================
function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean is
begin
return ite(IsRegistered, rising_edge(Clock), TRUE);
end function;
-- FlipFlops
-- ===========================================================================
-- D-flipflop with reset and enable
function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is
begin
if not SIMULATION then
if (INIT = '0') then
return ((d and en) or (q and not en)) and not rst;
elsif (INIT = '1') then
return ((d and en) or (q and not en)) or rst;
else
report "Unsupported INIT value for synthesis." severity FAILURE;
return 'X';
end if;
elsif (rst = '1') then
return INIT;
else
return ((d and en) or (q and not en));
end if;
end function;
function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector is
constant INIT_I : std_logic_vector(q'range) := resize(INIT, q'length);
variable Result : std_logic_vector(q'range);
begin
for i in q'range loop
Result(i) := ffdre(q => q(i), d => d(i), rst => rst, en => en, INIT => INIT_I(i));
end loop;
return Result;
end function;
-- D-flipflop with set and enable
function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is
begin
return ffdre(q => q, d => d, rst => set, en => en, INIT => '1');
end function;
-- T-flipflop with reset and enable
function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is
begin
if not SIMULATION then
if (INIT = '0') then
return ((not q and (t and en)) or (q and not (t and en))) and not rst;
elsif (INIT = '1') then
return ((not q and (t and en)) or (q and not (t and en))) or rst;
else
report "Unsupported INIT value for synthesis." severity FAILURE;
return 'X';
end if;
elsif (rst = '1') then
return INIT;
else
return ((not q and (t and en)) or (q and not (t and en)));
end if;
end function;
-- T-flipflop with set and enable
function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is
begin
return fftre(q => q, t => t, rst => set, en => en, INIT => '1');
end function;
-- RS-flipflop with dominant rst
function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is
begin
return (q or set) and not rst;
end function;
-- RS-flipflop with dominant set
function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is
begin
return (q and not rst) or set;
end function;
-- Counters
-- ===========================================================================
-- up-counter
function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned is
begin
if (rst = '1') then
return to_unsigned(INIT, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : unsigned; value : natural) return std_logic is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
-- down-counter
function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed is
begin
if (rst = '1') then
return to_signed(INIT, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : signed; value : integer) return std_logic is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : signed) return std_logic is
begin
return cnt(cnt'high);
end function;
-- Shift/Rotate Registers
-- ===========================================================================
function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'left - 1 downto q'right) & i);
end function;
function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, i & q(q'left downto q'right - 1));
end function;
function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'left - 1 downto q'right) & q(q'left));
end function;
function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'right) & q(q'left downto q'right - 1));
end function;
-- compare functions
-- ===========================================================================
-- Returns, when
-- 1- => value1 < value2 (difference is negative)
-- 00 => value1 = value2 (difference is zero)
-- -1 => value1 > value2 (difference is positive)
function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : unsigned; value2 : unsigned) return unsigned is
begin
if value1 < value2 then
return "10";
elsif value1 = value2 then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : signed; value2 : signed) return signed is
begin
if value1 < value2 then
return "10";
elsif value1 = value2 then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : std_logic_vector) return std_logic is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : unsigned) return std_logic is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : signed) return std_logic is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : std_logic_vector) return std_logic is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : unsigned) return std_logic is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : signed) return std_logic is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexers
function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : std_logic; s0 : signed; s1 : signed) return signed is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc536.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00536ent IS
port (a,b: in integer; c,d: out integer);
END c03s03b00x00p05n02i00536ent;
ARCHITECTURE c03s03b00x00p05n02i00536arch OF c03s03b00x00p05n02i00536ent IS
type typer is array (integer range <>) of integer;
subtype suber is typer (1 to 10);
type arst is access typer;
BEGIN
TESTING: PROCESS
variable correct : boolean;
variable varst : arst;
BEGIN
varst := new typer (1 to 10);
varst(1) := 1;
varst(2) := 2;
varst(12) := 3; -- illegal (LRM 3.3)
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c03s03b00x00p05n02i00536 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00536arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc536.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00536ent IS
port (a,b: in integer; c,d: out integer);
END c03s03b00x00p05n02i00536ent;
ARCHITECTURE c03s03b00x00p05n02i00536arch OF c03s03b00x00p05n02i00536ent IS
type typer is array (integer range <>) of integer;
subtype suber is typer (1 to 10);
type arst is access typer;
BEGIN
TESTING: PROCESS
variable correct : boolean;
variable varst : arst;
BEGIN
varst := new typer (1 to 10);
varst(1) := 1;
varst(2) := 2;
varst(12) := 3; -- illegal (LRM 3.3)
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c03s03b00x00p05n02i00536 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00536arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc536.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00536ent IS
port (a,b: in integer; c,d: out integer);
END c03s03b00x00p05n02i00536ent;
ARCHITECTURE c03s03b00x00p05n02i00536arch OF c03s03b00x00p05n02i00536ent IS
type typer is array (integer range <>) of integer;
subtype suber is typer (1 to 10);
type arst is access typer;
BEGIN
TESTING: PROCESS
variable correct : boolean;
variable varst : arst;
BEGIN
varst := new typer (1 to 10);
varst(1) := 1;
varst(2) := 2;
varst(12) := 3; -- illegal (LRM 3.3)
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c03s03b00x00p05n02i00536 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00536arch;
|
entity FIFO IS
end entity;
entity FIFO IS
end entity;
entity FIFO IS
end entity;
|
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_sr.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-15
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display shift register
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-15 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity disp_sr is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end disp_sr;
architecture rtl of disp_sr is
signal trig : std_logic;
signal trig_arm : std_logic;
SIGNAL bit_sr : std_logic_vector(255 downto 0);
SIGNAL bit_cnt : std_logic_vector(8 downto 0);
signal finish : std_logic;
signal lat : std_logic;
signal sclk : std_logic;
signal sin : std_logic;
begin
--
-- __
-- disp_lat ____| |_____________ ______________________
-- _______ _____ _____ _ __ _____ _____ _______
-- disp_sin _______X_____X_____X_ __X_____X_____X_______
-- __ __ __ __ __
-- disp_sclk __________| |__| |_ |__| |__| |_______
--
-- Bit 255 254 .. 1 0
--
-- Start triggering
disp_trig:
process (rst_n, clk) is
begin
if (rst_n = '0') then
trig <= '0';
trig_arm <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
trig_arm <= '1';
elsif (tsc_1ppus = '1') then
trig_arm <= '0';
end if;
if (tsc_1ppus = '1' and trig_arm = '1') then
trig <= '1';
elsif (finish = '1') then
trig <= '0';
end if;
end if;
end process;
-- bit counter
disp_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_cnt <= (others => '0');
finish <= '0';
elsif (clk'event and clk = '1') then
if (trig = '0') then
bit_cnt <= (others => '0');
elsif (tsc_1ppus = '1' and trig = '1') then
bit_cnt <= bit_cnt + 1;
end if;
if (tsc_1ppus = '1' and bit_cnt = 511) then
finish <= '1';
else
finish <= '0';
end if;
end if;
end process;
-- Generate DISP control signals
disp_shift:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_sr <= (others => '0');
bit_sr( 7 downto 0) <= x"1c";
bit_sr(15 downto 8) <= x"ce";
bit_sr(23 downto 16) <= x"bc";
lat <= '0';
sclk <= '0';
sin <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
bit_sr <= disp_data;
elsif (tsc_1ppus = '1' and bit_cnt(0) = '1') then
bit_sr <= bit_sr(bit_sr'left - 1 downto 0) & '0';
end if;
if (tsc_1ppus = '1') then
lat <= trig_arm;
sclk <= bit_cnt(0);
sin <= bit_sr(bit_sr'left);
end if;
end if;
end process;
-- Final output register
disp_olat: delay_sig generic map (1) port map (rst_n, clk, lat, disp_lat);
disp_osclk: delay_sig generic map (1) port map (rst_n, clk, sclk, disp_sclk);
disp_osin: delay_sig generic map (1) port map (rst_n, clk, sin, disp_sin);
end rtl;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
-- clkin1_buf : IBUFG
-- port map
-- (O => clkin1,
-- I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_100,--clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
-- clkin1_buf : IBUFG
-- port map
-- (O => clkin1,
-- I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_100,--clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
-- clkin1_buf : IBUFG
-- port map
-- (O => clkin1,
-- I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_100,--clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
entity aes_encrypt_unit_tb is
end aes_encrypt_unit_tb;
architecture tb of aes_encrypt_unit_tb is
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal key_in : std_logic_vector(127 downto 0);
signal key_wren : std_logic;
signal ready : std_logic;
signal data_in : std_logic_vector(127 downto 0);
signal data_wren : std_logic;
signal data_dv : std_logic;
signal data_out : std_logic_vector(127 downto 0);
begin
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
CRYPT0: aes_encrypt_unit
port map (
key_in => key_in,
key_wren => key_wren,
ready => ready,
data_in => data_in,
data_wren => data_wren,
data_dv => data_dv,
data_out => data_out,
clk => clk,
reset => reset);
TESTBENCH: process
begin
reset <= '1';
data_in <= (others => '0');
key_in <= (others => '0');
data_wren <= '0';
key_wren <= '0';
wait for 50 ns;
reset <= '0';
wait for 20 ns;
key_in <= X"2b7e151628aed2a6abf7158809cf4f3c";
key_wren <= '1';
wait for 10 ns;
key_wren <= '0';
wait until ready='1';
wait for 40 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
data_wren <= '1';
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_wren <= '0';
data_in <= (others => '0');
wait until data_dv='1';
wait;
end process TESTBENCH;
end tb;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 4K program for KCPSM6 in a Virtex-6 device using
2 x RAMB36E1 primitives.
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG363.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 4K program for KCPSM6 in a Virtex-6 device using
-- 2 x RAMB36E1 primitives.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_V6_4K_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
--
begin
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
--
address_b <= "1111111111111111";
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
enable_b <= '0';
we_b <= "00000000";
clk_b <= '0';
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $
--
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.3; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
-- since ibus V2 update, never tested afterwards...
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_renb : integer := 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pbuf_ibf_pval : integer := 8;
constant pbuf_ibf_rbusy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0', -- rintreq
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibreq = '1' then -- !! PC11 is unusual !!
n.rdone := '0'; -- *any* read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then
n.rintreq := '1';
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_rbusy) := r.rbusy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
|
--
-- Boundary Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
use FPGALIB.Sync.all;
entity Boundary_Tb is
end entity Boundary_Tb;
architecture Test of Boundary_Tb is
constant FREQUENCY : positive:=150e6;
signal clk, rst : std_logic;
signal stop : boolean;
-- dut
constant PATTERN : std_logic_vector(3 downto 0):="1111";
type comma_t is array(0 to 23) of std_logic_vector (3 downto 0);
signal comma_in : comma_t:=(
"0000", -- aligned
"0000", -- aligned
"0000", -- aligned
"1000", -- 3
"0111", -- 3
"0000", -- 3
"1100", -- 2
"0011", -- 2
"0000", -- 2
"0000", -- 2
"1110", -- 1
"0001", -- 1
"0000", -- 1
"0000", -- 1
"1111", -- aligned
"0000", -- aligned
"0110", -- aligned
"1001", -- aligned
"0100", -- aligned
"0100", -- aligned
others => "0000"
);
signal index : natural:=0;
signal comma_aux, comma_out : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (31 downto 0);
begin
do_clk: Clock
generic map(FREQUENCY => FREQUENCY)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: Boundary
port map(
clk_i => clk,
pattern_i => PATTERN,
comma_i => comma_aux,
data_i => x"01234567",
comma_o => comma_out,
data_o => data_out
);
feeder: process
begin
wait until rising_edge(clk) and rst='0';
for i in 0 to 20 loop
comma_aux <= comma_in(i);
wait until rising_edge(clk);
end loop;
wait;
end process feeder;
checker: process
begin
wait until rising_edge(clk) and rst='0';
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"23456701";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"45670123";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"67012345";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"01234567";
stop <= TRUE;
wait;
end process checker;
end architecture Test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity multiplier_test is
end entity multiplier_test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity multiplier_test is
end entity multiplier_test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity multiplier_test is
end entity multiplier_test;
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions for CRC32/Ethernet frame check sequence calculation
library ieee;
use ieee.std_logic_1164.all;
use work.crc.all;
package crc32 is
-- As defined in IEEE 802.3 clause 3.2.9
-- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
constant CRC32_POLYNOMIAL : std_ulogic_vector(32 downto 0) := (
32 | 26 | 23 | 22 | 16 | 12 | 11 | 10 | 8 | 7 | 5 | 4 | 2 | 1 | 0 => '1',
others => '0'
);
-- CRC32 value type
subtype t_crc32 is std_ulogic_vector(31 downto 0);
-- Value that remains as CRC value when incoming data including the original FCS is piped through update_crc32
-- and the FCS is correct.
-- Usually this would be zero, but the inversion of the FCS in clause 3.2.9 e changes it to this magic value.
constant CRC32_POSTINVERT_MAGIC : t_crc32 := X"C704DD7B";
-- Update CRC32 old_crc by one bit (input)
function update_crc32(old_crc : t_crc32; input : std_ulogic) return t_crc32;
-- Update CRC32 old_crc by an arbitrary number of bits (input)
function update_crc32(old_crc : t_crc32; input : std_ulogic_vector) return t_crc32;
constant CRC32_BYTES : positive := (t_crc32'length / 8);
end package;
package body crc32 is
function update_crc32(old_crc : t_crc32; input : std_ulogic) return t_crc32 is
begin
return update_crc(old_crc, input, CRC32_POLYNOMIAL);
end function;
function update_crc32(old_crc : t_crc32; input : std_ulogic_vector) return t_crc32 is
begin
return update_crc(old_crc, input, CRC32_POLYNOMIAL);
end function;
end package body;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_5_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_5_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_5_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_5_e
--
architecture rtl of inst_5_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
p1: process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
v(2) := s(3);
s <= v;
v := s;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package packagefa00 is
component or00
port(
Ao: in std_logic ;
Bo: in std_logic ;
Yo: out std_logic );
end component;
component topha00
port(
A0: in std_logic ;
B0: in std_logic ;
S0: out std_logic ;
C0: out std_logic );
end component;
end packagefa00;
|
entity bot is
end entity;
architecture test of bot is
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename1 is
end entity;
architecture test of ename1 is
begin
uut: entity work.bot;
p2: process is
begin
assert <<signal uut.x : natural>> = 0;
wait for 1 ns;
<<signal uut.y : natural>> <= force 5;
wait for 0 ns;
assert <<signal uut.x : natural>> = 5;
wait for 0 ns;
assert <<signal .ename1.uut.x : natural>> = 10;
<<signal uut.y : natural>> <= release;
wait for 1 ns;
assert <<signal .ename1.uut.x : natural>> = 5;
wait for 10 ns;
assert <<signal .ename1.uut.x : natural>> = 25;
wait;
end process;
p3: process is
alias y is <<signal uut.y : natural>>;
begin
y <= 0;
wait for 10 ns;
y <= 20;
wait;
end process;
end architecture;
|
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity gmem_atomics is
port( -- {{{
rcv_atomic_type : in be_array(N_RECEIVERS-1 downto 0);
rcv_atomic_rqst : in std_logic_vector(N_RECEIVERS-1 downto 0);
rcv_gmem_addr : in gmem_word_addr_array(N_RECEIVERS-1 downto 0);
rcv_gmem_data : in SLV32_ARRAY(N_RECEIVERS-1 downto 0) := (others=>(others=>'0'));
rcv_must_read : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0');
rcv_atomic_ack : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0');
-- read data path (in)
gmem_rdAddr_p0 : in unsigned(GMEM_WORD_ADDR_W-N-1 downto 0);
gmem_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0);
gmem_rdData_v_p0 : in std_logic := '0';
-- atomic data path (out)
atomic_rdData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
rcv_retire : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- this signals implies the validety of atomic_rdData
-- it is 2 clock cycles in advance
-- atomic flushing
flush_v : out std_logic := '0';
flush_gmem_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
flush_data : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
flush_ack : in std_logic;
flush_done : in std_logic;
finish : in std_logic;
atomic_can_finish : out std_logic := '0';
WGsDispatched : in std_logic;
clk, nrst : std_logic
); -- }}}
end entity;
architecture basic of gmem_atomics is
-- general control signals {{{
signal rcv_slctd_indx : integer range 0 to N_RECEIVERS := 0;
attribute max_fanout of rcv_slctd_indx : signal is 60;
signal rcv_slctd_indx_d0 : integer range 0 to N_RECEIVERS := 0;
attribute max_fanout of rcv_slctd_indx_d0 : signal is 40;
signal check_rqst, check_rqst_d0 : std_logic := '0';
signal rqst_type : std_logic_vector(2 downto 0) := (others=>'0');
attribute max_fanout of rqst_type : signal is 60;
signal rqst_val : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal rqst_gmem_addr : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
type atomic_unit_state is (idle, listening, latch_gmem_data, select_word, functioning);
signal rcv_half_select : std_logic := '0';
signal rcv_is_reading : std_logic := '0';
-- }}}
-- atomic max signals -----------------------------------------------------------------------------------{{{
signal st_amax, st_amax_n : atomic_unit_state := idle;
signal amax_gmem_addr, amax_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
signal amax_data, amax_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal amax_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal amax_addr_v, amax_addr_v_n : std_logic := '0';
signal amax_addr_v_d0 : std_logic := '0';
signal amax_exec, amax_exec_d0 : std_logic := '0';
signal amax_latch_gmem_rdData : std_logic := '0';
signal amax_latch_gmem_rdData_n : std_logic := '0';
---------------------------------------------------------------------------------------------------------}}}
-- atomic add signals -----------------------------------------------------------------------------------{{{
signal st_aadd, st_aadd_n : atomic_unit_state := idle;
signal aadd_gmem_addr, aadd_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
signal aadd_data, aadd_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal aadd_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal gmem_rdData_ltchd : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0);
signal aadd_latch_gmem_rdData : std_logic := '0';
signal aadd_latch_gmem_rdData_n : std_logic := '0';
signal aadd_addr_v, aadd_addr_v_n : std_logic := '0';
signal aadd_addr_v_d0 : std_logic := '0';
signal aadd_exec, aadd_exec_d0 : std_logic := '0';
---------------------------------------------------------------------------------------------------------}}}
-- flushing aadd results --------------------------------------------------------------------------------{{{
type flush_state_type is (idle, dirty, flushing, wait_flush_done);
signal st_aadd_flush, st_aadd_flush_n : flush_state_type := idle;
constant FLUSH_TIMER_W : integer := 3;
signal aadd_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0');
signal aadd_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0');
signal aadd_flush_rqst : std_logic := '0';
signal aadd_flush_rqst_n : std_logic := '0';
signal aadd_flush_started : std_logic := '0';
signal aadd_flush_done : std_logic := '0';
signal flush_ack_d0 : std_logic := '0';
signal aadd_dirty_content : std_logic := '0';
signal aadd_dirty_content_n : std_logic := '0';
signal WGsDispatched_ltchd : std_logic := '0';
signal aadd_flush_active : std_logic := '0';
---------------------------------------------------------------------------------------------------------}}}
-- flushing amax results --------------------------------------------------------------------------------{{{
signal st_amax_flush, st_amax_flush_n : flush_state_type := idle;
signal amax_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0');
signal amax_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0');
signal amax_flush_rqst : std_logic := '0';
signal amax_flush_rqst_n : std_logic := '0';
signal amax_flush_started : std_logic := '0';
signal amax_flush_done : std_logic := '0';
signal amax_dirty_content : std_logic := '0';
signal amax_dirty_content_n : std_logic := '0';
signal amax_flush_active : std_logic := '0';
---------------------------------------------------------------------------------------------------------}}}
begin
-- TODO: implement atomic address changing. Now only one address can be used by an atomic unit
-- TODO: consider the case when two atomic units work on the same global address
-- asserts & internals ----------------------------------------------------------------------------------{{{
assert FLUSH_TIMER_W < 4 report "make FLUSH_TIMER_W less than 4 otherwise FGPU will finish while there is dirty data in the atomic units";
---------------------------------------------------------------------------------------------------------}}}
-- receivers interface ----------------------------------------------------------------------------------{{{
RCV_INTERFACE: if AADD_ATOMIC = 1 or AMAX_ATOMIC = 1 generate
process(clk)
variable rcv_slctd_indx_unsigned : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0');
begin
if rising_edge(clk) then
rcv_half_select <= not rcv_half_select;
-- stage 0:
-- select requesting receiver
check_rqst <= '0';
rcv_atomic_ack <= (others=>'0');
for i in N_RECEIVERS/2-1 downto 0 loop
rcv_slctd_indx_unsigned(N_RECEIVERS_W-1 downto 1) := to_unsigned(i, N_RECEIVERS_W-1);
rcv_slctd_indx_unsigned(0) := rcv_half_select;
if rcv_atomic_rqst(to_integer(rcv_slctd_indx_unsigned)) = '1' then
rcv_slctd_indx <= to_integer(rcv_slctd_indx_unsigned);
rcv_atomic_ack(to_integer(rcv_slctd_indx_unsigned)) <= '1';
-- assert(rcv_atomic_type(i) = CODE_AADD(2 downto 0));
check_rqst <= '1';
exit;
end if;
end loop;
-- stage 1:
-- latch request
rqst_type <= rcv_atomic_type(rcv_slctd_indx)(2 downto 0);
rqst_gmem_addr <= rcv_gmem_addr(rcv_slctd_indx);
check_rqst_d0 <= check_rqst;
rcv_slctd_indx_d0 <= rcv_slctd_indx;
-- stage 2:
-- check validety
rcv_must_read <= (others=>'0');
rcv_retire <= (others=>'0');
aadd_exec <= '0';
amax_exec <= '0';
if check_rqst_d0 = '1' then
case rqst_type is
when CODE_AADD(2 downto 0) =>
if aadd_addr_v = '0' or aadd_gmem_addr /= rqst_gmem_addr then
if rcv_is_reading = '0' then
rcv_must_read(rcv_slctd_indx_d0) <= '1';
rcv_is_reading <= '1';
end if;
else
rcv_retire(rcv_slctd_indx_d0) <= '1';
aadd_exec <= '1';
end if;
when CODE_AMAX(2 downto 0) =>
if amax_addr_v = '0' or amax_gmem_addr /= rqst_gmem_addr then
if rcv_is_reading = '0' then
rcv_must_read(rcv_slctd_indx_d0) <= '1';
rcv_is_reading <= '1';
end if;
else
rcv_retire(rcv_slctd_indx_d0) <= '1';
amax_exec <= '1';
end if;
when others =>
assert(false);
end case;
end if;
rqst_val <= unsigned(rcv_gmem_data(rcv_slctd_indx_d0));
-- stage3:
-- wait for result
aadd_exec_d0 <= aadd_exec;
amax_exec_d0 <= amax_exec;
--stage 4:
-- forward result
if aadd_exec_d0 = '1' then
atomic_rdData <= std_logic_vector(aadd_data_d0);
-- if _d0 is removed then the atomic will giv back the new result instead of the old one
else -- if amax_exec_d0 = '1'
atomic_rdData <= std_logic_vector(amax_data_d0);
end if;
-- atomic_rdAddr <= aadd_gmem_addr; -- no need for the performed atomic address; it is included in the signature
-- atomic_rdData_type <= CODE_AADD(2 downto 0); -- no need to send the atomic type back; it is included in the signature
-- other tasks
if (aadd_addr_v = '1' and aadd_addr_v_d0 = '0') or (amax_addr_v = '1' and amax_addr_v_d0 = '0') then
rcv_is_reading <= '0';
end if;
if aadd_latch_gmem_rdData = '1' or amax_latch_gmem_rdData = '1' then
gmem_rdData_ltchd <= gmem_rdData;
end if;
end if;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- flushing amax ----------------------------------------------------------------------------------------{{{
AMAX_FLUSHING: if AMAX_ATOMIC = 1 generate
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
st_amax_flush <= idle;
amax_flush_rqst <= '0';
amax_dirty_content <= '0';
else
st_amax_flush <= st_amax_flush_n;
amax_flush_rqst <= amax_flush_rqst_n;
amax_dirty_content <= amax_dirty_content_n;
end if;
amax_flush_timer <= amax_flush_timer_n;
end if;
end process;
process(st_amax_flush, amax_exec, amax_flush_timer, amax_flush_rqst, amax_flush_started, flush_done, amax_dirty_content,
WGsDispatched_ltchd)
begin
st_amax_flush_n <= st_amax_flush;
amax_flush_timer_n <= amax_flush_timer;
amax_flush_rqst_n <= amax_flush_rqst;
amax_dirty_content_n <= amax_dirty_content;
case st_amax_flush is
when idle =>
amax_flush_timer_n <= (others=>'0');
if amax_exec = '1' or amax_dirty_content = '1' then
st_amax_flush_n <= dirty;
end if;
when dirty =>
if WGsDispatched_ltchd = '1' then
amax_flush_timer_n <= amax_flush_timer + 1;
if amax_exec = '1' then
amax_flush_timer_n <= (others=>'0');
elsif amax_flush_timer = (amax_flush_timer'reverse_range =>'1') then
st_amax_flush_n <= flushing;
amax_flush_rqst_n <= '1';
amax_dirty_content_n <= '0';
end if;
end if;
when flushing =>
if amax_exec = '1' then
amax_dirty_content_n <= '1';
end if;
if amax_flush_started = '1' then
st_amax_flush_n <= wait_flush_done;
amax_flush_rqst_n <= '0';
end if;
when wait_flush_done =>
if flush_done = '1' then
st_amax_flush_n <= idle;
end if;
if amax_exec = '1' then
amax_dirty_content_n <= '1';
end if;
end case;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- flushing aadd ----------------------------------------------------------------------------------------{{{
AADD_FLUSH: if AADD_ATOMIC = 1 generate
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
st_aadd_flush <= idle;
aadd_flush_rqst <= '0';
aadd_dirty_content <= '0';
else
st_aadd_flush <= st_aadd_flush_n;
aadd_flush_rqst <= aadd_flush_rqst_n;
aadd_dirty_content <= aadd_dirty_content_n;
end if;
aadd_flush_timer <= aadd_flush_timer_n;
end if;
end process;
process(st_aadd_flush, aadd_exec, aadd_flush_timer, aadd_flush_rqst, aadd_flush_started, flush_done, aadd_dirty_content,
WGsDispatched_ltchd)
begin
st_aadd_flush_n <= st_aadd_flush;
aadd_flush_timer_n <= aadd_flush_timer;
aadd_flush_rqst_n <= aadd_flush_rqst;
aadd_dirty_content_n <= aadd_dirty_content;
case st_aadd_flush is
when idle =>
aadd_flush_timer_n <= (others=>'0');
if aadd_exec = '1' or aadd_dirty_content = '1' then
st_aadd_flush_n <= dirty;
end if;
when dirty =>
if WGsDispatched_ltchd = '1' then
aadd_flush_timer_n <= aadd_flush_timer + 1;
if aadd_exec = '1' then
aadd_flush_timer_n <= (others=>'0');
elsif aadd_flush_timer = (aadd_flush_timer'reverse_range =>'1') then
st_aadd_flush_n <= flushing;
aadd_flush_rqst_n <= '1';
aadd_dirty_content_n <= '0';
end if;
end if;
when flushing =>
if aadd_exec = '1' then
aadd_dirty_content_n <= '1';
end if;
if aadd_flush_started = '1' then
st_aadd_flush_n <= wait_flush_done;
aadd_flush_rqst_n <= '0';
end if;
when wait_flush_done =>
if flush_done = '1' then
st_aadd_flush_n <= idle;
end if;
if aadd_exec = '1' then
aadd_dirty_content_n <= '1';
end if;
end case;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- atomic max -------------------------------------------------------------------------------------------{{{
AMAX_BODY: if AMAX_ATOMIC = 1 generate
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
amax_addr_v <= '0';
st_amax <= idle;
else
st_amax <= st_amax_n;
amax_addr_v <= amax_addr_v_n;
end if;
amax_addr_v_d0 <= amax_addr_v;
amax_gmem_addr <= amax_gmem_addr_n;
amax_data <= amax_data_n;
amax_data_d0 <= amax_data;
amax_latch_gmem_rdData <= amax_latch_gmem_rdData_n;
end if;
end process;
process(st_amax, check_rqst_d0, rqst_type, amax_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, amax_data, gmem_rdData_ltchd,
amax_addr_v, amax_exec, rqst_val, finish)
variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0;
-- variable n_amax_exec : integer := 0;
-- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0');
-- variable written_index : integer range 0 to 2047 := 0;
begin
st_amax_n <= st_amax;
amax_gmem_addr_n <= amax_gmem_addr;
amax_data_n <= amax_data;
amax_addr_v_n <= amax_addr_v;
amax_latch_gmem_rdData_n <= '0';
case st_amax is
when idle =>
if check_rqst_d0 = '1' and rqst_type = CODE_AMAX(2 downto 0) then
st_amax_n <= listening;
amax_gmem_addr_n <= rqst_gmem_addr;
end if;
when listening =>
if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = amax_gmem_addr(amax_gmem_addr'high downto N) then
st_amax_n <= latch_gmem_data;
amax_latch_gmem_rdData_n <= '1';
end if;
when latch_gmem_data =>
st_amax_n <= select_word;
when select_word =>
word_indx := to_integer(amax_gmem_addr(N-1 downto 0));
amax_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx));
st_amax_n <= functioning;
amax_addr_v_n <= '1';
when functioning =>
if amax_exec = '1' then
-- n_amax_exec := n_amax_exec + 1;
if signed(amax_data) < signed(rqst_val) then
amax_data_n <= rqst_val;
end if;
-- written_index := ((to_integer(rqst_val)-6) / 16);
-- assert written_index < 2048 severity failure;
-- assert written_vals(written_index) = '0' severity failure;
-- written_vals(written_index) := '1';
-- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure;
end if;
if finish = '1' then
-- assert written_vals = (written_vals'reverse_range=>'1') severity failure;
-- written_vals := (others=>'0');
-- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_amax_exec);
-- n_amax_exec := 0;
st_amax_n <= idle;
amax_addr_v_n <= '0';
end if;
end case;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- atomic add -------------------------------------------------------------------------------------------{{{
AADD_BODY: if AADD_ATOMIC = 1 generate
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
aadd_addr_v <= '0';
st_aadd <= idle;
else
st_aadd <= st_aadd_n;
aadd_addr_v <= aadd_addr_v_n;
end if;
aadd_addr_v_d0 <= aadd_addr_v;
aadd_gmem_addr <= aadd_gmem_addr_n;
aadd_data <= aadd_data_n;
aadd_data_d0 <= aadd_data;
aadd_latch_gmem_rdData <= aadd_latch_gmem_rdData_n;
end if;
end process;
process(st_aadd, check_rqst_d0, rqst_type, aadd_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, aadd_data, gmem_rdData_ltchd,
aadd_addr_v, aadd_exec, rqst_val, finish)
variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0;
-- variable n_aadd_exec : integer := 0;
-- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0');
-- variable written_index : integer range 0 to 2047 := 0;
begin
st_aadd_n <= st_aadd;
aadd_gmem_addr_n <= aadd_gmem_addr;
aadd_data_n <= aadd_data;
aadd_addr_v_n <= aadd_addr_v;
aadd_latch_gmem_rdData_n <= '0';
case st_aadd is
when idle =>
if check_rqst_d0 = '1' and rqst_type = CODE_AADD(2 downto 0) then
st_aadd_n <= listening;
aadd_gmem_addr_n <= rqst_gmem_addr;
end if;
when listening =>
if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = aadd_gmem_addr(aadd_gmem_addr'high downto N) then
st_aadd_n <= latch_gmem_data;
aadd_latch_gmem_rdData_n <= '1';
end if;
when latch_gmem_data =>
st_aadd_n <= select_word;
when select_word =>
word_indx := to_integer(aadd_gmem_addr(N-1 downto 0));
aadd_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx));
st_aadd_n <= functioning;
aadd_addr_v_n <= '1';
when functioning =>
if aadd_exec = '1' then
-- n_aadd_exec := n_aadd_exec + 1;
aadd_data_n <= aadd_data + rqst_val;
-- written_index := ((to_integer(rqst_val)-6) / 16);
-- assert written_index < 2048 severity failure;
-- assert written_vals(written_index) = '0' severity failure;
-- written_vals(written_index) := '1';
-- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure;
end if;
if finish = '1' then
-- assert written_vals = (written_vals'reverse_range=>'1') severity failure;
-- written_vals := (others=>'0');
-- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_aadd_exec);
-- n_aadd_exec := 0;
st_aadd_n <= idle;
aadd_addr_v_n <= '0';
end if;
end case;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- flushing ---------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
WGsDispatched_ltchd <= '0';
else
if finish = '1' then
WGsDispatched_ltchd <= '0';
elsif WGsDispatched = '1' then
WGsDispatched_ltchd <= '1';
end if;
end if;
atomic_can_finish <= '0';
if st_aadd_flush = idle and st_amax_flush = idle then
atomic_can_finish <= '1';
end if;
flush_v <= (aadd_flush_rqst or amax_flush_rqst) and not (flush_ack or flush_ack_d0);
flush_ack_d0 <= flush_ack;
aadd_flush_started <= '0';
amax_flush_started <= '0';
aadd_flush_active <= '0';
amax_flush_active <= '0';
if flush_ack = '0' then
if aadd_flush_rqst = '1' then
flush_gmem_addr <= aadd_gmem_addr;
flush_data <= std_logic_vector(aadd_data);
aadd_flush_active <= '1';
elsif amax_flush_rqst = '1' then
flush_gmem_addr <= amax_gmem_addr;
flush_data <= std_logic_vector(amax_data);
amax_flush_active <= '1';
end if;
else
if aadd_flush_active = '1' then
aadd_flush_started <= '1';
else -- amax_flush_active = '1'
amax_flush_started <= '1';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
end architecture;
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 44160)
`protect data_block
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`protect end_protected
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_rx_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
enable_dpa_mode : string := "OFF";
data_align_rollover: vl_notype;
lose_lock_on_one_change: string := "OFF";
reset_fifo_at_first_lock: string := "ON";
x_on_bitslip : string := "ON";
rx_align_data_reg: string := "RISING_EDGE";
enable_soft_cdr_mode: string := "OFF";
sim_dpa_output_clock_phase_shift: integer := 0;
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enable_dpa_initial_phase_selection: string := "OFF";
dpa_initial_phase_value: integer := 0;
registered_output: string := "ON";
use_external_pll: string := "OFF";
use_dpa_calibration: integer := 0;
enable_clock_pin_mode: string := "UNUSED";
ARRIAII_RX_STYLE: integer := 0;
STRATIXV_RX_STYLE: integer := 0;
REGISTER_WIDTH : vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_reset : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_enable : in vl_logic;
rx_dpll_reset : in vl_logic_vector;
rx_dpll_hold : in vl_logic_vector;
rx_dpll_enable : in vl_logic_vector;
rx_fifo_reset : in vl_logic_vector;
rx_channel_data_align: in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_out : out vl_logic_vector;
rx_dpa_locked : out vl_logic_vector;
rx_cda_max : out vl_logic_vector;
rx_divfwdclk : out vl_logic_vector;
rx_locked : in vl_logic;
rx_dpa_lock_reset: in vl_logic_vector;
rx_dpaclock : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1;
attribute mti_svvh_generic_type of data_align_rollover : constant is 3;
attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1;
attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1;
attribute mti_svvh_generic_type of x_on_bitslip : constant is 1;
attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1;
attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1;
attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of use_dpa_calibration : constant is 1;
attribute mti_svvh_generic_type of enable_clock_pin_mode : constant is 1;
attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 1;
attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
end stratixiii_lvds_rx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1267.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01267ent IS
END c08s02b00x00p07n01i01267ent;
ARCHITECTURE c08s02b00x00p07n01i01267arch OF c08s02b00x00p07n01i01267ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01267 - This test needs manual check. The assertion message consists at least that 1.An indication that this message is from an assertion. 2.Severity level. 3.Value of the message string. 4.The name of the design unit."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01267arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1267.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01267ent IS
END c08s02b00x00p07n01i01267ent;
ARCHITECTURE c08s02b00x00p07n01i01267arch OF c08s02b00x00p07n01i01267ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01267 - This test needs manual check. The assertion message consists at least that 1.An indication that this message is from an assertion. 2.Severity level. 3.Value of the message string. 4.The name of the design unit."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01267arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1267.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01267ent IS
END c08s02b00x00p07n01i01267ent;
ARCHITECTURE c08s02b00x00p07n01i01267arch OF c08s02b00x00p07n01i01267ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01267 - This test needs manual check. The assertion message consists at least that 1.An indication that this message is from an assertion. 2.Severity level. 3.Value of the message string. 4.The name of the design unit."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01267arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
immediate_data(0) <= x"00000000";
immediate_data(1) <= x"06666668";
immediate_data(2) <= x"08ccccd0";
immediate_data(3) <= x"00000001";
immediate_data(4) <= x"00000010";
immediate_data(5) <= x"00000002";
immediate_data(6) <= x"00000003";
immediate_data(7) <= x"000000ff";
immediate_data(8) <= x"40000000";
immediate_data(9) <= x"00000046";
instruction_data(1) <= "010100000001";
instruction_data(2) <= "010100000000";
instruction_data(3) <= "110001000000";
instruction_data(4) <= "010100000010";
instruction_data(5) <= "010100000011";
instruction_data(6) <= "110001000000";
instruction_data(7) <= "010100000010";
instruction_data(8) <= "010101000000";
instruction_data(9) <= "001011000000";
instruction_data(10) <= "010100000001";
instruction_data(11) <= "010101000000";
instruction_data(12) <= "001011000000";
instruction_data(13) <= "010100000010";
instruction_data(14) <= "010100000010";
instruction_data(15) <= "010100000001";
instruction_data(16) <= "001011000000";
instruction_data(17) <= "000111000000";
instruction_data(18) <= "000001000000";
instruction_data(19) <= "010010000000";
instruction_data(20) <= "010100000011";
instruction_data(21) <= "110000000000";
instruction_data(22) <= "010010000000";
instruction_data(23) <= "000010000000";
instruction_data(24) <= "000001000000";
instruction_data(25) <= "010001000000";
instruction_data(26) <= "010101000000";
instruction_data(27) <= "010101000000";
instruction_data(28) <= "001011000000";
instruction_data(29) <= "010101000000";
instruction_data(30) <= "010100000101";
instruction_data(31) <= "110001000000";
instruction_data(32) <= "010010000000";
instruction_data(33) <= "011010000000";
instruction_data(34) <= "010101000000";
instruction_data(35) <= "001011000000";
instruction_data(36) <= "010101000000";
instruction_data(37) <= "010100000101";
instruction_data(38) <= "110000000000";
instruction_data(39) <= "000001000000";
instruction_data(40) <= "010100000101";
instruction_data(41) <= "110001000000";
instruction_data(42) <= "010010000000";
instruction_data(43) <= "010001000000";
instruction_data(44) <= "010100000011";
instruction_data(45) <= "110000000000";
instruction_data(46) <= "010010000000";
instruction_data(47) <= "010100000110";
instruction_data(48) <= "110000000000";
instruction_data(49) <= "010100000011";
instruction_data(50) <= "000001000000";
instruction_data(51) <= "010100000111";
instruction_data(52) <= "000110000000";
instruction_data(53) <= "010000000000";
instruction_data(54) <= "010100000110";
instruction_data(55) <= "110001000000";
instruction_data(56) <= "010100000101";
instruction_data(57) <= "010100001001";
instruction_data(58) <= "100001000000";
instruction_data(59) <= "010100000101";
instruction_data(60) <= "110000000000";
instruction_data(61) <= "010100001000";
instruction_data(62) <= "000110000000";
instruction_data(63) <= "010000000000";
instruction_data(64) <= "010000000000";
instruction_data(65) <= "010100000110";
instruction_data(66) <= "010100001001";
instruction_data(67) <= "100001000000";
instruction_data(68) <= "010100000100";
instruction_data(69) <= "100000000000";
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
PORT(
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0); --ENTRADAS TOP
piso_actual: IN std_logic_vector(2 DOWNTO 0);
nivel, celula, abierto, cerrado: IN std_logic;
puerta, motor_subir, motor_bajar: OUT std_logic; --SALIDAS TOP
piso0_sel, piso1_sel, piso2_sel: OUT std_logic;
segmentos: OUT std_logic_vector(7 DOWNTO 0);
seg_ctrl: OUT std_logic_vector(3 DOWNTO 0);
clk: in std_logic; --clk:antes de entrar al divisorfrec
reset: in std_logic
);
end TOP;
architecture Behavioral of TOP is
COMPONENT convertidor_piso_actual
PORT(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
piso_actual: IN std_logic_vector(2 DOWNTO 0);
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0);
piso_actual_convertido: OUT std_logic_vector(1 DOWNTO 0);
boton_seleccionado_convertido: OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT divisorfrec
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida:out STD_LOGIC
);
END COMPONENT;
COMPONENT FSM
PORT(
clock,reset,nivel,abierto, cerrado: IN std_logic;
piso,boton :IN STD_LOGIC_VECTOR (1 DOWNTO 0);
boton_memoria: out STD_LOGIC_VECTOR (1 DOWNTO 0);
accionador_puerta: out STD_LOGIC;
accionador_subir, accionador_bajar: out STD_LOGIC
);
END COMPONENT;
COMPONENT gestor_display
PORT (
CLK : in STD_LOGIC;
piso_now : in STD_LOGIC_VECTOR (1 downto 0);
piso_obj : in STD_LOGIC_VECTOR (1 downto 0);
piso_seleccionado : out STD_LOGIC_VECTOR (1 downto 0);
piso_actual : out STD_LOGIC_VECTOR (1 downto 0);
accion : out STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
COMPONENT decoder
PORT (
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector(1 DOWNTO 0);
action : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0);
dig_ctrl : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT dec_piso_seleccion
PORT (
piso_code : in STD_LOGIC_VECTOR (1 downto 0);
piso0 : out STD_LOGIC;
piso1 : out STD_LOGIC;
piso2 : out STD_LOGIC
);
END COMPONENT;
COMPONENT motor_puerta
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
nivel : in STD_LOGIC;
celula : in STD_LOGIC;
accionar_puerta : in STD_LOGIC;
actuador_puerta : out STD_LOGIC
);
END COMPONENT;
COMPONENT motor_ascensor
PORT(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
accionar_bajar: in STD_LOGIC;
accionar_subir: in STD_LOGIC;
motor_subir: out STD_LOGIC;
motor_bajar : out STD_LOGIC
);
END COMPONENT;
signal sig_puerta:std_logic; --Senal para motor_puerta
signal sig_subir:std_logic; --Senal para motor_subir
signal sig_bajar:std_logic; --Senal para motor_bajar
signal inoutreloj:std_logic; --Senal del divisor de frecuencia
signal inoutpiso_actual:std_logic_vector (1 DOWNTO 0);
signal inoutpiso_deseado:std_logic_vector (1 DOWNTO 0);
signal sig_boton_pulsado:std_logic_vector (1 DOWNTO 0);
signal code_piso_actual:std_logic_vector (1 DOWNTO 0);
signal code_piso_objetivo:std_logic_vector (1 DOWNTO 0);
signal sig_action:std_logic_vector (1 DOWNTO 0);
begin
inst_convertidor_piso_actual:convertidor_piso_actual port map(
clk => clk,
rst => reset,
piso_actual => piso_actual,
boton_seleccionado => boton_seleccionado,
piso_actual_convertido => inoutpiso_actual,
boton_seleccionado_convertido => inoutpiso_deseado
);
inst_divisorfrec:divisorfrec port map(
clk => clk,
reset => reset,
salida => inoutreloj
);
inst_FSM:FSM port map(
abierto => abierto,
cerrado => cerrado,
clock => inoutreloj,
reset => reset,
nivel => nivel,
piso => inoutpiso_actual,
boton => inoutpiso_deseado,
boton_memoria => sig_boton_pulsado,
accionador_puerta => sig_puerta,
accionador_subir => sig_subir,
accionador_bajar => sig_bajar
);
inst_gestor_display:gestor_display port map(
CLK => inoutreloj,
piso_now => inoutpiso_actual,
piso_obj => sig_boton_pulsado,
piso_seleccionado => code_piso_objetivo,
piso_actual => code_piso_actual,
accion => sig_action
);
inst_decoder: decoder port map(
CLK => inoutreloj,
RST => reset,
code => code_piso_actual,
action => sig_action,
led => segmentos (7 downto 1),
dig_ctrl => seg_ctrl
);
segmentos(0) <= '1'; --punto decimal
inst_dec_piso_seleccion:dec_piso_seleccion port map(
piso_code => code_piso_objetivo,
piso0 => piso0_sel,
piso1 => piso1_sel,
piso2 => piso2_sel
);
inst_motor_puerta:motor_puerta port map(
CLK => clk,
RST => reset,
nivel => nivel,
celula => celula,
accionar_puerta => sig_puerta,
actuador_puerta => puerta
);
inst_motor_ascensor:motor_ascensor port map(
CLK => clk,
RST => reset,
accionar_bajar => sig_bajar,
accionar_subir => sig_subir,
motor_subir => motor_subir,
motor_bajar => motor_bajar
);
end Behavioral; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_eb_fifo_counted_resized_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_eb_fifo_counted_resized_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(15-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(15-1 DOWNTO 0);
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_eb_fifo_counted_resized_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_eb_fifo_counted_resized_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_eb_fifo_counted_resized_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 15,
C_RD_PNTR_WIDTH => 15,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_eb_fifo_counted_resized_inst : k7_eb_fifo_counted_resized_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
VALID => valid,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Final stage of SHA1 algorithm - process existing buffer and calc outputs
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity sha1_process_buffer is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end sha1_process_buffer;
architecture RTL of sha1_process_buffer is
signal w: w_full;
--signal w_con: w_full;
signal w_hold: w_full;
signal running: std_ulogic;
-- synthesis translate_off
signal test_word_1: std_ulogic_vector(0 to 31);
signal test_word_2: std_ulogic_vector(0 to 31);
signal test_word_3: std_ulogic_vector(0 to 31);
signal test_word_4: std_ulogic_vector(0 to 31);
signal test_word_5: std_ulogic_vector(0 to 31);
-- synthesis translate_on
signal i : integer range 0 to 79;
signal a: unsigned(0 to 31);
signal b: unsigned(0 to 31);
signal c: unsigned(0 to 31);
signal d: unsigned(0 to 31);
signal e: unsigned(0 to 31);
signal a_con: std_ulogic_vector(0 to 31);
signal b_con: std_ulogic_vector(0 to 31);
signal c_con: std_ulogic_vector(0 to 31);
signal d_con: std_ulogic_vector(0 to 31);
signal e_con: std_ulogic_vector(0 to 31);
--Algorithm variables
constant h0i : std_ulogic_vector(0 to 31) := X"67452301"; -- H0 (a)
constant h1i : std_ulogic_vector(0 to 31) := X"EFCDAB89"; -- H1 (b)
constant h2i : std_ulogic_vector(0 to 31) := X"98BADCFE"; -- H2 (c)
constant h3i : std_ulogic_vector(0 to 31) := X"10325476"; -- H3 (d)
constant h4i : std_ulogic_vector(0 to 31) := X"C3D2E1F0"; -- H4 (e)
constant k0 : std_ulogic_vector(0 to 31) := X"5A827999"; -- ( 0 <= t <= 19)
constant k1 : std_ulogic_vector(0 to 31) := X"6ED9EBA1"; -- (20 <= t <= 39)
constant k2 : std_ulogic_vector(0 to 31) := X"8F1BBCDC"; -- (40 <= t <= 59)
constant k3 : std_ulogic_vector(0 to 31) := X"CA62C1D6"; -- (60 <= t <= 79)
signal h0 : std_ulogic_vector(0 to 31) := h0i;
signal h1 : std_ulogic_vector(0 to 31) := h1i;
signal h2 : std_ulogic_vector(0 to 31) := h2i;
signal h3 : std_ulogic_vector(0 to 31) := h3i;
signal h4 : std_ulogic_vector(0 to 31) := h4i;
signal h0out : unsigned(0 to 31);
signal h1out : unsigned(0 to 31);
signal h2out : unsigned(0 to 31);
signal h3out : unsigned(0 to 31);
signal h4out : unsigned(0 to 31);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
--running <= '0';
--Todo: Reset input too, if needed
--for x in 0 to 79 loop
-- w_hold(x) <= "00000000000000000000000000000000";
--end loop;
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
else
if load_i = '1' then
if new_i = '1' then
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
a <= unsigned((h1i and h2i) or ((not h1i) and h3i)) +
rotate_left(unsigned(h0i), 5) +
unsigned(h4i) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(h0i);
c <= rotate_left(unsigned(h1i), 30);
d <= unsigned(h2i);
e <= unsigned(h3i);
else
h0 <= dat_w_i(0);
h1 <= dat_w_i(1);
h2 <= dat_w_i(2);
h3 <= dat_w_i(3);
h4 <= dat_w_i(4);
a <= unsigned((dat_w_i(1) and dat_w_i(2)) or ((not dat_w_i(1)) and dat_w_i(3))) +
rotate_left(unsigned(dat_w_i(0)), 5) +
unsigned(dat_w_i(4)) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(dat_w_i(0));
c <= rotate_left(unsigned(dat_w_i(1)), 30);
d <= unsigned(dat_w_i(2));
e <= unsigned(dat_w_i(3));
end if;
i <= 0;
else
--TEMP = S^5(A) + f(t;B,C,D) + E + W(t) + K(t);
--Alt: gotta be better way!
case i is
--f(t;B,C,D) = (B AND C) OR ((NOT B) AND D)
when 0 to 18 => a <= unsigned((b_con and c_con) or ((not b_con) and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k0);
--f(t;B,C,D) = B XOR C XOR D
when 19 to 38 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k1);
--f(t;B,C,D) = (B AND C) OR (B AND D) OR (C AND D)
when 39 to 58 => a <= unsigned((b_con and c_con) or (b_con and d_con) or (c_con and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k2);
--f(t;B,C,D) = B XOR C XOR D
when 59 to 78 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k3);
when 79 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i)) +
unsigned(k3);
end case;
--E = D; D = C; C = S^30(B); B = A; A = TEMP;
e <= unsigned(d_con);
d <= unsigned(c_con);
c <= rotate_left(unsigned(b_con), 30);
b <= unsigned(a_con);
i <= i + 1;
end if;
if i = 79 then
--i <= 0;
--Todo: AND 'running' signal with i = 79 to stop incorrect 'valid_o' outputs
valid_o <= '1';
h0out <= unsigned(h0) + a;
h1out <= unsigned(h1) + b;
h2out <= unsigned(h2) + c;
h3out <= unsigned(h3) + d;
h4out <= unsigned(h4) + e;
else
valid_o <= '0';
end if;
end if;
end if;
end process;
dat_w_o(0) <= std_ulogic_vector(h0out);
dat_w_o(1) <= std_ulogic_vector(h1out);
dat_w_o(2) <= std_ulogic_vector(h2out);
dat_w_o(3) <= std_ulogic_vector(h3out);
dat_w_o(4) <= std_ulogic_vector(h4out);
w <= dat_i;
--w_con <= w;
a_con <= std_ulogic_vector(a);
b_con <= std_ulogic_vector(b);
c_con <= std_ulogic_vector(c);
d_con <= std_ulogic_vector(d);
e_con <= std_ulogic_vector(e);
-- synthesis translate_off
test_word_1 <= w(0);
test_word_2 <= w(79);
test_word_3 <= h0;
test_word_4 <= std_ulogic_vector(h0out);
test_word_5 <= std_ulogic_vector(h1out);
-- synthesis translate_on
end RTL; |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 313 WoS January 2015
-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
-- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
--
-- Ver 312 WoS January 2015
-- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
-- Added comments in MCode section to find handling of individual opcodes more easily
-- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with
-- actual FPGAARCADE C64 core (sources used: SVN version 1021).
--
-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
-- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
-- SAX opcode
-- SHA opcode
-- SHX opcode
-- SHY opcode
-- SHS opcode
-- LAS opcode
-- alternate SBC opcode
-- fixed NOP with immediate param (caused Lorenz trap test to fail)
-- IRQ and NMI timing fixes (in conjuction with branches)
--
-- Ver 304 WoS December 2014
-- Undoc opcode fixes:
-- ARR opcode
-- ANE/XAA opcode
-- Corrected issue with NMI/IRQ prio (when asserted the same time)
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Ver 303,302 WoS April 2014
-- Bugfixes for NMI from foft
-- Bugfix for BRK command (and its special flag)
--
-- Ver 300,301 WoS January 2014
-- More merging
-- Bugfixes by ehenciak added, started tidyup *bust*
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
-- ****
--
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- ----- IMPORTANT NOTES -----
--
-- Limitations:
-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
-- 65C02 supported : inc, dec, phx, plx, phy, ply
-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
-- Some interface signals behave incorrect
-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
--
-- Usage:
-- The enable signal allows clock gating / throttling without using the ready signal.
-- Set it to constant '1' when using the Clk input as the CPU clock directly.
--
-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
-- otherwise some undocumented opcodes won't work correctly.
-- EXAMPLE:
-- CPU : entity work.T65
-- port map (
-- R_W_n => cpu_rwn_s,
-- [....all other ports....]
-- DI => cpu_din_s,
-- DO => cpu_dout_s
-- );
-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
-- [....other sources from peripherals and memories...]
--
-- ----- IMPORTANT NOTES -----
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal BusB_r : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal Res_n_i : std_logic;
signal Res_n_d : std_logic;
signal really_rdy : std_logic;
signal WRn_i : std_logic;
signal NMI_entered : std_logic;
begin
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
R_W_n <= WRn_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
VPA <= '1' when Jump(1) = '0' else '0';
-- debugging signals
DEBUG.I <= IR;
DEBUG.A <= ABC(7 downto 0);
DEBUG.X <= X(7 downto 0);
DEBUG.Y <= Y(7 downto 0);
DEBUG.S <= std_logic_vector(S(7 downto 0));
DEBUG.P <= P;
Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
mcode : entity work.T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
-- the 65xx design requires at least two clock cycles before
-- starting its reset sequence (according to datasheet)
process (Res_n_i, Clk)
begin
if Res_n = '0' then
Res_n_i <= '0';
Res_n_d <= '0';
elsif Clk'event and Clk = '1' then
Res_n_i <= Res_n_d;
Res_n_d <= '1';
end if;
end process;
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
WRn_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
WRn_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
S(7 downto 0) <= unsigned(ALU_Q);
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n_i, Clk)
variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n_i = '0' then
P <= x"00"; -- ensure we have nothing set on reset
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
tmpP:=P_Out;
end if;
if LDP = '1' then
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
tmpP(Flag_B) := '1';
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
--This should happen after P has been pushed to stack
tmpP(Flag_I) := '1';
end if;
if SO_n_o = '1' and SO_n = '0' then
tmpP(Flag_V) := '1';
end if;
if RstCycle = '1' then
tmpP(Flag_I) := '1';
tmpP(Flag_D) := '0';
end if;
tmpP(Flag_1) := '1';
P<=tmpP;--new way
SO_n_o <= SO_n;
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
IRQ_n_o <= IRQ_n;
end if;
end if;
-- detect nmi even if not rdy
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
BusB_r <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
NMI_entered <= '0';
if (really_rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
-- not really nice, but no better way found yet !
if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- modified to use Y register as well
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
BAL(2 downto 0) <= "010";
if MCycle="100" then
NMI_entered <= '1';
end if;
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
ABC(7 downto 0) and DI when Set_BusA_To_DA,
(ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
(ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP,
DBR & "00000000" & AD when Set_Addr_To_ZPG,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
with Write_Data_r select
DO <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX,
ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
NMICycle <= '1';
NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
--detect NMI even if not rdy
if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
NMIAct <= '1';
end if;
-- we entered NMI during BRK instruction
if NMI_entered='1' then
NMIAct <= '0';
end if;
end if;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- system_clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03_a;
use clock_generator_0_v4_03_a.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity system_clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end system_clock_generator_0_wrapper;
architecture STRUCTURE of system_clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_DEVICE : STRING;
C_PACKAGE : STRING;
C_SPEEDGRADE : STRING
);
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "virtex5",
C_DEVICE => "5vlx50t",
C_PACKAGE => "ff1136",
C_SPEEDGRADE => "-1"
)
port map (
CLKIN => CLKIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBIN => CLKFBIN,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-01 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_00700_good.vhd
-- File Creation date : 2015-04-01
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of signal name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_00700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_00700_good;
--CODE
architecture Behavioral of STD_00700_good is
signal D : std_logic; -- First Flip-Flop output
signal Q : std_logic; -- Block output
begin
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => D,
o_Q_n => open
);
P_FlipFlop : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= D;
end if;
end process;
end Behavioral;
--CODE
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
USE work.UMDRISC_pkg.ALL;
entity RegR_LATCH_tb is
end RegR_LATCH_tb;
architecture Behavioral of RegR_LATCH_tb is
component RegR_LATCH is
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
HOLD_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
signal CLOCK : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal ENABLE : STD_LOGIC := '0';
signal D : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q2 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q3 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q4 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
--DEBUG TO SEE THE OUTPUT OF HOLD
signal H : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H2 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H3 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H4 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
constant period : time := 10 ns;
begin
-- Register 1
Reg1: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => D,
HOLD_OUT => H,
OUTPUT => Q
);
-- Register 2
Reg2: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q,
HOLD_OUT => H2,
OUTPUT => Q2
);
-- Register 3
Reg3: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q2,
HOLD_OUT => H3,
OUTPUT => Q3
);
-- Register 4
Reg4: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q3,
HOLD_OUT => H4,
OUTPUT => Q4
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
--Reset disable
RESETN <= '1'; wait for period;
assert (Q = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned(Q))) severity ERROR;
D <= x"FFFFFF";
--Enabling the register
ENABLE <= '1'; wait for 2*period;
-- Test each input via loop
for i in 0 to 256 loop
D <= std_logic_vector(to_signed(i,D'length)); wait for 2*period;
end loop;
end process;
end Behavioral;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity StateMachineEditor1_import is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end entity StateMachineEditor1_import;
architecture rtl of StateMachineEditor1_import is
component StateMachineEditor1_import_GN is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end component StateMachineEditor1_import_GN;
begin
StateMachineEditor1_import_GN_0: if true generate
inst_StateMachineEditor1_import_GN_0: StateMachineEditor1_import_GN
port map(clock => clock, col_select => col_select, data => data, data_en => data_en, reset => reset);
end generate;
end architecture rtl;
|
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