content stringlengths 1 1.04M ⌀ |
|---|
package foo is
alias bar is baz;
alias bar is baz [];
alias bar is baz [a,b,c];
alias bar is baz [return d];
alias bar is baz [a,b,c return d];
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revis... |
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100"... |
entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100"... |
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
entity Debounce is
port (clock: in STD_LOGIC;
input_h: in STD_LOGIC;
output_h: out STD_LOGIC;
--internal structure
input_temp1_h: out STD_LOGIC;
input_temp2_h: out STD_LOGIC;
... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_utilities.all;
--! @brief Simp... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:54:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-e.vhd,v 1.2 ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wb_stream_pkg.all;
use work.wb_stream_generic_pkg.all;
use work.fmc_adc_pkg.all;
use work.wr_fabric_pkg.all;
package dbe_wishbone_pkg is
--------------------------------------------------------------------
-... |
-- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- -------... |
----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for vgca
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vg... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_sender is
port (
send_start: in std_logic;
clock_master: in std_logic; -- clk_500KHz
slave_id: in std_logic_vector(6 downto 0);
rw: in std_logic;
sub_address: in std_log... |
configuration blah of blah is
end blah;
configuration blah of blah is
for beh
end for beh;
end blah;
configuration blah of blah is
use blah.blah.blah;
end blah;
configuration blah of blah is
attribute attribute_designator of entity_designator : entity is 0;
end blah;
configuration blah of blah is
group i... |
------------------------------------------------------------
-- VGA Simulator projet VHDL
-- The whole system implementation that holds the three modules
-- Elhamer Oussama abdelkhalek
-- Generate a picture, save if on a spesific location on the disk, and generate the corresponding H_Sync and V_Sync
-- the three modu... |
library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(
-- GLOBAL SIGNALS:
clk : in std_logic;
reset : in std_logic;
-- COMMAND INTERFACE:
data_in_vld : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out_vld : out std_logic;
data_out : out std_logic_vector(7 downto 0);
... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:55:20)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input... |
--------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF AN... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this f... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32 -- ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg32 is
port(
d : in std_logic_vector(31 downto 0);
rst : in std_logic;
en : in std_logic;
clk : in std_logic; -- clock.
q : out std_logic_vector(31 DOWNTO 0) -- outpu... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_conte... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_conte... |
library ieee;
use ieee.std_logic_1164.all;
entity matching is
end matching;
architecture behav of matching is
constant ceq11 : std_logic := '1' ?= '1';
constant ceq1h : std_logic := '1' ?= 'H';
constant ceq1w : std_logic := '1' ?= 'W';
begin
assert ceq11 = '1';
assert ceq1h = '1';
assert ceq1w = 'X';
end ... |
constant FONT_ROM : glyph_rom_t = (
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:28:39 04/11/2017
-- Design Name:
-- Module Name: variable_clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Calculator is
port (clock : in STD_LOGIC;
btn_reset : in STD_LOGIC;
btn_inc : in STD_LOGIC;
btn_dec : in STD_LOGIC;
switch_input : in STD_LOGIC;
switch_operation : in STD_LOGIC... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
-- ------------------------------------------------------------------------
entity gigatron_tb_rom is
port (
a : in unsigned(15 downto 0);
q : out unsigned(15 downto 0)
);
end entity;
-- -------------------------------------------------------... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
e... |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
e... |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
e... |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
e... |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
e... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PISO is
port (
Pattern : in std_logic_vector(7 downto 0);
DataIn : in std_logic;
Load : in std_logic;
Reset : in std_logic;
Clk : in std_logic;
Found : out std_logic
);
e... |
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 8x1
entity mux8x1 is
port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7: in std_logic;
REG: out std_logic;
SW: in std_logic_vector(2 downto 0)
);
end mux8x1;
--Definicao Arquitetura
architecture circuito of mux8x1 is
begin
REG <= IN0 when SW = "000" else
IN1... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
------------------------------------------------------... |
----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : With this example it is possible to generate
-- control-commands for the LCD-Display by using
-- switch 0 to 7. The command is send by pressing
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives describ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity FIFO IS
end entity;
entity FIFO IS
end entity;
entity FIFO IS
end entity;
|
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_sr.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-15
... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaime... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaime... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaime... |
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. F... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
-- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $
--
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
--
-- Boundary Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
use FPGALIB.Sync.all;
entity Boundary_Tb is
end entity Boundary_Tb;
architecture... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions for CRC32/Ethernet frame check sequence calculation
library ieee;
use ieee.std_logic_1164.all;
use work.crc.all;
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_5_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
p1: process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
v(2) := s(3);
s <= v;
v := s;
wait;
end process;
end... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package packagefa00 is
component or00
port(
Ao: in std_logic ;
Bo: in std_logic ;
Yo: out std_logic );
end component;
component topha00
port(
A0: in std_logic ;
B0: in... |
entity bot is
end entity;
architecture test of bot is
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename1 is
end entity;
architecture test of ename1 is... |
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
enable_dpa_mode : string := "OFF";
data_align_rollover: vl_notype;
lose_lock_on_one_change: string := "OFF";
rese... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
PORT(
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0); --ENTRADAS TOP
piso_actual: IN std_logic_vector(2 DOWNTO 0);
nivel, celula, abierto, cerrado: IN std_logic;
puerta, motor_subir, motor_bajar: OUT std_logic; --SALIDAS TOP
piso0... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- Final stage of SHA1 algorithm - process existing buffer and calc outputs
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU G... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 313 WoS January 2015
-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
-- This i... |
-------------------------------------------------------------------------------
-- system_clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
USE work.UMDRISC_pkg.ALL;
entity RegR_LATCH_tb is
end RegR_LATCH_tb;
architecture Behavioral of RegR_LATCH_tb is
component RegR_LATCH is
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
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