content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------------------------------------
-- Title : ARP Responder
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpResponder.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Receives ARP requests, sends back ARP responses.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpResponder is
generic (
NUM_IP_G : integer := 1;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethClk : in sl;
ethRst : in sl := '0';
-- Local MAC/IP settings
macAddress : in MacAddrType;
ipAddresses : in IpAddrArray(NUM_IP_G-1 downto 0);
-- Connection to ARP RX
arpRxOp : in slv(15 downto 0);
arpRxSenderMac : in MacAddrType;
arpRxSenderIp : in IpAddrType;
arpRxTargetMac : in MacAddrType;
arpRxTargetIp : in IpAddrType;
arpRxValid : in sl;
-- Connection to ARP TX
arpTxSenderMac : out MacAddrType;
arpTxSenderIp : out IpAddrType;
arpTxTargetMac : out MacAddrType;
arpTxTargetIp : out IpAddrType;
arpTxOp : out slv(15 downto 0);
arpTxReq : out sl;
arpTxAck : in sl
);
end ArpResponder;
architecture rtl of ArpResponder is
type StateType is (IDLE_S, CHECK_IP_S, RESPOND_S, WAIT_S);
type RegType is record
state : StateType;
rxSenderMac : MacAddrType;
rxSenderIp : IpAddrType;
rxTargetMac : MacAddrType;
rxTargetIp : IpAddrType;
txSenderMac : MacAddrType;
txSenderIp : IpAddrType;
txTargetMac : MacAddrType;
txTargetIp : IpAddrType;
txOp : slv(15 downto 0);
txReq : sl;
matchedIp : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
rxSenderMac => MAC_ADDR_INIT_C,
rxSenderIp => IP_ADDR_INIT_C,
rxTargetMac => MAC_ADDR_INIT_C,
rxTargetIp => IP_ADDR_INIT_C,
txSenderMac => MAC_ADDR_INIT_C,
txSenderIp => IP_ADDR_INIT_C,
txTargetMac => MAC_ADDR_INIT_C,
txTargetIp => IP_ADDR_INIT_C,
txOp => (others => '0'),
txReq => '0',
matchedIp => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethRst,macAddress,ipAddresses,
arpRxOp,arpRxSenderMac,arpRxSenderIp,arpRxTargetMac,
arpRxTargetIp,arpRxValid,arpTxAck) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.txReq := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.matchedIp := '0';
if (arpRxValid = '1') then
v.rxSenderMac := arpRxSenderMac;
v.rxSenderIp := arpRxSenderIp;
v.rxTargetMac := arpRxTargetMac;
v.rxTargetIp := arpRxTargetIp;
if (arpRxOp = ARP_OP_REQ_C) then
v.state := CHECK_IP_S;
end if;
end if;
when CHECK_IP_S =>
for ipNum in NUM_IP_G-1 downto 0 loop
if (r.rxTargetIp = ipAddresses(ipNum)) then
v.matchedIp := '1';
end if;
end loop;
if (v.matchedIp = '1') then
v.state := RESPOND_S;
else
v.state := IDLE_S;
end if;
when RESPOND_S =>
v.txReq := '1';
v.txSenderMac := macAddress;
v.txSenderIp := r.rxTargetIp;
v.txTargetMac := r.rxSenderMac;
v.txTargetIp := r.rxSenderIp;
v.txOp := ARP_OP_RES_C;
if (arpTxAck = '1') then
v.state := WAIT_S;
end if;
when WAIT_S =>
if (arpTxAck = '0') then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
arpTxSenderMac <= r.txSenderMac;
arpTxSenderIp <= r.txSenderIp;
arpTxTargetMac <= r.txTargetMac;
arpTxTargetIp <= r.txTargetIp;
arpTxOp <= r.txOp;
arpTxReq <= r.txReq;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethClk) is
begin
if (rising_edge(ethClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_or1knd_i5_mmu_inst_pass_pkg.all;
entity cpu_or1knd_i5_mmu_inst_pass is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_or1knd_i5_mmu_inst_pass_ctrl_in : in cpu_or1knd_i5_mmu_inst_pass_ctrl_in_type;
cpu_or1knd_i5_mmu_inst_pass_dp_in : in cpu_or1knd_i5_mmu_inst_pass_dp_in_type;
cpu_or1knd_i5_mmu_inst_pass_ctrl_out : out cpu_or1knd_i5_mmu_inst_pass_ctrl_out_type;
cpu_or1knd_i5_mmu_inst_pass_dp_out : out cpu_or1knd_i5_mmu_inst_pass_dp_out_type;
cpu_or1knd_i5_mmu_inst_pass_ctrl_in_pipe : in cpu_or1knd_i5_mmu_inst_pass_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_inst_pass_dp_in_pipe : in cpu_or1knd_i5_mmu_inst_pass_dp_in_pipe_type;
cpu_or1knd_i5_mmu_inst_pass_ctrl_out_pipe : out cpu_or1knd_i5_mmu_inst_pass_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_inst_pass_dp_out_pipe : out cpu_or1knd_i5_mmu_inst_pass_dp_out_pipe_type
);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: svgactrl
-- File: svgactrl.vhd
-- Author: Hans Soderlund
-- Modified: Jiri Gaisler, Edvin Catovic, Jan Andersson
-- Contact: support@gaisler.com
-- Description: SVGA Controller core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity svgactrl is
generic(
length : integer := 384; -- FIFO length in 32-bit words
part : integer := 128; -- FIFO-part length in 32-bit words
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0 -- Enable async. reset of VGA CD
);
port (
rst : in std_logic; -- Synchronous reset
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1' -- Asynchronous reset
);
end ;
architecture rtl of svgactrl is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
-- Calculates the required number of address bits for 32 bit buffer
function addrbits return integer is
begin
for i in 1 to 30 loop
if (2**i >= length) then return(i);
end if;
end loop;
return(30);
end function addrbits;
constant WPAC : integer := ahbaccsz/32; -- Words Per AHB Access.
constant FIFO_DW : integer := ahbaccsz; -- FIFO data width
constant FIFOCNTR : integer := log2(WPAC);
constant ABITS : integer := addrbits - FIFOCNTR; -- FIFO address bits
constant FIFOCNTL : integer := addrbits - 1;
subtype FIFO_CNT_R is natural range FIFOCNTL downto FIFOCNTR;
constant BURSTL : integer := burstlen + 1;
constant BURSTR : integer := log2(ahbaccsz/8);
type register_type is array (1 to 5) of std_logic_vector(31 downto 0);
type state_type is (running, not_running, reset);
type read_type is record
read_pointer : std_logic_vector(FIFOCNTL downto 0);
read_pointer_out : std_logic_vector(FIFOCNTL downto 0);
sync : std_logic_vector(2 downto 0);
data_out : std_logic_vector(23 downto 0);
lock : std_logic;
index : std_logic_vector(1 downto 0);
read_pointer_clut : std_logic_vector(7 downto 0);
hcounter : std_logic_vector(15 downto 0);
vcounter : std_logic_vector(15 downto 0);
fifo_ren : std_logic;
fifo_en : std_logic;
hsync : std_logic ;
vsync : std_logic ;
csync : std_logic ;
blank : std_logic ;
hsync2 : std_logic ;
vsync2 : std_logic ;
csync2 : std_logic ;
blank2 : std_logic ;
end record;
type control_type is record
int_reg : register_type;
state : state_type;
enable : std_logic;
reset : std_logic;
sync_c : std_logic_vector(2 downto 0);
sync_w : std_logic_vector(2 downto 0);
write_pointer_clut : std_logic_vector(7 downto 0);
datain_clut : std_logic_vector(23 downto 0);
write_en_clut : std_logic;
address : std_logic_vector(31 downto 0);
start : std_logic;
write_pointer : integer range 0 to length/WPAC;
ram_address : integer range 0 to length/WPAC;
data : std_logic_vector(FIFO_DW-1 downto 0);
level : integer range 0 to part/WPAC + 1;
status : integer range 0 to 3;
hpolarity : std_ulogic;
vpolarity : std_ulogic;
func : std_logic_vector(1 downto 0);
clk_sel : std_logic_vector(1 downto 0);
end record;
type sync_regs is record
s1 : std_logic_vector(2 downto 0);
s2 : std_logic_vector(2 downto 0);
s3 : std_logic_vector(2 downto 0);
end record;
signal t,tin : read_type;
signal r,rin : control_type;
signal sync_w : sync_regs;
signal sync_ra : sync_regs;
signal sync_rb : sync_regs;
signal sync_c : sync_regs;
signal read_status : std_logic_vector(2 downto 0);
signal write_status : std_logic_vector(2 downto 0);
signal write_en : std_logic;
signal res_mod :std_logic;
signal en_mod : std_logic;
signal fifo_en : std_logic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal equal : std_logic;
signal hmax : std_logic_vector(15 downto 0);
signal hfporch : std_logic_vector(15 downto 0);
signal hsyncpulse : std_logic_vector(15 downto 0);
signal hvideo : std_logic_vector(15 downto 0);
signal vmax : std_logic_vector(15 downto 0);
signal vfporch : std_logic_vector(15 downto 0);
signal vsyncpulse : std_logic_vector(15 downto 0);
signal vvideo : std_logic_vector(15 downto 0);
signal write_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal write_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal datain_clut : std_logic_vector(23 downto 0);
signal dataout_clut : std_logic_vector(23 downto 0);
signal dataout_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal datain_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal write_en_clut, read_en_clut : std_logic;
signal vcc : std_logic;
signal read_en_fifo, write_en_fifo : std_logic;
begin
vcc <= '1';
ram0 : syncram_2p
generic map (
tech => memtech,
abits => ABITS,
dbits => FIFO_DW,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_fifo,
raddress => read_pointer_fifo,
dataout => dataout_fifo,
wclk => clk,
write => write_en_fifo,
waddress => write_pointer_fifo,
datain => datain_fifo);
clutram : syncram_2p
generic map (
tech => memtech,
abits => 8,
dbits => 24,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_clut,
raddress => read_pointer_clut,
dataout => dataout_clut,
wclk => clk,
write => write_en_clut,
waddress => write_pointer_clut,
datain => datain_clut);
ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER,
GAISLER_SVGACTRL, 0, 3, 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod,sync_w)
variable v : control_type;
variable apbrdata : std_logic_vector(31 downto 0);
variable apbwrite : std_logic;
variable we_fifo : std_logic;
begin
v := r; v.write_en_clut := '0'; apbrdata := (others =>'0'); we_fifo := '0';
---------------------------------------------------------------------------
-- Control. Handles the APB accesses and stores the internal registers
---------------------------------------------------------------------------
apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
case apbi.paddr(5 downto 2) is
when "0000" =>
-- Status register
if apbwrite = '1' then
v.enable := apbi.pwdata(0);
v.reset := apbi.pwdata(1);
v.hpolarity := apbi.pwdata(8);
v.vpolarity := apbi.pwdata(9);
v.func := apbi.pwdata(5 downto 4);
v.clk_sel := apbi.pwdata(7 downto 6);
end if;
apbrdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel &
r.func & fifo_en & '0' & r.reset & r.enable;
when "1010" =>
-- CLUT access register
if apbwrite = '1' then
v.datain_clut := apbi.pwdata(23 downto 0);
v.write_pointer_clut := apbi.pwdata(31 downto 24);
v.write_en_clut := '1';
end if;
when "0001" =>
-- Video length register
if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if;
apbrdata := r.int_reg(1);
when "0010" =>
-- Front porch register
if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if;
apbrdata := r.int_reg(2);
when "0011" =>
-- Sync length register
if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if;
apbrdata := r.int_reg(3);
when "0100" =>
-- Line length register
if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if;
apbrdata := r.int_reg(4);
when "0101" =>
-- Framebuffer memory position register
if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if;
apbrdata := r.int_reg(5);
-- Dynamic clock registers 0 - 3
when "0110" => apbrdata := conv_std_logic_vector(clk0,32);
when "0111" => apbrdata := conv_std_logic_vector(clk1,32);
when "1000" => apbrdata := conv_std_logic_vector(clk2,32);
when "1001" => apbrdata := conv_std_logic_vector(clk3,32);
when others =>
end case;
---------------------------------------------------------------------------
-- Control state machine
---------------------------------------------------------------------------
case r.state is
when running =>
if r.enable = '0' then
v.sync_c := "011";
v.state := not_running;
end if;
when not_running =>
if r.enable = '1' then
v.sync_c := "001";
v.state := reset;
end if;
when reset =>
if sync_c.s3 = "001" then
v.sync_c := "010";
v.state := running;
end if;
end case;
---------------------------------------------------------------------------
-- Control reset
---------------------------------------------------------------------------
if r.reset = '1' or rst = '0' then
v.state := not_running;
v.enable := '0';
v.int_reg := (others => (others => '0'));
v.sync_c := "011";
v.reset := '0';
v.clk_sel := "00";
end if;
---------------------------------------------------------------------------
-- Write part. This part reads from the memory framebuffer and places the
-- data in the designated fifo specified from the generic.
---------------------------------------------------------------------------
v.start := '0';
if write_en = '0' then
if (r.start or not dmao.active) = '1' then v.start := '1'; end if;
-- AHB access and FIFO write
if dmao.ready = '1' then
v.data := ahbreaddata(dmao.rdata, r.address(4 downto 2),
conv_std_logic_vector(log2(FIFO_DW/8), 3));
v.ram_address := v.write_pointer;
v.write_pointer := v.write_pointer + 1; we_fifo := '1';
if v.write_pointer = length/WPAC then
v.write_pointer := 0;
end if;
v.level := v.level + 1;
if dmao.haddr = (9 downto 0 => '0') then
v.address := (v.address(31 downto 10) + 1) & dmao.haddr;
else
v.address := v.address(31 downto 10) & dmao.haddr;
end if;
if (dmao.haddr(BURSTL downto 0) =
((BURSTL downto BURSTR => '1') & zero32(BURSTR-1 downto 0))) then
v.start := '0';
end if;
end if;
-- FIFO sync
v.sync_w := v.sync_w and read_status;
if v.level >= (part/WPAC-1) then
if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part/WPAC then
v.level := 0;
if r.status = 0 then
v.sync_w(2) := '1';
else
v.sync_w(r.status -1) := '1';
end if;
v.status := v.status + 1;
if v.status = 3 then
v.status := 0;
end if;
else
v.start := '0';
end if;
end if;
end if;
---------------------------------------------------------------------------
--- Write reset part
---------------------------------------------------------------------------
if res_mod = '0' or write_en = '1' then
if dmao.active = '0' then v.address := r.int_reg(5); end if;
v.start := '0';
v.sync_w := "000";
v.status := 1;
v.ram_address := 0;
v.write_pointer := 0;
v.level := 0;
end if;
if (r.start and dmao.active and not dmao.ready) = '1' then
v.start := '1';
end if;
---------------------------------------------------------------------------
-- Drive process outputs
---------------------------------------------------------------------------
rin <= v;
sync_c.s1 <= v.sync_c;
sync_w.s1 <= r.sync_w;
res_mod <= sync_c.s3(1);
en_mod <= sync_c.s3(0);
write_status <= sync_w.s3;
hvideo <= r.int_reg(1)(15 downto 0);
vvideo <= r.int_reg(1)(31 downto 16);
hfporch <= r.int_reg(2)(15 downto 0);
vfporch <= r.int_reg(2)(31 downto 16);
hsyncpulse <= r.int_reg(3)(15 downto 0);
vsyncpulse <= r.int_reg(3)(31 downto 16);
hmax <= r.int_reg(4)(15 downto 0);
vmax <= r.int_reg(4)(31 downto 16);
apbo.prdata <= apbrdata;
dmai.wdata <= (others => '0');
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= conv_std_logic_vector(log2(ahbaccsz/8), 3);
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= r.start and r.enable;
dmai.address <= r.address;
write_pointer_fifo <= conv_std_logic_vector(v.ram_address, ABITS);
write_pointer_clut <= r.write_pointer_clut;
datain_fifo <= v.data;
datain_clut <= r.datain_clut;
write_en_clut <= r.write_en_clut;
clk_sel <= r.clk_sel;
write_en_fifo <= we_fifo;
end process;
read_proc : process(t, res_mod, en_mod, write_status, dataout_fifo, sync_rb,
dataout_clut, vmax, hmax, hvideo, hfporch, hsyncpulse,
vvideo, vfporch, vsyncpulse, sync_ra, r)
variable v : read_type;
variable inc_pointer : std_logic;
variable fifo_word : std_logic_vector(31 downto 0);
variable rpo1 : std_logic_vector(1 downto 0);
variable rpo2 : std_logic_vector(2 downto 0);
begin
v := t; fifo_word := (others => '0');
rpo1 := (others => '0'); rpo2 := (others => '0');
v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync;
v.blank2 := t.blank;
---------------------------------------------------------------------------
-- Sync signals generation
---------------------------------------------------------------------------
if en_mod = '0' then
-- vertical counter
if (t.vcounter = vmax ) and (t.hcounter = hmax ) then
v.vcounter := (others => '0');
elsif t.hcounter = hmax then
v.vcounter := t.vcounter + 1;
end if;
-- horizontal counter
if t.hcounter < hmax then v.hcounter := t.hcounter + 1;
else v.hcounter := (others => '0'); end if;
-- generate hsync
if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch-1)) then
v.hsync := r.hpolarity;
else v.hsync := not r.hpolarity; end if;
-- generate vsync
if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then
v.vsync := r.vpolarity;
else v.vsync := not r.vpolarity; end if;
--generate csync & blank signal
v.csync := not (v.hsync xor v.vsync);
v.blank := not t.fifo_ren;
--generate fifo_ren signal
if (t.hcounter = (hmax-1) and t.vcounter = vmax) or
(t.hcounter = (hmax-1) and t.vcounter < vvideo) then
v.fifo_ren := '0';
elsif t.hcounter = (hvideo-1) and t.vcounter <= vvideo then
v.fifo_ren := '1';
end if;
--generate fifo_en signal
if t.vcounter = vmax then
v.fifo_en := '0';
elsif t.vcounter = vvideo and t.hcounter = (hvideo-1) then
v.fifo_en := '1';
end if;
else
-- Prevent uninitialized fifo_en signal that leads to uninitialized
-- bit in APB status register
v.fifo_en := '1';
end if;
if r.func /= "01" then -- do not delay strobes when not using CLUT
v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync;
v.blank2 := v.blank;
end if;
---------------------------------------------------------------------------
-- Sync reset
---------------------------------------------------------------------------
if res_mod = '0' then
v.hcounter := hmax;
v.vcounter := vmax - 1;
v.hsync := r.hpolarity;
v.vsync := r.vpolarity;
v.blank := '0';
v.fifo_ren := '1';
v.fifo_en := '1';
end if;
---------------------------------------------------------------------------
-- Read from fifo.
---------------------------------------------------------------------------
inc_pointer := '0';
if t.fifo_en = '0' then
-- Fifo sync
if ((t.read_pointer_out = zero32(t.read_pointer_out'range) or
t.read_pointer_out = conv_std_logic_vector(part, FIFOCNTL+1) or
t.read_pointer_out = conv_std_logic_vector(2*part, FIFOCNTL+1)) and
t.fifo_ren = '0' and v.index = "00") then
case t.sync is
when "111" | "011" =>
if write_status(0) = '1' then
v.sync := "110"; v.lock := '0';
else v.lock := '1'; end if;
when "110" =>
if write_status(1) = '1' then
v.sync := "101"; v.lock := '0';
else v.lock := '1'; end if;
when "101" =>
if write_status(2) = '1' then
v.sync := "011"; v.lock := '0';
else v.lock := '1'; end if;
when others => null;
end case;
end if;
-------------------------------------------------------------------------
-- FIFO read and CLUT access
-------------------------------------------------------------------------
if t.fifo_ren = '0' and v.lock = '0' then
if FIFO_DW = 32 then
fifo_word(FIFO_DW-1 downto 0) := dataout_fifo(FIFO_DW-1 downto 0);
elsif FIFO_DW = 64 then
if t.read_pointer_out(0) = '0' then
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto FIFO_DW/2);
else
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW/2-1 downto 0);
end if;
elsif FIFO_DW = 128 then
rpo1 := t.read_pointer_out(1 downto 0);
case rpo1 is
when "00" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 3*(FIFO_DW/4));
when "01" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/4)-1 downto 2*(FIFO_DW/4));
when "10" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/4)-1 downto 1*(FIFO_DW/4));
when others =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo((FIFO_DW/4)-1 downto 0);
end case;
elsif FIFO_DW = 256 then
rpo2 := t.read_pointer_out(2 downto 0);
case rpo2 is
when "000" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 7*(FIFO_DW/8));
when "001" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(7*(FIFO_DW/8)-1 downto 6*(FIFO_DW/8));
when "010" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(6*(FIFO_DW/8)-1 downto 5*(FIFO_DW/8));
when "011" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(5*(FIFO_DW/8)-1 downto 4*(FIFO_DW/8));
when "100" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(4*(FIFO_DW/8)-1 downto 3*(FIFO_DW/8));
when "101" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/8)-1 downto 2*(FIFO_DW/8));
when "110" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/8)-1 downto 1*(FIFO_DW/8));
when others =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo((FIFO_DW/8)-1 downto 0);
end case;
end if;
case r.func is
when "01" =>
if t.index = "00" then
v.read_pointer_clut := fifo_word(31 downto 24);
v.index := "01";
elsif t.index = "01" then
v.read_pointer_clut := fifo_word(23 downto 16);
v.index := "10";
elsif t.index = "10" then
v.read_pointer_clut := fifo_word(15 downto 8);
v.index := "11";
else
v.read_pointer_clut := fifo_word(7 downto 0);
v.index := "00"; inc_pointer := '1';
end if;
v.data_out := dataout_clut;
when "10" =>
if t.index = "00" then
v.data_out := fifo_word(31 downto 27) & "000" &
fifo_word(26 downto 21) & "00" &
fifo_word(20 downto 16) & "000";
v.index := "01";
else
v.data_out := fifo_word(15 downto 11) & "000" &
fifo_word(10 downto 5) & "00" &
fifo_word(4 downto 0) & "000";
v.index := "00"; inc_pointer := '1';
end if;
when "11" =>
v.data_out := fifo_word(23 downto 0);
v.index := "00"; inc_pointer := '1';
when others =>
v.data_out := (23 downto 0 => '1');
v.index := "00"; inc_pointer := '1';
end case;
else
v.data_out := (others => '0');
end if;
if inc_pointer = '1' then
v.read_pointer_out := t.read_pointer;
v.read_pointer := t.read_pointer + 1;
if v.read_pointer(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer := (others => '0');
end if;
if v.read_pointer_out(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer_out := (others => '0');
end if;
end if;
else
v.data_out := (others => '0');
end if;
---------------------------------------------------------------------------
-- FIFO read reset
---------------------------------------------------------------------------
if res_mod = '0' or t.fifo_en = '1' then
v.sync := "111";
v.read_pointer_out := (others => '0');
v.read_pointer := conv_std_logic_vector(1, ABITS+FIFOCNTR);
v.data_out := (others => '0');
v.lock := '1';
v.index := "00";
v.read_pointer_clut := (others => '0');
end if;
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
tin <= v;
sync_ra.s1 <= t.sync;
sync_rb.s1 <= t.fifo_en & "00";
read_status <= sync_ra.s3;
write_en <= sync_rb.s3(2);
fifo_en <= t.fifo_en;
read_pointer_clut <= v.read_pointer_clut;
read_pointer_fifo <= v.read_pointer_out(FIFO_CNT_R);
read_en_fifo <= not v.fifo_ren;
read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0);
vgao.video_out_r <= t.data_out(23 downto 16);
vgao.video_out_g <= t.data_out(15 downto 8);
vgao.video_out_b <= t.data_out(7 downto 0);
vgao.hsync <= t.hsync2;
vgao.vsync <= t.vsync2;
vgao.comp_sync <= t.csync2;
vgao.blank <= t.blank2;
vgao.bitdepth <= r.func;
end process;
-----------------------------------------------------------------------------
-- Registers in system clock domain
-----------------------------------------------------------------------------
proc_clk : process(clk)
begin
if rising_edge(clk) then
r <= rin; -- Control
sync_ra.s2 <= sync_ra.s1; -- Write
sync_ra.s3 <= sync_ra.s2; -- Write
sync_rb.s2 <= sync_rb.s1; -- Write
sync_rb.s3 <= sync_rb.s2; -- Write
end if;
end process;
-----------------------------------------------------------------------------
-- Registers in video clock domain
-----------------------------------------------------------------------------
proc_vgaclk : process(arst, vgaclk)
begin
if asyncrst = 1 and arst = '0' then
t.fifo_en <= '1';
sync_c.s2 <= "011";
sync_c.s3 <= "011";
elsif rising_edge(vgaclk) then
t <= tin; -- Read
sync_c.s2 <= sync_c.s1; -- Control
sync_c.s3 <= sync_c.s2; -- Control
sync_w.s2 <= sync_w.s1; -- Read
sync_w.s3 <= sync_w.s2; -- Read
end if;
end process;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"svgactrl" & tost(pindex) & ": SVGA controller rev " &
tost(REVISION) & ", FIFO length: " & tost(length) &
", FIFO part length: " & tost(part) &
", FIFO address bits: " & tost(ABITS) &
", AHB access size: " & tost(ahbaccsz) & " bits");
-- pragma translate_on
end;
|
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
--use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 256x192
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0010000000"; -- 128
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0001100000"; -- 96
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "0011111111"; -- 255
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "0010111111"; -- 191
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block4
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_10_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_10_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_14_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_14_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_12_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_12_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block4 IS
-- Signals
SIGNAL twdlXdin_10_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_10_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_14_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_14_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_11_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_11_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_12_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_12_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
twdlXdin_10_re_signed <= signed(twdlXdin_10_re);
twdlXdin_10_im_signed <= signed(twdlXdin_10_im);
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_10_re_signed,
twdlXdin_10_im_signed, twdlXdin_14_re_signed, twdlXdin_14_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(19 DOWNTO 0);
VARIABLE add_cast_0 : signed(19 DOWNTO 0);
VARIABLE sub_cast : signed(19 DOWNTO 0);
VARIABLE sub_cast_0 : signed(19 DOWNTO 0);
VARIABLE add_cast_1 : signed(19 DOWNTO 0);
VARIABLE add_cast_2 : signed(19 DOWNTO 0);
VARIABLE sub_cast_1 : signed(19 DOWNTO 0);
VARIABLE sub_cast_2 : signed(19 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_10_re_signed, 20);
add_cast_0 := resize(twdlXdin_14_re_signed, 20);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_10_re_signed, 20);
sub_cast_0 := resize(twdlXdin_14_re_signed, 20);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_10_im_signed, 20);
add_cast_2 := resize(twdlXdin_14_im_signed, 20);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_10_im_signed, 20);
sub_cast_2 := resize(twdlXdin_14_im_signed, 20);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_11_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(18 DOWNTO 0);
dout_11_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(18 DOWNTO 0);
dout_12_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(18 DOWNTO 0);
dout_12_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(18 DOWNTO 0);
dout_11_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re <= std_logic_vector(dout_12_re_tmp);
dout_12_im <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
------------------------------------------------------------------------------
-- Title : Inverter Channels Top Entity
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design takes the signals from ADC FMC and invert them
-- according to control signals status[2..1]_i from swap_cnt_test
-- block.
-- This mechaninsm is necessary to compensate delay propagation
-- at ADC module.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-18 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity inv_chs_top is
generic(
g_delay_vec_width : natural range 0 to 16 := 10
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
const_aa_i : in std_logic_vector(15 downto 0);
const_bb_i : in std_logic_vector(15 downto 0);
const_cc_i : in std_logic_vector(15 downto 0);
const_dd_i : in std_logic_vector(15 downto 0);
const_ac_i : in std_logic_vector(15 downto 0);
const_bd_i : in std_logic_vector(15 downto 0);
const_ca_i : in std_logic_vector(15 downto 0);
const_db_i : in std_logic_vector(15 downto 0);
delay1_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
delay2_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
-- input from rf_ch_swap core:
status1_i : in std_logic;
status2_i : in std_logic;
status_en_i : in std_logic;
--output for debugging
flag1_o : out std_logic;
flag2_o : out std_logic;
-- input from ADC FMC board:
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- output to data processing level:
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0));
end inv_chs_top;
architecture rtl of inv_chs_top is
signal en1 : std_logic;
signal en2 : std_logic;
signal s_cha : std_logic_vector(15 downto 0);
signal s_chb : std_logic_vector(15 downto 0);
signal s_chc : std_logic_vector(15 downto 0);
signal s_chd : std_logic_vector(15 downto 0);
----------------------------------------------------------------
-- Components Declaration
----------------------------------------------------------------
component inv_ch
--generic(
--);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
flag_o : out std_logic;
flasg_en_i : in std_logic;
ch1_i : in std_logic_vector(15 downto 0);
ch2_i : in std_logic_vector(15 downto 0);
ch1_o : out std_logic_vector(15 downto 0);
ch2_o : out std_logic_vector(15 downto 0)
);
end component;
----------------------------------------------------------------
component delay_inv_ch
generic(
g_delay_vec_width : natural range 0 to 16 := g_delay_vec_width
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
trg_i : in std_logic; -- trigger
cnt_lmt_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
-- counter limit
en_o : out std_logic
);
end component;
----------------------------------------------------------------
component dyn_mult_2chs
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
const_11_i : in std_logic_vector(15 downto 0);
const_22_i : in std_logic_vector(15 downto 0);
const_12_i : in std_logic_vector(15 downto 0);
const_21_i : in std_logic_vector(15 downto 0);
ch1_i : in std_logic_vector(15 downto 0);
ch2_i : in std_logic_vector(15 downto 0);
ch1_o : out std_logic_vector(15 downto 0);
ch2_o : out std_logic_vector(15 downto 0)
);
end component;
----------------------------------------------------------------
begin
----------------------------------------------------------------
-- Components instantiation
----------------------------------------------------------------
delay_inst_1: delay_inv_ch
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
trg_i => status1_i,
cnt_lmt_i => delay1_i,
en_o => en1
);
delay_inst_2: delay_inv_ch
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
trg_i => status2_i,
cnt_lmt_i => delay2_i,
en_o => en2
);
inv_ch_inst_1: inv_ch
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => en1,
flag_o => flag1_o,
flasg_en_i => status_en_i,
ch1_i => cha_i,
ch2_i => chc_i,
ch1_o => s_cha,
ch2_o => s_chc
);
inv_ch_inst_2: inv_ch
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => en2,
flag_o => flag2_o,
flasg_en_i => status_en_i,
ch1_i => chb_i,
ch2_i => chd_i,
ch1_o => s_chb,
ch2_o => s_chd
);
mult_ch_pair1: dyn_mult_2chs
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => en1,
const_11_i => const_aa_i,
const_22_i => const_cc_i,
const_12_i => const_ac_i,
const_21_i => const_ca_i,
ch1_i => s_cha,
ch2_i => s_chc,
ch1_o => cha_o,
ch2_o => chc_o
);
mult_ch_pair2: dyn_mult_2chs
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => en2,
const_11_i => const_bb_i,
const_22_i => const_dd_i,
const_12_i => const_bd_i,
const_21_i => const_db_i,
ch1_i => s_chb,
ch2_i => s_chd,
ch1_o => chb_o,
ch2_o => chd_o
);
end;
|
--
-- TEXTIO package as defined by IEEE 1076-1993
--
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
procedure readline (file f: text; l: inout line);
procedure read (l : inout line;
value : out bit;
good : out boolean );
procedure read (l : inout line;
value : out bit );
procedure read (l : inout line;
value : out bit_vector;
good : out boolean );
procedure read (l : inout line;
value : out bit_vector );
procedure read (l : inout line;
value : out boolean;
good : out boolean );
procedure read (l : inout line;
value : out boolean );
procedure read (l : inout line;
value : out character;
good : out boolean );
procedure read (l : inout line;
value : out character );
procedure read (l : inout line;
value : out integer;
good : out boolean );
procedure read (l : inout line;
value : out integer );
procedure read (l : inout line;
value : out real;
good : out boolean );
procedure read (l : inout line;
value : out real );
procedure read (l : inout line;
value : out string;
good : out boolean );
procedure read (l : inout line;
value : out string );
procedure read (l : inout line;
value : out time;
good : out boolean );
procedure read (l : inout line;
value : out time );
procedure writeline (file f : text; l : inout line);
procedure tee (file f : text; l : inout line);
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 );
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns );
end package;
package body textio is
procedure grow (l : inout line;
extra : in natural;
old_size : out natural ) is
variable tmp : line;
begin
if l = null then
l := new string(1 to extra);
old_size := 0;
elsif extra > 0 then
old_size := l'length;
tmp := new string(1 to l'length + extra);
tmp(1 to l'length) := l.all;
deallocate(l);
l := tmp;
end if;
end procedure;
procedure shrink (l : inout line; size : in natural) is
variable tmp : line;
begin
assert l /= null;
assert size < l'length;
tmp := new string(1 to size);
tmp.all := l.all(1 to size);
deallocate(l);
l := tmp;
end procedure;
procedure consume (l : inout line; nchars : in natural) is
variable tmp : line;
begin
if nchars = 0 then
return;
end if;
assert l /= null;
if nchars = l'length then
tmp := new string'("");
else
assert nchars <= l'length;
tmp := new string(1 to l'length - nchars);
tmp.all := l.all(1 + nchars to l'length);
end if;
deallocate(l);
l := tmp;
end procedure;
function is_whitespace (x : character) return boolean is
begin
return x = ' ' or x = CR or x = LF or x = HT;
end function;
procedure skip_whitespace (l : inout line) is
variable skip : natural := 0;
begin
while skip < l'length and is_whitespace(l.all(1 + skip)) loop
skip := skip + 1;
end loop;
consume(l, skip);
end procedure;
function max (a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
procedure read (l : inout line;
value : out bit;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out bit )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit read failed";
end procedure;
procedure read (l : inout line;
value : out bit_vector;
good : out boolean ) is
variable consumed : natural := 0;
variable char : character;
begin
good := true;
skip_whitespace(l);
for i in value'range loop
if l.all'length < consumed then
good := false;
exit;
end if;
char := l.all(consumed + 1);
if char = '0' then
value(i) := '0';
elsif char = '1' then
value(i) := '1';
else
good := false;
exit;
end if;
consumed := consumed + 1;
end loop;
consume(l, consumed);
end procedure;
procedure read (l : inout line;
value : out bit_vector )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit_vector read failed";
end procedure;
procedure read (l : inout line;
value : out boolean;
good : out boolean ) is
begin
good := false;
skip_whitespace(l);
if l.all'length = 0 then
return;
end if;
if l(1) = 'T' or l(1) = 't' then
if l.all'length >= 4
and (l(2) = 'R' or l(2) = 'r')
and (l(3) = 'U' or l(3) = 'u')
and (l(4) = 'E' or l(4) = 'e')
then
consume(l, 4);
good := true;
value := true;
end if;
elsif l(1) = 'F' or l(1) = 'f' then
if l.all'length >= 5
and (l(2) = 'A' or l(2) = 'a')
and (l(3) = 'L' or l(3) = 'l')
and (l(4) = 'S' or l(4) = 's')
and (l(5) = 'E' or l(5) = 'e')
then
consume(l, 5);
good := true;
value := false;
end if;
end if;
end procedure;
procedure read (l : inout line;
value : out boolean )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "boolean read failed";
end procedure;
procedure read (l : inout line;
value : out character;
good : out boolean ) is
begin
if l'length > 0 then
value := l.all(1);
consume(l, 1);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out character )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "character read failed";
end procedure;
procedure read (l : inout line;
value : out integer;
good : out boolean ) is
variable pos : integer := 1;
variable digit : integer;
variable result : integer := 0;
variable is_negative : boolean := false;
begin
skip_whitespace(l);
if pos <= l.all'right and l.all(pos) = '-' then
pos := pos + 1;
is_negative := true;
end if;
while pos <= l.all'right loop
exit when l.all(pos) < '0' or l.all(pos) > '9';
digit := character'pos(l.all(pos)) - character'pos('0');
if is_negative then
digit := -digit;
end if;
result := (result * 10) + digit;
pos := pos + 1;
end loop;
if is_negative and pos = 2 then
-- Single dash without trailing digit is not good
pos := 1;
end if;
good := pos > 1;
value := result;
consume(l, pos - 1);
end procedure;
procedure read (l : inout line;
value : out integer )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "integer read failed";
end procedure;
procedure read (l : inout line;
value : out real;
good : out boolean ) is
variable prefix : integer;
variable result : real;
variable pgood : boolean;
variable digit : integer;
variable shift : real := 0.1;
variable pos : integer := 2;
begin
read(l, prefix, pgood);
if not pgood then
good := false;
return;
end if;
result := real(prefix);
good := true;
if l.all'length > 0 and l.all(1) = '.' then
while pos <= l.all'right loop
exit when l.all(pos) < '0' or l.all(pos) > '9';
digit := character'pos(l.all(pos)) - character'pos('0');
result := result + (real(digit) * shift);
shift := shift / 10.0;
pos := pos + 1;
end loop;
good := pos > 2;
consume(l, pos - 1);
end if;
value := result;
end procedure;
procedure read (l : inout line;
value : out real )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "real read failed";
end procedure;
procedure read (l : inout line;
value : out string;
good : out boolean ) is
begin
if value'length <= l'length then
value := l.all(1 to value'length);
consume(l, value'length);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out string )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "string read failed";
end procedure;
procedure read (l : inout line;
value : out time;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out time )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "time read failed";
end procedure;
procedure readline (file f: text; l: inout line) is
variable tmp : line;
variable ch : string(1 to 1);
variable used : natural;
variable got : integer;
begin
if l /= null then
deallocate(l);
end if;
tmp := new string(1 to 128);
loop
exit when endfile(f);
read(f, ch, got);
exit when got /= 1;
next when ch(1) = CR;
if ch(1) = LF then
exit;
else
if used = tmp'length then
grow(tmp, 128, used);
end if;
used := used + 1;
tmp(used) := ch(1);
end if;
end loop;
if used = 0 then
l := new string'("");
else
shrink(tmp, used);
l := tmp;
end if;
end procedure;
procedure writeline (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
l := new string'("");
end procedure;
procedure tee (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
write(output, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
write(output, (1 => LF));
l := new string'("");
end procedure;
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 )
is
variable orig : natural;
variable width : natural;
begin
width := max(value'length, field);
grow(l, width, orig);
if justified = left then
l(orig + 1 to orig + value'length) := value;
for i in orig + value'length + 1 to orig + width loop
l(i) := ' ';
end loop;
else
for i in orig + 1 to orig + width - value'length loop
l(i) := ' ';
end loop;
l(orig + 1 + width - value'length to orig + width) := value;
end if;
end procedure;
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, string'(1 => value), justified, field);
end procedure;
function bit_to_char (b : bit) return character is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' );
begin
return table(b);
end function;
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, bit_to_char(value), justified, field);
end procedure;
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 )
is
variable s : string(1 to value'length);
alias v : bit_vector(1 to value'length) is value;
begin
for i in s'range loop
s(i) := bit_to_char(v(i));
end loop;
write(l, s, justified, field);
end procedure;
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, boolean'image(value), justified, field);
end procedure;
function unit_string (unit : time) return string is
begin
-- Standard requires unit in lower case
if unit = fs then
return " fs";
elsif unit = ps then
return " ps";
elsif unit = ns then
return " ns";
elsif unit = us then
return " us";
elsif unit = ms then
return " ms";
elsif unit = sec then
return " sec";
elsif unit = min then
return " min";
elsif unit = hr then
return " hr";
else
report "invalid unit " & time'image(unit);
end if;
end function;
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns )
is
variable value_time: time := abs(value);
variable digit_time: time := unit;
variable str : string (1 to 22);
variable pos : natural := str'left;
variable digit : integer;
begin
if value < 0 ns then
str(pos) := '-';
pos := pos + 1;
end if;
while value_time / 10 >= digit_time loop
digit_time := digit_time * 10;
end loop;
while (pos <= str'right) loop
digit := value_time / digit_time;
value_time := value_time - digit * digit_time;
str(pos) := character'val(digit + character'pos ('0'));
pos := pos + 1;
exit when value_time = 0 fs and digit_time <= unit;
if digit_time = unit and pos <= str'right then
str(pos) := '.';
pos := pos + 1;
end if;
exit when (digit_time / 10) * 10 /= digit_time;
digit_time := digit_time / 10;
end loop;
write(l, str(1 to pos-1) & unit_string(unit), justified, field);
end procedure;
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, integer'image(value), justified, field);
end procedure;
end package body;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_MUX IS
END tb_MUX;
ARCHITECTURE behavior OF tb_MUX IS
CONSTANT N : INTEGER := 32;
--Inputs
SIGNAL tb_mux_in0 : std_logic_vector(N - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_mux_in1 : std_logic_vector(N - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_mux_ctl : std_logic := '0';
--Outputs
SIGNAL tb_mux_out : std_logic_vector(N - 1 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (U1_Test)
U1_Test : ENTITY work.MUX(Behavioral)
GENERIC MAP(N => 32)
PORT MAP(
mux_in0 => tb_mux_in0,
mux_in1 => tb_mux_in1,
mux_ctl => tb_mux_ctl,
mux_out => tb_mux_out
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- 32 bit 2 to 1 mux
tb_mux_in0 <= x"AAAA5555";
tb_mux_in1 <= x"5555AAAA";
tb_mux_ctl <= '0';
WAIT FOR 100 ns;
tb_mux_ctl <= '1';
WAIT FOR 100 ns;
tb_mux_ctl <= '0';
WAIT FOR 100 ns;
-- 5 bit 2 to 1 mux
-- tb_mux_in0 <= "10101";
-- tb_mux_in1 <= "01010";
-- tb_mux_ctl <= '0';
-- wait for 100 ns;
-- tb_mux_ctl <= '1';
-- wait for 100 ns;
-- tb_mux_ctl <= '0';
-- wait for 100 ns;
-- allow to zoom to full view
-- always at the end otherwise program will break
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel is
component FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_cols_V_channel_shiftReg : FIFO_image_filter_img_0_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel is
component FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_cols_V_channel_shiftReg : FIFO_image_filter_img_0_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel is
component FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_cols_V_channel_shiftReg : FIFO_image_filter_img_0_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel is
component FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_cols_V_channel_shiftReg : FIFO_image_filter_img_0_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_swapper_tb is
end entity;
architecture number_swapper_tb_arq of number_swapper_tb is
signal man_1_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_1_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_2_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_2_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_greater_out : std_logic_vector(15 downto 0) := (others => '0');
signal man_smaller_out : std_logic_vector(15 downto 0) := (others => '0');
signal exp_greater_out : std_logic_vector(5 downto 0) := (others => '0');
signal exp_smaller_out : std_logic_vector(5 downto 0) := (others => '0');
component number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_greater_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
man_smaller_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_greater_out : out std_logic_vector(EXP_BITS - 1 downto 0);
exp_smaller_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for number_swapper_0 : number_swapper use entity work.number_swapper;
begin
number_swapper_0 : number_swapper
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
exp_1_in => exp_1_in,
exp_2_in => exp_2_in,
man_1_in => man_1_in,
man_2_in => man_2_in,
exp_greater_out => exp_greater_out,
exp_smaller_out => exp_smaller_out,
man_greater_out => man_greater_out,
man_smaller_out => man_smaller_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
e1 : std_logic_vector(5 downto 0);
m2 : std_logic_vector(15 downto 0);
e2 : std_logic_vector(5 downto 0);
mg : std_logic_vector(15 downto 0);
ms : std_logic_vector(15 downto 0);
eg : std_logic_vector(5 downto 0);
es : std_logic_vector(5 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000001", "000000", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000000","000000"),
("0000000000000001", "000100", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000100","000000"),
("0000000110000000", "000011", "0000000000000001", "000001", "0000000110000000", "0000000000000001", "000011","000001"),
("0000000000000001", "000001", "0000000011000000", "000011", "0000000011000000", "0000000000000001", "000011","000001"),
("1111111111111111", "111110", "0000000000000000", "111111", "0000000000000000", "1111111111111111", "111111","111110")
);
begin
for i in patterns'range loop
-- Set the inputs.
exp_1_in <= patterns(i).e1;
exp_2_in <= patterns(i).e2;
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
wait for 1 ns;
assert patterns(i).mg = man_greater_out report "BAD MANTISSA G, GOT: " & integer'image(to_integer(unsigned(man_greater_out)));
assert patterns(i).ms = man_smaller_out report "BAD MANTISSA S, GOT: " & integer'image(to_integer(unsigned(man_smaller_out)));
assert patterns(i).eg = exp_greater_out report "BAD EXP G, GOT: " & integer'image(to_integer(unsigned(exp_greater_out)));
assert patterns(i).es = exp_smaller_out report "BAD EXP S, GOT: " & integer'image(to_integer(unsigned(exp_smaller_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity preprocessor_tb is
end entity;
architecture preprocessor_tb_arq of preprocessor_tb is
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal y_in : std_logic_vector(31 downto 0) := (others => '0');
signal angle_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
signal angle_out : std_logic_vector(31 downto 0) := (others => '0');
component preprocessor is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_in : in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
preprocessor_0 : preprocessor
generic map(TOTAL_BITS => 32)
port map(
x_in => x_in,
y_in => y_in,
angle_in => angle_in,
x_out => x_out,
y_out => y_out,
angle_out => angle_out
);
process
type pattern_type is record
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
ai : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
ao : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001000101",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001000101"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001100000",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000110"),
("00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000001100000",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000110"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"11111111111111111111111110100000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111010")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
angle_in <= patterns(i).ai;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
assert patterns(i).ao = angle_out report "BAD ANGLE, GOT: " & integer'image(to_integer(signed(angle_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 21:11:41 05/16/2016
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY lcd_driver_tb IS
END lcd_driver_tb;
ARCHITECTURE behavior OF lcd_driver_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lcd_driver
PORT(
clk : IN std_logic;
busy : out STD_LOGIC;
reset : IN std_logic;
data : IN std_logic_vector(7 downto 0);
new_character : IN std_logic;
new_pos : IN std_logic;
lcd_db : OUT std_logic_vector(7 downto 0);
lcd_en : OUT std_logic;
lcd_rs : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal new_character : std_logic := '0';
signal new_pos : std_logic := '0';
--Outputs
signal lcd_db : std_logic_vector(7 downto 0);
signal lcd_en : std_logic;
signal lcd_rs : std_logic;
signal busy : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lcd_driver PORT MAP (
clk => clk,
reset => reset,
data => data,
new_character => new_character,
new_pos => new_pos,
lcd_db => lcd_db,
lcd_en => lcd_en,
lcd_rs => lcd_rs,
busy => busy
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 100 ns; -- hold reset state for 100 ns.
reset <= '0';
wait for 50ms;
-- test sending character
data <= "11111111";
new_character <= '1';
new_pos <= '0';
wait until busy = '0';
wait for 10ms;
-- test sending character
data <= "10101010";
new_character <= '0';
new_pos <= '1';
wait until busy = '0';
wait for 10ms;
-- Reset
data <= "00000000";
new_character <= '0';
new_pos <= '0';
wait;
end process;
END;
|
7890
htns
1234
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.3 2005/07/19 07:13:17 wig Exp $
-- $Date: 2005/07/19 07:13:17 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:17 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : John Doe (Developper Company JohnDoeCompany on behalf of ContractorBigcompany )
-- Copyright : Copyright (c) CNES.
-- Licensing : This VHDL entity can be licensed to be be used in the frame of CNES contracts.
-- Ask CNES for an end-user license agreement (EULA).
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : yyyy-mm-dd : Author name's John Doe (JohnDoeCompany): Creation
-- V2 : yyyy-mm-dd : Author name's John Toe (JohnToeCompany):
-- Modification description
-- Modifications impacts
-- Modifications reasons
-------------------------------------------------------------------------------------------------
-- File name : header.vhd
-- File Creation date : yyyy-mm-dd
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : PC (OS version) - Editor (Version) - Synthetizer (Version) - P&R (Version)
-- Automatic VHDL coding : YES/NO
-- Tool used + Version
-- Source file information
-------------------------------------------------------------------------------------------------
-- Description : Relevant information related to this entity
--
-- Limitations : Hypothesis/constraints made on the external interfaces or configuration
-- that will impact this entity
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity header is
port (
);
end header;
architecture Behavioral of header is
begin
-- Behavioral code of header
end Behavioral; |
--------------------------------------------------------------------------------
--|
--| Filename : uart_bhv
--| Author : Russell L Friesenhahn
--| Origin Date : 20130828
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--| Behavorial architecture of UART core
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
architecture bhv of uart is
-----------------------------
-- Component Declarations
-----------------------------
component cntr is
generic (
CntrWidth : integer := 8
);
port (
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
Clr : in std_ulogic;
CritValue : in std_ulogic_vector(CntrWidth-1 downto 0);
CntrValue : out std_ulogic_vector(CntrWidth-1 downto 0);
CntReached : out std_ulogic
);
end component;
-----------------------------
-- Constant Declarations
-----------------------------
-- constant clk16Gen : integer := SysClkRate / BaudRate / 16;
-----------------------------
-- Type Declarations
-----------------------------
type rxst is (
IDLE,
START,
RX,
PARITYCK,
STOP,
ERR
);
type txst is (
IDLE,
START,
TX,
TXPARITY,
STOP
);
-----------------------------
-- Signal Declarations
-----------------------------
signal clkCntr : unsigned(19 downto 0);
signal clkTxCntr : unsigned(23 downto 0);
-- signal clkTxGen : unsigned(23 downto 0);
signal clkTxGen : std_ulogic_vector(23 downto 0);
signal ClkTxPulse : std_ulogic;
signal startTxCntr : std_ulogic;
signal clk16Pulse : std_ulogic;
signal rxcs : rxst;
signal din_d0 : std_ulogic;
signal din_d1 : std_ulogic;
signal din_d2 : std_ulogic;
signal clk16Cnt : unsigned(3 downto 0);
-- signal dout_int : std_ulogic_vector(7 downto 0);
signal rxCnt : unsigned(3 downto 0);
signal dout_i : std_ulogic_vector(7 downto 0);
signal parity : std_ulogic;
signal txcs : txst;
signal bitTxParity : std_ulogic;
signal txCnt : unsigned(2 downto 0);
signal byteRx_d1 : std_ulogic_vector(7 downto 0);
signal byteRx_d2 : std_ulogic_vector(7 downto 0);
signal byteRxValid_d1 : std_ulogic;
signal txBusy_i : std_ulogic;
begin
ByteTx <= dout_i;
TxBusy <= txBusy_i;
clkTxGen <= BaudRateGen & X"0";
cntr_tx : cntr
generic map (
CntrWidth => 24
)
port map (
Clk => Clk,
Rst => Rst,
En => '1',
Clr => startTxCntr,
CritValue => clkTxGen,
CntrValue => open,
CntReached => ClkTxPulse
);
P_TX : process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
BitTx <= '1';
txBusy_i <= '1';
clkTxCntr <= (others => '0');
byteRxValid_d1 <= '0';
startTxCntr <= '0';
else
if ByteRxValid = '1' and txBusy_i = '0' then
byteRx_d1 <= ByteRx;
byteRxValid_d1 <= ByteRxValid;
txBusy_i <= '1';
end if;
C_TX : case txcs is
when IDLE =>
txBusy_i <= '0';
BitTx <= '1';
bitTxParity <= ParityType;
txCnt <= (others => '0');
if byteRxValid_d1 = '1' then
byteRx_d2 <= byteRx_d1;
startTxCntr <= '1';
txBusy_i <= '1';
txcs <= START;
byteRxValid_d1 <= '0';
end if;
when START =>
startTxCntr <= '0';
BitTx <= '0';
if ClkTxPulse = '1' then
txcs <= TX;
BitTx <= byteRx_d1(0);
bitTxParity <= bitTxParity xor byteRx_d1(0);
txCnt <= txCnt + 1;
end if;
when TX =>
if ClkTxPulse = '1' then
if txCnt = to_unsigned(0, txCnt'length) then
BitTx <= bitTxParity;
txcs <= TXPARITY;
else
BitTx <= byteRx_d1(to_integer(txCnt));
bitTxParity <= bitTxParity xor byteRx_d1(to_integer(txCnt));
txCnt <= txCnt + 1;
end if;
end if;
when TXPARITY =>
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= STOP;
end if;
when STOP =>
txBusy_i <= '0';
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= IDLE;
end if;
when others => null;
end case C_TX;
end if;
end if;
end process P_TX;
CLK16_PULSE_GEN : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clkCntr <= (others => '0');
clk16Pulse <= '0';
else
-- if clkCntr = to_unsigned(clk16Gen, clkCntr'length)
if clkCntr = unsigned(BaudRateGen)
then
clkCntr <= (others => '0');
clk16Pulse <= '1';
else
clkCntr <= clkCntr + 1;
clk16Pulse <= '0';
end if;
end if;
end if;
end process CLK16_PULSE_GEN;
P_STABLE_DATA : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
din_d0 <= '0';
din_d1 <= '0';
din_d2 <= '0';
else
din_d2 <= din_d1;
din_d1 <= din_d0;
din_d0 <= BitRx;
end if;
end if;
end process P_STABLE_DATA;
P_CLK16_CNTR : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clk16Cnt <= (others => '0');
else
if clk16Pulse = '1'
then
clk16Cnt <= clk16Cnt + 1;
end if;
if din_d1 /= din_d2
then
clk16Cnt <= (others => '0');
end if;
end if;
end if;
end process P_CLK16_CNTR;
P_RX : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
rxcs <= IDLE;
dout_i <= (others => '0');
ParErr <= '0';
StopErr <= '0';
else
CO_RX_SM : case rxcs is
when IDLE =>
ByteTxValid <= '0';
rxCnt <= (others => '0');
parity <= ParityType;
if din_d1 = '0'
and din_d2 = '1'
then
rxcs <= START;
end if;
when START =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '0'
then
rxcs <= RX;
else
rxcs <= IDLE;
end if;
end if;
when RX =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
rxCnt <= rxCnt + 1;
end if;
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
dout_i <= din_d2 & dout_i(7 downto 1);
parity <= parity xor din_d2;
end if;
if rxCnt = to_unsigned(8, 4)
then
if UseParity = '1'
then
rxcs <= PARITYCK;
else
rxcs <= STOP;
end if;
end if;
when PARITYCK =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if parity /= din_d2
then
ParErr <= '1';
rxcs <= ERR;
assert false
report "ERROR: parity incorrect"
severity error;
else
rxcs <= STOP;
end if;
end if;
when STOP =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '1'
then
ByteTxValid <= '1';
rxcs <= IDLE;
else
StopErr <= '1';
rxcs <= ERR;
end if;
end if;
when ERR =>
ParErr <= '0';
StopErr <= '0';
rxcs <= IDLE;
end case;
end if;
end if;
end process P_RX;
end architecture bhv;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_437;
architecture augh of sub_437 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_437;
architecture augh of sub_437 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:00 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top zqynq_lab_1_design_auto_pc_2 -prefix
-- zqynq_lab_1_design_auto_pc_2_ zqynq_lab_1_design_auto_pc_1_stub.vhdl
-- Design : zqynq_lab_1_design_auto_pc_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zqynq_lab_1_design_auto_pc_2 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_2;
architecture stub of zqynq_lab_1_design_auto_pc_2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
begin
end;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram.vhd when simulating
-- the core, ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram;
ARCHITECTURE ram_a OF ram IS
-- synthesis translate_off
COMPONENT wrapped_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END ram_a;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end des_round;
architecture Behavioral of des_round is
component f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end component;
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
signal f_out_s : std_logic_vector(31 downto 0);
begin
F_FUN_0 : f_fun port map (clk, r_0, k_i, f_out_s);
l_1 <= r_0;
r_1 <= l_0 xor f_out_s;
end Behavioral;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: clock_gen.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:20:50 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for clock generator
--
entity clock_gen is
generic (Tpw : Time; -- clock pulse width
Tps : Time; -- clock pulse separation
tag : string := "";
origin_x, origin_y : real := 0.0);
port (phi1, phi2 : out bit; -- two-phase non-overlapping clocks
reset : out bit); -- synchronous reset
end clock_gen;
|
-- Automatically generated: write_netlist -wrapapp -vhdl -module reconflogic-wrapmax6682.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MyReconfigLogic is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end MyReconfigLogic;
architecture WrapMAX6682 of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgMode_o : out std_logic;
CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgDataOut_o : out std_logic;
CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0)
);
end component;
component MAX6682
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component ParamIntf
generic (
WrAddrWidth : integer range 1 to 15 := 4;
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end component;
component ParamOutReg
generic (
Width : integer := 16
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
ParamWrData_i : in std_logic_vector(Width-1 downto 0);
Param_o : out std_logic_vector(Width-1 downto 0)
);
end component;
signal PeriodCounterPresetH_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_s : std_logic_vector(15 downto 0);
signal SensorValue_s : std_logic_vector(15 downto 0);
signal Threshold_s : std_logic_vector(15 downto 0);
signal CfgClk_s : std_logic_vector(0 downto 0);
signal CfgMode_s : std_logic;
signal CfgShift_s : std_logic_vector(0 downto 0);
signal CfgDataOut_s : std_logic;
signal CfgDataIn_s : std_logic_vector(0 downto 0);
signal ParamWrAddr_s : std_logic_vector(2 downto 0);
signal ParamWrData_s : std_logic_vector(15 downto 0);
signal ParamWr_s : std_logic;
signal ParamRdAddr_s : std_logic_vector(0 downto 0);
signal ParamRdData_s : std_logic_vector(15 downto 0);
type Params_t is array(0 to 1) of std_logic_vector(15 downto 0);
signal Params_s : Params_t;
signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0);
signal ParamI2C_Divider800Enable_s : std_logic;
signal ParamI2C_ErrAckParamEnable_s : std_logic;
signal ParamPeriodCounterPresetHEnable_s : std_logic;
signal ParamPeriodCounterPresetLEnable_s : std_logic;
signal ParamThresholdEnable_s : std_logic;
begin
-- Configuration Interface
CfgIntf_0: CfgIntf
generic map (
BaseAddr => 16#0180#,
NumCfgs => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => CfgIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
CfgClk_o => CfgClk_s,
CfgMode_o => CfgMode_s,
CfgShift_o => CfgShift_s,
CfgDataOut_o => CfgDataOut_s,
CfgDataIn_i => CfgDataIn_s
);
-- Parameterization Interface: 5 write addresses, 2 read addresses
ParamIntf_0: ParamIntf
generic map (
BaseAddr => 16#0188#,
WrAddrWidth => 3,
RdAddrWidth => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => ParamIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
ParamWrAddr_o => ParamWrAddr_s,
ParamWrData_o => ParamWrData_s,
ParamWr_o => ParamWr_s,
ParamRdAddr_o => ParamRdAddr_s,
ParamRdData_i => ParamRdData_s
);
MAX6682_0: MAX6682
port map (
MAX6682CS_n_o => Outputs_o(0),
CpuIntr_o => ReconfModuleIRQs_o(0),
SPI_Data_o => SPI_DataIn_o,
SPI_Data_i => SPI_DataOut_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Transmission_i => SPI_Transmission_i,
SPI_Write_o => SPI_Write_o,
Enable_i => ReconfModuleIn_i(0),
Clk_i => Clk_i,
Reset_n_i => Reset_n_i,
PeriodCounterPresetH_i => PeriodCounterPresetH_s,
PeriodCounterPresetL_i => PeriodCounterPresetL_s,
SensorValue_o => SensorValue_s,
Threshold_i => Threshold_s
);
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReadCount_o <= "0000";
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
Outputs_o(1) <= '0';
Outputs_o(2) <= '0';
Outputs_o(3) <= '0';
Outputs_o(4) <= '0';
Outputs_o(5) <= '0';
Outputs_o(6) <= '0';
Outputs_o(7) <= '0';
ReconfModuleIRQs_o(1) <= '0';
ReconfModuleIRQs_o(2) <= '0';
ReconfModuleIRQs_o(3) <= '0';
ReconfModuleIRQs_o(4) <= '0';
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_LSBFE_o <= '0';
SPI_SPPR_SPR_o <= "00000000";
ReconfModuleOut_o(0) <= '0';
ReconfModuleOut_o(1) <= '0';
ReconfModuleOut_o(2) <= '0';
ReconfModuleOut_o(3) <= '0';
ReconfModuleOut_o(4) <= '0';
ReconfModuleOut_o(5) <= '0';
ReconfModuleOut_o(6) <= '0';
ReconfModuleOut_o(7) <= '0';
-- just a fixed value for the config interface
CfgDataIn_s <= "0";
-- Param read address decoder
-- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
-- hope that the synthesis optimizes the MUX
-- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
-- 0 to n.", even during param write cycles, because ParamRdAddr has the
-- source as ParamWrAddr. Use the parameter "-noindexcheck" during
-- compilation ("vcom"). Simulation works fine then, but ModelSim generates
-- numerous "INTERNAL ERROR"s to stdout, which seem harmless.
ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s)));
ParamOutReg_I2C_Divider800: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_Divider800_o,
Enable_i => ParamI2C_Divider800Enable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_I2C_ErrAckParam: ParamOutReg
generic map (
Width => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_ErrAckParam_s,
Enable_i => ParamI2C_ErrAckParamEnable_s,
ParamWrData_i => ParamWrData_s(0 downto 0)
);
ParamOutReg_PeriodCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetH_s,
Enable_i => ParamPeriodCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetL_s,
Enable_i => ParamPeriodCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_Threshold: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => Threshold_s,
Enable_i => ParamThresholdEnable_s,
ParamWrData_i => ParamWrData_s
);
I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0);
-- Address $00
Params_s(0) <= "00000000" & I2C_Errors_i;
-- Address $01
Params_s(1) <= SensorValue_s;
-- Address $00
ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else
'0';
-- Address $01
ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else
'0';
-- Address $02
ParamPeriodCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else
'0';
-- Address $03
ParamPeriodCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else
'0';
-- Address $04
ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else
'0';
end WrapMAX6682;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity mux_1hot_inferred is
generic (
data_bits : natural := 1;
sel_bits : natural := 2
);
port (
din : in std_ulogic_vector2(sel_bits-1 downto 0, data_bits-1 downto 0);
sel : in std_ulogic_vector(sel_bits-1 downto 0);
dout : out std_ulogic_vector(data_bits-1 downto 0)
);
end;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: support@gaisler.com
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc48.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00048ent IS
END c04s03b01x01p03n02i00048ent;
ARCHITECTURE c04s03b01x01p03n02i00048arch OF c04s03b01x01p03n02i00048ent IS
constant test: integer := 10; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00048 - The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p03n02i00048arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc48.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00048ent IS
END c04s03b01x01p03n02i00048ent;
ARCHITECTURE c04s03b01x01p03n02i00048arch OF c04s03b01x01p03n02i00048ent IS
constant test: integer := 10; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00048 - The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p03n02i00048arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc48.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00048ent IS
END c04s03b01x01p03n02i00048ent;
ARCHITECTURE c04s03b01x01p03n02i00048arch OF c04s03b01x01p03n02i00048ent IS
constant test: integer := 10; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00048 - The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p03n02i00048arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.ml50x.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int : std_ulogic := '1';
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal sysace_clk_in : std_ulogic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_dvi <= 'H'; iic_sda_dvi <= 'H';
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, clk_200_p, clk_200_n, sysace_clk_in,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_oen,
sram_flash_we_n, flash_cen, flash_oen, flash_adv_n,sram_clk,
sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_dvi, iic_sda_dvi,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
-- ddr2mem : for i in 0 to 3 generate
-- u1 : ddr2
-- PORT MAP(
-- ck => ddr_clk(0), ck_n => ddr_clkb(0), cke => ddr_cke(0), cs_n => ddr_csb(0),
-- ras_n => ddr_rasb, cas_n => ddr_casb, we_n => ddr_web,
-- dm_rdqs => ddr_dm(i*2+1 downto i*2), ba => ddr_ba,
-- addr => ddr_ad(12 downto 0), dq => ddr_dq(i*16+15 downto i*16),
-- dqs => ddr_dqsp(i*2+1 downto i*2), dqs_n => ddr_dqsn(i*2+1 downto i*2),
-- rdqs_n => ddr_rdqs(i*2+1 downto i*2), odt => ddr_odt(0));
-- end generate;
ddr2ranks: for j in 0 to CS_NUM-1 generate
-- ddr2chips: for i in 0 to 3 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2),
-- LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1),
-- UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2),
-- WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(j),
-- BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(j),
-- CLK => ddr_clk(j), CLKB => ddr_clkb(j), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>0, density => 2,
lddelay => 100 us * CFG_MIG_DDR2)
port map (ck => ddr_clk(j), ckn => ddr_clkb(j), cke => ddr_cke(j), csn => ddr_csb(j),
odt => ddr_odt(j), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqsp, dqsn =>ddr_dqsn);
end generate;
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 4.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
-- p0: phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:34:40 03/09/2015
-- Design Name:
-- Module Name: DIV_FREC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity div_frec is
Generic ( SAT_BPSK : integer := 650;
SAT_QPSK : integer := 650;
SAT_8PSK : integer := 650 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
sat : out STD_LOGIC);
end div_frec;
architecture Behavioral of div_frec is
type estado is ( reposo,
inicio,
activo );
signal estado_actual : estado;
signal estado_nuevo : estado;
signal cuenta, p_cuenta : integer ;--range 0 to SAT_BPSK;
begin
comb : process ( cuenta, estado_actual, button, modulation )
begin
sat <= '0';
p_cuenta <= cuenta;
estado_nuevo <= estado_actual;
case estado_actual is
when reposo =>
if ( button = '1' ) then
estado_nuevo <= inicio;
end if;
when inicio =>
case modulation is
when "100" =>
p_cuenta <= SAT_BPSK;
when "010" =>
p_cuenta <= SAT_QPSK;
when OTHERS =>
p_cuenta <= SAT_8PSK;
end case;
estado_nuevo <= activo;
when activo =>
if ( cuenta = 0 ) then
estado_nuevo <= inicio;
sat <= '1';
else
p_cuenta <= cuenta -1;
end if;
end case;
end process;
sinc : process(clk, reset)
begin
if ( reset = '1' ) then
cuenta <= 0;
estado_actual <= reposo;
elsif ( rising_edge(clk) ) then
cuenta <= p_cuenta;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_decode.all;
-- this module puts the alu, shifter and bit/compare unit together
entity data_oper is
generic (
support_bcd : boolean := true );
port (
inst : in std_logic_vector(7 downto 0);
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
i_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
a_reg : in std_logic_vector(7 downto 0);
x_reg : in std_logic_vector(7 downto 0);
y_reg : in std_logic_vector(7 downto 0);
s_reg : in std_logic_vector(7 downto 0);
alu_sel_o : out std_logic_vector(1 downto 0);
alu_out : out std_logic_vector(7 downto 0);
mem_out : out std_logic_vector(7 downto 0);
mem_c : out std_logic;
mem_n : out std_logic;
mem_z : out std_logic;
impl_out : out std_logic_vector(7 downto 0);
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
flags_imm : out std_logic;
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
d_out : out std_logic;
i_out : out std_logic );
end data_oper;
architecture gideon of data_oper is
signal shift_sel : std_logic_vector(1 downto 0) := "00";
signal shift_din : std_logic_vector(7 downto 0) := X"00";
signal shift_dout: std_logic_vector(7 downto 0) := X"00";
signal alu_sel : std_logic_vector(1 downto 0) := "00";
signal alu_data_a: std_logic_vector(7 downto 0) := X"00";
signal alu_out_i : std_logic_vector(7 downto 0) := X"00";
signal row0_n : std_logic;
signal row0_v : std_logic;
signal row0_z : std_logic;
signal row0_c : std_logic;
signal shft_n : std_logic;
signal shft_z : std_logic;
signal shft_c : std_logic;
signal alu_n : std_logic;
signal alu_v : std_logic;
signal alu_z : std_logic;
signal alu_c : std_logic;
signal impl_n : std_logic;
signal impl_z : std_logic;
signal impl_c : std_logic;
signal impl_v : std_logic;
signal n, z : std_logic;
signal shift_en : std_logic;
signal alu_en : std_logic;
signal full_carry : std_logic := '0';
signal half_carry : std_logic := '0';
signal bypass_shift : std_logic;
signal flag_select : t_result_select;
begin
shift_en <= '1' when is_shift(inst) else '0';
alu_en <= '1' when is_alu(inst) else '0';
bypass_shift <= do_bypass_shift(inst);
flag_select <= flags_from(inst);
shift_sel <= shifter_in_select(inst);
with shift_sel select shift_din <=
data_in when "01",
a_reg when "10",
data_in and a_reg when "11",
data_in and (a_reg or X"EE") when others; -- for LAX #$
alu_sel(0) <= '1' when x_to_alu(inst) else '0';
alu_sel(1) <= shift_sel(0) and shift_sel(1);
with alu_sel select alu_data_a <=
a_reg and x_reg when "01",
a_reg and data_in when "10",
a_reg and x_reg and data_in when "11",
a_reg when others;
alu_sel_o <= alu_sel;
i_row0: entity work.bit_cpx_cpy
port map (
operation => inst(7 downto 5),
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
n_out => row0_n,
v_out => row0_v,
z_out => row0_z,
c_out => row0_c );
i_shft: entity work.shifter
port map (
operation => inst(7 downto 5),
bypass => bypass_shift,
c_in => c_in,
n_in => n_in,
z_in => z_in,
data_in => shift_din,
c_out => shft_c,
n_out => shft_n,
z_out => shft_z,
data_out => shift_dout );
i_alu: entity work.alu
generic map (
support_bcd => support_bcd )
port map (
operation => inst(7 downto 5),
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
data_a => alu_data_a,
data_b => shift_din,
n_out => alu_n,
v_out => alu_v,
z_out => alu_z,
c_out => alu_c,
half_carry => half_carry,
full_carry => full_carry,
data_out => alu_out_i );
mem_out <= shift_dout;
p_bcd_fixer: process(shift_dout, alu_out_i, d_in, shift_en, alu_en, inst, full_carry, half_carry)
variable sum_l : unsigned(3 downto 0);
variable sum_h : unsigned(3 downto 0);
begin
if shift_en = '1' then
sum_h := unsigned(shift_dout(7 downto 4));
sum_l := unsigned(shift_dout(3 downto 0));
else
sum_h := unsigned(alu_out_i(7 downto 4));
sum_l := unsigned(alu_out_i(3 downto 0));
end if;
n <= sum_h(3);
if sum_h = "0000" and sum_l = "0000" then
z <= '1';
else
z <= '0';
end if;
if d_in='1' and support_bcd then
if alu_en = '1' then
if inst(7 downto 5)="011" then -- ADC
if half_carry = '1' then
sum_l := sum_l + 6;
end if;
if full_carry = '1' then
sum_h := sum_h + 6;
end if;
elsif inst(7 downto 5)="111" then -- SBC
if half_carry = '0' then
sum_l := sum_l - 6;
end if;
if full_carry = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
end if;
alu_out <= std_logic_vector(sum_h) & std_logic_vector(sum_l);
end process;
i_impl: entity work.implied
port map (
inst => inst,
c_in => c_in,
i_in => i_in,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => a_reg,
reg_x => x_reg,
reg_y => y_reg,
reg_s => s_reg,
data_in => data_in,
flags_imm => flags_imm,
i_out => i_out,
d_out => d_out,
c_out => impl_c,
n_out => impl_n,
z_out => impl_z,
v_out => impl_v,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => impl_out );
process(flag_select,
n_in, v_in, z_in, c_in,
impl_n, impl_v, impl_z, impl_c,
row0_n, row0_v, row0_z, row0_c,
alu_n, alu_v, alu_z, alu_c,
shft_n, shft_z, shft_c, n, z )
begin
case flag_select is
when alu =>
n_out <= n;
v_out <= alu_v;
z_out <= z;
c_out <= alu_c;
when impl =>
n_out <= impl_n;
v_out <= impl_v;
z_out <= impl_z;
c_out <= impl_c;
when row0 =>
n_out <= row0_n;
v_out <= row0_v;
z_out <= row0_z;
c_out <= row0_c;
when shift =>
n_out <= n;
v_out <= v_in;
z_out <= z;
c_out <= shft_c;
when others =>
n_out <= n_in;
v_out <= v_in;
z_out <= z_in;
c_out <= c_in;
end case;
end process;
mem_c <= shft_c;
mem_z <= shft_z;
mem_n <= shft_n;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.cu.all;
entity cu_test is
end cu_test;
architecture TEST of cu_test is
component CU_UP is
port (
-- Inputs
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset:Active-Low
IR : in std_logic_vector(31 downto 0);
JMP_PREDICT : in std_logic; -- Jump Prediction
JMP_REAL : in std_logic; -- Jump real condition
ICACHE_STALL: in std_logic; -- The WRF is busy
WRF_STALL: in std_logic; -- The WRF is busy
-- Outputs
MUXBOOT_CTR: out std_logic;
PIPEREG1_ENABLE: out std_logic;
MUXRD_CTR: out std_logic;
WRF_ENABLE: out std_logic;
WRF_CALL: out std_logic;
WRF_RET: out std_logic;
WRF_RS1_ENABLE: out std_logic;
WRF_RS2_ENABLE: out std_logic;
WRF_RD_ENABLE: out std_logic;
WRF_MEM_BUS: out std_logic;
WRF_MEM_CTR: out std_logic;
PIPEREG2_ENABLE: out std_logic;
MUXA_CTR: out std_logic;
MUXB_CTR: out std_logic;
ALU_FUNC: out std_logic_vector(1 downto 0);
PIPEREG3_ENABLE: out std_logic;
MUXC_CTR: out std_logic;
MEMORY_ENABLE: out std_logic;
MEMORY_RNOTW: out std_logic;
PIPEREG4_ENABLE: out std_logic;
MUXWB_CTR: out std_logic
);
end component;
-- Inputs
signal Clk : std_logic := '0'; -- Clock
signal Rst : std_logic; -- Reset:Active-Low
signal IR : std_logic_vector(31 downto 0);
signal JMP_PREDICT : std_logic; -- Jump Prediction
signal JMP_REAL : std_logic; -- Jump real condition
signal ICACHE_STALL: std_logic; -- Instruction cache stall
signal WRF_STALL: std_logic; -- The WRF is busy
-- Outputs
signal MUXBOOT_CTR: std_logic;
signal PIPEREG1_ENABLE: std_logic;
signal MUXRD_CTR: std_logic;
signal WRF_ENABLE: std_logic;
signal WRF_CALL: std_logic;
signal WRF_RET: std_logic;
signal WRF_RS1_ENABLE: std_logic;
signal WRF_RS2_ENABLE: std_logic;
signal WRF_RD_ENABLE: std_logic;
signal WRF_MEM_BUS: std_logic;
signal WRF_MEM_CTR: std_logic;
signal PIPEREG2_ENABLE: std_logic;
signal MUXA_CTR: std_logic;
signal MUXB_CTR: std_logic;
signal ALU_FUNC: std_logic_vector(1 downto 0);
signal PIPEREG3_ENABLE: std_logic;
signal MUXC_CTR: std_logic;
signal MEMORY_ENABLE: std_logic;
signal MEMORY_RNOTW: std_logic;
signal PIPEREG4_ENABLE: std_logic;
signal MUXWB_CTR: std_logic;
begin
-- instance of DLX
dut: CU_UP
port map (Clk, Rst, IR, JMP_PREDICT, JMP_REAL, ICACHE_STALL, WRF_STALL, MUXBOOT_CTR, PIPEREG1_ENABLE, MUXRD_CTR, WRF_ENABLE, WRF_CALL, WRF_RET, WRF_RS1_ENABLE, WRF_RS2_ENABLE, WRF_RD_ENABLE, WRF_MEM_BUS, WRF_MEM_CTR, PIPEREG2_ENABLE, MUXA_CTR, MUXB_CTR ,ALU_FUNC, PIPEREG3_ENABLE, MUXC_CTR,MEMORY_ENABLE, MEMORY_RNOTW, PIPEREG4_ENABLE ,MUXWB_CTR);
Clk <= not Clk after 10 ns;
Rst <= '0', '1' after 5 ns;
CONTROL: process(Clk)
begin
IR <= ITYPE_ADD & "00000000000000000000000000";
end process;
end test;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 - 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : ddrram
generic map(width => 16, abits => 14, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n,
rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n,
dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d,
dqs => ram_dqs);
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_64i_16o_s6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(16-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(14-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_64i_16o_s6_top;
architecture xilinx of afifo_64i_16o_s6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_64i_16o_s6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_64i_16o_s6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
entity mul32 is
generic (
infer : integer range 0 to 1 := 1;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (rst = '0') then v.nready := '0'; v.ready := '0'; v.state := "00"; v.start := '0'; end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
i0 : if (infer = 1) and (pipe = 0) generate
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end generate;
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end if;
end if;
end process;
end generate;
i2 : if infer = 0 generate
m0 : mul_17_17
generic map (pipe)
port map (clk, holdn, ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
i0 : if infer = 1 generate
prod(41 downto 0) <= smult (ma(32 downto 0), mb(8 downto 0));
end generate;
i1 : if infer = 0 generate
m0 : mul_33_9
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
i1 : if infer = 1 generate
prod(49 downto 0) <= smult (ma(32 downto 0), mb(16 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_17
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end if;
end if;
end process;
end generate;
i0 : if (infer = 1) and (pipe = 0) generate
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_33 generic map (pipe)
port map (clk, holdn, ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then -- needed to preserve sync resets in synopsys ...
rm.nready <= '0'; rm.ready <= '0'; rm.state <= "00"; rm.start <= '0';
end if;
end if;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
entity mul32 is
generic (
infer : integer range 0 to 1 := 1;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (rst = '0') then v.nready := '0'; v.ready := '0'; v.state := "00"; v.start := '0'; end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
i0 : if (infer = 1) and (pipe = 0) generate
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end generate;
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end if;
end if;
end process;
end generate;
i2 : if infer = 0 generate
m0 : mul_17_17
generic map (pipe)
port map (clk, holdn, ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
i0 : if infer = 1 generate
prod(41 downto 0) <= smult (ma(32 downto 0), mb(8 downto 0));
end generate;
i1 : if infer = 0 generate
m0 : mul_33_9
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
i1 : if infer = 1 generate
prod(49 downto 0) <= smult (ma(32 downto 0), mb(16 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_17
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end if;
end if;
end process;
end generate;
i0 : if (infer = 1) and (pipe = 0) generate
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_33 generic map (pipe)
port map (clk, holdn, ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then -- needed to preserve sync resets in synopsys ...
rm.nready <= '0'; rm.ready <= '0'; rm.state <= "00"; rm.start <= '0';
end if;
end if;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_types.all;
-- use PoC.sim_random.all;
use PoC.simulation.all;
package waveform is
-- clock generation
-- ===========================================================================
procedure simGenerateClock(
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive);
procedure simGenerateClock2(constant TestID : in T_SIM_TEST_ID; signal Clock : out std_logic; signal Debug : out REAL; constant Period : in time);
-- waveform description
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : time;
Value : std_logic;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : time;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : time;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : time;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : time;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : time;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : time;
Value : T_SLV_64;
end record;
subtype T_SIM_WAVEFORM is TIME_VECTOR; -- use predefined physical type TIME here
type T_SIM_WAVEFORM_SL is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
-- waveform generation procedures
-- ===========================================================================
-- TODO: get initial value from Waveform(0) if .Delay = o fs, otherwise use (others => 'U') ?
procedure simGenerateWaveform(
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
);
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
);
function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM;
function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM;
function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM;
function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8;
function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8;
function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16;
function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16;
function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24;
function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24;
function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32;
function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32;
function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48;
function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48;
function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64;
function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64;
-- convert arrays to waveforms
-- TODO: optimize waveform if input data doesn't change
-- TODO: write single bit variant
function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM;
function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL;
function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8;
function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16;
function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24;
function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32;
function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48;
function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64;
-- predefined common waveforms
function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
end package;
package body waveform is
-- clock generation
-- ===========================================================================
procedure simGenerateClock(
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant Period : time := to_time(Frequency);
begin
simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant Period : time := to_time(Frequency);
begin
simGenerateClock(TestID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
begin
simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
constant Delay : time := Period * PhaseAsFactor;
constant TimeHigh : time := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
constant TimeLow : time := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
constant ClockAfterRun_cy : positive := 5;
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateClock(period=" & to_string(Period, 2) & ")", IsLowPriority => TRUE);
begin
-- report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & LF &
-- "Period: " & TIME'image(Period) & LF &
-- "Phase: " & T_PHASE'image(Phase) & LF &
-- "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & LF &
-- "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & LF &
-- "WanderAsFactor: " & REAL'image(WanderAsFactor) & LF &
-- "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & LF &
-- "Delay: " & TIME'image(Delay) & LF &
-- "TimeHigh: " & TIME'image(TimeHigh) & LF &
-- "TimeLow: " & TIME'image(TimeLow)
-- severity NOTE;
if (Delay = 0 ns) then
null;
elsif (Delay <= TimeLow) then
Clock <= '0';
wait for Delay;
else
Clock <= '1';
wait for Delay - TimeLow;
Clock <= '0';
wait for TimeLow;
end if;
Clock <= '1';
while not simIsStopped(TestID) loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
simDeactivateProcess(PROCESS_ID);
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
type T_SIM_NORMAL_DIST_PARAMETER is record
StandardDeviation : REAL;
Mean : REAL;
end record;
type T_JITTER_DISTRIBUTION is array (natural range <>) of T_SIM_NORMAL_DIST_PARAMETER;
procedure simGenerateClock2(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
signal Debug : out REAL;
constant Period : in time
) is
constant TimeHigh : time := Period * 0.5;
constant TimeLow : time := Period - TimeHigh;
constant JitterPeakPeak : REAL := 0.1; -- UI
constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
constant JitterDistribution : T_JITTER_DISTRIBUTION := (
-- 0 => (StandardDeviation => 0.2, Mean => -0.4),
-- 1 => (StandardDeviation => 0.2, Mean => 0.4)
-- 0 => (StandardDeviation => 0.2, Mean => -0.4),
-- 1 => (StandardDeviation => 0.3, Mean => -0.1),
-- 2 => (StandardDeviation => 0.5, Mean => 0.0),
-- 3 => (StandardDeviation => 0.3, Mean => 0.1),
-- 4 => (StandardDeviation => 0.2, Mean => 0.4)
0 => (StandardDeviation => 0.15, Mean => -0.6),
1 => (StandardDeviation => 0.2, Mean => -0.3),
2 => (StandardDeviation => 0.25, Mean => -0.2),
3 => (StandardDeviation => 0.3, Mean => 0.0),
4 => (StandardDeviation => 0.25, Mean => 0.2),
5 => (StandardDeviation => 0.2, Mean => 0.3),
6 => (StandardDeviation => 0.15, Mean => 0.6)
);
variable Seed : T_SIM_RAND_SEED;
variable rand : REAL;
variable Jitter : REAL;
variable Index : natural;
constant ClockAfterRun_cy : positive := 5;
begin
Clock <= '1';
randInitializeSeed(Seed);
while not simIsStopped(TestID) loop
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
Index := scale(rand, 0, JitterDistribution'length * 10) mod JitterDistribution'length;
randNormalDistributedValue(Seed, rand, JitterDistribution(Index).StandardDeviation, JitterDistribution(Index).Mean, -1.0, 1.0);
Jitter := JitterAsFactor * rand;
Debug <= rand;
-- Debug <= integer(rand * 256.0 + 256.0);
wait for TimeHigh + (Period * Jitter);
Clock <= '0';
wait for TimeLow + (Period * Jitter);
Clock <= '1';
end loop;
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive) is
begin
simWaitUntilRisingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times);
end procedure;
procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is
begin
for i in 1 to Times loop
wait until rising_edge(Clock);
exit when simIsStopped(TestID);
end loop;
end procedure;
procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive) is
begin
simWaitUntilFallingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times);
end procedure;
procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is
begin
for i in 1 to Times loop
wait until falling_edge(Clock);
exit when simIsStopped(TestID);
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
variable State : boolean;
begin
State := InitialValue;
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
variable State : std_logic;
begin
State := InitialValue;
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
-- Waveform arithmetic
function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is
begin
return (Wave(Wave'low) + Offset) & Wave(Wave'low + 1 to Wave'high);
end function;
function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(Wave'range);
variable TimePos : time;
begin
report "Has bugs" severity ERROR;
TimePos := 0 fs;
for i in Wave'range loop
TimePos := TimePos + Wave(i);
if TimePos > Offset then
return (TimePos - Offset) & Wave(i + 1 to Wave'high);
end if;
end loop;
return (0 => 0 fs);
end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8 is
variable Result : T_SIM_WAVEFORM_SLV_8(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_8'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16 is
variable Result : T_SIM_WAVEFORM_SLV_16(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_16'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24 is
variable Result : T_SIM_WAVEFORM_SLV_24(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_24'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32 is
variable Result : T_SIM_WAVEFORM_SLV_32(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_32'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48 is
variable Result : T_SIM_WAVEFORM_SLV_48(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_48'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64 is
variable Result : T_SIM_WAVEFORM_SLV_64(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_64'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(0 to bv'length - 1);
begin
report "Has bugs" severity ERROR;
for i in 0 to bv'length - 1 loop
Result(i) := Delay;
end loop;
return Result;
end function;
function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to slv'length - 1);
begin
for i in 0 to slv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8 is
variable Result : T_SIM_WAVEFORM_SLV_8(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16 is
variable Result : T_SIM_WAVEFORM_SLV_16(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24 is
variable Result : T_SIM_WAVEFORM_SLV_24(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32 is
variable Result : T_SIM_WAVEFORM_SLV_32(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48 is
variable Result : T_SIM_WAVEFORM_SLV_48(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64 is
variable Result : T_SIM_WAVEFORM_SLV_64(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
-- predefined common waveforms
function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM is
variable p : time;
variable rp : time;
begin
-- WORKAROUND: for Mentor QuestaSim/ModelSim
-- Version: 10.4c
-- Issue:
-- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
-- regardless of the passed function parameters
-- Bugfix:
-- The bugfix will be included in 10.5a, but this workaround must be
-- present until Altera updates the embedded ModelSim Altera Edition.
p := Pause;
rp := ResetPulse;
return (0 => p, 1 => rp);
end function;
end package body;
|
entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
z <= x & y;
end architecture;
-------------------------------------------------------------------------------
entity elab11 is
end entity;
architecture test of elab11 is
signal a, b : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
port map (
x(0) => '0'; -- Error
x(3 downto 1) => a(7 downto 5),
y => a(5 downto 2),
z => b );
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:54:13 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa-e.vhd,v 1.3 2005/04/14 06:53:01 wig Exp $
-- $Date: 2005/04/14 06:53:01 $
-- $Log: inst_aa-e.vhd,v $
-- Revision 1.3 2005/04/14 06:53:01 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa
--
entity inst_aa is
-- Generics:
-- No Generated Generics for Entity inst_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end inst_aa;
--
-- End of Generated Entity inst_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constant declaration for a formal generic of an entity passed
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constant declaration for a formal parameter of a procedure passed
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constant declaration for a formal generic of a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00644
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00644(ARCH00644)
-- ENT00644_Test_Bench(ARCH00644_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00644 is
generic ( constant G1 : integer := 0 ;
constant G2, G3, G4 : in integer := 3 ) ;
end ENT00644 ;
--
architecture ARCH00644 of ENT00644 is
procedure Proc ( constant P1 : integer := 0 ;
constant P2, P3, P4 : in integer := 3 ) is
begin
test_report ( "ARCH00644" ,
"The keyword 'in' is optional in a "&
"constant declaration for a formal parameter of "&
"a procedure" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
end Proc ;
begin
process
begin
test_report ( "ARCH00644" ,
"The keyword 'in' is optional in a "&
"constant declaration for a formal generic of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
Proc (P1 => G1, P2 => G2, P4 => G4) ;
wait ;
end process ;
L1 :
block
generic ( constant BG1 : integer := 0 ;
constant BG2, BG3, BG4 : in integer := 3 ) ;
generic map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00644" ,
"The keyword 'in' is optional in a "&
"constant declaration for a formal generic of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00644 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00644_Test_Bench is
end ENT00644_Test_Bench ;
architecture ARCH00644_Test_Bench of ENT00644_Test_Bench is
begin
L1:
block
component UUT
generic ( constant CG1 : integer ;
constant CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00644 ( ARCH00644 )
generic map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
begin
CIS1 : UUT
generic map ( 1, 2, 4 );
end block L1 ;
end ARCH00644_Test_Bench ;
--
|
use work.resource_handles_pkg.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.npc_pkg.all;
use work.resource_data_pkg.all;
use work.resource_handles_helper_pkg.all;
package resource_data_helper_pkg is
function sprite_initial_value_from_id(sprite_id: natural) return sprite_type;
function get_bitmap_from_handle(handle: bitmap_handle_type) return paletted_bitmap_type;
function make_sprites_initial_values(sprite_init_array: sprite_init_array_type) return sprites_array_type;
function make_sprite_positions(pairs: sprite_positions_init_array) return point_array_type;
function make_sprites_collision_query(collisions: sprite_collision_init_array_type) return sprite_collision_query_type;
function make_npcs_initial_values(npcs_init_array: npc_init_array_type) return npc_array_type;
end;
package body resource_data_helper_pkg is
function get_bitmap_from_handle(handle: bitmap_handle_type) return paletted_bitmap_type is
variable bitmap_init_value: bitmap_init_type;
begin
bitmap_init_value := GAME_BITMAPS( get_bitmap_id_from_handle(handle) );
return bitmap_init_value.bitmap;
end;
-- Merges all information provided by the user with the aditional information
-- required to create a sprite
function sprite_initial_value_from_id(sprite_id: natural) return sprite_type is
variable bitmap: paletted_bitmap_type(0 to BITMAP_WIDTH-1, 0 to BITMAP_HEIGHT-1);
variable bitmap_handle: bitmap_handle_type;
begin
bitmap_handle := GAME_SPRITES(sprite_id).bitmap_handle;
bitmap := get_bitmap_from_handle(bitmap_handle);
return (bitmap => bitmap, enabled => true, others => 0);
end;
-- We need to initialize the sprites engine with the game sprites. This
-- initialization array helps us do it neatly. The helper function will
-- fetch user-provided data from the GAME_SPRITES array and return an
-- array of sprites ready to be assigned to sprite engine upon reset.
function make_sprites_initial_values(sprite_init_array: sprite_init_array_type) return sprites_array_type is
variable sprites: sprites_array_type(sprite_init_array'range);
begin
for i in sprites'range loop
sprites(i) := sprite_initial_value_from_id(i);
end loop;
return sprites;
end;
function make_sprites_collision_query(collisions: sprite_collision_init_array_type) return sprite_collision_query_type is
variable query: sprite_collision_query_type(collisions'range);
begin
for i in query'range loop
query(i) := (
get_sprite_id_from_handle( collisions(i).sprite_1 ),
get_sprite_id_from_handle( collisions(i).sprite_2 )
);
end loop;
return query;
end;
function make_npcs_initial_values(npcs_init_array: npc_init_array_type) return npc_array_type is
variable npcs: npc_array_type(npcs_init_array'range);
begin
for i in npcs'range loop
npcs( get_id(npcs_init_array(i).npc_handle) ) := npcs_init_array(i).npc;
end loop;
return npcs;
end;
function make_sprite_positions(pairs: sprite_positions_init_array) return point_array_type is
variable positions: point_array_type(pairs'range);
begin
for i in pairs'range loop
positions(get_sprite_id_from_handle(pairs(i).id)) := pairs(i).position;
end loop;
return positions;
end;
end;
|
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Sonido de choque.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_onda is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector(17 downto 0);
clear : in std_logic;
onda_out : out std_logic
);
end gen_onda;
architecture rtl of gen_onda is
signal count : unsigned(17 downto 0);
signal temp : std_logic;
begin
gen_signal : process(clk, rst)
begin
if(rst = '0')then
count <= (others => '0');
temp <= '0';
elsif(rising_edge(clk)) then
if(clear = '1') then
count <= (others=>'0');
elsif(count = unsigned(note_in)) then
temp <= not(temp);
count <= (others => '0');
else
count <= count + 1;
end if;
end if;
end process;
onda_out <= temp;
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.components.all;
entity controller is
port (Op, Funct: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluControl: out std_logic_vector(2 downto 0));
end entity;
architecture arq_controller of controller is
signal AluOp: std_logic_vector(1 downto 0); --Pablo hacer señal temporal;
begin
p0: maindec port map (Op, MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump, AluOp);
p1: aludec port map(aluop => AluOp, Funct => funct, AluControl => alucontrol);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.std_logic_arith.all;
entity DATAPATH is
port(
INPUT : in std_logic_vector (7 downto 0);
CLK, RESET, POSUN, SCIT : in std_logic;
OUTPUT : out std_logic_vector (15 downto 0);
SHOW1OUT : out std_logic_vector (15 downto 0);
SHOW2OUT : out std_logic_vector (15 downto 0);
ZERO : out std_logic
);
end DATAPATH;
architecture DATAPATH_BODY of DATAPATH is
signal A0, A1, A2, A3 : std_logic_vector (7 downto 0); -- hodnoty
signal extA0, extA1, extA2, extA3, SUM, AIN : std_logic_vector (9 downto 0);
signal COUNT_VAL : std_logic_vector (2 downto 0); -- counter pro scitani
begin
LOAD : process (CLK)
begin
if CLK = '1' and CLK'event then
if POSUN = '1' then
A3 <= A2;
A2 <= A1;
A1 <= A0;
A0 <= INPUT;
elsif RESET = '1' then
A3 <= (others => '0');
A2 <= (others => '0');
A1 <= (others => '0');
A0 <= (others => '0');
end if;
end if;
end process;
-- rozsirime hodnoty, abysme neztratili znaminko
extA0 <= A0(7) & A0(7) & A0;
extA1 <= A1(7) & A1(7) & A1;
extA2 <= A2(7) & A2(7) & A2;
extA3 <= A3(7) & A3(7) & A3;
-- v registru AIN je hodnota, kterou budeme tedka pricitat k sume,
-- do ni budeme davat postupne vsichni hodnoty od extA0 do extA3 a bude se to ridit countrem
process(RESET, COUNT_VAL, extA0, extA1, extA2, extA3, SCIT)
begin
if RESET = '1' then
AIN <= (others => '0');
elsif SCIT = '1' then
case COUNT_VAL is
when "100" => AIN <= extA3;
when "011" => AIN <= extA2;
when "010" => AIN <= extA1;
when others => AIN <= extA0;
end case;
else
AIN <= (others => '0');
end if;
end process;
-- pocitani sumy
REG_SUM : process (CLK)
begin
if CLK = '1' and CLK'event then
if POSUN = '1' or RESET = '1' then
SUM <= (others => '0'); -- posun nam vysledek zresetuje
COUNT_VAL <= "100"; -- a nastavi counter na 4
elsif SCIT = '1' then
SUM <= SUM + AIN; -- scitame
COUNT_VAL <= COUNT_VAL - 1; -- zmensujeme counter
end if;
end if;
end process;
-- signal, ktery rekne, ze scitani je dodelano
ZERO <= '1' when COUNT_VAL = "001" else '0';
-- deleni 4 (vememe sumu bez 2 dolnich bitu a rozsirime ji pro snadne zobrazeni)
OUTPUT <= SUM(9) & SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) & SUM(9 downto 2);
-- udelame vystup pro ukazani obsahu jednotlivych registru
SHOW1OUT <= A1 & A0;
SHOW2OUT <= A3 & A2;
end architecture;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.clog2;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v1_01_a.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for tap_con
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: tap_con-e.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: tap_con-e.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity tap_con
--
entity tap_con is
-- Generics:
-- No Generated Generics for Entity tap_con
-- Generated Port Declaration:
-- No Generated Port for Entity tap_con
end tap_con;
--
-- End of Generated Entity tap_con
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Swap data channels when the deswap input signal is high; keep
-- channels paths unchanged otherwise.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deswap_channels is
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end deswap_channels;
architecture rtl of deswap_channels is
begin
deswap_proc : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= (others => '0');
ch2_o <= (others => '0');
ch_valid_o <= '0';
else
ch_valid_o <= ch_valid_i;
if (ch_valid_i = '1') then
deswap_o <= deswap_i;
if (deswap_i = '1') then
ch1_o <= ch2_i;
ch2_o <= ch1_i;
else
ch1_o <= ch1_i;
ch2_o <= ch2_i;
end if;
end if;
end if;
end if;
end process deswap_proc;
end;
|
------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Swap data channels when the deswap input signal is high; keep
-- channels paths unchanged otherwise.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deswap_channels is
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end deswap_channels;
architecture rtl of deswap_channels is
begin
deswap_proc : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= (others => '0');
ch2_o <= (others => '0');
ch_valid_o <= '0';
else
ch_valid_o <= ch_valid_i;
if (ch_valid_i = '1') then
deswap_o <= deswap_i;
if (deswap_i = '1') then
ch1_o <= ch2_i;
ch2_o <= ch1_i;
else
ch1_o <= ch1_i;
ch2_o <= ch2_i;
end if;
end if;
end if;
end if;
end process deswap_proc;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:13:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : system_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end system_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of system_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end system_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of system_rst_ps7_0_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end system_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of system_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_lpf : entity is "lpf";
end system_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of system_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.system_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.system_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end system_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of system_rst_ps7_0_100M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.system_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of system_rst_ps7_0_100M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.system_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.system_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rst_ps7_0_100M_0 : entity is "system_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2016.4";
end system_rst_ps7_0_100M_0;
architecture STRUCTURE of system_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.system_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
bid_gets_fifo_load : out STD_LOGIC;
axi_wdata_full_cmb114_out : out STD_LOGIC;
\axi_bid_int_reg[0]\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
axi_awid_pipe : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC;
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC;
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair44";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[0]_i_2_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => bid_fifo_not_empty,
R => s_axi_aresetn
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld,
Q => bid_fifo_rd
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_awid_pipe,
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACA0"
)
port map (
I0 => bid_fifo_ld,
I1 => bid_fifo_rd,
I2 => \^bid_gets_fifo_load\,
I3 => \axi_bid_int[0]_i_2_n_0\,
I4 => s_axi_bid(0),
O => \axi_bid_int_reg[0]\
);
\axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[0]_i_2_n_0\
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[2]_0\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[2]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair47";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[2]_0\ <= \^wrap_burst_total_reg[2]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F909090900000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \wrap_burst_total[0]_i_4__0_n_0\,
I3 => Q(1),
I4 => Q(2),
I5 => \wrap_burst_total[0]_i_5_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(2),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_4__0_n_0\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awlen(0),
I1 => Q(0),
I2 => s_axi_awlen(3),
I3 => axi_awaddr_full,
I4 => Q(3),
O => \wrap_burst_total[0]_i_5_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000008F3"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5000000044004400"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(2),
I2 => Q(2),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"335FFF5F"
)
port map (
I0 => s_axi_awlen(1),
I1 => Q(1),
I2 => s_axi_awlen(0),
I3 => axi_awaddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \^wrap_burst_total_reg[2]_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
ar_active : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair4";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0F0E0FFE0F0E0F0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => Q(1),
I4 => Q(3),
I5 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D00000000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => axi_rvalid_int_reg,
I4 => s_axi_rready,
I5 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => axi_rvalid_int_reg,
I3 => s_axi_rready,
I4 => end_brst_rd,
I5 => brst_zero,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030203020300"
)
port map (
I0 => Q(0),
I1 => Q(3),
I2 => Q(2),
I3 => Q(1),
I4 => axi_rd_burst_two_reg,
I5 => axi_rd_burst,
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888A88888888"
)
port map (
I0 => axi_aresetn_d2,
I1 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[15]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => \^save_init_bram_addr_ld_reg[15]_1\,
I5 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000054"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => no_ar_ack,
I4 => pend_rd_op,
I5 => ar_active,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => brst_zero,
I1 => s_axi_rready,
I2 => axi_rvalid_int_reg,
O => \save_init_bram_addr_ld[15]_i_3__0_n_0\
);
\save_init_bram_addr_ld[15]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A000C300"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \^wrap_burst_total_reg[0]_1\,
I3 => \^wrap_burst_total_reg[0]_2\,
I4 => \wrap_burst_total[0]_i_5__0_n_0\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_5__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I5 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000888800000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => s_axi_arlen(2),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => axi_arsize_pipe(0),
I4 => axi_araddr_full,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_reg_n_0_[0]\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_i_5_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC;
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_2_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC;
signal axi_rid_temp2 : STD_LOGIC;
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_12_n_0 : STD_LOGIC;
signal bram_en_int_i_13_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_5_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_one_i_2_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_rlast_sm_cs[2]_i_2\ : label is "soft_lutpair14";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_int[0]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp[0]_i_2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of act_rd_burst_i_5 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of axi_rd_burst_two_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of bram_en_int_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of bram_en_int_i_11 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of bram_en_int_i_13 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of bram_en_int_i_6 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of bram_en_int_i_9 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of brst_one_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of last_bram_addr_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[1]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair21";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rid(0) <= \^s_axi_rid\(0);
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03C4000400C40004"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_9_n_0,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEAAAEAFFFFAAEA"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFBF0F0F0F0"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => bram_addr_ld_en,
I3 => \rd_data_sm_cs[2]_i_5_n_0\,
I4 => rd_adv_buf67_out,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0FFBFFFB0FFBF0F"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFFFFFF"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF70FFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => brst_zero,
I3 => I_WRAP_BRST_n_26,
I4 => I_WRAP_BRST_n_27,
I5 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arlen(7),
I2 => s_axi_arlen(4),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(3),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_24,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_14,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_13,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_12,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_22,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_21,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_20,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_19,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_18,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_17,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_16,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_15,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
O => rd_adv_buf67_out
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAABAAAAAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E200E200F0000000"
)
port map (
I0 => \^s_axi_rid\(0),
I1 => axi_rvalid_set,
I2 => axi_rid_temp,
I3 => s_axi_aresetn,
I4 => axi_b2b_brst,
I5 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
O => \GEN_RID.axi_rid_int[0]_i_1_n_0\
);
\GEN_RID.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
O => \GEN_RID.axi_rid_int[0]_i_2_n_0\
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_int[0]_i_1_n_0\,
Q => \^s_axi_rid\(0),
R => '0'
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFFFFFB8000000"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
O => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\,
Q => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAACFCFC0AAC0C0"
)
port map (
I0 => axi_rid_temp2,
I1 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
I2 => \GEN_RID.axi_rid_temp[0]_i_3_n_0\,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => axi_rid_temp,
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp2
);
\GEN_RID.axi_rid_temp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA08AAAAAA08AA08"
)
port map (
I0 => axi_rid_temp2_full,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp_full,
I3 => axi_rvalid_set,
I4 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
I5 => axi_b2b_brst,
O => \GEN_RID.axi_rid_temp[0]_i_3_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp,
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_9,
D(12) => I_WRAP_BRST_n_10,
D(11) => I_WRAP_BRST_n_11,
D(10) => I_WRAP_BRST_n_12,
D(9) => I_WRAP_BRST_n_13,
D(8) => I_WRAP_BRST_n_14,
D(7) => I_WRAP_BRST_n_15,
D(6) => I_WRAP_BRST_n_16,
D(5) => I_WRAP_BRST_n_17,
D(4) => I_WRAP_BRST_n_18,
D(3) => I_WRAP_BRST_n_19,
D(2) => I_WRAP_BRST_n_20,
D(1) => I_WRAP_BRST_n_21,
D(0) => I_WRAP_BRST_n_22,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_7,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_24,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_27,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A888A888888888"
)
port map (
I0 => \rd_data_sm_cs[2]_i_3_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => act_rd_burst_i_5_n_0,
I3 => axi_rd_burst_i_2_n_0,
I4 => I_WRAP_BRST_n_4,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"20000040FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"5500FC00"
)
port map (
I0 => bram_en_int_i_12_n_0,
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => act_rd_burst_i_4_n_0
);
act_rd_burst_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => act_rd_burst_i_5_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F074F0F0F074"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst_i_2_n_0,
I2 => axi_b2b_brst,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => disable_b2b_brst_i_2_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AA080000"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => end_brst_rd,
I2 => axi_b2b_brst,
I3 => brst_zero,
I4 => rd_adv_buf67_out,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_2_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000111"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => I_WRAP_BRST_n_5,
I2 => axi_arlen_pipe(1),
I3 => axi_araddr_full,
I4 => s_axi_arlen(1),
I5 => axi_rd_burst_i_3_n_0,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => axi_arlen_pipe(4),
I4 => s_axi_arlen(4),
I5 => last_bram_addr_i_9_n_0,
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFA0022000A"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT5
generic map(
INIT => X"E0000000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => bram_addr_ld_en,
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_12: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFBFBFBFFFBFFF"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => brst_zero,
I4 => axi_b2b_brst,
I5 => end_brst_rd,
O => bram_en_int_i_12_n_0
);
bram_en_int_i_13: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => bram_en_int_i_13_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4044"
)
port map (
I0 => bram_en_int_i_5_n_0,
I1 => rd_data_sm_cs(1),
I2 => bram_en_int_i_6_n_0,
I3 => rd_data_sm_cs(2),
I4 => bram_en_int_i_7_n_0,
I5 => I_WRAP_BRST_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"707370707C7F7C7C"
)
port map (
I0 => bram_en_int_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_adv_buf67_out,
I4 => bram_en_int_i_9_n_0,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A0001111AAAA1111"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => bram_addr_ld_en,
I2 => bram_en_int_i_11_n_0,
I3 => brst_one,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_12_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0044054455440544"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => bram_en_int_i_9_n_0,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_13_n_0,
O => bram_en_int_i_5_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"ECCC"
)
port map (
I0 => pend_rd_op,
I1 => bram_addr_ld_en,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5554005500540000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => bram_addr_ld_en,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_5,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(2),
I2 => brst_cnt(0),
I3 => brst_cnt(1),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(4),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(3),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one_i_2_n_0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_2_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(1),
I2 => brst_cnt(0),
O => brst_one_i_2_n_0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEE00EE0EEEE"
)
port map (
I0 => disable_b2b_brst_i_4_n_0,
I1 => disable_b2b_brst,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(3),
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FE0000000000"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
I2 => brst_one,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_3_n_0\,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFCD00002200"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAAAAAAAAAAAAFAB"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => rd_data_sm_cs(2),
I3 => last_bram_addr_i_4_n_0,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F707F7F7F7F7F"
)
port map (
I0 => p_0_in13_in,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(3),
I3 => bram_addr_ld_en,
I4 => I_WRAP_BRST_n_4,
I5 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A888200000000000"
)
port map (
I0 => rd_adv_buf67_out,
I1 => bram_addr_ld_en,
I2 => pend_rd_op,
I3 => p_0_in13_in,
I4 => last_bram_addr_i_6_n_0,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => brst_cnt(7),
I2 => brst_cnt(3),
I3 => brst_cnt(4),
I4 => brst_cnt(2),
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => last_bram_addr_i_9_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => I_WRAP_BRST_n_5,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_4,
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(4),
I1 => axi_arlen_pipe(4),
I2 => s_axi_arlen(5),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(5),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(6),
I1 => axi_arlen_pipe(6),
I2 => s_axi_arlen(7),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"88C8AAAAAAAAAAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_data_sm_cs(0),
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080FFD5FF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_adv_buf67_out,
I2 => pend_rd_op,
I3 => rd_data_sm_cs(1),
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"F1FF"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_8_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000E0E0FFFFFFFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => bram_addr_ld_en,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"001100F7001100D5"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAEAAAEFFFFAAAE"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[1]_i_2_n_0\,
I2 => end_brst_rd,
I3 => brst_zero,
I4 => I_WRAP_BRST_n_25,
I5 => \rd_data_sm_cs[2]_i_4_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEAEAEA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => \rd_data_sm_cs[2]_i_4_n_0\,
I3 => p_0_in13_in,
I4 => disable_b2b_brst_i_2_n_0,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000007000F000000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C808C8C8C8"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => I_WRAP_BRST_n_27,
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400040000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7444777730007444"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800000AA800000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => bram_addr_ld_en,
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000D0000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(3),
I5 => \rd_data_sm_cs[0]_i_3_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0053"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => act_rd_burst_two,
I3 => act_rd_burst,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000111111110000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"D208D208D208F208"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => act_rd_burst,
I5 => act_rd_burst_two,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"A007AF07AF07AF07"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_1 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC;
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair53";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair51";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair50";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awid_pipe => axi_awid_pipe,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
\axi_bid_int_reg[0]\ => BID_FIFO_n_4,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_1,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn_0,
s_axi_awid(0) => s_axi_awid(0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => \^s_axi_bid\(0),
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => s_axi_aresetn_0
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => s_axi_aresetn_0
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_24,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_25,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_22,
\wrap_burst_total_reg[2]_0\ => I_WRAP_BRST_n_23
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => BID_FIFO_n_4,
Q => \^s_axi_bid\(0),
R => s_axi_aresetn_0
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_1,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => s_axi_aresetn_0
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => s_axi_aresetn_0
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => s_axi_aresetn_0
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000151"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => s_axi_awlen(2),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(2),
I4 => I_WRAP_BRST_n_22,
I5 => curr_awlen_reg_1_or_2_i_2_n_0,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F5F5F5F5F5C5"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => axi_awlen_pipe(5),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(6),
I4 => axi_awlen_pipe(7),
I5 => axi_awlen_pipe(4),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => s_axi_aresetn_0
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_24,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_25,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bram_rst_a\,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : hex7seg_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Convert a hex digit to 7 segment dislplay according
--
-- +-------+---+---+---+---+---+---+---+
-- | digit | a | b | c | d | e | f | g |
-- +-------+---+---+---+---+---+---+---+
-- | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
-- | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
-- | 2 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
-- | 3 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
-- | 4 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
-- | 5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
-- | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
-- | 7 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
-- | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-- | 9 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-- | A | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-- | b | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
-- | C | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
-- | d | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
-- | E | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
-- | F | 0 | 1 | 1 | 1 | 0 | 0 | 0 |
-- +-------+---+---+---+---+---+---+---+
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0));
end hex7seg;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/hdl_modulator_pac.vhd
-- Created: 2018-02-20 12:01:50
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE hdl_modulator_pac IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
TYPE vector_of_unsigned9 IS ARRAY (NATURAL RANGE <>) OF unsigned(8 DOWNTO 0);
END hdl_modulator_pac;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
|
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub type
subtype Myrange_t is integer range 0 to 4;
-- some constants
constant ZERO: Myrange_t := 0;
constant ONE: Myrange_t := 1;
constant TWO: Myrange_t := 2;
constant THREE: Myrange_t := 3;
constant FOUR: Myrange_t := 4;
-- another subtype
subtype AdderWidth_t is bit_vector (THREE downto ZERO);
subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package mypackage;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
use work.mypackage.all;
entity fa4 is
port (va_i, vb_i: in AdderWidth_t;
c_i: in bit;
vs_o: out AdderWidth_t;
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- auxiliary signal for carry
signal c_int: CarryWidth_t;
begin
-- carry in
c_int(ZERO) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(ZERO),
a_i => va_i(ZERO),
b_i => vb_i(ZERO),
s_o => vs_o(ZERO),
c_o => c_int(ONE)
);
-- slice 1
s1: fa1 port map (c_i => c_int(ONE),
a_i => va_i(ONE),
b_i => vb_i(ONE),
s_o => vs_o(ONE),
c_o => c_int(TWO)
);
-- slice 2
s2: fa1 port map (c_i => c_int(TWO),
a_i => va_i(TWO),
b_i => vb_i(TWO),
s_o => vs_o(TWO),
c_o => c_int(THREE)
);
-- slice 3
s3: fa1 port map (c_i => c_int(THREE),
a_i => va_i(THREE),
b_i => vb_i(THREE),
s_o => vs_o(THREE),
c_o => c_int(FOUR)
);
-- carry out
c_o <= c_int(FOUR);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub type
subtype Myrange_t is integer range 0 to 4;
-- some constants
constant ZERO: Myrange_t := 0;
constant ONE: Myrange_t := 1;
constant TWO: Myrange_t := 2;
constant THREE: Myrange_t := 3;
constant FOUR: Myrange_t := 4;
-- another subtype
subtype AdderWidth_t is bit_vector (THREE downto ZERO);
subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package mypackage;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
use work.mypackage.all;
entity fa4 is
port (va_i, vb_i: in AdderWidth_t;
c_i: in bit;
vs_o: out AdderWidth_t;
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- auxiliary signal for carry
signal c_int: CarryWidth_t;
begin
-- carry in
c_int(ZERO) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(ZERO),
a_i => va_i(ZERO),
b_i => vb_i(ZERO),
s_o => vs_o(ZERO),
c_o => c_int(ONE)
);
-- slice 1
s1: fa1 port map (c_i => c_int(ONE),
a_i => va_i(ONE),
b_i => vb_i(ONE),
s_o => vs_o(ONE),
c_o => c_int(TWO)
);
-- slice 2
s2: fa1 port map (c_i => c_int(TWO),
a_i => va_i(TWO),
b_i => vb_i(TWO),
s_o => vs_o(TWO),
c_o => c_int(THREE)
);
-- slice 3
s3: fa1 port map (c_i => c_int(THREE),
a_i => va_i(THREE),
b_i => vb_i(THREE),
s_o => vs_o(THREE),
c_o => c_int(FOUR)
);
-- carry out
c_o <= c_int(FOUR);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub type
subtype Myrange_t is integer range 0 to 4;
-- some constants
constant ZERO: Myrange_t := 0;
constant ONE: Myrange_t := 1;
constant TWO: Myrange_t := 2;
constant THREE: Myrange_t := 3;
constant FOUR: Myrange_t := 4;
-- another subtype
subtype AdderWidth_t is bit_vector (THREE downto ZERO);
subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package mypackage;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
use work.mypackage.all;
entity fa4 is
port (va_i, vb_i: in AdderWidth_t;
c_i: in bit;
vs_o: out AdderWidth_t;
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- auxiliary signal for carry
signal c_int: CarryWidth_t;
begin
-- carry in
c_int(ZERO) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(ZERO),
a_i => va_i(ZERO),
b_i => vb_i(ZERO),
s_o => vs_o(ZERO),
c_o => c_int(ONE)
);
-- slice 1
s1: fa1 port map (c_i => c_int(ONE),
a_i => va_i(ONE),
b_i => vb_i(ONE),
s_o => vs_o(ONE),
c_o => c_int(TWO)
);
-- slice 2
s2: fa1 port map (c_i => c_int(TWO),
a_i => va_i(TWO),
b_i => vb_i(TWO),
s_o => vs_o(TWO),
c_o => c_int(THREE)
);
-- slice 3
s3: fa1 port map (c_i => c_int(THREE),
a_i => va_i(THREE),
b_i => vb_i(THREE),
s_o => vs_o(THREE),
c_o => c_int(FOUR)
);
-- carry out
c_o <= c_int(FOUR);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub type
subtype Myrange_t is integer range 0 to 4;
-- some constants
constant ZERO: Myrange_t := 0;
constant ONE: Myrange_t := 1;
constant TWO: Myrange_t := 2;
constant THREE: Myrange_t := 3;
constant FOUR: Myrange_t := 4;
-- another subtype
subtype AdderWidth_t is bit_vector (THREE downto ZERO);
subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package mypackage;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
use work.mypackage.all;
entity fa4 is
port (va_i, vb_i: in AdderWidth_t;
c_i: in bit;
vs_o: out AdderWidth_t;
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- auxiliary signal for carry
signal c_int: CarryWidth_t;
begin
-- carry in
c_int(ZERO) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(ZERO),
a_i => va_i(ZERO),
b_i => vb_i(ZERO),
s_o => vs_o(ZERO),
c_o => c_int(ONE)
);
-- slice 1
s1: fa1 port map (c_i => c_int(ONE),
a_i => va_i(ONE),
b_i => vb_i(ONE),
s_o => vs_o(ONE),
c_o => c_int(TWO)
);
-- slice 2
s2: fa1 port map (c_i => c_int(TWO),
a_i => va_i(TWO),
b_i => vb_i(TWO),
s_o => vs_o(TWO),
c_o => c_int(THREE)
);
-- slice 3
s3: fa1 port map (c_i => c_int(THREE),
a_i => va_i(THREE),
b_i => vb_i(THREE),
s_o => vs_o(THREE),
c_o => c_int(FOUR)
);
-- carry out
c_o <= c_int(FOUR);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The LessOrEqualThanInstructionExecutor entity
entity LessOrEqualThanInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end LessOrEqualThanInstructionExecutor;
architecture LessOrEqualThanInstructionExecutorImpl of LessOrEqualThanInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: std_logic;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
if arg0 <= arg1 then
result <= '1';
else
result <= '0';
end if;
state <= store_result;
when store_result =>
register_address <= SpecialRegister;
register_operation <= OP_REG_SET;
register_data_write(CarryBit) <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end LessOrEqualThanInstructionExecutorImpl;
|
library IEEE;
use IEEE.std_logic_1164.All;
entity explorer_testbench is end explorer_testbench;
architecture tb_explorer of explorer_testbench is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal level : std_logic := '0';
signal tick : std_logic := '0';
constant twenty_five_nsec : time := 25 ns;
component Explorer port (
clk : in std_logic;
reset : in std_logic);
end component Explorer;
begin
Explorer1 : Explorer
port map (
clk => clk,
reset => reset);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
end tb_explorer; |
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Hex_ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Hex_ROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END Hex_ROM;
ARCHITECTURE SYN OF hex_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "Hex_ROM.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "Hex_ROM.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "Hex_ROM.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library ieee;
use ieee.std_logic_1164.all;
entity topo_selec is
port (SW: in std_logic_vector(9 downto 0);
AGENDA: in std_logic_vector(19 downto 0);
CONTA_ASC: in std_logic_vector(19 downto 0);
CONTA_DESC: in std_logic_vector(9 downto 0);
SEL_DISP: in std_logic_vector(1 downto 0);
TENTATIVAS: in std_logic_vector(1 downto 0);
SEL_LED: in std_logic;
REG: out std_logic_vector(19 downto 0);
LED_OUT: out std_logic_vector(9 downto 0)
);
end topo_selec;
architecture topo_selec_arch of topo_selec is
signal S: std_logic_vector(9 downto 0);
signal S0: std_logic_vector(19 downto 0);
signal S1: std_logic_vector(19 downto 0);
signal IN_PASS: std_logic_vector(4 downto 0);
component decod10x5
port (C: in std_logic_vector(9 downto 0);
F: out std_logic_vector(4 downto 0)
);
end component;
component mux2x1
port (x: in std_logic_vector(9 downto 0);
y: in std_logic_vector(9 downto 0);
s: in std_logic;
m: out std_logic_vector(9 downto 0)
);
end component;
component mux4x1
port (w: in std_logic_vector(19 downto 0);
x: in std_logic_vector(19 downto 0);
y: in std_logic_vector(19 downto 0);
z: in std_logic_vector(19 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(19 downto 0)
);
end component;
begin
S <= TENTATIVAS&"00000000";
S0 <= "00000000000000000000";
S1 <= IN_PASS&IN_PASS&IN_PASS&IN_PASS;
L0: decod10x5 port map (SW, IN_PASS);
L1: mux2x1 port map (S, CONTA_DESC, SEL_LED, LED_OUT);
L2: mux4x1 port map (S0, S1, AGENDA, CONTA_ASC, SEL_DISP, REG);
end topo_selec_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atmel_components
-- File: atmel_components.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atc18_components is
-- input pad
component pc33d00 port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00u port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20 port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20u port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01 port (i : in std_logic; pad : out std_logic); end component;
component pt33o02 port (i : in std_logic; pad : out std_logic); end component;
component pt33o03 port (i : in std_logic; pad : out std_logic); end component;
component pt33o04 port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04 port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04u port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b015vt
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t015vt
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00526
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00526_1
-- PKG00526_2
-- PKG00526_2/BODY
-- ENT00526(ARCH00526)
-- ENT00526_Test_Bench(ARCH00526_Test_Bench)
--
-- REVISION HISTORY:
--
-- 14-AUG-1987 - initial revision
-- 28-NOV-1989 - (ESL) remove test where entity name is used as prefix
--
-- NOTES:
--
-- self-checking
--
--
package PKG00526_1 is
type A1 is range 1 to 5;
type B1 is range 1.0 to 10.0;
type CC is (C1, C2, C3) ;
end PKG00526_1;
package PKG00526_2 is
subtype A is CHARACTER range '1' to '5';
constant C : PKG00526_2.A := '4';
-- selected name is also directly visible
function Func return boolean ;
end PKG00526_2;
package body PKG00526_2 is
constant CC : A := PKG00526_2.C ;
-- selected name is also directly visible
function Func return boolean is
constant CCC : A := PKG00526_2.C ;
begin
Lp :
for i in True to True loop
return (CC = C) and
(Func.CCC = C) and
(Lp.i) ;
end loop Lp ;
end Func ;
end PKG00526_2 ;
entity ENT00526 is
end ENT00526 ;
use WORK.STANDARD_TYPES.all, WORK.PKG00526_1, WORK.PKG00526_2;
architecture ARCH00526 of ENT00526 is
constant ArchCons : boolean := True ;
use PKG00526_1."=" ;
use PKG00526_2."=" ;
begin
B1 :
block
constant F : boolean := true ;
begin
Pcs :
process
variable B : integer := 5;
variable D : PKG00526_1.B1 := 2.3;
constant Q : PKG00526_1.CC := PKG00526_1.C2;
begin
test_report ( "ARCH00526.B1" ,
"Selected names whose suffix is a package are allowed" ,
(Pcs.B = 5) and
(Pcs.D = 2.3) and
(Pcs.Q = PKG00526_1.C2) and
(PKG00526_2.Func) and
(ARCH00526.ArchCons) ) ;
wait ;
end process;
B2 :
block
constant F : bit := '1' ;
constant G : bit := B1.B2.F;
constant H : PKG00526_2.A := PKG00526_2.C;
signal S : PKG00526_1.A1 := 3 ;
begin
process
begin
test_report ( "ARCH00526.B2" ,
"Selected names whose suffix is a package are allowed" ,
(B2.F = '1') and
(B1.B2.G = '1') and
(B2.H = '4') and
(B1.B2.S = 3) );
wait ;
end process ;
end block B2 ;
end block B1 ;
end ARCH00526 ;
entity ENT00526_Test_Bench is
end ENT00526_Test_Bench ;
architecture ARCH00526_Test_Bench of ENT00526_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00526 ( ARCH00526 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00526_Test_Bench ;
|
-- NEED RESULT: ARCH00385.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00385
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00385(ARCH00385)
-- ENT00385_Test_Bench(ARCH00385_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00385 is
end ENT00385 ;
--
--
architecture ARCH00385 of ENT00385 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb) after 5 ns
when 3,
--
c_st_boolean_vector_1(lowb) after 100 ns
when 4,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb) after 5 ns
when 3,
--
c_st_severity_level_vector_1(lowb) after 100 ns
when 4,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when 1,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 2,
--
c_st_string_1(highb) after 5 ns
when 3,
--
c_st_string_1(highb) after 100 ns
when 4,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb) after 5 ns
when 3,
--
c_st_enum1_vector_1(highb) after 100 ns
when 4,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb) after 5 ns
when 3,
--
c_st_integer_vector_1(lowb) after 100 ns
when 4,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when 1,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 2,
--
c_st_time_vector_1(lowb) after 5 ns
when 3,
--
c_st_time_vector_1(lowb) after 100 ns
when 4,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when 1,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 2,
--
c_st_real_vector_1(highb) after 5 ns
when 3,
--
c_st_real_vector_1(highb) after 100 ns
when 4,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb) after 5 ns
when 3,
--
c_st_rec1_vector_1(highb) after 100 ns
when 4,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with st_arr2_select select
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when 1,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 2,
--
c_st_arr2_1(highb,false) after 5 ns
when 3,
--
c_st_arr2_1(highb,false) after 100 ns
when 4,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns when 6 ;
--
end ARCH00385 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00385_Test_Bench is
end ENT00385_Test_Bench ;
--
--
architecture ARCH00385_Test_Bench of ENT00385_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00385 ( ARCH00385 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00385_Test_Bench ;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- M_j_memory.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_sha256 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- to_integer()
entity M_j_memory is
generic (
row_size : natural := 32;
address_size : natural := 4
);
port (
clk : in std_ulogic; -- clock
rcs_n : in std_ulogic; -- read chip select: when asserted low, memory can be read
wcs_n : in std_ulogic; -- write chip select: when asserted low, memory can be written if also we_n is low
we_n : in std_ulogic; -- write enable: when asserted low, memory can be written
r_addr : in std_ulogic_vector(address_size-1 downto 0);
w_addr : in std_ulogic_vector(address_size-1 downto 0);
data_in : in std_ulogic_vector(row_size-1 downto 0);
data_out : out std_ulogic_vector(row_size-1 downto 0)
);
end entity M_j_memory;
architecture behav of M_j_memory is
type ram_type is array (0 to 2**address_size-1) of std_ulogic_vector(row_size-1 downto 0);
signal RAM : ram_type;
begin
process(clk)
begin
if clk'event and clk = '1' then
if wcs_n = '0' then
if we_n = '0' then
RAM(to_integer(unsigned(w_addr))) <= data_in;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if rcs_n = '0' then
data_out <= RAM(to_integer(unsigned(r_addr)));
end if;
end if;
end process;
end behav; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity check_setup is
end entity check_setup;
architecture test of check_setup is
-- code from book
procedure check_setup ( signal data, clock : in bit;
constant Tsu : in time ) is
begin
if clock'event and clock = '1' then
assert data'last_event >= Tsu
report "setup time violation" severity error;
end if;
end procedure check_setup;
-- end code from book
signal ready, phi2 : bit := '0';
constant Tsu_rdy_clk : delay_length := 4 ns;
begin
-- code from book (in text)
check_ready_setup : check_setup ( data => ready, clock => phi2,
Tsu => Tsu_rdy_clk );
-- end code from book
clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
stimulus : ready <= '1' after 4 ns,
'0' after 56 ns,
'1' after 87 ns,
'0' after 130 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity check_setup is
end entity check_setup;
architecture test of check_setup is
-- code from book
procedure check_setup ( signal data, clock : in bit;
constant Tsu : in time ) is
begin
if clock'event and clock = '1' then
assert data'last_event >= Tsu
report "setup time violation" severity error;
end if;
end procedure check_setup;
-- end code from book
signal ready, phi2 : bit := '0';
constant Tsu_rdy_clk : delay_length := 4 ns;
begin
-- code from book (in text)
check_ready_setup : check_setup ( data => ready, clock => phi2,
Tsu => Tsu_rdy_clk );
-- end code from book
clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
stimulus : ready <= '1' after 4 ns,
'0' after 56 ns,
'1' after 87 ns,
'0' after 130 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity check_setup is
end entity check_setup;
architecture test of check_setup is
-- code from book
procedure check_setup ( signal data, clock : in bit;
constant Tsu : in time ) is
begin
if clock'event and clock = '1' then
assert data'last_event >= Tsu
report "setup time violation" severity error;
end if;
end procedure check_setup;
-- end code from book
signal ready, phi2 : bit := '0';
constant Tsu_rdy_clk : delay_length := 4 ns;
begin
-- code from book (in text)
check_ready_setup : check_setup ( data => ready, clock => phi2,
Tsu => Tsu_rdy_clk );
-- end code from book
clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
stimulus : ready <= '1' after 4 ns,
'0' after 56 ns,
'1' after 87 ns,
'0' after 130 ns;
end architecture test;
|
--------------------------------------------------------------------------
--Autor: Jorge Márquez
--fecha: julio 2008
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tope_tb is
-- generic(
-- vwidth : INTEGER := 8;
-- order : INTEGER := 5;
-- num_cols : INTEGER := 512;
-- num_rows : INTEGER := 512 );
end tope_tb;
architecture TB_ARCHITECTURE of tope_tb is
component tope_rof512_uart --componente
-- generic( --componente
-- vwidth : INTEGER := 8; --componente
-- order : INTEGER := 5; --componente
-- num_cols : INTEGER := 512; --componente
-- num_rows : INTEGER := 512 ); --componente
Port ( tx_female : out std_logic;
rx_female : in std_logic;
LED : out std_logic_vector(7 downto 0);
RSTn : in std_logic;
clk : in std_logic); --componente
end component; --componente
signal tx_female : std_logic:= '0'; --decl señales
signal rx_female : std_logic:= '0'; --decl señales
signal LED : std_logic_vector(7 downto 0) := "00000000"; --decl señales
signal RSTn : std_logic:= '0'; --decl señales
signal clk : std_logic:= '0'; --decl señales
signal TT : std_logic:= '0';
signal byteindata: std_logic_vector(7 downto 0) := "00000000";
begin
UUT : tope_rof512_uart
port map --portmap
(clk => clk, --portmap
RSTn => RSTn, --portmap
LED => LED, --portmap
rx_female => rx_female, --portmap
tx_female => tx_female ); --portmap
rx_female <= byteindata(0);
read_from_file: process(TT) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "C:\MATLAB701\work\lena512_syp_inicializ.ser"; --read_from_file
begin --read_from_file
if rising_edge(TT) or falling_edge(TT) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
byteindata <= conv_std_logic_vector(indata,8); --original: D <= conv_std_logic_vector(indata,8);
-- rx_female <= byteindata(0);
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"C:\MATLAB701\work\lena512_syp_inicializ.ser"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
-- write_to_file: process(Clk) --write_to_file
-- variable outdata_line: line; --write_to_file
-- variable outdata: integer:=0; --write_to_file
-- file output_data_file: text open write_mode is "D:\JORGETESIS\proc_HW1lena512_syp.ser"; --write_to_file
-- begin --write_to_file
-- if rising_edge(Clk) then --write_to_file
-- outdata := CONV_INTEGER(tx_female); --write_to_file --original: outdata := CONV_INTEGER(unsigned(Dout));
-- -- if DV = '1' then --write_to_file
-- write(outdata_line,outdata); --write_to_file
-- writeline(output_data_file,outdata_line); --write_to_file
-- -- end if; --write_to_file
-- end if; --write_to_file
-- end process; --write_to_file
clock_gen: process --reloj
begin --reloj
Clk <= '0'; --reloj
wait for 10 ns; --reloj
Clk <= '1'; --reloj
wait for 10 ns; --reloj
end process; --reloj
TT_gen: process --patron de transmisión (8680=~1/115200)
begin --patron de transmisión (8680=~1/115200)
TT <= '0'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
TT <= '1'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
end process;
reset_gen: process --reset
begin --reset
RSTn <= '0'; --reset
wait for 20 ns; --reset
RSTn <= '1'; --reset
wait; --reset
end process; --reset
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_tope_rof512_uart of tope_tb is
for TB_ARCHITECTURE
for UUT : tope_rof512_uart
use entity work.tope_rof512_uart(comportamiento);
end for;
end for;
end TESTBENCH_FOR_tope_rof512_uart;
|
-- This code is used to configure the Marvell 88e1111 and handle the MDIO pins (PHY_RESET, PHY_MDC and PHY_MDIO).
-- It can write and read the internals registers of the marvell.
-- Right now, the configuration used is the configuration by default and this entity only outputs an hardware reset when power up.
-- You can add a configuration only by uncommenting the request signal (just set your address register and the data you want to write).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_mdio is
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
E_RST_L : out STD_LOGIC;
E_MDC : out STD_LOGIC;
E_MDIO : inout STD_LOGIC);
end eth_mdio;
architecture Behavioral of eth_mdio is
signal count : unsigned(27 downto 0) ;
signal request : unsigned(0 to 31);--write
signal request_r : unsigned(0 to 13);--read
signal stop_count_s : std_logic:='0';
type state_mdio is (idle, set_conf, reset_st,read_st,wait_st,config);
signal state : state_mdio;
signal count_conf : unsigned(3 downto 0):=x"0";
signal reset_done : std_logic:='0';
signal tempo : std_logic:='1';
begin
process(CLK,RESET)
begin
if RESET = '0' then
E_RST_L <= '0';--hold reset condition for 1 second
E_MDC <= '1';
E_MDIO <= 'Z';
stop_count_s <= '0';
count <= x"0000000";
elsif CLK'event and CLK = '1' then
if (count(11) = '1' or count(4) = '1') then
E_MDC <= '1';
else--maximum frequency of E_MDC is 8.3 MHz
E_MDC <= '0';--3.9 MHz
end if;
case state is
when idle =>
if count = x"F000000" and stop_count_s='0' then
state <= wait_st;
count <= x"0000000";
elsif count > x"0140000" and count < x"0280000" and stop_count_s='0' then
E_RST_L <= '0';
count <= count +1;
elsif count = x"F000000" and stop_count_s='1' then
state <= read_st;
count <= x"8000000";
else
E_RST_L <= '1';
count <= count +1;
end if;
when wait_st =>
if count = x"FFFFFFF" then
count <= x"8000000";
if reset_done='0' then
state <= set_conf;
elsif reset_done='1' and tempo='1' then
state <= wait_st;
tempo <= '0';
else
state <= config;
end if;
else
count <= count +1;
end if;
when set_conf =>
--request <= "0101" & "10010" & "10100" & "100000110011100000"; -- set delay for RX and TX in rgmii mode
if count=x"8000FFF" then
state <= reset_st;
count <= x"8000000";
else
count <= count +1;
end if;
when reset_st =>
--request <= "0101" & "10010" & "00000" & "101001000101000000"; -- reset PHY
if count=x"8000FFF" then
--stop_count_s <= '1';
count <= x"0000000";
state <= wait_st;
reset_done<='1' ;
else
count <= count +1;
end if;
when config =>
if count_conf=x"0" then
--request <= "0101" & "10010" & "10100" & "100000110011100001"; -- set reg 20 for rgmii
--request <= "0101" & "10010" & "00000" & "100101000101000000"; -- stop loopback = 100101000101000000 --reg 0
else
--request <= "0101" & "10010" & "11110" & "101000100100100000"; -- packet generator activated
end if;
if count=x"8000FFF" then
if count_conf=x"0" then
state <= config;
count <= x"8000000";
count_conf <= count_conf +1;
else
stop_count_s <= '1';
state <= idle;
end if;
else
count <= count +1;
end if;
when read_st =>
request_r <= "0110" & "10010" & "10100";
if count=x"8000FFF" then
state <= idle;
count <= x"8000000";
else
count <= count +1;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
E_MDIO <= '1' when count(11 downto 5) < "0100000" and (state=set_conf or state=reset_st or state=read_st or state=config) --32 1's preamble
else request(to_integer(count(9 downto 5))) when (state=set_conf or state=reset_st or state=config) and count(11 downto 5) <= "0111111" --write data
else request_r(to_integer(count(9 downto 5))) when state=read_st and count(11 downto 5) <= "0101101" -- read data
else 'Z';
end Behavioral;
|
package pack is
type params is record
x, y : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( p : params );
end entity;
architecture test of sub is
constant px : integer := p.x;
constant py : integer := p.y;
begin
g: for i in px to py generate
end generate;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity issue514 is
end entity;
architecture test of issue514 is
function get_params return params is
begin
return (x => 4, y => 6);
end function;
begin
u: entity work.sub
generic map (p => get_params);
end architecture;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.