content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------------------------------------
-- Title : ARP Responder
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpResponder.vhd
-- Author : Kurtis Nishimura
-----------... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
------------------------------------------------------------------------------
-- Title : Inverter Channels Top Entity
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
--------------... |
--
-- TEXTIO package as defined by IEEE 1076-1993
--
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
pr... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_MUX IS
END tb_MUX;
ARCHITECTURE behavior OF tb_MUX IS
CONSTANT N : INTEGER := 32;
--Inputs
SIGNAL tb_mux_in0 : std_logic_vector(N - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_mux_in1 : std_logic_vector(N - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_mux_ctl : std_l... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_swapper_tb is
end entity;
architecture number_swapper_tb_arq of number_swapper_tb is
signal man_1_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_1_in : std_logic_vector(5 downto 0) := (others => '0');
signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity preprocessor_tb is
end entity;
architecture preprocessor_tb_arq of preprocessor_tb is
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal y_in : std_logic_vector(31 downto 0) := (others => '0');
signal angle_in : std_lo... |
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 21:11:41 05/16/2016
------------... |
7890
htns
1234
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : John Doe (Developper Company JohnDoeCompany on behalf of ContractorBigcompany )
-- Copyright : Copyright (c) CNES.
-- Licensing : This VHDL entity can be licensed to be be used in the fra... |
--------------------------------------------------------------------------------
--|
--| Filename : uart_bhv
--| Author : Russell L Friesenhahn
--| Origin Date : 20130828
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--| Behavorial architecture of UAR... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_437;
architecture augh of sub_437 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_437;
architecture augh of sub_437 is
signal carry_inA : std_l... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:00 2017
-- Host : DarkCube running 64-bit major re... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This pro... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- Automatically generated: write_netlist -wrapapp -vhdl -module reconflogic-wrapmax6682.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MyReconfigLogic is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out st... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:34:40 03/09/2015
-- Design Name:
-- Module Name: DIV_FREC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_decode.all;
-- this module puts the alu, shifter and bit/compare unit together
entity data_oper is
generic (
support_bcd : boolean := true );
port (
inst : in std_logic_vector(7 dow... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.cu.all;
entity cu_test is
end cu_test;
architecture TEST of cu_test is
component CU_UP is
port (
-- Inputs
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset:Active-Low
I... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Si... |
entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
z <= x & y;
end architecture;
-------------------------------------------------------------------------------
entity elab11 is
end entity;
architecture ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:54:13 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ... |
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constant declaration for a formal generic of an entity passed
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constant declaration for a formal parameter of a procedure passed
-- NEED RESULT: ARCH00644: The keyword 'in' is optional in a constan... |
use work.resource_handles_pkg.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.npc_pkg.all;
use work.resource_data_pkg.all;
use work.resource_handles_helper_pkg.all;
package resource_data_helper_pkg is
function sprite_initial_value_from_id(sprite_id: natural) return sprite_type;
... |
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Sonido de choque.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_onda is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vecto... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.components.all;
entity controller is
port (Op, Funct: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluControl: out std_logic_vector(2 downto 0));
end enti... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.std_logic_arith.all;
entity DATAPATH is
port(
INPUT : in std_logic_vector (7 downto 0);
CLK, RESET, POSUN, SCIT : in std_logic;
OUTPUT : out std_logic_vector (15 downto 0);
SHOW1OUT : out std_l... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-- -------------------------------------------------------------
--
-- Entity Declaration for tap_con
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------... |
------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:13:47 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major releas... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : hex7seg_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/hdl_modulator_pac.vhd
-- Created: 2018-02-20 12:01:50
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub ... |
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub ... |
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub ... |
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub ... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
library IEEE;
use IEEE.std_logic_1164.All;
entity explorer_testbench is end explorer_testbench;
architecture tb_explorer of explorer_testbench is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal level : std_logic := '0';
signal tick : std_logic := '0';
constant twenty_five_n... |
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Hex_ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================... |
library ieee;
use ieee.std_logic_1164.all;
entity topo_selec is
port (SW: in std_logic_vector(9 downto 0);
AGENDA: in std_logic_vector(19 downto 0);
CONTA_ASC: in std_logic_vector(19 downto 0);
CONTA_DESC: in std_logic_vector(9 downto 0);
SEL_DISP: in std_logic_vector(1 downto 0);
TENTATIVAS: in std_logic_ve... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00526
--
-- AUTHOR:
--
-- G. Tomi... |
-- NEED RESULT: ARCH00385.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- M_j_memory.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------
--Autor: Jorge Márquez
--fecha: julio 2008
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tope_tb is
-- generic(
--... |
-- This code is used to configure the Marvell 88e1111 and handle the MDIO pins (PHY_RESET, PHY_MDC and PHY_MDIO).
-- It can write and read the internals registers of the marvell.
-- Right now, the configuration used is the configuration by default and this entity only outputs an hardware reset when power up.
-- You can... |
package pack is
type params is record
x, y : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( p : params );
end entity;
architecture test of sub is
constant px : integer := p.x;
co... |
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