content stringlengths 1 1.04M ⌀ |
|---|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity StateMachineEditor1_import is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end entity StateMachineEditor1_import;
architecture rtl of StateMachineEditor1_import is
component StateMachineEditor1_import_GN is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end component StateMachineEditor1_import_GN;
begin
StateMachineEditor1_import_GN_0: if true generate
inst_StateMachineEditor1_import_GN_0: StateMachineEditor1_import_GN
port map(clock => clock, col_select => col_select, data => data, data_en => data_en, reset => reset);
end generate;
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity multiplexador2x1 is
generic(largura: natural := 8);
port(
entrada0, entrada1: in std_logic_vector(largura-1 downto 0);
selecao: in std_logic;
saida: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of multiplexador2x1 is
begin
saida <= entrada0 when selecao='0' else
entrada1;
end architecture;
|
-- internal_flash.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_flash is
port (
clock : in std_logic := '0'; -- clk.clk
avmm_csr_addr : in std_logic := '0'; -- csr.address
avmm_csr_read : in std_logic := '0'; -- .read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_csr_write : in std_logic := '0'; -- .write
avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_addr : in std_logic_vector(11 downto 0) := (others => '0'); -- data.address
avmm_data_read : in std_logic := '0'; -- .read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_data_write : in std_logic := '0'; -- .write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_waitrequest : out std_logic; -- .waitrequest
avmm_data_readdatavalid : out std_logic; -- .readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
reset_n : in std_logic := '0' -- nreset.reset_n
);
end entity internal_flash;
architecture rtl of internal_flash is
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
begin
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "C:/Users/phil2/Dropbox/myelin-acorn-electron-hardware/bga_in_two_layers/10m04_cpu_socket/rom_one.hex",
INIT_FILENAME_SIM => "altera_onchip_flash.dat",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M04SCU169C8G",
DEVICE_ID => "04",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 0,
SECTOR2_END_ADDR => 0,
SECTOR3_START_ADDR => 0,
SECTOR3_END_ADDR => 0,
SECTOR4_START_ADDR => 0,
SECTOR4_END_ADDR => 0,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 4095,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 4095,
SECTOR1_MAP => 2,
SECTOR2_MAP => 0,
SECTOR3_MAP => 0,
SECTOR4_MAP => 0,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 4095,
ADDR_RANGE1_OFFSET => 4608,
ADDR_RANGE2_OFFSET => 0,
AVMM_DATA_ADDR_WIDTH => 12,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 30,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 4,
FLASH_RESET_CYCLE_MAX_INDEX => 29,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 139,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40600000,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35380,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => true,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "False"
)
port map (
clock => clock, -- clk.clk
reset_n => reset_n, -- nreset.reset_n
avmm_data_addr => avmm_data_addr, -- data.address
avmm_data_read => avmm_data_read, -- .read
avmm_data_writedata => avmm_data_writedata, -- .writedata
avmm_data_write => avmm_data_write, -- .write
avmm_data_readdata => avmm_data_readdata, -- .readdata
avmm_data_waitrequest => avmm_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => avmm_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => avmm_data_burstcount, -- .burstcount
avmm_csr_addr => avmm_csr_addr, -- csr.address
avmm_csr_read => avmm_csr_read, -- .read
avmm_csr_writedata => avmm_csr_writedata, -- .writedata
avmm_csr_write => avmm_csr_write, -- .write
avmm_csr_readdata => avmm_csr_readdata -- .readdata
);
end architecture rtl; -- of internal_flash
|
-------------------------------------------------------------------------------
--! @file nf_rx_registers.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-22
--! @brief NanoFIP receiver registers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.nf_pkg.all;
use work.cf_pkg.all;
--! @brief Entity declaration of nf_rx_registers
--! @details
--! The gateway is sending 32-bit long commands to the FGClite which are stored
--! in this register map. Each address is then assigned to internal control
--! signals.
entity nf_rx_registers is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name NanoFIP write interface
--! @{
--! Write enable
wr_en_i : in std_ulogic;
--! Address
addr_i : in std_ulogic_vector(1 downto 0);
--! Data
data_i : in std_ulogic_vector(31 downto 0);
--! @}
--! @name Registers
--! @{
--! Gateway commands
command_o : out nf_command_t);
--! @}
end entity nf_rx_registers;
--! RTL implementation of nf_rx_registers
architecture rtl of nf_rx_registers is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type reg_t is array (0 to 2**addr_i'length - 1) of std_ulogic_vector(data_i'range);
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal reg : reg_t;
signal cmd1 : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
-- Command 0
command_o.sefi_test_vs_m0 <= reg(0)(27 downto 26);
command_o.sefi_test_vs_m1 <= reg(0)(25 downto 24);
command_o.sefi_test_ia_m0 <= reg(0)(23 downto 22);
command_o.sefi_test_ia_m1 <= reg(0)(21 downto 20);
command_o.sefi_test_ib_m0 <= reg(0)(19 downto 18);
command_o.sefi_test_ib_m1 <= reg(0)(17 downto 16);
command_o.ms_period <= reg(0)(15 downto 0);
-- Command 1
command_o.serial_data <= reg(1);
command_o.serial_data_en <= cmd1;
-- Command 2
command_o.index <= reg(2)(30 downto 16);
command_o.index_type <= reg(2)(10 downto 8);
command_o.adc_log_freeze <= reg(2)(6);
command_o.dim_log_freeze <= reg(2)(5);
command_o.dim_reset <= reg(2)(4);
command_o.ow_scan <= reg(2)(3);
command_o.ow_bus_select <= reg(2)(2 downto 0);
-- Command 3
-- Had to flip signed bit for gateway
command_o.v_ref <= (not reg(3)(31)) & reg(3)(30 downto 16);
command_o.cal_source <= reg(3)(15 downto 14);
command_o.cal_vs_en <= reg(3)(13);
command_o.cal_ia_en <= reg(3)(12);
command_o.cal_ib_en <= reg(3)(11);
command_o.adc_vs_reset_n <= reg(3)(10);
command_o.adc_ia_reset_n <= reg(3)(9);
command_o.adc_ib_reset_n <= reg(3)(8);
command_o.vs_cmd <= reg(3)(7 downto 0);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= (others => (others => '0'));
reg(0)(15 downto 0) <= ms_period_c;
reg(3)(10 downto 8) <= "111";
cmd1 <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
cmd1 <= '0';
if wr_en_i = '1' then
reg(to_integer(unsigned(addr_i))) <= data_i;
if to_integer(unsigned(addr_i)) = 1 then
cmd1 <= '1';
end if;
end if;
end if;
end if;
end process regs;
end architecture rtl;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Oct 16 23:04:57 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target Program_Counter_wrapper.bd
--Design : Program_Counter_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Program_Counter_wrapper is
port (
CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
PC_INC : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
RST : in STD_LOGIC
);
end Program_Counter_wrapper;
architecture STRUCTURE of Program_Counter_wrapper is
component Program_Counter is
port (
PC_LD : in STD_LOGIC;
PC_INC : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component Program_Counter;
begin
Program_Counter_i: component Program_Counter
port map (
CLK => CLK,
FROM_IMMED(9 downto 0) => FROM_IMMED(9 downto 0),
FROM_STACK(9 downto 0) => FROM_STACK(9 downto 0),
PC_COUNT(0 to 9) => PC_COUNT(0 to 9),
PC_INC => PC_INC,
PC_LD => PC_LD,
PC_MUX_SEL(1 downto 0) => PC_MUX_SEL(1 downto 0),
RST => RST
);
end STRUCTURE;
|
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------------------------------------------------------------------
package body one is
function add_one(x : my_int) return my_int is
variable x : integer;
begin
null;
end function add_one;
shared variable x : integer;
end package body;
-------------------------------------------------------------------------------
library foo;
package three is
signal s : integer;
alias sa is s;
end package;
|
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------------------------------------------------------------------
package body one is
function add_one(x : my_int) return my_int is
variable x : integer;
begin
null;
end function add_one;
shared variable x : integer;
end package body;
-------------------------------------------------------------------------------
library foo;
package three is
signal s : integer;
alias sa is s;
end package;
|
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------------------------------------------------------------------
package body one is
function add_one(x : my_int) return my_int is
variable x : integer;
begin
null;
end function add_one;
shared variable x : integer;
end package body;
-------------------------------------------------------------------------------
library foo;
package three is
signal s : integer;
alias sa is s;
end package;
|
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------------------------------------------------------------------
package body one is
function add_one(x : my_int) return my_int is
variable x : integer;
begin
null;
end function add_one;
shared variable x : integer;
end package body;
-------------------------------------------------------------------------------
library foo;
package three is
signal s : integer;
alias sa is s;
end package;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option) any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the Lesser GNU General Public License for more
-- details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description:
--
-- This IP was created as a part of the IIR Hardware proect. It will resize a
-- 12 bit input to a 32 bit output.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity resize_IP is
Port ( i_value : in STD_LOGIC_VECTOR (11 downto 0);
o_value : out STD_LOGIC_VECTOR (31 downto 0));
end resize_IP;
architecture Behavioral of resize_IP is
begin
p_resize : process (i_value)
begin
o_value <= std_logic_vector(resize(signed(i_value), 32));
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : in STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
--register 26 is output, flags go there
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end entity superip_internal;
architecture RTL of superip_internal is
-- Internals
signal Mux3_BalanceORMux2_Left : std_logic_vector(23 downto 0);
signal Mux3_BalanceORMux2_Right : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Left : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Right : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Left_out : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Right_out : std_logic_vector(23 downto 0);
signal Filter_Left_out : std_logic_vector(23 downto 0);
signal Filter_Right_out : std_logic_vector(23 downto 0);
signal OUT_VOLCTRL_L : signed(23 downto 0);
signal OUT_VOLCTRL_R : signed(23 downto 0);
signal Balance_L_OUT : signed(23 downto 0);
signal Balance_R_OUT : signed(23 downto 0);
-- Outputs Register 26
ALIAS VolCtrl_RDY_L : STD_LOGIC is slv_reg26(0);
ALIAS VolCtrl_RDY_R : STD_LOGIC is slv_reg26(1);
ALIAS Filter_ready_out : STD_LOGIC is slv_reg26(2);
ALIAS READY_BAL : STD_LOGIC is slv_reg26(3);
-- Inputs Register 27
ALIAS HP_SW : STD_LOGIC is slv_reg27(0); --1 will enable it
ALIAS BP_SW : STD_LOGIC is slv_reg27(4); --1 will enable it
ALIAS LP_SW : STD_LOGIC is slv_reg27(8); --1 will enable it
ALIAS Reset_in : STD_LOGIC is slv_reg27(16);--1 will reset everything
ALIAS sample_trigger_en : STD_LOGIC is slv_reg27(20);--1 will set filter to wait for SAMPLE_TRIG from audioIP, otherwise, its constantly calculating
ALIAS bus_frames_en : std_logic is slv_reg27(31);--1 will
-- inputs register 25
signal Mux_Select_in : std_logic_vector(2 downto 0);
--slv_reg25(0) -> Mux1:= Volctrl or rawAudio; 0 for Volctrl pass
--slv_reg25(4) -> Mux2:= Filter or Mux1; 0 for Filter pass
--slv_reg25(8) -> mux3:= Balance or Mux2 0 for Balance pass
-- inputs register 24
ALIAS Reset_Filter : STD_LOGIC is slv_reg24(0); --1 will reset filter only, we use this because its unstable
begin
Mux_Select_in <= slv_reg25(8) & slv_reg25(4) & slv_reg25(0);
slv_reg28 <= x"00" & Mux3_BalanceORMux2_Left; --this goes out, and should arrive in mixerboard
slv_reg29 <= x"00" & Mux3_BalanceORMux2_Right; --this goes out, and should arrive in mixerboard
Mux_Frames_or_internal : process(Mux3_BalanceORMux2_Left, Mux3_BalanceORMux2_Right, slv_reg27(31), slv_reg30(23 downto 0), slv_reg31(23 downto 0))
begin
if bus_frames_en = '0' then
Mux3_BalanceORMux2_Left_out <= Mux3_BalanceORMux2_Left;
Mux3_BalanceORMux2_Right_out <= Mux3_BalanceORMux2_Right;
else
Mux3_BalanceORMux2_Left_out <= slv_reg30(23 downto 0); --this is input from mixerIP,
Mux3_BalanceORMux2_Right_out <= slv_reg31(23 downto 0);
end if;
end process;
Tester_inst : entity work.Tester
port map(
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
VolCtrl_Left_out_in => std_logic_vector(OUT_VOLCTRL_L),
VolCtrl_Right_out_in => std_logic_vector(OUT_VOLCTRL_R),
Mux1_VolCtrlORAudio_Left_out => Mux1_VolCtrlORAudio_Left_out,
Mux1_VolCtrlORAudio_Right_out => Mux1_VolCtrlORAudio_Right_out,
Filter_Left_out_in => Filter_Left_out,
Filter_Right_out_in => Filter_Right_out,
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right,
Balance_Left_out_in => std_logic_vector(Balance_L_OUT),
Balance_Right_out_in => std_logic_vector(Balance_R_OUT),
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right,
Mux_Select_in => Mux_Select_in
);
VolCtrl_inst : entity work.VolCtrl
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8
)
port map(
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY_L => VolCtrl_RDY_L,
OUT_RDY_R => VolCtrl_RDY_R,
IN_SIG_L => signed(Audio_Left_in),
IN_SIG_R => signed(Audio_Right_in),
IN_COEF_L => signed(slv_reg15),
IN_COEF_R => signed(slv_reg16),
RESET => Reset_in,
CLK_48 => CLK_48_in,
CLK_100M => CLK_100M_in
);
filter_Comp : entity work.Filter_Top_Level
port map(
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
CLK_48 => CLK_48_in,
RST => Reset_Filter,
SAMPLE_TRIG => SAMPLE_TRIG,
sample_trigger_en => sample_trigger_en,
HP_SW => HP_SW,
BP_SW => BP_SW,
LP_SW => LP_SW,
AUDIO_IN_L => Mux1_VolCtrlORAudio_Left_out,
AUDIO_IN_R => Mux1_VolCtrlORAudio_Right_out,
AUDIO_OUT_L => Filter_Left_out,
AUDIO_OUT_R => Filter_Right_out,
FILTER_DONE => Filter_ready_out
);
Balance_inst : entity work.Balance
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8,
N => 32,
Attenuation_Const => 11
)
port map(
CLK_BAL => CLK_48_in,
RESET_BAL => Reset_in,
POINTER => to_integer(signed(slv_reg17)),
CH_L_IN => signed(Mux2_FilterORMux1_Left),
CH_R_IN => signed(Mux2_FilterORMux1_Right),
CH_L_OUT => Balance_L_OUT,
CH_R_OUT => Balance_R_OUT,
READY_BAL => READY_BAL
);
end architecture RTL;
|
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
entity e is
end entity;
architecture a of e is
signal a : boolean;
begin
process(a)
begin
case a is
when false => report "FALSE";
when true => report "TRUE";
when others => report "others";
end case;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_full of tb_elem is
for behav
for dut_b : chip
use configuration work.chip_full_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
end for;
end tb_elem_behav_full;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_3_full_dsp_32_u : component convolve_kernel_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_3_full_dsp_32_u : component convolve_kernel_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00434ent IS
END c03s02b01x01p19n01i00434ent;
ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2real_cons_vector is array (row,column) of real;
constant C1 : s2real_cons_vector := (others => (others => 3.0));
function complex_scalar(s : s2real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2real_cons_vector;
signal S2 : s2real_cons_vector;
signal S3 : s2real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00434"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00434arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00434ent IS
END c03s02b01x01p19n01i00434ent;
ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2real_cons_vector is array (row,column) of real;
constant C1 : s2real_cons_vector := (others => (others => 3.0));
function complex_scalar(s : s2real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2real_cons_vector;
signal S2 : s2real_cons_vector;
signal S3 : s2real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00434"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00434arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00434ent IS
END c03s02b01x01p19n01i00434ent;
ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2real_cons_vector is array (row,column) of real;
constant C1 : s2real_cons_vector := (others => (others => 3.0));
function complex_scalar(s : s2real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2real_cons_vector;
signal S2 : s2real_cons_vector;
signal S3 : s2real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00434"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00434arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
B : out std_logic;
C : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if A = B then
if not A then
C <= '1';
end if;
end if;
end process;
end behv;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
use work.cpu_l1mem_inst_cache_replace_pkg.all;
entity cpu_l1mem_inst_cache_ctrl is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_ctrl_in : out cpu_mmu_inst_ctrl_in_type;
cpu_mmu_inst_ctrl_out : in cpu_mmu_inst_ctrl_out_type;
cpu_l1mem_inst_cache_ctrl_in : in cpu_l1mem_inst_cache_ctrl_in_type;
cpu_l1mem_inst_cache_ctrl_out : out cpu_l1mem_inst_cache_ctrl_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
cpu_l1mem_inst_cache_ctrl_out_vram : out cpu_l1mem_inst_cache_ctrl_out_vram_type;
cpu_l1mem_inst_cache_ctrl_in_vram : in cpu_l1mem_inst_cache_ctrl_in_vram_type;
cpu_l1mem_inst_cache_ctrl_out_tram : out cpu_l1mem_inst_cache_ctrl_out_tram_type;
cpu_l1mem_inst_cache_ctrl_out_dram : out cpu_l1mem_inst_cache_ctrl_out_dram_type;
cpu_l1mem_inst_cache_dp_in_ctrl : out cpu_l1mem_inst_cache_dp_in_ctrl_type;
cpu_l1mem_inst_cache_dp_out_ctrl : in cpu_l1mem_inst_cache_dp_out_ctrl_type;
cpu_l1mem_inst_cache_replace_ctrl_in : out cpu_l1mem_inst_cache_replace_ctrl_in_type;
cpu_l1mem_inst_cache_replace_ctrl_out : in cpu_l1mem_inst_cache_replace_ctrl_out_type
);
end;
|
-------------------------------------------------------------------------------
--! @file xf.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-08
--! @brief Auxiliary FPGA communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.xf_pkg.all;
use work.nf_pkg.all;
--! @brief Entity declaration of xf
--! @details
--! This component handles the NanoFIP communication and provides a
--! synchronization mechanism with the field-bus cycle.
entity xf is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Auxiliary FPGA interface
--! @{
--! Inputs
xf_i : in xf_in_t;
--! Outputs
xf_o : out xf_out_t;
--! @}
--! @name Internal interface
--! @{
--! Millisecond strobe indicating start of cycle
ms_0_strobe_i : in std_ulogic;
--! Millisecond strobe indicating start of second millisecond
ms_1_strobe_i : in std_ulogic;
--! Commands
command_i : in nf_command_t;
--! @}
--! @name Auxiliary FPGA data
--! @{
--! DIM analogue data
dim_o : out std_ulogic_vector(19 downto 0);
--! DIM analogue data enable
dim_en_o : out std_ulogic;
--! DIM trigger number
dim_trig_num_o : out std_ulogic_vector(3 downto 0);
--! DIM latched trigger
dim_trig_lat_o : out std_ulogic;
--! DIM unlatched trigger
dim_trig_unl_o : out std_ulogic;
--! Backplane type
backplane_type_o : out std_ulogic_vector(7 downto 0);
--! Backplane type enable
backplane_type_en_o : out std_ulogic;
--! XF and PF versions
version_xfpf_o : out std_ulogic_vector(7 downto 0);
--! XF and PF versions enable
version_xfpf_en_o : out std_ulogic;
--! Single-event upset (SEU) count
seu_count_o : out std_ulogic_vector(7 downto 0);
--! Single-event upset (SEU) count enable
seu_count_en_o : out std_ulogic;
--! 1-wire scan busy
ow_scan_busy_o : out std_ulogic;
--! @}
--! @name DIM data
--! @{
--! Address
dim_addr_i : in std_ulogic_vector(6 downto 0);
--! Read enable
dim_rd_en_i : in std_ulogic;
--! Data output
dim_data_o : out std_ulogic_vector(15 downto 0);
--! Data output enable
dim_data_en_o : out std_ulogic;
--! @}
--! @name One-wire data
--! @{
--! Address
ow_addr_i : in std_ulogic_vector(5 downto 0);
--! Read enable
ow_rd_en_i : in std_ulogic;
--! Data output
ow_data_o : out std_ulogic_vector(79 downto 0);
--! Data output enable
ow_data_en_o : out std_ulogic);
--! @}
end entity xf;
--! RTL implementation of xf
architecture rtl of xf is
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal ow_scan_busy : std_ulogic;
signal dim_trigger : std_ulogic;
signal dim_reset : std_ulogic;
signal ow_scan : std_ulogic;
signal ow_bus_select : std_ulogic_vector(2 downto 0);
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal xf_rx_data_0 : std_ulogic_vector(41 downto 0);
signal xf_rx_data_en_0 : std_ulogic;
signal xf_rx_error_0 : std_ulogic;
signal xf_rx_data_1 : std_ulogic_vector(83 downto 0);
signal xf_rx_data_en_1 : std_ulogic;
signal xf_rx_error_1 : std_ulogic;
signal dim_addr : std_ulogic_vector(6 downto 0);
signal ow_addr : std_ulogic_vector(5 downto 0);
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
xf_o.dim_trig <= dim_trigger;
xf_o.dim_rst <= dim_reset;
xf_o.ow_trig <= ow_scan;
xf_o.ow_bus_select <= ow_bus_select;
backplane_type_o <= "00" & xf_rx_data_0(13 downto 8);
backplane_type_en_o <= xf_rx_data_en_0;
version_xfpf_o <= xf_rx_data_0(7 downto 0);
version_xfpf_en_o <= xf_rx_data_en_0;
seu_count_o <= xf_rx_data_0(21 downto 14);
seu_count_en_o <= xf_rx_data_en_0 when dim_addr = "0000000" else '0';
ow_scan_busy_o <= ow_scan_busy;
dim_o <= xf_rx_data_0(41 downto 22);
dim_en_o <= xf_rx_data_en_0 and xf_rx_data_0(36); -- only save analogue values
dim_trig_num_o <= xf_rx_data_0(41 downto 38);
dim_trig_lat_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36 downto 34) = "010") else '0';
dim_trig_unl_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36) = '1') else '0';
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
dim_addr <= xf_rx_data_0(41 downto 38) & xf_rx_data_0(36 downto 34);
ow_addr <= "00" & xf_rx_data_1(83 downto 80);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! 1st 3-wire serial receiver from XF
xf_rx_inst_0 : entity work.serial_3wire_rx
generic map (
data_width_g => 42)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_frame_i => xf_i.rx_frame(0),
rx_bit_en_i => xf_i.rx_bit_en(0),
rx_i => xf_i.rx(0),
data_o => xf_rx_data_0,
data_en_o => xf_rx_data_en_0,
error_o => xf_rx_error_0);
--! 2nd 3-wire serial receiver from XF
xf_rx_inst_1 : entity work.serial_3wire_rx
generic map (
data_width_g => 84)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_frame_i => xf_i.rx_frame(1),
rx_bit_en_i => xf_i.rx_bit_en(1),
rx_i => xf_i.rx(1),
data_o => xf_rx_data_1,
data_en_o => xf_rx_data_en_1,
error_o => xf_rx_error_1);
--! DIM pages
dim_page_inst : entity work.two_port_ram_tmr
generic map (
depth_g => 128,
width_g => 16)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => dim_addr,
wr_en_i => xf_rx_data_en_0,
wr_data_i => xf_rx_data_0(37 downto 22),
wr_done_o => open,
wr_busy_o => open,
rd_addr_i => dim_addr_i,
rd_en_i => dim_rd_en_i,
rd_data_o => dim_data_o,
rd_data_en_o => dim_data_en_o,
rd_busy_o => open);
--! One-wire pages
ow_page_inst : entity work.two_port_ram_tmr
generic map (
depth_g => 64,
width_g => 80)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => ow_addr,
wr_en_i => xf_rx_data_en_1,
wr_data_i => xf_rx_data_1(79 downto 0),
wr_done_o => open,
wr_busy_o => open,
rd_addr_i => ow_addr_i,
rd_en_i => ow_rd_en_i,
rd_data_o => ow_data_o,
rd_data_en_o => ow_data_en_o,
rd_busy_o => open);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
dim_trigger <= '0';
ow_scan_busy <= '0';
dim_reset <= '0';
ow_scan <= '0';
ow_bus_select <= (others => '0');
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if ms_0_strobe_i = '1' then
dim_reset <= command_i.dim_reset;
ow_scan <= command_i.ow_scan;
ow_bus_select <= command_i.ow_bus_select;
end if;
if ms_0_strobe_i = '1' then
dim_trigger <= '1';
elsif ms_1_strobe_i = '1' then
dim_trigger <= '0';
end if;
if command_i.ow_scan = '1' then
ow_scan_busy <= '1';
elsif xf_rx_data_en_1 = '1' then
ow_scan_busy <= '0';
end if;
end if;
end if;
end process regs;
end architecture rtl;
|
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic;
B1AUX : INOUT std_logic_vector(16 downto 9);
B2AUX : INOUT std_logic_vector(16 downto 1)
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
signal B1AUX : std_logic_vector(16 downto 9);
signal B2AUX : std_logic_vector(16 downto 1);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK,
B1AUX => B1AUX,
B2AUX => B2AUX
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= (others => '0');
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= (others => '1');
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc302.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00302ent IS
END c03s01b04x00p04n01i00302ent;
ARCHITECTURE c03s01b04x00p04n01i00302arch OF c03s01b04x00p04n01i00302ent IS
type REAL1 is range 1.0 to 9; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00302 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00302arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc302.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00302ent IS
END c03s01b04x00p04n01i00302ent;
ARCHITECTURE c03s01b04x00p04n01i00302arch OF c03s01b04x00p04n01i00302ent IS
type REAL1 is range 1.0 to 9; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00302 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00302arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc302.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00302ent IS
END c03s01b04x00p04n01i00302ent;
ARCHITECTURE c03s01b04x00p04n01i00302arch OF c03s01b04x00p04n01i00302ent IS
type REAL1 is range 1.0 to 9; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00302 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00302arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nor00 is
port(
clknr: in std_logic ;
codopnr: in std_logic_vector ( 3 downto 0 );
portAnr: in std_logic_vector ( 7 downto 0 );
portBnr: in std_logic_vector ( 7 downto 0 );
inFlagnr: in std_logic;
outnr: out std_logic_vector ( 7 downto 0 );
outFlagnr: out std_logic );
end;
architecture nor0 of nor00 is
begin
pnor: process(codopnr, portAnr, portBnr)
begin
if(codopnr = "0101") then
outnr <= portAnr nor portBnr;
outFlagnr <= '1';
else
outnr <= (others => 'Z');
outFlagnr <= 'Z';
end if;
end process pnor;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end nor0;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
library std;
use std.env.all;
entity testbench_file is
generic(
constant period: time:= 20 ps
);
end entity;
architecture arch of testbench_file is
component COUNTER8
port (
DATA: in std_logic_vector(7 downto 0);
NCCLR, NCCKEN, CCK, NCLOAD, RCK: in std_logic;
NRCO: out std_logic;
QDATA: out std_logic_vector(7 downto 0)
);
end component;
signal TEST_DATA: std_logic_vector(7 downto 0) := b"00000000";
signal NRCO: std_logic;
signal NCCLR: std_logic := '0';
signal RCK: std_logic := '0';
signal NCLOAD: std_logic := '1';
signal NCCKEN: std_Logic := '0';
signal CCK: std_logic := '0';
signal NRCO_FILE: std_logic := '0';
signal QDATA: std_logic_vector(7 downto 0) := b"00000000";
begin
COUNTER80: COUNTER8 port map(DATA=>TEST_DATA, NRCO=>NRCO, NCCKEN=>NCCKEN, CCK=>CCK, NCLOAD=>NCLOAD, RCK=>RCK, NCCLR=>NCCLR, QDATA=>QDATA);
CCK <= not CCK after period / 2;
--genereate data test file
create_data_file : process
file file_pointer : text;
variable file_status : file_open_status;
variable current_line : line;
-- prefix 'f' mean data readed from file
variable fDATA: std_logic_vector(7 downto 0);
variable fNCCLR, fNCCKEN, fCCK, fNCLOAD, fRCK: std_logic;
variable fNRCO: std_logic;
variable timestamp: time;
variable fQDATA: std_logic_vector(7 downto 0);
begin
-- create file
file_open(file_status, file_pointer, "test.data", READ_MODE);
-- check file open ok
assert(file_status = OPEN_OK)
report "ERROR: open file WRITE_MODE "
severity failure;
wait for period;
readloop:
while not endfile(file_pointer)
loop
-- DATA: in std_logic_vector(7 downto 0);
-- NCCLR, NCCKEN, CCK, NCLOAD, RCK: in std_logic;
-- NRCO: out std_logic
readline(file_pointer, current_line);
read(current_line, timestamp);
readline(file_pointer, current_line);
read(current_line, fDATA);
readline(file_pointer, current_line);
read(current_line, fNCCLR);
readline(file_pointer, current_line);
read(current_line, fNCCKEN);
readline(file_pointer, current_line);
read(current_line, fNCLOAD);
readline(file_pointer, current_line);
read(current_line, fRCK);
readline(file_pointer, current_line);
read(current_line, fNRCO);
readline(file_pointer, current_line);
read(current_line, fQDATA);
TEST_DATA <= fDATA;
NCCLR <= fNCCLR;
NCCKEN <= fNCCKEN;
NCLOAD <= fNCLOAD;
NRCO_FILE <= fNRCO;
RCK <= fRCK;
wait for period / 2;
assert(NRCO = NRCO_FILE) report ("Test failed on test.data");
assert(QDATA = fQDATA) report ("Test (2) failed");
end loop;
file_close(file_pointer);
stop(2);
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLROM_3_12.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_12
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLROM_3_12
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.OFDM_transmitter_pkg.ALL;
ENTITY TWDLROM_3_12 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : OUT std_logic
);
END TWDLROM_3_12;
ARCHITECTURE rtl OF TWDLROM_3_12 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_12_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_12_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_12_re_tmp <= twdlIn_re;
twdl_3_12_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_12_re <= std_logic_vector(twdl_3_12_re_tmp);
twdl_3_12_im <= std_logic_vector(twdl_3_12_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_12_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_12_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capability of a simulator.
--
--
-- Revision History: For more details, see CoveragePkg_release_notes.pdf
-- Date Version Description
-- 11/2016: 2016.11 Initial revision
-- 12/2016 2016.11a Fixed an issue with attributes
-- 1/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2016 - 2020 by Aldec
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
package VendorCovApiPkg is
subtype VendorCovHandleType is integer;
-- Types for how coverage bins are represented. Matches OSVVM types.
type VendorCovRangeType is record
min: integer;
max: integer;
end record;
type VendorCovRangeArrayType is array ( integer range <> ) of VendorCovRangeType;
-- Create Initial Data Structure for Point/Item Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovPointCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovPointCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CvpCreate";
-- Create Initial Data Structure for Cross Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovCrossCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovCrossCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CrCreate";
-- Sets/Updates the name of the Coverage Model.
-- Should not be called until the data structure is created by VendorCovPointCreate or VendorCovCrossCreate.
-- Replaces name that was set by VendorCovPointCreate or VendorCovCrossCreate.
procedure VendorCovSetName( obj: VendorCovHandleType; name: string );
attribute foreign of VendorCovSetName[ VendorCovHandleType, string ]: procedure is "VHPI systf; cvg_SetCoverName";
-- Add a bin or set of bins to either a Point/Item or Cross Functional Coverage Model
-- Checking for sizing that is different from original sizing already done in OSVVM CoveragePkg
-- It is important to maintain an index that corresponds to the order the bins were entered as
-- that is used when coverage is recorded.
procedure VendorCovBinAdd( obj: VendorCovHandleType; bins: VendorCovRangeArrayType; Action: integer; atleast: integer; name: string );
attribute foreign of VendorCovBinAdd[ VendorCovHandleType, VendorCovRangeArrayType, integer, integer, string ]: procedure is "VHPI systf; cvg_CvpCrBinCreate";
-- Increment the coverage of bin identified by index number.
-- Index ranges from 1 to Number of Bins.
-- Index corresponds to the order the bins were entered (starting from 1)
procedure VendorCovBinInc( obj: VendorCovHandleType; index: integer );
attribute foreign of VendorCovBinInc[ VendorCovHandleType, integer ]: procedure is "VHPI systf; cvg_CvpCrBinIncr";
-- Action (integer):
-- constant COV_COUNT : integer := 1;
-- constant COV_IGNORE : integer := 0;
-- constant COV_ILLEGAL : integer := -1;
end package;
package body VendorCovApiPkg is
-- Replace any existing package body for this package
end package body VendorCovApiPkg ;
|
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capability of a simulator.
--
--
-- Revision History: For more details, see CoveragePkg_release_notes.pdf
-- Date Version Description
-- 11/2016: 2016.11 Initial revision
-- 12/2016 2016.11a Fixed an issue with attributes
-- 1/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2016 - 2020 by Aldec
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
package VendorCovApiPkg is
subtype VendorCovHandleType is integer;
-- Types for how coverage bins are represented. Matches OSVVM types.
type VendorCovRangeType is record
min: integer;
max: integer;
end record;
type VendorCovRangeArrayType is array ( integer range <> ) of VendorCovRangeType;
-- Create Initial Data Structure for Point/Item Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovPointCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovPointCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CvpCreate";
-- Create Initial Data Structure for Cross Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovCrossCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovCrossCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CrCreate";
-- Sets/Updates the name of the Coverage Model.
-- Should not be called until the data structure is created by VendorCovPointCreate or VendorCovCrossCreate.
-- Replaces name that was set by VendorCovPointCreate or VendorCovCrossCreate.
procedure VendorCovSetName( obj: VendorCovHandleType; name: string );
attribute foreign of VendorCovSetName[ VendorCovHandleType, string ]: procedure is "VHPI systf; cvg_SetCoverName";
-- Add a bin or set of bins to either a Point/Item or Cross Functional Coverage Model
-- Checking for sizing that is different from original sizing already done in OSVVM CoveragePkg
-- It is important to maintain an index that corresponds to the order the bins were entered as
-- that is used when coverage is recorded.
procedure VendorCovBinAdd( obj: VendorCovHandleType; bins: VendorCovRangeArrayType; Action: integer; atleast: integer; name: string );
attribute foreign of VendorCovBinAdd[ VendorCovHandleType, VendorCovRangeArrayType, integer, integer, string ]: procedure is "VHPI systf; cvg_CvpCrBinCreate";
-- Increment the coverage of bin identified by index number.
-- Index ranges from 1 to Number of Bins.
-- Index corresponds to the order the bins were entered (starting from 1)
procedure VendorCovBinInc( obj: VendorCovHandleType; index: integer );
attribute foreign of VendorCovBinInc[ VendorCovHandleType, integer ]: procedure is "VHPI systf; cvg_CvpCrBinIncr";
-- Action (integer):
-- constant COV_COUNT : integer := 1;
-- constant COV_IGNORE : integer := 0;
-- constant COV_ILLEGAL : integer := -1;
end package;
package body VendorCovApiPkg is
-- Replace any existing package body for this package
end package body VendorCovApiPkg ;
|
library ieee;
use ieee.std_logic_1164.all;
entity case02 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case02;
architecture behav of case02 is
begin
with a select o <=
'1' when "00011",
'1' when "00110" | "00111" | "10001",
'0' when "00100",
'1' when "01100",
'1' when "10000",
'0' when others;
end behav;
|
-- Author : Miguel Morales-Sandoval
-- Project : "Reconfigurable ECC
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo grado del polinomio de reduccion D más 2 es menor a m.
-- Se trata básicamente de un multiplicador de digito combinacional. El tamaño del digito es D+2;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-----------------------------------------------------------------------------------
entity squarer_163 is
generic(
NUM_BITS : positive := 163 -- 163, 233, 277, 283, 409, 571 -- Orden del campo finito
);
port(
-- clk : in std_logic;
-- en : in std_logic;
Ax : in std_logic_vector(NUM_BITS-1 downto 0);-- 2
C_out : out std_logic_vector(NUM_BITS-1 downto 0)-- A2_x = (A_x) mod Fx
);
end;
---------------------------------------------------------------------------------------------------
architecture behave of squarer_163 is
--constant F_x: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
begin
C_out(162) <= ( Ax(81) xor Ax(159) ) xor Ax(161);
C_out(161) <= Ax(159) xor Ax(162);
C_out(160) <= ( Ax(80) xor Ax(158) ) xor Ax(160);
C_out(159) <= Ax(158) xor Ax(161);
C_out(158) <= ( Ax(79) xor Ax(157) ) xor Ax(159);
C_out(157) <= Ax(157) xor Ax(160);
C_out(156) <= ( Ax(78) xor Ax(156) ) xor Ax(158);
C_out(155) <= Ax(156) xor Ax(159);
C_out(154) <= ( Ax(77) xor Ax(155) ) xor Ax(157);
C_out(153) <= Ax(155) xor Ax(158);
C_out(152) <= ( Ax(76) xor Ax(154) ) xor Ax(156);
C_out(151) <= Ax(154) xor Ax(157);
C_out(150) <= ( Ax(75) xor Ax(153) ) xor Ax(155);
C_out(149) <= Ax(153) xor Ax(156);
C_out(148) <= ( Ax(74) xor Ax(152) ) xor Ax(154);
C_out(147) <= Ax(152) xor Ax(155);
C_out(146) <= ( Ax(73) xor Ax(151) ) xor Ax(153);
C_out(145) <= Ax(151) xor Ax(154);
C_out(144) <= ( Ax(72) xor Ax(150) ) xor Ax(152);
C_out(143) <= Ax(150) xor Ax(153);
C_out(142) <= ( Ax(71) xor Ax(149) ) xor Ax(151);
C_out(141) <= Ax(149) xor Ax(152);
C_out(140) <= ( Ax(70) xor Ax(148) ) xor Ax(150);
C_out(139) <= Ax(148) xor Ax(151);
C_out(138) <= ( Ax(69) xor Ax(147) ) xor Ax(149);
C_out(137) <= Ax(147) xor Ax(150);
C_out(136) <= ( Ax(68) xor Ax(146) ) xor Ax(148);
C_out(135) <= Ax(146) xor Ax(149);
C_out(134) <= ( Ax(67) xor Ax(145) ) xor Ax(147);
C_out(133) <= Ax(145) xor Ax(148);
C_out(132) <= ( Ax(66) xor Ax(144) ) xor Ax(146);
C_out(131) <= Ax(144) xor Ax(147);
C_out(130) <= ( Ax(65) xor Ax(143) ) xor Ax(145);
C_out(129) <= Ax(143) xor Ax(146);
C_out(128) <= ( Ax(64) xor Ax(142) ) xor Ax(144);
C_out(127) <= Ax(142) xor Ax(145);
C_out(126) <= ( Ax(63) xor Ax(141) ) xor Ax(143);
C_out(125) <= Ax(141) xor Ax(144);
C_out(124) <= ( Ax(62) xor Ax(140) ) xor Ax(142);
C_out(123) <= Ax(140) xor Ax(143);
C_out(122) <= ( Ax(61) xor Ax(139) ) xor Ax(141);
C_out(121) <= Ax(139) xor Ax(142);
C_out(120) <= ( Ax(60) xor Ax(138) ) xor Ax(140);
C_out(119) <= Ax(138) xor Ax(141);
C_out(118) <= ( Ax(59) xor Ax(137) ) xor Ax(139);
C_out(117) <= Ax(137) xor Ax(140);
C_out(116) <= ( Ax(58) xor Ax(136) ) xor Ax(138);
C_out(115) <= Ax(136) xor Ax(139);
C_out(114) <= ( Ax(57) xor Ax(135) ) xor Ax(137);
C_out(113) <= Ax(135) xor Ax(138);
C_out(112) <= ( Ax(56) xor Ax(134) ) xor Ax(136);
C_out(111) <= Ax(134) xor Ax(137);
C_out(110) <= ( Ax(55) xor Ax(133) ) xor Ax(135);
C_out(109) <= Ax(133) xor Ax(136);
C_out(108) <= ( Ax(54) xor Ax(132) ) xor Ax(134);
C_out(107) <= Ax(132) xor Ax(135);
C_out(106) <= ( Ax(53) xor Ax(131) ) xor Ax(133);
C_out(105) <= Ax(131) xor Ax(134);
C_out(104) <= ( Ax(52) xor Ax(130) ) xor Ax(132);
C_out(103) <= Ax(130) xor Ax(133);
C_out(102) <= ( Ax(51) xor Ax(129) ) xor Ax(131);
C_out(101) <= Ax(129) xor Ax(132);
C_out(100) <= ( Ax(50) xor Ax(128) ) xor Ax(130);
C_out(99) <= Ax(128) xor Ax(131);
C_out(98) <= ( Ax(49) xor Ax(127) ) xor Ax(129);
C_out(97) <= Ax(127) xor Ax(130);
C_out(96) <= ( Ax(48) xor Ax(126) ) xor Ax(128);
C_out(95) <= Ax(126) xor Ax(129);
C_out(94) <= ( Ax(47) xor Ax(125) ) xor Ax(127);
C_out(93) <= Ax(125) xor Ax(128);
C_out(92) <= ( Ax(46) xor Ax(124) ) xor Ax(126);
C_out(91) <= Ax(124) xor Ax(127);
C_out(90) <= ( Ax(45) xor Ax(123) ) xor Ax(125);
C_out(89) <= Ax(123) xor Ax(126);
C_out(88) <= ( Ax(44) xor Ax(122) ) xor Ax(124);
C_out(87) <= Ax(122) xor Ax(125);
C_out(86) <= ( Ax(43) xor Ax(121) ) xor Ax(123);
C_out(85) <= Ax(121) xor Ax(124);
C_out(84) <= ( Ax(42) xor Ax(120) ) xor Ax(122);
C_out(83) <= Ax(120) xor Ax(123);
C_out(82) <= ( Ax(41) xor Ax(119) ) xor Ax(121);
C_out(81) <= Ax(119) xor Ax(122);
C_out(80) <= ( Ax(40) xor Ax(118) ) xor Ax(120);
C_out(79) <= Ax(118) xor Ax(121);
C_out(78) <= ( Ax(39) xor Ax(117) ) xor Ax(119);
C_out(77) <= Ax(117) xor Ax(120);
C_out(76) <= ( Ax(38) xor Ax(116) ) xor Ax(118);
C_out(75) <= Ax(116) xor Ax(119);
C_out(74) <= ( Ax(37) xor Ax(115) ) xor Ax(117);
C_out(73) <= Ax(115) xor Ax(118);
C_out(72) <= ( Ax(36) xor Ax(114) ) xor Ax(116);
C_out(71) <= Ax(114) xor Ax(117);
C_out(70) <= ( Ax(35) xor Ax(113) ) xor Ax(115);
C_out(69) <= Ax(113) xor Ax(116);
C_out(68) <= ( Ax(34) xor Ax(112) ) xor Ax(114);
C_out(67) <= Ax(112) xor Ax(115);
C_out(66) <= ( Ax(33) xor Ax(111) ) xor Ax(113);
C_out(65) <= Ax(111) xor Ax(114);
C_out(64) <= ( Ax(32) xor Ax(110) ) xor Ax(112);
C_out(63) <= Ax(110) xor Ax(113);
C_out(62) <= ( Ax(31) xor Ax(109) ) xor Ax(111);
C_out(61) <= Ax(109) xor Ax(112);
C_out(60) <= ( Ax(30) xor Ax(108) ) xor Ax(110);
C_out(59) <= Ax(108) xor Ax(111);
C_out(58) <= ( Ax(29) xor Ax(107) ) xor Ax(109);
C_out(57) <= Ax(107) xor Ax(110);
C_out(56) <= ( Ax(28) xor Ax(106) ) xor Ax(108);
C_out(55) <= Ax(106) xor Ax(109);
C_out(54) <= ( Ax(27) xor Ax(105) ) xor Ax(107);
C_out(53) <= Ax(105) xor Ax(108);
C_out(52) <= ( Ax(26) xor Ax(104) ) xor Ax(106);
C_out(51) <= Ax(104) xor Ax(107);
C_out(50) <= ( Ax(25) xor Ax(103) ) xor Ax(105);
C_out(49) <= Ax(103) xor Ax(106);
C_out(48) <= ( Ax(24) xor Ax(102) ) xor Ax(104);
C_out(47) <= Ax(102) xor Ax(105);
C_out(46) <= ( Ax(23) xor Ax(101) ) xor Ax(103);
C_out(45) <= Ax(101) xor Ax(104);
C_out(44) <= ( Ax(22) xor Ax(100) ) xor Ax(102);
C_out(43) <= Ax(100) xor Ax(103);
C_out(42) <= ( Ax(21) xor Ax(99) ) xor Ax(101);
C_out(41) <= Ax(99) xor Ax(102);
C_out(40) <= ( Ax(20) xor Ax(98) ) xor Ax(100);
C_out(39) <= Ax(98) xor Ax(101);
C_out(38) <= ( Ax(19) xor Ax(97) ) xor Ax(99);
C_out(37) <= Ax(97) xor Ax(100);
C_out(36) <= ( Ax(18) xor Ax(96) ) xor Ax(98);
C_out(35) <= Ax(96) xor Ax(99);
C_out(34) <= ( Ax(17) xor Ax(95) ) xor Ax(97);
C_out(33) <= Ax(95) xor Ax(98);
C_out(32) <= ( Ax(16) xor Ax(94) ) xor Ax(96);
C_out(31) <= Ax(94) xor Ax(97);
C_out(30) <= ( Ax(15) xor Ax(93) ) xor Ax(95);
C_out(29) <= Ax(93) xor Ax(96);
C_out(28) <= ( Ax(14) xor Ax(92) ) xor Ax(94);
C_out(27) <= Ax(92) xor Ax(95);
C_out(26) <= ( Ax(13) xor Ax(91) ) xor Ax(93);
C_out(25) <= Ax(91) xor Ax(94);
C_out(24) <= ( Ax(12) xor Ax(90) ) xor Ax(92);
C_out(23) <= Ax(90) xor Ax(93);
C_out(22) <= ( Ax(11) xor Ax(89) ) xor Ax(91);
C_out(21) <= Ax(89) xor Ax(92);
C_out(20) <= ( Ax(10) xor Ax(88) ) xor Ax(90);
C_out(19) <= Ax(88) xor Ax(91);
C_out(18) <= ( Ax(9) xor Ax(87) ) xor Ax(89);
C_out(17) <= Ax(87) xor Ax(90);
C_out(16) <= ( Ax(8) xor Ax(86) ) xor Ax(88);
C_out(15) <= Ax(86) xor Ax(89);
C_out(14) <= ( Ax(7) xor Ax(85) ) xor Ax(87);
C_out(13) <= Ax(85) xor Ax(88);
C_out(12) <= ( Ax(6) xor Ax(84) ) xor (Ax(86) xor Ax(162));
C_out(11) <= Ax(84) xor Ax(87);
C_out(10) <= Ax(5) xor Ax(83) xor Ax(85) xor Ax(161) xor Ax(162);
C_out(9) <= Ax(83) xor Ax(86);
C_out(8) <= Ax(4) xor Ax(82) xor Ax(84) xor Ax(160) xor Ax(161);
C_out(7) <= Ax(82) xor Ax(85);
C_out(6) <= Ax(3) xor Ax(83) xor Ax(160) xor Ax(161);
C_out(5) <= Ax(84) xor Ax(161) xor Ax(162);
C_out(4) <= Ax(2) xor Ax(82) xor Ax(160);
C_out(3) <= Ax(83) xor Ax(160) xor Ax(161);
C_out(2) <= Ax(1) xor Ax(161);
C_out(1) <= Ax(82) xor Ax(160) xor Ax(162);
C_out(0) <= Ax(0) xor Ax(160);
end behave;
|
--
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix / Suffix
--
--
-- Description:
-- Alert handling and log filtering (verbosity control)
-- Alert handling provides a method to count failures, errors, and warnings
-- To accumlate counts, a data structure is created in a shared variable
-- It is of type AlertLogStructPType which is defined in AlertLogBasePkg
-- Log filtering provides verbosity control for logs (display or do not display)
-- AlertLogPkg provides a simplified interface to the shared variable
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Initial revision
-- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail,
-- ReportNonZeroAlerts, ReadLogEnables
-- 05/2015 2015.06 Added IncAlertCount, AffirmIf
-- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs
-- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel)
-- Created LocalInitialize
-- 05/2017 2017.05 AffirmIfEqual, AffirmIfDiff,
-- GetAffirmCount (deprecates GetAffirmCheckCount), IncAffirmCount (deprecates IncAffirmCheckCount),
-- IsAlertEnabled (alias), IsLogEnabled (alias)
-- 04/2018 2018.04 Fix to PathTail. Prep to change AlertLogIDType to a type.
-- 10/2018 2018.10 Added pragmas to allow alerts, logs, and affirmations in RTL code
-- Added local variable to mirror top level ErrorCount and display in simulator
-- Added prefix and suffix
-- Debug printing with number of errors as prefix
-- 01/2020 2020.01 Updated Licenses to Apache
-- 05/2020 2020.05 Added internal variables AlertCount (W, E, F) and ErrorCount (integer)
-- that hold the error state. These can be displayed in wave windows
-- in simulation to track number of errors.
-- Calls to std.env.stop now return ErrorCount
-- Updated calls to check for valid AlertLogIDs
-- Added affirmation count for each level.
-- Turn off reporting with SetAlertLogOptions (PrintAffirmations => TRUE) ;
-- Disabled Alerts now handled in separate bins and reported separately.
-- Turn off reporting with SetAlertLogOptions (PrintDisabledAlerts => TRUE) ;
-- 08/2020 2020.08 Alpha Test Release of Specification Tracking - Changes are provisional and subject to change
-- Added Passed Goals - reported with ReportAlerts and ReportRequirements.
-- Added WriteAlerts - CSV format of the information in ReportAlerts
-- Tests fail when requirements are not met and FailOnRequirementErrors is true (default TRUE).
-- Set using: SetAlertLogOptions(FailOnRequirementErrors => TRUE)
-- Turn on requirements printing in summary and details with PrintRequirements (default FALSE,
-- Turn on requirements printing in summary with PrintIfHaveRequirements (Default TRUE)
-- Added Requirements Bin, ReadSpecification, GetReqID, SetPassedGoal
-- Added AffirmIf("Req ID 1", ...) -- will work even if ID not set by GetReqID or ReadSpecification
-- Added ReportRequirements, WriteRequirements, and ReadRequirements (to merge results of multiple tests)
-- Added WriteTestSummary, ReadTestSummaries, ReportTestSummaries, and WriteTestSummaries.
-- 10/2020 2020.10 Added MetaMatch.
-- Updated AlertIfEqual and AlertIfNotEqual for std_logic family to use MetaMatch
-- 12/2020 2020.12 Added MetaMatch to AffirmIfEqual and AffirmIfNotEqual for std_logic family to use MetaMatch
-- Added AffirmIfEqual for boolean
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0.
constant ALERTLOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_BASE_ID + 1 ;
constant OSVVM_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 2 ; -- reporting for packages
constant REQUIREMENT_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 3 ;
-- May have its own ID or OSVVM_ALERTLOG_ID as default - most scoreboards allocate their own ID
constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- Same as ALERTLOG_DEFAULT_ID
constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right
constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ;
constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated
alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
------------------------------------------------------------
-- Alert always goes to the transcript file
procedure Alert(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) ;
procedure Alert( Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure IncAlertCount( -- A silent form of alert
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) ;
procedure IncAlertCount( Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Similar to assert, except condition is positive
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- Direct replacement for assert
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- overloading for common functionality
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Simple Diff for file comparisons
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) ;
procedure AffirmError( Message : string ) ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE );
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
-- Support for Specification / Requirements Tracking
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) ;
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure WriteTestSummary ( FileName : string ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean := FALSE
) ;
procedure ReadTestSummaries (FileName : string) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
procedure ClearAlertCounts ;
function "ABS" (L : AlertCountType) return AlertCountType ;
function "+" (L, R : AlertCountType) return AlertCountType ;
function "-" (L, R : AlertCountType) return AlertCountType ;
function "-" (R : AlertCountType) return AlertCountType ;
impure function SumAlertCount(AlertCount: AlertCountType) return integer ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount return integer ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ;
------------------------------------------------------------
-- log filtering for verbosity control, optionally has a separate file parameter
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ;
------------------------------------------------------------
-- Alert Enables
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
impure function GetAlertEnable(Level : AlertType) return boolean ;
alias IsAlertEnabled is GetAlertEnable[AlertLogIDType, AlertType return boolean] ;
alias IsAlertEnabled is GetAlertEnable[AlertType return boolean] ;
-- Log Enables
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
impure function GetLogEnable(Level : LogType) return boolean ;
alias IsLogEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as GetLogEnable
alias IsLogEnabled is GetLogEnable [LogType return boolean] ; -- same as GetLogEnable
procedure ReportLogEnables ;
procedure SetAlertLogName(Name : string ) ;
-- synthesis translate_off
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ;
-- synthesis translate_on
procedure DeallocateAlertLogStruct ;
procedure InitializeAlertLogStruct ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
------------------------------------------------------------
-- Accessor Methods
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertStopCount(Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertStopCount(Level : AlertType) return integer ;
------------------------------------------------------------
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
-- synthesis translate_off
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogPrintPassed return AlertLogOptionsType ;
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType ;
impure function GetAlertLogPrintRequirements return AlertLogOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
-- File Reading Utilities
function IsLogEnableType (Name : String) return boolean ;
procedure ReadLogEnables (file AlertLogInitFile : text) ;
procedure ReadLogEnables (FileName : string) ;
-- String Helper Functions -- This should be in a more general string package
function PathTail (A : string) return string ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
function MetaMatch (l, r : std_ulogic) return boolean ;
function MetaMatch (L, R : std_ulogic_vector) return boolean ;
function MetaMatch (L, R : unresolved_unsigned) return boolean ;
function MetaMatch (L, R : unresolved_signed) return boolean ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) ;
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) ;
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
alias IncAffirmCheckCount is IncAffirmCount [AlertLogIDType] ;
alias GetAffirmCheckCount is GetAffirmCount [return natural] ;
alias IsLoggingEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as IsLogEnabled
alias IsLoggingEnabled is GetLogEnable [LogType return boolean] ; -- same as IsLogEnabled
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
use work.NamePkg.all ;
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
type LogNameType is array(LogType) of string(1 to 7) ;
constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER "
------------------------------------------------------------
-- Package Local
function LeftJustify(A : String; Amount : integer) return string is
------------------------------------------------------------
constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ;
begin
if A'length >= Amount then
return A ;
else
return A & Spaces(1 to Amount - A'length) ;
end if ;
end function LeftJustify ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
------------------------------------------------------------
procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ;
procedure SetJustify (
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) ;
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ;
procedure WriteTestSummary ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
------------------------------------------------------------
-- FILE IO Controls
-- procedure SetTranscriptEnable (A : boolean := TRUE) ;
-- impure function IsTranscriptEnabled return boolean ;
-- procedure MirrorTranscript (A : boolean := TRUE) ;
-- impure function IsTranscriptMirrored return boolean ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) ;
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) ;
procedure Deallocate ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
-- Reporting Accessor
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType ;
FailOnDisabledErrors : AlertLogOptionsType ;
FailOnRequirementErrors : AlertLogOptionsType ;
ReportHierarchy : AlertLogOptionsType ;
WriteAlertErrorCount : AlertLogOptionsType ;
WriteAlertLevel : AlertLogOptionsType ;
WriteAlertName : AlertLogOptionsType ;
WriteAlertTime : AlertLogOptionsType ;
WriteLogErrorCount : AlertLogOptionsType ;
WriteLogLevel : AlertLogOptionsType ;
WriteLogName : AlertLogOptionsType ;
WriteLogTime : AlertLogOptionsType ;
PrintPassed : AlertLogOptionsType ;
PrintAffirmations : AlertLogOptionsType ;
PrintDisabledAlerts : AlertLogOptionsType ;
PrintRequirements : AlertLogOptionsType ;
PrintIfHaveRequirements : AlertLogOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogPrintPassed return AlertLogOptionsType ;
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType ;
impure function GetAlertLogPrintRequirements return AlertLogOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
end protected AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on
variable AffirmCheckCountVar : natural := 0 ;
variable PassedCountVar : natural := 0 ;
variable ErrorCount : integer := 0 ;
variable AlertCount : AlertCountType := (0, 0, 0) ;
------------------------------------------------------------
type AlertLogRecType is record
------------------------------------------------------------
Name : Line ;
NameLower : Line ;
Prefix : Line ;
Suffix : Line ;
ParentID : AlertLogIDType ;
ParentIDSet : Boolean ;
SiblingID : AlertLogIDType ;
ChildID : AlertLogIDType ;
ChildIDLast : AlertLogIDType ;
AlertCount : AlertCountType ;
DisabledAlertCount : AlertCountType ;
AffirmCount : Integer ;
PassedCount : Integer ;
PassedGoal : Integer ;
PassedGoalSet : Boolean ;
AlertStopCount : AlertCountType ;
AlertEnabled : AlertEnableType ;
LogEnabled : LogEnableType ;
-- Used only by ReadTestSummaries
TotalErrors : integer ;
AffirmPassedCount : integer ;
-- IsRequirment : boolean ;
end record AlertLogRecType ;
------------------------------------------------------------
-- Basis for AlertLog Data Structure
variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize
variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ;
type AlertLogRecPtrType is access AlertLogRecType ;
type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ;
type AlertLogArrayPtrType is access AlertLogArrayType ;
variable AlertLogPtr : AlertLogArrayPtrType ;
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
variable FailOnWarningVar : boolean := TRUE ;
variable FailOnDisabledErrorsVar : boolean := TRUE ;
variable FailOnRequirementErrorsVar : boolean := TRUE ;
variable ReportHierarchyVar : boolean := TRUE ;
variable FoundReportHierVar : boolean := FALSE ;
variable FoundAlertHierVar : boolean := FALSE ;
variable WriteAlertErrorCountVar : boolean := FALSE ;
variable WriteAlertLevelVar : boolean := TRUE ;
variable WriteAlertNameVar : boolean := TRUE ;
variable WriteAlertTimeVar : boolean := TRUE ;
variable WriteLogErrorCountVar : boolean := FALSE ;
variable WriteLogLevelVar : boolean := TRUE ;
variable WriteLogNameVar : boolean := TRUE ;
variable WriteLogTimeVar : boolean := TRUE ;
variable AlertPrefixVar : NamePType ;
variable LogPrefixVar : NamePType ;
variable ReportPrefixVar : NamePType ;
variable DoneNameVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
variable AlertLogJustifyAmountVar : integer := 0 ;
variable ReportJustifyAmountVar : integer := 0 ;
------------------------------------------------------------
-- PT Local
impure function VerifyID(
AlertLogID : AlertLogIDType ;
LOWEST_ID : AlertLogIDType := ALERTLOG_BASE_ID
) return AlertLogIDType is
------------------------------------------------------------
begin
if AlertLogID < LOWEST_ID or AlertLogID > NumAlertLogIDsVar then
Alert("Invalid AlertLogID") ;
return LOWEST_ID ;
else
return AlertLogID ;
end if ;
end function VerifyID ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
begin
return AffirmCheckCountVar ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).PassedCount := AlertLogPtr(localAlertLogID).PassedCount + 1 ;
PassedCountVar := PassedCountVar + 1 ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
begin
return PassedCountVar ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
-- PT Local
procedure IncrementAlertCount(
------------------------------------------------------------
constant AlertLogID : in AlertLogIDType ;
constant Level : in AlertType ;
variable StopDueToCount : inout boolean ;
variable IncrementByAmount : in integer := 1
) is
begin
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + IncrementByAmount ;
-- Exceeded Stop Count at this level?
if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then
StopDueToCount := TRUE ;
end if ;
-- Propagate counts to parent(s) -- Ascend Hierarchy
if AlertLogID /= ALERTLOG_BASE_ID then
IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount, IncrementByAmount) ;
end if ;
else
-- Disabled, increment disabled count
AlertLogPtr(AlertLogID).DisabledAlertCount(Level) := AlertLogPtr(AlertLogID).DisabledAlertCount(Level) + IncrementByAmount ;
end if ;
end procedure IncrementAlertCount ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
-- Only write and count when GlobalAlertEnabledVar is enabled
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
-- Write when Alert is Enabled
if AlertLogPtr(localAlertLogID).AlertEnabled(Level) then
-- Print %% Alert (nominally)
write(buf, AlertPrefix) ;
-- Debug Mode
if WriteAlertErrorCountVar then
write(buf, ' ' & justify(to_string(ErrorCount + 1), RIGHT, 2));
end if ;
-- Level Name, when enabled (default)
if WriteAlertLevelVar then
write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteAlertNameVar then
write(buf, " in " & LeftJustify(AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
-- Prefix
if AlertLogPtr(localAlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(localAlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteAlertTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end if ;
-- Always Count
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure IncAlertCount ;
------------------------------------------------------------
-- PT Local
impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is
------------------------------------------------------------
variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
variable CurID : AlertLogIDType ;
begin
ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar
ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
LowerLevelValues := CalcJustify(CurID, AlertLogPtr(CurID).Name'length, IndentAmount + 2) ;
ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ;
ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return ResultValues ;
end function CalcJustify ;
------------------------------------------------------------
procedure SetJustify (
------------------------------------------------------------
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) is
begin
if Enable then
(AlertLogJustifyAmountVar, ReportJustifyAmountVar) := CalcJustify(AlertLogID, 0, 0) ;
else
AlertLogJustifyAmountVar := 0 ;
ReportJustifyAmountVar := 0 ;
end if;
end procedure SetJustify ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertCount ;
end function GetAlertCount ;
------------------------------------------------------------
-- Local
impure function RemoveNonFailingWarnings(A : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
begin
Count := A ;
if not FailOnWarningVar then
Count(WARNING) := 0 ;
end if ;
return Count ;
end function RemoveNonFailingWarnings ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
variable Count : AlertCountType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return RemoveNonFailingWarnings( AlertLogPtr(localAlertLogID).AlertCount ) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Count := Count + AlertLogPtr(i).DisabledAlertCount ;
--? Should excluded warnings get counted as disabled errors?
--? if not FailOnWarningVar then
--? Count(WARNING) := Count(WARNING) + AlertLogPtr(i).AlertCount(WARNING) ;
--? end if ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function LocalGetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
variable CurID : AlertLogIDType ;
begin
Count := AlertLogPtr(AlertLogID).DisabledAlertCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
Count := Count + LocalGetDisabledAlertCount(CurID) ; -- Recursively descend into children
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return Count ;
end function LocalGetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return LocalGetDisabledAlertCount(localAlertLogID) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
-- Local
procedure GetRequirementsCount(
AlertLogID : AlertLogIDType;
RequirementsPassed : out integer ;
RequirementsGoal : out integer
) is
------------------------------------------------------------
variable ChildRequirementsPassed, ChildRequirementsGoal : integer ;
variable CurID : AlertLogIDType ;
begin
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
if AlertLogPtr(AlertLogID).PassedGoal > 0 then
RequirementsGoal := 1 ;
if AlertLogPtr(AlertLogID).PassedCount >= AlertLogPtr(AlertLogID).PassedGoal then
RequirementsPassed := 1 ;
end if ;
end if ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetRequirementsCount(CurID, ChildRequirementsPassed, ChildRequirementsGoal) ;
RequirementsPassed := RequirementsPassed + ChildRequirementsPassed ;
RequirementsGoal := RequirementsGoal + ChildRequirementsGoal ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetRequirementsCount ;
------------------------------------------------------------
-- Local
procedure GetPassedAffirmCount(
AlertLogID : AlertLogIDType;
PassedCount : out integer ;
AffirmCount : out integer
) is
------------------------------------------------------------
variable ChildPassedCount, ChildAffirmCount : integer ;
variable CurID : AlertLogIDType ;
begin
PassedCount := AlertLogPtr(AlertLogID).PassedCount ;
AffirmCount := AlertLogPtr(AlertLogID).AffirmCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetPassedAffirmCount(CurID, ChildPassedCount, ChildAffirmCount) ;
PassedCount := PassedCount + ChildPassedCount ;
AffirmCount := AffirmCount + ChildAffirmCount ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetPassedAffirmCount ;
------------------------------------------------------------
-- PT Local
procedure PrintTopAlerts (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Name : string ;
ExternalErrors : AlertCountType ;
variable HasDisabledAlerts : inout Boolean ;
variable TestFailed : inout Boolean
) is
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal, TotalRequirementErrors : integer ;
variable AlertCountVar, DisabledAlertCount : AlertCountType ;
variable PassedCount, AffirmCheckCount : integer ;
begin
AlertCountVar := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(AlertCountVar)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
HasDisabledAlerts := TotalDisabledAlertErrors /= 0 ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
TestFailed := TotalErrors /= 0 ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCheckCount) ;
if not TestFailed then
write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; -- PASSED
else
write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; -- FAILED
end if ;
--? Also print when warnings exist and are hidden by FailOnWarningVar=FALSE
if TestFailed then
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCountVar(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCountVar(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCountVar(WARNING) ) ) ;
end if ;
if HasDisabledAlerts or PrintDisabledAlertsVar then -- print if exist or enabled
write(buf, " Total Disabled Error(s) = " & to_string(TotalDisabledAlertErrors)) ;
end if ;
if (HasDisabledAlerts and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then -- print if enabled
write(buf, " Failures: " & to_string(DisabledAlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or (AffirmCheckCount /= 0) or PrintAffirmationsVar then -- Print if passed or printing affirmations
write(buf, " Passed: " & to_string(PassedCount)) ;
end if;
if (AffirmCheckCount /= 0) or PrintAffirmationsVar then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCount)) ;
end if ;
if PrintRequirementsVar or
(PrintIfHaveRequirementsVar and HasRequirementsVar) or
(FailOnRequirementErrorsVar and TotalRequirementErrors /= 0)
then
write(buf, " Requirements Passed: " & to_string(TotalRequirementsPassed) &
" of " & to_string(TotalRequirementsGoal) ) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end procedure PrintTopAlerts ;
------------------------------------------------------------
-- PT Local
procedure PrintOneChild(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportAll : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
alias CurID : AlertLogIDType is AlertLogID ;
begin
if
ReportAll or -- ReportAlerts
-- ReportNonZeroAlerts and (AlertCount or (FailOn and DisabledAlertCount))
(SumAlertCount(AlertLogPtr(CurID).AlertCount) > 0) or
(FailOnDisabledErrorsVar and (SumAlertCount(AlertLogPtr(CurID).DisabledAlertCount) > 0)) or
(FailOnRequirementErrorsVar and (AlertLogPtr(CurID).PassedCount < AlertLogPtr(CurID).PassedGoal))
then
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(CurID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
write(buf, " Failures: " & to_string(AlertLogPtr(CurID).AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).AlertCount(WARNING) ) ) ;
if (HasDisabledErrors and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then
write(buf, " Disabled Failures: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or PrintRequirementsVar then
write(buf, " Passed: " & to_string(AlertLogPtr(CurID).PassedCount)) ;
end if;
if PrintRequirementsVar then
write(buf, " of " & to_string(AlertLogPtr(CurID).PassedGoal) ) ;
end if ;
if PrintAffirmationsVar then
write(buf, " Affirmations: " & to_string(AlertLogPtr(CurID).AffirmCount ) ) ;
end if ;
WriteLine(buf) ;
end if ;
end procedure PrintOneChild ;
------------------------------------------------------------
-- PT Local
procedure IterateAndPrintChildren(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportAll : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
PrintOneChild(
AlertLogID => CurID,
Prefix => Prefix,
IndentAmount => IndentAmount,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors
) ;
IterateAndPrintChildren(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure IterateAndPrintChildren ;
------------------------------------------------------------
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := TRUE
) is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
if IsOsvvmStringSet(Name) then
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => Name,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
else
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => AlertLogPtr(localAlertLogID).Name.all,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
end if ;
--Print Hierarchy when enabled and test failed
if (FoundReportHierVar and ReportHierarchyVar) and TestFailed then
-- (NumErrors /= 0 or (NumDisabledErrors /=0 and FailOnDisabledErrorsVar)) then
IterateAndPrintChildren(
AlertLogID => localAlertLogID,
Prefix => ReportPrefix & " ",
IndentAmount => 2,
ReportAll => ReportAll,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
end if ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable SavedPrintRequirementsVar : boolean ;
begin
SavedPrintRequirementsVar := PrintRequirementsVar ;
PrintRequirementsVar := TRUE ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintTopAlerts (
AlertLogID => ALERTLOG_BASE_ID,
Name => AlertLogPtr(ALERTLOG_BASE_ID).Name.all,
ExternalErrors => (0,0,0),
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
IterateAndPrintChildren(
AlertLogID => REQUIREMENT_ALERTLOG_ID,
Prefix => ReportPrefix & " ",
IndentAmount => 2,
ReportAll => TRUE,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
PrintRequirementsVar := SavedPrintRequirementsVar ;
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is
------------------------------------------------------------
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable NumErrors : integer ;
begin
NumErrors := SumAlertCount(AlertCount) ;
if NumErrors = 0 then
-- Passed
write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
else
-- Failed
write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ;
write(buf, " Total Error(s) = " & to_string(NumErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
writeLine(buf) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
-- PT Local
impure function IsRequirement(AlertLogID : AlertLogIDType) return boolean is
------------------------------------------------------------
begin
if AlertLogID = REQUIREMENT_ALERTLOG_ID then
return TRUE ;
elsif AlertLogID <= ALERTLOG_BASE_ID then
return FALSE ;
else
return IsRequirement(AlertLogPtr(AlertLogID).ParentID) ;
end if ;
end function IsRequirement ;
------------------------------------------------------------
-- pt local
procedure WriteOneTestSummary (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
begin
-- Should disabled errors be included here?
-- In the previous step, we counted DisabledErrors as a regular error if FailOnDisabledErrorsVar (default TRUE)
write(buf, AlertLogPtr(AlertLogID).Name.all & Delimiter) ;
write(buf, to_string( RequirementsGoal ) & Delimiter) ;
write(buf, to_string( RequirementsPassed ) & Delimiter) ;
write(buf, to_string( TotalErrors ) & Delimiter) ;
write(buf, to_string( AlertCount(FAILURE) ) & Delimiter) ;
write(buf, to_string( AlertCount(ERROR) ) & Delimiter) ;
write(buf, to_string( AlertCount(WARNING) ) & Delimiter) ;
write(buf, to_string( AffirmCount ) & Delimiter) ;
write(buf, to_string( PassedCount )) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (file TestFile : text) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal : integer ;
variable TotalRequirementErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
constant AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
variable PassedCount, AffirmCount : integer ;
constant DELIMITER : string := "," ;
begin
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCount) ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => AlertLogID,
RequirementsGoal => TotalRequirementsGoal,
RequirementsPassed => TotalRequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => TotalAlertCount,
AffirmCount => AffirmCount,
PassedCount => PassedCount,
Delimiter => DELIMITER
) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummary(TestFile => TestFile) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries ( -- PT Local
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
-- Descend from WriteRequirements
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
WriteTestSummaries(TestFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummaries(
TestFile => TestFile,
AlertLogID => REQUIREMENT_ALERTLOG_ID
) ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportOneTestSummary ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
begin
write(buf, ReportPrefix & " ") ;
if (AffirmCount > 0) and (TotalErrors = 0) then
write(buf, PassName) ;
elsif TotalErrors > 0 then
write(buf, FailName) ;
else
write(buf, string'("??????")) ;
end if ;
write(buf, " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar)) ;
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " Affirmations Passed: " & to_string(PassedCount) &
" of " & to_string(AffirmCount)) ;
write(buf, " Requirements Passed: " & to_string(RequirementsPassed) &
" of " & to_string(RequirementsGoal) ) ;
WriteLine(buf) ;
end procedure ReportOneTestSummary ;
------------------------------------------------------------
procedure ReportTestSummaries ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
ReportOneTestSummary(
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
ReportTestSummaries(
AlertLogID => CurID
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
variable IgnoredValue, OldReportJustifyAmount : integer ;
begin
OldReportJustifyAmount := ReportJustifyAmountVar ;
(IgnoredValue, ReportJustifyAmountVar) := CalcJustify(REQUIREMENT_ALERTLOG_ID, 0, 0) ;
ReportTestSummaries(AlertLogID => REQUIREMENT_ALERTLOG_ID) ;
ReportJustifyAmountVar := OldReportJustifyAmount ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
-- pt local
procedure WriteAlerts ( -- pt local
file AlertsFile : text ;
AlertLogID : AlertLogIDType
) is
------------------------------------------------------------
-- Format: Name, PassedGoal, #Passed, #TotalErrors, FAILURE, ERROR, WARNING, Affirmations
variable buf : line ;
variable AlertCountVar : AlertCountType ;
constant DELIMITER : character := ',' ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
write(buf, AlertLogPtr(CurID).Name.all) ;
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedGoal)) ;
-- Handling for PassedCount > PassedGoal done in ReadRequirements
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ;
AlertCountVar := AlertLogPtr(CurID).AlertCount ;
if FailOnDisabledErrorsVar then
AlertCountVar := AlertCountVar + AlertLogPtr(CurID).DisabledAlertCount ;
end if;
-- TotalErrors
write(buf, DELIMITER & to_string( SumAlertCount(RemoveNonFailingWarnings(AlertCountVar)))) ;
write(buf, DELIMITER & to_string( AlertCountVar(FAILURE) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(ERROR) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(WARNING) )) ;
write(buf, DELIMITER & to_string( AlertLogPtr(CurID).AffirmCount )) ;
-- write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ; -- redundancy intentional, for reading WriteTestSummary
WriteLine(AlertsFile, buf) ;
WriteAlerts(AlertsFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(RequirementsFile) ;
if IsRequirement(localAlertLogID) then
WriteAlerts(RequirementsFile, localAlertLogID) ;
else
Alert("WriteRequirements: Called without a Requirement") ;
WriteAlerts(RequirementsFile, REQUIREMENT_ALERTLOG_ID) ;
end if ;
end procedure WriteRequirements ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file AlertsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(AlertsFile) ;
WriteAlerts(AlertsFile, localAlertLogID) ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure ReadSpecification (file SpecificationFile : text ; PassedGoalIn : integer ) is -- PT Local
------------------------------------------------------------
variable buf,Name,Description : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable PassedGoal : integer ;
variable PassedGoalSet : boolean ;
variable Char : character ;
constant DELIMITER : character := ',' ;
variable AlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
-- Format: Spec Name, [Spec Description = "",] [Requirement Goal = 0]
ReadFileLoop : while not EndFile(SpecificationFile) loop
ReadLoop : loop
ReadLine(SpecificationFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
PassedGoal := DefaultPassedGoalVar ;
PassedGoalSet := FALSE ;
-- Read Name and Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Name", FAILURE) ;
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Optional: Read Description
ReadUntilDelimiterOrEOL(buf, Description, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Description", FAILURE) ;
if IsNumber(Description.all) then
read(Description, PassedGoal, ReadValid) ;
deallocate(Description) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal (while skipping Description)", FAILURE) ;
PassedGoalSet := TRUE ;
else
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Read PassedGoal
read(buf, PassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal", FAILURE) ;
PassedGoalSet := TRUE ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ; -- For new items, sets DefaultPassedGoalVar and PassedGoalSet = FALSE.
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ;
deallocate(Name) ;
deallocate(Description) ; -- not used
-- Implementation 1: Just put the values in
-- If Override values specified, then use them.
if PassedGoalIn >= 0 then
PassedGoal := PassedGoalIn ;
PassedGoalSet := TRUE ;
end if ;
if PassedGoalSet then
-- Is there a goal to update?
if AlertLogPtr(AlertLogID).PassedGoalSet then
-- Merge Old and New
AlertLogPtr(AlertLogID).PassedGoal := maximum(PassedGoal, AlertLogPtr(AlertLogID).PassedGoal) ;
else
-- No Old, Just use New
AlertLogPtr(AlertLogID).PassedGoal := PassedGoal ;
end if ;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end if ;
end loop ReadFileLoop ;
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file SpecificationFile : text open READ_MODE is FileName ;
begin
ReadSpecification(SpecificationFile, PassedGoal) ;
end procedure ReadSpecification ;
------------------------------------------------------------
-- PT Local
procedure ReadRequirements ( -- PT Local
file RequirementsFile : text ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
constant DELIMITER : character := ',' ;
variable buf,Name : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable StopDueToCount : boolean := FALSE ;
-- variable ReadFailed : boolean := TRUE ;
variable Found : boolean ;
variable ReqPassedGoal : integer ;
variable ReqPassedCount : integer ;
variable TotalErrorCount : integer ;
variable AlertCount : AlertCountType ;
variable AffirmCount : integer ;
variable AffirmPassedCount : integer ;
variable AlertLogID : AlertLogIDType ;
begin
if not TestSummary then
-- For requirements, skip the first line that has the test summary
ReadLine(RequirementsFile, buf) ;
end if ;
ReadFileLoop : while not EndFile(RequirementsFile) loop
ReadLoop : loop
ReadLine(RequirementsFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
-- ReadFailed := TRUE ;
ReqPassedGoal := 0 ;
ReqPassedCount := 0 ;
TotalErrorCount := 0 ;
AlertCount := (0, 0, 0) ;
AffirmCount := 0 ;
AffirmPassedCount := 0 ;
-- Read Name. Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading Name", FAILURE) ;
-- Read ReqPassedGoal
read(buf, ReqPassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedGoal", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedGoal", FAILURE) ;
-- Read ReqPassedCount
read(buf, ReqPassedCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedCount", FAILURE) ;
AffirmPassedCount := ReqPassedGoal ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read TotalErrorCount
read(buf, TotalErrorCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading TotalErrorCount", FAILURE) ;
AlertCount := (0, TotalErrorCount, 0) ; -- Default
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read AlertCount
for i in AlertType'left to AlertType'right loop
read(buf, AlertCount(i), ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
end loop ;
-- Read AffirmCount
read(buf, AffirmCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading AffirmCount", FAILURE) ;
if TestSummary then
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading AffirmCount", FAILURE) ;
-- Read AffirmPassedCount
read(buf, AffirmPassedCount, ReadValid) ;
if not ReadValid then
AffirmPassedCount := ReqPassedGoal ;
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadRequirements: Failed while reading AffirmPassedCount", FAILURE) ;
exit ReadFileLoop ;
end if ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ;
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ; --! GHDL
deallocate(Name) ;
-- if Merge then
-- Passed Goal
if AlertLogPtr(AlertLogID).PassedGoalSet then
AlertLogPtr(AlertLogID).PassedGoal := maximum(AlertLogPtr(AlertLogID).PassedGoal, ReqPassedGoal) ;
else
AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
end if ;
-- Requirements Passed Count
if ThresholdPassed then
ReqPassedCount := minimum(ReqPassedCount, ReqPassedGoal) ;
end if ;
AlertLogPtr(AlertLogID).PassedCount := AlertLogPtr(AlertLogID).PassedCount + ReqPassedCount ;
AlertLogPtr(AlertLogID).TotalErrors := AlertLogPtr(AlertLogID).TotalErrors + TotalErrorCount ;
-- AlertCount
IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
-- AffirmCount
AlertLogPtr(AlertLogID).AffirmCount := AlertLogPtr(AlertLogID).AffirmCount + AffirmCount ;
AlertLogPtr(AlertLogID).AffirmPassedCount := AlertLogPtr(AlertLogID).AffirmPassedCount + AffirmPassedCount ;
-- else
-- AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
-- AlertLogPtr(AlertLogID).PassedCount := ReqPassedCount ;
--
-- IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
-- IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
-- IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
--
-- AlertLogPtr(AlertLogID).AffirmCount := ReqPassedCount + TotalErrorCount ;
-- end if;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end loop ReadFileLoop ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open READ_MODE is FileName ;
begin
ReadRequirements(RequirementsFile, ThresholdPassed, TestSummary) ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
AlertCount := (0, 0, 0) ;
ErrorCount := 0 ;
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertCount := (0, 0, 0) ;
AlertLogPtr(i).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(i).AffirmCount := 0 ;
AlertLogPtr(i).PassedCount := 0 ;
AlertLogPtr(i).PassedGoal := 0 ;
end loop ;
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end loop ;
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
-- PT Local
procedure LocalLog (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType
) is
variable buf : line ;
constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
begin
-- Print %% log (nominally)
write(buf, LogPrefix) ;
-- Debug Mode
if WriteLogErrorCountVar then
if WriteAlertErrorCountVar then
if ErrorCount > 0 then
write(buf, ' ' & justify(to_string(ErrorCount), RIGHT, 2)) ;
else
swrite(buf, " ") ;
end if ;
end if ;
end if ;
-- Level Name, when enabled (default)
if WriteLogLevelVar then
write(buf, " " & LOG_NAME(Level) ) ;
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteLogNameVar then
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
-- Prefix
if AlertLogPtr(AlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(AlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteLogTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end procedure LocalLog ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS or Enable then
LocalLog(localAlertLogID, Message, Level) ;
elsif AlertLogPtr(localAlertLogID).LogEnabled(Level) then
LocalLog(localAlertLogID, Message, Level) ;
end if ;
if Level = PASSED then
IncAffirmPassedCount(AlertLogID) ; -- count the passed and affirmation
end if ;
end procedure log ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).NameLower := new string'(to_lower(NAME)) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Name.all ;
end function GetAlertLogName ;
------------------------------------------------------------
-- PT Local
procedure DeQueueID(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable ParentID, CurID : AlertLogIDType ;
begin
ParentID := AlertLogPtr(AlertLogID).ParentID ;
CurID := AlertLogPtr(ParentID).ChildID ;
-- Found at top of list
if AlertLogPtr(ParentID).ChildID = AlertLogID then
AlertLogPtr(ParentID).ChildID := AlertLogPtr(AlertLogID).SiblingID ;
else
-- Find among Siblings
loop
if AlertLogPtr(CurID).SiblingID = AlertLogID then
AlertLogPtr(CurID).SiblingID := AlertLogPtr(AlertLogID).SiblingID ;
exit ;
end if ;
if AlertLogPtr(CurID).SiblingID <= ALERTLOG_BASE_ID then
Alert("DeQueueID: AlertLogID not found") ;
exit ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure DeQueueID ;
------------------------------------------------------------
-- PT Local
procedure EnQueueID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
AlertLogPtr(AlertLogID).ParentID := ParentID ;
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
if AlertLogPtr(ParentID).ChildID < ALERTLOG_BASE_ID then
AlertLogPtr(ParentID).ChildID := AlertLogID ;
else
CurID := AlertLogPtr(ParentID).ChildIDLast ;
AlertLogPtr(CurID).SiblingID := AlertLogID ;
end if ;
AlertLogPtr(ParentID).ChildIDLast := AlertLogID ;
end procedure EnQueueID ;
------------------------------------------------------------
-- PT Local
procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is
------------------------------------------------------------
variable AlertEnabled : AlertEnableType ;
variable AlertStopCount : AlertCountType ;
variable LogEnabled : LogEnableType ;
begin
AlertLogPtr(AlertLogID) := new AlertLogRecType ;
if AlertLogID = ALERTLOG_BASE_ID then
AlertEnabled := (TRUE, TRUE, TRUE) ;
LogEnabled := (others => FALSE) ;
AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, TRUE) ;
else
if ParentID < ALERTLOG_BASE_ID then
AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ;
LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, FALSE) ;
else
AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ;
LogEnabled := AlertLogPtr(ParentID).LogEnabled ;
EnQueueID(AlertLogID, ParentID, TRUE) ;
end if ;
AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end if ;
AlertLogPtr(AlertLogID).Name := new string'(NAME) ;
AlertLogPtr(AlertLogID).NameLower := new string'(to_lower(NAME)) ;
AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).AffirmCount := 0 ;
AlertLogPtr(AlertLogID).PassedCount := 0 ;
AlertLogPtr(AlertLogID).PassedGoal := 0 ;
AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ;
AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ;
AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ;
-- Set ChildID, ChildIDLast, SiblingID to ALERTLOG_ID_NOT_ASSIGNED
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildIDLast := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).TotalErrors := 0 ;
AlertLogPtr(AlertLogID).AffirmPassedCount := 0 ;
end procedure NewAlertLogRec ;
------------------------------------------------------------
-- PT Local
-- Construct initial data structure
procedure LocalInitialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
if NumAllocatedAlertLogIDsVar /= 0 then
Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ;
return ;
end if ;
-- Initialize Pointer
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
-- Create BASE AlertLogID (if it differs from DEFAULT
NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ;
-- Create DEFAULT AlertLogID
NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := ALERT_DEFAULT_ID ;
-- Create OSVVM AlertLogID (if it differs from DEFAULT
if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if REQUIREMENT_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(REQUIREMENT_ALERTLOG_ID, "Requirements", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then
NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
end procedure LocalInitialize ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
LocalInitialize(NewNumAlertLogIDs) ;
end procedure Initialize ;
------------------------------------------------------------
-- PT Local
-- Constructs initial data structure using constant below
impure function LocalInitialize return boolean is
------------------------------------------------------------
begin
LocalInitialize(MIN_NUM_AL_IDS) ;
return TRUE ;
end function LocalInitialize ;
constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Deallocate(AlertLogPtr(i).Name) ;
Deallocate(AlertLogPtr(i)) ;
end loop ;
deallocate(AlertLogPtr) ;
-- Free up space used by protected types within AlertLogPkg
AlertPrefixVar.Deallocate ;
LogPrefixVar.Deallocate ;
ReportPrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
-- Restore variables to their initial state
PrintPassedVar := TRUE ;
PrintAffirmationsVar := FALSE ;
PrintDisabledAlertsVar := FALSE ;
PrintRequirementsVar := FALSE ;
PrintIfHaveRequirementsVar := TRUE ;
DefaultPassedGoalVar := 1 ;
NumAlertLogIDsVar := 0 ;
NumAllocatedAlertLogIDsVar := 0 ;
GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
FailOnWarningVar := TRUE ;
FailOnDisabledErrorsVar := TRUE ;
FailOnRequirementErrorsVar := TRUE ;
ReportHierarchyVar := TRUE ;
FoundReportHierVar := FALSE ;
FoundAlertHierVar := FALSE ;
WriteAlertErrorCountVar := FALSE ;
WriteAlertLevelVar := TRUE ;
WriteAlertNameVar := TRUE ;
WriteAlertTimeVar := TRUE ;
WriteLogErrorCountVar := FALSE ;
WriteLogLevelVar := TRUE ;
WriteLogNameVar := TRUE ;
WriteLogTimeVar := TRUE ;
end procedure Deallocate ;
------------------------------------------------------------
-- PT Local.
procedure GrowAlertStructure (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NumAllocatedAlertLogIDsVar = 0 then
Initialize (NewNumAlertLogIDs) ; -- Construct initial structure
else
oldAlertLogPtr := AlertLogPtr ;
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ;
AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ;
deallocate(oldAlertLogPtr) ;
end if ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
end procedure GrowAlertStructure ;
------------------------------------------------------------
-- Sets a AlertLogPtr to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NewNumAlertLogIDs) ;
end if;
end procedure SetNumAlertLogIDs ;
------------------------------------------------------------
-- PT Local
impure function GetNextAlertLogID return AlertLogIDType is
------------------------------------------------------------
variable NewNumAlertLogIDs : AlertLogIDType ;
begin
NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ;
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ;
end if ;
NumAlertLogIDsVar := NewNumAlertLogIDs ;
return NumAlertLogIDsVar ;
end function GetNextAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
impure function LocalFindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
if ParentID = ALERTLOG_ID_NOT_ASSIGNED then
return FindAlertLogID(Name) ;
else
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all and
(AlertLogPtr(i).ParentID = ParentID or AlertLogPtr(i).ParentIDSet = FALSE)
then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end if ;
end function LocalFindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
return LocalFindAlertLogID(Name, localParentID) ;
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure AdjustID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
begin
if IsRequirement(AlertLogID) and not IsRequirement(ParentID) then
Alert(AlertLogID, "GetAlertLogID/GetReqID: Parent of a Requirement must be a Requirement") ;
else
if ParentID /= AlertLogPtr(AlertLogID).ParentID then
DeQueueID(AlertLogID) ;
EnQueueID(AlertLogID, ParentID, ParentIDSet) ;
else
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
end if ;
end if ;
end procedure AdjustID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set localParentID
if AlertLogPtr(ResultID).ParentIDSet = FALSE and localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
-- else -- do not update as ParentIDs are either same or input localParentID = ALERTLOG_ID_NOT_ASSIGNED
end if ;
else
-- Create a new ID
ResultID := GetNextAlertLogID ;
NewAlertLogRec(ResultID, Name, localParentID) ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
AlertLogPtr(ResultID).PassedGoal := 0 ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
return ResultID ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set localParentID
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
else
AdjustID(ResultID, REQUIREMENT_ALERTLOG_ID, FALSE) ;
end if ;
end if ;
if AlertLogPtr(ResultID).PassedGoalSet = FALSE then
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
else
-- Create a new ID
ResultID := GetNextAlertLogID ;
if localParentID = ALERTLOG_ID_NOT_ASSIGNED then
NewAlertLogRec(ResultID, Name, REQUIREMENT_ALERTLOG_ID) ;
AlertLogPtr(ResultID).ParentIDSet := FALSE ;
else
NewAlertLogRec(ResultID, Name, localParentID) ;
end if ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
return ResultID ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localAlertLogID := VerifyID(AlertLogID) ;
if PassedGoal >= 0 then
AlertLogPtr(localAlertLogID).PassedGoal := PassedGoal ;
else
AlertLogPtr(localAlertLogID).PassedGoal := DefaultPassedGoalVar ;
end if ;
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ParentID ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Prefix := new string'(Name) ;
end if ;
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
end procedure UnSetAlertLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Prefix.all ;
end function GetAlertLogPrefix ;
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Suffix := new string'(Name) ;
end if ;
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
end procedure UnSetAlertLogSuffix ;
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Suffix.all ;
end function GetAlertLogSuffix ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
GlobalAlertEnabledVar := A ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return GlobalAlertEnabledVar ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
-- PT LOCAL
procedure SetOneStopCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType ;
Count : integer
) is
begin
if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then
AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ;
else
AlertLogPtr(AlertLogID).AlertStopCount(Level) :=
AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ;
end if ;
end procedure SetOneStopCount ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
SetOneStopCount(AlertLogID, Level, Count) ;
if AlertLogID /= ALERTLOG_BASE_ID then
LocalSetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ;
end if ;
end procedure LocalSetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertStopCount(AlertLogID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertStopCount(Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertEnabled(Level) := Enable ;
end loop ;
end procedure SetAlertEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetAlertEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertEnabled(Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).LogEnabled(Level) := Enable ;
end loop ;
end procedure SetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetLogEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetLogEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS then
return TRUE ;
else
return AlertLogPtr(localAlertLogID).LogEnabled(Level) ;
end if ;
end function GetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure PrintLogLevels(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
for i in LogIndexType loop
if AlertLogPtr(AlertLogID).LogEnabled(i) then
-- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ;
write(buf, " " & to_string(i)) ;
end if ;
end loop ;
WriteLine(buf) ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Always print requirements
-- if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
-- CurID := AlertLogPtr(CurID).SiblingID ;
-- next ;
-- end if ;
PrintLogLevels(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure PrintLogLevels ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
variable TurnedOnJustify : boolean := FALSE ;
begin
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType ;
FailOnDisabledErrors : AlertLogOptionsType ;
FailOnRequirementErrors : AlertLogOptionsType ;
ReportHierarchy : AlertLogOptionsType ;
WriteAlertErrorCount : AlertLogOptionsType ;
WriteAlertLevel : AlertLogOptionsType ;
WriteAlertName : AlertLogOptionsType ;
WriteAlertTime : AlertLogOptionsType ;
WriteLogErrorCount : AlertLogOptionsType ;
WriteLogLevel : AlertLogOptionsType ;
WriteLogName : AlertLogOptionsType ;
WriteLogTime : AlertLogOptionsType ;
PrintPassed : AlertLogOptionsType ;
PrintAffirmations : AlertLogOptionsType ;
PrintDisabledAlerts : AlertLogOptionsType ;
PrintRequirements : AlertLogOptionsType ;
PrintIfHaveRequirements : AlertLogOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string
) is
begin
if FailOnWarning /= OPT_INIT_PARM_DETECT then
FailOnWarningVar := IsEnabled(FailOnWarning) ;
end if ;
if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then
FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ;
end if ;
if FailOnRequirementErrors /= OPT_INIT_PARM_DETECT then
FailOnRequirementErrorsVar := IsEnabled(FailOnRequirementErrors) ;
end if ;
if ReportHierarchy /= OPT_INIT_PARM_DETECT then
ReportHierarchyVar := IsEnabled(ReportHierarchy) ;
end if ;
if WriteAlertErrorCount /= OPT_INIT_PARM_DETECT then
WriteAlertErrorCountVar := IsEnabled(WriteAlertErrorCount) ;
end if ;
if WriteAlertLevel /= OPT_INIT_PARM_DETECT then
WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ;
end if ;
if WriteAlertName /= OPT_INIT_PARM_DETECT then
WriteAlertNameVar := IsEnabled(WriteAlertName) ;
end if ;
if WriteAlertTime /= OPT_INIT_PARM_DETECT then
WriteAlertTimeVar := IsEnabled(WriteAlertTime) ;
end if ;
if WriteLogErrorCount /= OPT_INIT_PARM_DETECT then
WriteLogErrorCountVar := IsEnabled(WriteLogErrorCount) ;
end if ;
if WriteLogLevel /= OPT_INIT_PARM_DETECT then
WriteLogLevelVar := IsEnabled(WriteLogLevel) ;
end if ;
if WriteLogName /= OPT_INIT_PARM_DETECT then
WriteLogNameVar := IsEnabled(WriteLogName) ;
end if ;
if WriteLogTime /= OPT_INIT_PARM_DETECT then
WriteLogTimeVar := IsEnabled(WriteLogTime) ;
end if ;
if PrintPassed /= OPT_INIT_PARM_DETECT then
PrintPassedVar := IsEnabled(PrintPassed) ;
end if ;
if PrintAffirmations /= OPT_INIT_PARM_DETECT then
PrintAffirmationsVar := IsEnabled(PrintAffirmations) ;
end if ;
if PrintDisabledAlerts /= OPT_INIT_PARM_DETECT then
PrintDisabledAlertsVar := IsEnabled(PrintDisabledAlerts) ;
end if ;
if PrintRequirements /= OPT_INIT_PARM_DETECT then
PrintRequirementsVar := IsEnabled(PrintRequirements) ;
end if ;
if PrintIfHaveRequirements /= OPT_INIT_PARM_DETECT then
PrintIfHaveRequirementsVar := IsEnabled(PrintIfHaveRequirements) ;
end if ;
if DefaultPassedGoal > 0 then
DefaultPassedGoalVar := DefaultPassedGoal ;
end if ;
if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
AlertPrefixVar.Set(AlertPrefix) ;
end if ;
if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
LogPrefixVar.Set(LogPrefix) ;
end if ;
if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
ReportPrefixVar.Set(ReportPrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
variable buf : line ;
begin
-- Boolean Values
swrite(buf, "ReportAlertLogOptions" & LF ) ;
swrite(buf, "---------------------" & LF ) ;
swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ;
swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ;
swrite(buf, "FailOnRequirementErrorsVar: " & to_string(FailOnRequirementErrorsVar ) & LF ) ;
swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ;
swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user
swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user
swrite(buf, "WriteAlertErrorCountVar: " & to_string(WriteAlertErrorCountVar ) & LF ) ;
swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ;
swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ;
swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ;
swrite(buf, "WriteLogErrorCountVar: " & to_string(WriteLogErrorCountVar ) & LF ) ;
swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ;
swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ;
swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ;
swrite(buf, "PrintPassedVar: " & to_string(PrintPassedVar ) & LF ) ;
swrite(buf, "PrintAffirmationsVar: " & to_string(PrintAffirmationsVar ) & LF ) ;
swrite(buf, "PrintDisabledAlertsVar: " & to_string(PrintDisabledAlertsVar ) & LF ) ;
swrite(buf, "PrintRequirementsVar: " & to_string(PrintRequirementsVar ) & LF ) ;
swrite(buf, "PrintIfHaveRequirementsVar: " & to_string(PrintIfHaveRequirementsVar ) & LF ) ;
-- String
swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ;
swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ;
swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ;
swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ;
swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ;
swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ;
writeline(buf) ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnWarningVar) ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnRequirementErrorsVar) ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(ReportHierarchyVar) ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return FoundReportHierVar ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return FoundAlertHierVar ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertErrorCountVar) ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertLevelVar) ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertNameVar) ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertTimeVar) ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogErrorCountVar) ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogLevelVar) ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogNameVar) ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogTimeVar) ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintPassedVar) ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintAffirmationsVar) ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintDisabledAlertsVar) ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintRequirementsVar) ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintIfHaveRequirementsVar) ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return DefaultPassedGoalVar ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return ResolveOsvvmPassName(PassNameVar.GetOpt) ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return ResolveOsvvmFailName(FailNameVar.GetOpt) ;
end function GetAlertLogFailName ;
end protected body AlertLogStructPType ;
shared variable AlertLogStruct : AlertLogStructPType ;
-- synthesis translate_on
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure Alert(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure Alert( Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(AlertLogID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure IncAlertCount( Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIf( not ReadValid, failure, "Read Failed") ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIfNot( not ReadValid, failure, "Read Failed") ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
-- AlertIfEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfNotEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- AlertIfNotEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Simple diff.
------------------------------------------------------------
variable Buf1, Buf2 : line ;
variable File1Done, File2Done : boolean ;
variable LineCount : integer := 0 ;
begin
-- synthesis translate_off
ReadLoop : loop
File1Done := EndFile(File1) ;
File2Done := EndFile(File2) ;
exit ReadLoop when File1Done or File2Done ;
ReadLine(File1, Buf1) ;
ReadLine(File2, Buf2) ;
LineCount := LineCount + 1 ;
if Buf1.all /= Buf2.all then
AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ;
exit ReadLoop ;
end if ;
end loop ReadLoop ;
if File1Done /= File2Done then
if not File1Done then
AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ;
end if ;
if not File2Done then
AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ;
end if ;
end if;
if File1Done and File2Done then
Valid := TRUE ;
else
Valid := FALSE ;
end if ;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
file FileID1, FileID2 : text ;
variable status1, status2 : file_open_status ;
begin
-- synthesis translate_off
Valid := FALSE ;
file_open(status1, FileID1, Name1, READ_MODE) ;
file_open(status2, FileID2, Name2, READ_MODE) ;
if status1 = OPEN_OK and status2 = OPEN_OK then
LocalAlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level, Valid) ;
else
if status1 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ;
end if ;
if status2 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ;
end if ;
end if;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, ReceivedMessage, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, ReceivedMessage & ' ' & ExpectedMessage, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIf( ID, not ReadValid, "Read Failed") ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
------------------------------------------------------------
procedure AffirmError( Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
-- With AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hstring(Received),
"?= Expected : " & to_hstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
-- Support for Specification / Requirements Tracking
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetJustify(Enable) ;
-- synthesis translate_on
end procedure SetAlertLogJustify ;
------------------------------------------------------------
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertCount) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportRequirements ;
-- synthesis translate_on
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ;
-- synthesis translate_on
end procedure ReportNonZeroAlerts ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummary(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummaries(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportTestSummaries ;
-- synthesis translate_on
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlerts(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteRequirements(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteRequirements ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1 ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadSpecification(FileName, PassedGoal) ;
-- synthesis translate_on
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadRequirements (
------------------------------------------------------------
FileName : string ;
ThresholdPassed : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed, TestSummary => FALSE) ;
-- synthesis translate_on
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadTestSummaries (FileName : string) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- synthesis translate_on
end procedure ReadTestSummaries ;
-- ------------------------------------------------------------
-- procedure ReportTestSummaries (FileName : string) is
-- ------------------------------------------------------------
-- begin
-- -- synthesis translate_off
-- AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- -- synthesis translate_on
-- end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
-- synthesis translate_on
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
procedure ClearAlertCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertCounts ;
------------------------------------------------------------
function "ABS" (L : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := ABS( L(FAILURE) ) ;
Result(ERROR) := ABS( L(ERROR) ) ;
Result(WARNING) := ABS( L(WARNING) );
-- synthesis translate_on
return Result ;
end function "ABS" ;
------------------------------------------------------------
function "+" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) + R(FAILURE) ;
Result(ERROR) := L(ERROR) + R(ERROR) ;
Result(WARNING) := L(WARNING) + R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "+" ;
------------------------------------------------------------
function "-" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) - R(FAILURE) ;
Result(ERROR) := L(ERROR) - R(ERROR) ;
Result(WARNING) := L(WARNING) - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
function "-" (R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := - R(FAILURE) ;
Result(ERROR) := - R(ERROR) ;
Result(WARNING) := - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
impure function SumAlertCount(AlertCount: AlertCountType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
-- Using ABS ensures correct expected error handling.
result := abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ;
-- synthesis translate_on
return result ;
end function SumAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetEnabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportLogEnables ;
-- synthesis translate_on
end ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogName(Name) ;
-- synthesis translate_on
end procedure SetAlertLogName ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogName(AlertLogID) ;
end GetAlertLogName ;
-- synthesis translate_on
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Deallocate ;
-- synthesis translate_on
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
procedure InitializeAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Initialize ;
-- synthesis translate_on
end procedure InitializeAlertLogStruct ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name, ParentID) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ;
-- synthesis translate_on
return result ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetReqID(Name, PassedGoal, ParentID, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetPassedGoal(AlertLogID, PassedGoal) ;
-- synthesis translate_on
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogParentID(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrefix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogPrefix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogPrefix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrefix(AlertLogID) ;
end function GetAlertLogPrefix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogSuffix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogSuffix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogSuffix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogSuffix(AlertLogID) ;
end function GetAlertLogSuffix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
-- Set using constant. Set before code runs.
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
return A ;
end function SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetGlobalAlertEnable ;
-- synthesis translate_on
return result ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmCount ;
-- synthesis translate_on
return result ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmPassedCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmPassedCount ;
-- synthesis translate_on
return result ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogOptions (
FailOnWarning => FailOnWarning,
FailOnDisabledErrors => FailOnDisabledErrors,
FailOnRequirementErrors => FailOnRequirementErrors,
ReportHierarchy => ReportHierarchy,
WriteAlertErrorCount => WriteAlertErrorCount,
WriteAlertLevel => WriteAlertLevel,
WriteAlertName => WriteAlertName,
WriteAlertTime => WriteAlertTime,
WriteLogErrorCount => WriteLogErrorCount,
WriteLogLevel => WriteLogLevel,
WriteLogName => WriteLogName,
WriteLogTime => WriteLogTime,
PrintPassed => PrintPassed,
PrintAffirmations => PrintAffirmations,
PrintDisabledAlerts => PrintDisabledAlerts,
PrintRequirements => PrintRequirements,
PrintIfHaveRequirements => PrintIfHaveRequirements,
DefaultPassedGoal => DefaultPassedGoal,
AlertPrefix => AlertPrefix,
LogPrefix => LogPrefix,
ReportPrefix => ReportPrefix,
DoneName => DoneName,
PassName => PassName,
FailName => FailName
);
-- synthesis translate_on
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlertLogOptions ;
-- synthesis translate_on
end procedure ReportAlertLogOptions ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnWarning ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnDisabledErrors ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnRequirementErrors ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportHierarchy ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundReportHier ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundAlertHier ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertErrorCount ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertLevel ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertName ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertTime ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogErrorCount ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogLevel ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogName ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogTime ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintPassed ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintAffirmations ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintDisabledAlerts ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintRequirements ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintIfHaveRequirements ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDefaultPassedGoal ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogAlertPrefix ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogLogPrefix ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportPrefix ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDoneName ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPassName ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailName ;
end function GetAlertLogFailName ;
------------------------------------------------------------
function IsLogEnableType (Name : String) return boolean is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then return TRUE ;
elsif Name = "DEBUG" then return TRUE ;
elsif Name = "FINAL" then return TRUE ;
elsif Name = "INFO" then return TRUE ;
end if ;
return FALSE ;
end function IsLogEnableType ;
------------------------------------------------------------
procedure ReadLogEnables (file AlertLogInitFile : text) is
-- Preferred Read format
-- Line 1: instance1_name log_enable log_enable log_enable
-- Line 2: instance2_name log_enable log_enable log_enable
-- when reading multiple log_enables on a line, they must be separated by a space
--
--- Also supports alternate format from Lyle/....
-- Line 1: instance1_name
-- Line 2: log enable
-- Line 3: instance2_name
-- Line 4: log enable
--
------------------------------------------------------------
type ReadStateType is (GET_ID, GET_ENABLE) ;
variable ReadState : ReadStateType := GET_ID ;
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable Name : string(1 to 80) ;
variable NameLen : integer ;
variable AlertLogID : AlertLogIDType ;
variable ReadAnEnable : boolean ;
variable LogLevel : LogType ;
begin
ReadState := GET_ID ;
ReadLineLoop : while not EndFile(AlertLogInitFile) loop
ReadLine(AlertLogInitFile, buf) ;
if ReadAnEnable then
-- Read one or more enable values, next line read AlertLog name
-- Note that any newline with ReadAnEnable TRUE will result in
-- searching for another AlertLogID name - this includes multi-line comments.
ReadState := GET_ID ;
end if ;
ReadNameLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLineLoop when Empty ;
case ReadState is
when GET_ID =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ;
ReadState := GET_ENABLE ;
ReadAnEnable := FALSE ;
when GET_ENABLE =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
ReadAnEnable := TRUE ;
if not IsLogEnableType(Name(1 to NameLen)) then
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ;
exit ReadNameLoop ;
end if ;
-- Log(OSVVM_ALERTLOG_ID, "SetLogEnable(OSVVM_ALERTLOG_ID, " & Name(1 to NameLen) & ", TRUE) ;", DEBUG) ;
LogLevel := LogType'value("" & Name(1 to NameLen)) ; -- "" & added for RivieraPro 2020.10
SetLogEnable(AlertLogID, LogLevel, TRUE) ;
end case ;
end loop ReadNameLoop ;
end loop ReadLineLoop ;
end procedure ReadLogEnables ;
------------------------------------------------------------
procedure ReadLogEnables (FileName : string) is
------------------------------------------------------------
file AlertLogInitFile : text open READ_MODE is FileName ;
begin
ReadLogEnables(AlertLogInitFile) ;
end procedure ReadLogEnables ;
------------------------------------------------------------
function PathTail (A : string) return string is
------------------------------------------------------------
alias aA : string(1 to A'length) is A ;
variable LenA : integer := A'length ;
begin
if aA(LenA) = ':' then
LenA := LenA - 1 ;
end if ;
for i in LenA downto 1 loop
if aA(i) = ':' then
return aA(i+1 to LenA) ;
end if ;
end loop ;
return aA(1 to LenA) ;
end function PathTail ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
type BooleanTableType is array(std_ulogic, std_ulogic) of boolean;
constant MetaMatchTable : BooleanTableType := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
function MetaMatch (l, r : std_ulogic) return boolean is
begin
return MetaMatchTable(l, r);
end function MetaMatch;
function MetaMatch (L, R : std_ulogic_vector) return boolean is
alias aL : std_ulogic_vector(1 to L'length) is L;
alias aR : std_ulogic_vector(1 to R'length) is R;
begin
if aL'length /= aR'length then
--! log(OSVVM_ALERTLOG_ID, "AlertLogPkg.MetaMatch: Length Mismatch", DEBUG) ;
return FALSE;
else
for i in aL'range loop
if not (MetaMatchTable(aL(i), aR(i))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end function MetaMatch;
function MetaMatch (L, R : unresolved_unsigned) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
function MetaMatch (L, R : unresolved_signed) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
------------------------------------------------------------
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- deprecated
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIf ;
------------------------------------------------------------
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- deprecated
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIfNot ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
end package body AlertLogPkg ; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cla_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end cla_4_bit;
architecture Behavioral of cla_4_bit is
--these wire the output of the CLL to each FA.
signal Cin1, Cin2, Cin3 : std_logic:='0';
--these wire the result of the add/sub check to each FA.
signal b0, b1, b2, b3 : std_logic:='0';
signal Bxor : std_logic_vector (3 downto 0);
begin
--add/sub control; this flips B if necessary.
Bxor(0) <= B(0) XOR Cin;
Bxor(1) <= B(1) XOR Cin;
Bxor(2) <= B(2) XOR Cin;
Bxor(3) <= B(3) XOR Cin;
--Carry-Look-Ahead Logic
CLL0: entity work.cl_logic port map (A,Bxor,Cin,Cin1,Cin2,Cin3,Cout);
--Full adders; for CLA, then individual Couts dangle; they are
--handled by the CLL module and are technically unnecessary for
--the CLA implementation.
FA0: entity work.full_adder_1_bit port map (A(0),Bxor(0),Cin,open,Sum(0));
FA1: entity work.full_adder_1_bit port map (A(1),Bxor(1),Cin1,open,Sum(1));
FA2: entity work.full_adder_1_bit port map (A(2),Bxor(2),Cin2,open,Sum(2));
FA3: entity work.full_adder_1_bit port map (A(3),Bxor(3),Cin3,open,Sum(3));
end Behavioral;
|
package body b is
end b;
|
-------------------------------------------------------------------------------
--
-- The testbench for t8243 core.
--
-- $Id: tb_t8243-c.vhd,v 1.1 2006-07-14 01:02:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_t8243_behav_c0 of tb_t8243 is
for behav
for rom_internal_2k : lpm_rom
use configuration work.lpm_rom_c0;
end for;
for rom_external_2k : lpm_rom
use configuration work.lpm_rom_c0;
end for;
for ram_256 : generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
for ext_ram_b : generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
for t48_core_b : t48_core
use configuration work.t48_core_struct_c0;
end for;
for t8243_sync_notri_b : t8243_sync_notri
use configuration work.t8243_sync_notri_struct_c0;
end for;
for if_timing_b : if_timing
use configuration work.if_timing_behav_c0;
end for;
end for;
end tb_t8243_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------
-- DPIMREF.VHD -- Digilent Parallel Interface Module Reference Design
----------------------------------------------------------------------------
-- Author: Gene Apperson
-- Copyright 2004 Digilent, Inc.
----------------------------------------------------------------------------
-- IMPORTANT NOTE ABOUT BUILDING THIS LOGIC IN ISE
--
-- Before building the Dpimref logic in ISE:
-- 1. In Project Navigator, right-click on "Synthesize-XST"
-- (in the Process View Tab) and select "Properties"
-- 2. Click the "HDL Options" tab
-- 3. Set the "FSM Encoding Algorithm" to "None"
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This module contains an example implementation of Digilent Parallel
-- Interface Module logic. This interface is used in conjunction with the
-- DPCUTIL DLL and a Digilent Communications Module (USB, EtherNet, Serial)
-- to exchange data with an application running on a host PC and the logic
-- implemented in a gate array.
--
-- See the Digilent document, Digilent Parallel Interface Model Reference
-- Manual (doc # 560-000) for a description of the interface.
--
-- This module also conforms with the Digilent Asynchronous Parallel
-- Interface (DEPP) specification, as outlined in the document titled
-- "Digilent Asynchronous Parallel Interface(DEPP)" (doc # 564-000). This
-- allows for the host to make calls to the DEPP API, as introduced in
-- Adept SDK 2.
--
-- This design uses a state machine implementation to respond to transfer
-- cycles. It implements an address register, 8 internal data registers
-- that merely hold a value written, and interface registers to communicate
-- with a Digilent FPGA board. There is an LED output register whose value
-- drives the 8 discrete leds on the board. There are two input registers.
-- One reads the 8 switches on the board and the other reads the buttons.
--
-- The top level port names conform with the master .ucf files provided
-- on the Digilent website, www.digilentinc.com. If your Digilent board
-- is compatible with this project, then the master .ucf file available
-- for it there will contain ports with these names.
--
-- Interface signals used in top level entity port:
-- clk - master clock, generally 50Mhz osc on system board
-- DB - port data bus
-- EppASTB - address strobe
-- EppDSTB - data strobe
-- EppWRITE - data direction (described in reference manual as WRITE)
-- EppWAIT - transfer synchronization (described in reference manual
-- as WAIT)
-- Led - LED outputs
-- sw - switch inputs
-- btn - button inputs
--
----------------------------------------------------------------------------
-- Revision History:
-- 06/09/2004(GeneA): created
-- 08/10/2004(GeneA): initial public release
-- 04/25/2006(JoshP): comment addition
-- 01/30/2012(SamB) : Removed debugging led logic and ldb signal
-- Changed signal names to conform with General UCFs
-- Updated comments for DEPP and multiple boards
-- 08/02/2012(JoshS): Net names in general UCFs updated, applied changes
-- to demo to keep up to date.
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpimref is
Port (
clk : in std_logic;
DB : inout std_logic_vector(7 downto 0);
EppASTB : in std_logic;
EppDSTB : in std_logic;
EppWRITE : in std_logic;
EppWAIT : out std_logic;
Led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end dpimref;
architecture Behavioral of dpimref is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- The following constants define state codes for the EPP port interface
-- state machine. The high order bits of the state number give a unique
-- state identifier. The low order bits are the state machine outputs for
-- that state. This type of state machine implementation uses no
-- combination logic to generate outputs which should produce glitch
-- free outputs.
constant stEppReady : std_logic_vector(7 downto 0) := "0000" & "0000";
constant stEppAwrA : std_logic_vector(7 downto 0) := "0001" & "0100";
constant stEppAwrB : std_logic_vector(7 downto 0) := "0010" & "0001";
constant stEppArdA : std_logic_vector(7 downto 0) := "0011" & "0010";
constant stEppArdB : std_logic_vector(7 downto 0) := "0100" & "0011";
constant stEppDwrA : std_logic_vector(7 downto 0) := "0101" & "1000";
constant stEppDwrB : std_logic_vector(7 downto 0) := "0110" & "0001";
constant stEppDrdA : std_logic_vector(7 downto 0) := "0111" & "0010";
constant stEppDrdB : std_logic_vector(7 downto 0) := "1000" & "0011";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- State machine current state register
signal stEppCur : std_logic_vector(7 downto 0) := stEppReady;
signal stEppNext : std_logic_vector(7 downto 0);
signal clkMain : std_logic;
-- Internal control signales
signal ctlEppWait : std_logic;
signal ctlEppAstb : std_logic;
signal ctlEppDstb : std_logic;
signal ctlEppDir : std_logic;
signal ctlEppWr : std_logic;
signal ctlEppAwr : std_logic;
signal ctlEppDwr : std_logic;
signal busEppOut : std_logic_vector(7 downto 0);
signal busEppIn : std_logic_vector(7 downto 0);
signal busEppData : std_logic_vector(7 downto 0);
-- Registers
signal regEppAdr : std_logic_vector(3 downto 0);
signal regData0 : std_logic_vector(7 downto 0);
signal regData1 : std_logic_vector(7 downto 0);
signal regData2 : std_logic_vector(7 downto 0);
signal regData3 : std_logic_vector(7 downto 0);
signal regData4 : std_logic_vector(7 downto 0);
signal regData5 : std_logic_vector(7 downto 0);
signal regData6 : std_logic_vector(7 downto 0);
signal regData7 : std_logic_vector(7 downto 0);
signal regLed : std_logic_vector(7 downto 0);
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
clkMain <= clk;
ctlEppAstb <= EppASTB;
ctlEppDstb <= EppDSTB;
ctlEppWr <= EppWRITE;
EppWAIT <= ctlEppWait; -- drive WAIT from state machine output
-- Data bus direction control. The internal input data bus always
-- gets the port data bus. The port data bus drives the internal
-- output data bus onto the pins when the interface says we are doing
-- a read cycle and we are in one of the read cycles states in the
-- state machine.
busEppIn <= DB;
DB <= busEppOut when ctlEppWr = '1' and ctlEppDir = '1' else "ZZZZZZZZ";
-- Select either address or data onto the internal output data bus.
busEppOut <= "0000" & regEppAdr when ctlEppAstb = '0' else busEppData;
Led <= regLed;
-- Decode the address register and select the appropriate data register
busEppData <= regData0 when regEppAdr = "0000" else
regData1 when regEppAdr = "0001" else
regData2 when regEppAdr = "0010" else
regData3 when regEppAdr = "0011" else
regData4 when regEppAdr = "0100" else
regData5 when regEppAdr = "0101" else
regData6 when regEppAdr = "0110" else
regData7 when regEppAdr = "0111" else
sw when regEppAdr = "1000" else
"0000" & btn when regEppAdr = "1001" else
"00000000";
------------------------------------------------------------------------
-- EPP Interface Control State Machine
------------------------------------------------------------------------
-- Map control signals from the current state
ctlEppWait <= stEppCur(0);
ctlEppDir <= stEppCur(1);
ctlEppAwr <= stEppCur(2);
ctlEppDwr <= stEppCur(3);
-- This process moves the state machine to the next state
-- on each clock cycle
process (clkMain)
begin
if clkMain = '1' and clkMain'Event then
stEppCur <= stEppNext;
end if;
end process;
-- This process determines the next state machine state based
-- on the current state and the state machine inputs.
process (stEppCur, stEppNext, ctlEppAstb, ctlEppDstb, ctlEppWr)
begin
case stEppCur is
-- Idle state waiting for the beginning of an EPP cycle
when stEppReady =>
if ctlEppAstb = '0' then
-- Address read or write cycle
if ctlEppWr = '0' then
stEppNext <= stEppAwrA;
else
stEppNext <= stEppArdA;
end if;
elsif ctlEppDstb = '0' then
-- Data read or write cycle
if ctlEppWr = '0' then
stEppNext <= stEppDwrA;
else
stEppNext <= stEppDrdA;
end if;
else
-- Remain in ready state
stEppNext <= stEppReady;
end if;
-- Write address register
when stEppAwrA =>
stEppNext <= stEppAwrB;
when stEppAwrB =>
if ctlEppAstb = '0' then
stEppNext <= stEppAwrB;
else
stEppNext <= stEppReady;
end if;
-- Read address register
when stEppArdA =>
stEppNext <= stEppArdB;
when stEppArdB =>
if ctlEppAstb = '0' then
stEppNext <= stEppArdB;
else
stEppNext <= stEppReady;
end if;
-- Write data register
when stEppDwrA =>
stEppNext <= stEppDwrB;
when stEppDwrB =>
if ctlEppDstb = '0' then
stEppNext <= stEppDwrB;
else
stEppNext <= stEppReady;
end if;
-- Read data register
when stEppDrdA =>
stEppNext <= stEppDrdB;
when stEppDrdB =>
if ctlEppDstb = '0' then
stEppNext <= stEppDrdB;
else
stEppNext <= stEppReady;
end if;
-- Some unknown state
when others =>
stEppNext <= stEppReady;
end case;
end process;
------------------------------------------------------------------------
-- EPP Address register
------------------------------------------------------------------------
process (clkMain, ctlEppAwr)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppAwr = '1' then
regEppAdr <= busEppIn(3 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------------
-- EPP Data registers
------------------------------------------------------------------------
-- The following processes implement the interface registers. These
-- registers just hold the value written so that it can be read back.
-- In a real design, the contents of these registers would drive additional
-- logic.
-- The ctlEppDwr signal is an output from the state machine that says
-- we are in a 'write data register' state. This is combined with the
-- address in the address register to determine which register to write.
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0000" then
regData0 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0001" then
regData1 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0010" then
regData2 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0011" then
regData3 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0100" then
regData4 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0101" then
regData5 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0110" then
regData6 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0111" then
regData7 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "1010" then
regLed <= busEppIn;
end if;
end if;
end process;
----------------------------------------------------------------------------
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1696.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01696ent IS
END c09s02b00x00p05n01i01696ent;
ARCHITECTURE c09s02b00x00p05n01i01696arch OF c09s02b00x00p05n01i01696ent IS
BEGIN
TESTING: PROCESS
BEGIN
process -- ERROR:
begin
wait;
end process;
assert FALSE
report "***FAILED TEST: c09s02b00x00p05n01i01696 - Process statements are illegal inside the body a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01696arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1696.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01696ent IS
END c09s02b00x00p05n01i01696ent;
ARCHITECTURE c09s02b00x00p05n01i01696arch OF c09s02b00x00p05n01i01696ent IS
BEGIN
TESTING: PROCESS
BEGIN
process -- ERROR:
begin
wait;
end process;
assert FALSE
report "***FAILED TEST: c09s02b00x00p05n01i01696 - Process statements are illegal inside the body a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01696arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1696.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01696ent IS
END c09s02b00x00p05n01i01696ent;
ARCHITECTURE c09s02b00x00p05n01i01696arch OF c09s02b00x00p05n01i01696ent IS
BEGIN
TESTING: PROCESS
BEGIN
process -- ERROR:
begin
wait;
end process;
assert FALSE
report "***FAILED TEST: c09s02b00x00p05n01i01696 - Process statements are illegal inside the body a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01696arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc813.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ARCHITECTURE c01s02b00x00p04n02i00813arch OF c01s02b00x00p04n02i00813ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p04n02i00813 - Entity declaration and architecture body must reside in the same library."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p04n02i00813arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc813.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ARCHITECTURE c01s02b00x00p04n02i00813arch OF c01s02b00x00p04n02i00813ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p04n02i00813 - Entity declaration and architecture body must reside in the same library."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p04n02i00813arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc813.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ARCHITECTURE c01s02b00x00p04n02i00813arch OF c01s02b00x00p04n02i00813ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p04n02i00813 - Entity declaration and architecture body must reside in the same library."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p04n02i00813arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p12n01i00143pkg is
type fourstate is ('0','1','x','z');
function fourstate_to_bit(x : fourstate) return bit;
procedure simple ( crude : in bit;
signal refined : out bit);
end c04s03b02x02p12n01i00143pkg;
package body c04s03b02x02p12n01i00143pkg is
procedure simple ( crude : in bit;
signal refined : out bit) is
begin
refined <= crude after 5 ns;
end simple;
function fourstate_to_bit(x : fourstate) return bit is
variable newval: bit := '0';
begin
case x is
when '0' => newval := '0';
when '1' => newval := '1';
when 'z' => newval := '0';
when 'x' => newval := '0';
end case;
return newval;
end fourstate_to_bit;
end c04s03b02x02p12n01i00143pkg;
use work.c04s03b02x02p12n01i00143pkg.all;
ENTITY c04s03b02x02p12n01i00143ent IS
port( x, y: in fourstate);
END c04s03b02x02p12n01i00143ent;
ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
signal yint : bit;
BEGIN
simple ( fourstate_to_bit(y) , yint);
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( yint = '0' )
report "***PASSED TEST: c04s03b02x02p12n01i00143"
severity NOTE;
assert ( yint = '0' )
report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p12n01i00143arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p12n01i00143pkg is
type fourstate is ('0','1','x','z');
function fourstate_to_bit(x : fourstate) return bit;
procedure simple ( crude : in bit;
signal refined : out bit);
end c04s03b02x02p12n01i00143pkg;
package body c04s03b02x02p12n01i00143pkg is
procedure simple ( crude : in bit;
signal refined : out bit) is
begin
refined <= crude after 5 ns;
end simple;
function fourstate_to_bit(x : fourstate) return bit is
variable newval: bit := '0';
begin
case x is
when '0' => newval := '0';
when '1' => newval := '1';
when 'z' => newval := '0';
when 'x' => newval := '0';
end case;
return newval;
end fourstate_to_bit;
end c04s03b02x02p12n01i00143pkg;
use work.c04s03b02x02p12n01i00143pkg.all;
ENTITY c04s03b02x02p12n01i00143ent IS
port( x, y: in fourstate);
END c04s03b02x02p12n01i00143ent;
ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
signal yint : bit;
BEGIN
simple ( fourstate_to_bit(y) , yint);
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( yint = '0' )
report "***PASSED TEST: c04s03b02x02p12n01i00143"
severity NOTE;
assert ( yint = '0' )
report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p12n01i00143arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p12n01i00143pkg is
type fourstate is ('0','1','x','z');
function fourstate_to_bit(x : fourstate) return bit;
procedure simple ( crude : in bit;
signal refined : out bit);
end c04s03b02x02p12n01i00143pkg;
package body c04s03b02x02p12n01i00143pkg is
procedure simple ( crude : in bit;
signal refined : out bit) is
begin
refined <= crude after 5 ns;
end simple;
function fourstate_to_bit(x : fourstate) return bit is
variable newval: bit := '0';
begin
case x is
when '0' => newval := '0';
when '1' => newval := '1';
when 'z' => newval := '0';
when 'x' => newval := '0';
end case;
return newval;
end fourstate_to_bit;
end c04s03b02x02p12n01i00143pkg;
use work.c04s03b02x02p12n01i00143pkg.all;
ENTITY c04s03b02x02p12n01i00143ent IS
port( x, y: in fourstate);
END c04s03b02x02p12n01i00143ent;
ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
signal yint : bit;
BEGIN
simple ( fourstate_to_bit(y) , yint);
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( yint = '0' )
report "***PASSED TEST: c04s03b02x02p12n01i00143"
severity NOTE;
assert ( yint = '0' )
report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p12n01i00143arch;
|
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop;
FOR_LABEL : for index in 4 to 23 loop
end loop;
For_label : for index in 4 to 23 loop
end loop;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BlockRamFaces is
Port (
Clock : in STD_LOGIC;
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (5 downto 0);
Column : in STD_LOGIC_VECTOR (5 downto 0);
DataOutPixel : out STD_LOGIC_VECTOR(11 downto 0);
DataOutPixelR : out STD_LOGIC_VECTOR(11 downto 0)
);
end BlockRamFaces;
architecture Behavioral of BlockRamFaces is
signal Addr: STD_LOGIC_VECTOR(9 downto 0);
signal Memout: STD_LOGIC_VECTOR(799 downto 0);
signal Column_r: STD_LOGIC_VECTOR(5 downto 0);
signal dop, dopR: STD_LOGIC_VECTOR(15 downto 0);
begin
FacesToAddr: entity work.FaceAndRowToAddr PORT MAP(
Texture => Texture,
Row => Row,
AddressOut => Addr
);
CoreFaces: entity work.MemFaces PORT MAP(
addra => Addr,
clka =>Clock,
douta => Memout
);
Regist6: entity work.Reg6 PORT MAP(
Clock => Clock,
ColumnIn => Column,
ColumnOut => Column_r
);
ColumnMux: entity work.ToPixelFaces PORT MAP(
DataIn => Memout,
Column => Column_r,
PixelOut => dop,
PixelOutR => dopR
);
--16 bit color to 12 bit
DataOutPixel <= dop(15 downto 12) & dop(10 downto 7) & dop(4 downto 1);
DataOutPixelR <= dopR(15 downto 12) & dopR(10 downto 7) & dopR(4 downto 1);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use work.HMACSHA384_ISMAIL.all;
entity hmac_sha384 is
port ( clk: in std_logic;
salt : in std_logic_vector(383 downto 0);
pepper : in std_logic_vector(1023 downto 0);
small_msg: in std_logic_vector((6*4)-1 downto 0);
medium_msg: in std_logic_vector((46*4)-1 downto 0);
big_msg: in std_logic_vector((126*4)-1 downto 0);
hashed_code: out std_logic_vector(383 downto 0));
end entity ; -- main
architecture sha_behaviour of hmac_sha384 is
type msg is (small, medium, big);
signal cur_state, next_state : msg := small;
begin
p0: process(clk) is
begin
if (rising_edge(clk)) then
cur_state <= next_state;
end if;
end process;
p1: process (small_msg,medium_msg,big_msg,cur_state) is
begin
case (cur_state) is
when small =>
next_state <= medium;
hashed_code <= hmacsha384(salt,pepper,small_msg);
when medium =>
next_state <= big;
hashed_code <= hmacsha384(salt,pepper,medium_msg);
when big =>
next_state <= small;
hashed_code <= hmacsha384(salt,pepper,big_msg);
end case;
end process;
end architecture;
|
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
--
-- Simple RS232 sender with generic baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_sender is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- baudrate, in bps
BAUDRATE: integer
);
port(
clock: in std_logic;
-- RS232 for sending
data: in unsigned(7 downto 0);
-- RS232 TX pin
tx: out std_logic;
-- set this for one clock pulse to 1 for sending the data
sendTrigger: in std_logic;
-- this is set for one clock pulse to 1, when the data was sent
dataSent: out std_logic
);
end entity rs232_sender;
architecture rtl of rs232_sender is
constant MAX_COUNTER: natural := SYSTEM_SPEED / BAUDRATE;
signal baudrateCounter: natural range 0 to MAX_COUNTER := 0;
signal bitCounter: natural range 0 to 9 := 0;
signal shiftRegister: unsigned(9 downto 0) := (others => '0');
signal dataSendingStarted: std_logic := '0';
begin
process(clock)
begin
if rising_edge(clock) then
dataSent <= '0';
if dataSendingStarted = '1' then
if baudrateCounter = 0 then
tx <= shiftRegister(0);
shiftRegister <= shift_right(shiftRegister, 1);
if bitCounter > 0 then
bitCounter <= bitCounter - 1;
else
dataSendingStarted <= '0';
dataSent <= '1';
end if;
baudrateCounter <= MAX_COUNTER;
else
baudrateCounter <= baudrateCounter - 1;
end if;
else
tx <= '1';
if sendTrigger = '1' then
shiftRegister <= '1' & data & '0';
bitCounter <= 9;
baudrateCounter <= 0;
dataSendingStarted <= '1';
end if;
end if;
end if;
end process;
end architecture rtl;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00189
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00189
-- PKG00189/BODY
-- ENT00189(ARCH00189)
-- ENT00189_Test_Bench(ARCH00189_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00189 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00189 ;
--
package body PKG00189 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00189 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00189.all ;
entity ENT00189 is
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
end ENT00189 ;
--
architecture ARCH00189 of ENT00189 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00189 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00189.all ;
entity ENT00189_Test_Bench is
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
end ENT00189_Test_Bench ;
--
architecture ARCH00189_Test_Bench of ENT00189_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00189 ( ARCH00189 ) ;
begin
CIS1 : UUT
port map (
s_r_st_rec1
, s_r_st_rec2
, s_r_st_rec3
) ;
end block L1 ;
end ARCH00189_Test_Bench ;
|
-- Test case from Adam Barnes
--
package mycomp_pkg is
type int_array is array(natural range <>) of integer;
component mycomp is
generic (
mygen : int_array(1 to 6)
);
port (
i : in bit;
o : out bit
);
end component mycomp;
end package mycomp_pkg;
--------------------------------------------------------------------------------
library work;
use work.mycomp_pkg.all;
entity mycomp is
generic (
mygen : int_array(1 to 6)
);
port (
i : in bit;
o : out bit
);
end entity mycomp;
architecture sim of mycomp is
begin
o <= not i;
casep: process
begin
case mygen(1) is
when 0 to 128 => report "value of mygen(1) is in range 0..128; value is " & integer'image(mygen(1));
when others => report "value of mygen(1) is NOT in range 0..128; value is " & integer'image(mygen(1)) severity failure;
end case;
wait;
end process;
end architecture;
entity top is
end entity top;
library work;
use work.mycomp_pkg.all;
architecture sim of top is
signal test : bit;
constant mygen : int_array := (0,1,2,3,4,5);
begin
process
begin
case mygen(1) is
when 0 to 128 => report "value of mygen(1) is in range 0..128; value is " & integer'image(mygen(1));
when others => report "value of mygen(1) is NOT in range 0..128; value is " & integer'image(mygen(1));
end case;
wait;
end process;
UUT: component mycomp
generic map (
mygen => mygen
)
port map (
i => test,
o => open
);
end architecture sim;
|
entity tb_asgn01 is
end tb_asgn01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn01 is
signal a : std_logic_vector (2 downto 0);
signal s0 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn01
port map (a => a, s0 => s0, r => r);
process
begin
s0 <= '1';
wait for 1 ns;
assert r = "000" severity failure;
a <= "101";
s0 <= '0';
wait for 1 ns;
assert r = "101" severity failure;
a <= "110";
s0 <= '0';
wait for 1 ns;
assert r = "110" severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_reset is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_reset;
architecture Structural of vga_sync_reset is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk)
begin
if rising_edge(clk) then
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_reset is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_reset;
architecture Structural of vga_sync_reset is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk)
begin
if rising_edge(clk) then
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_reset is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_reset;
architecture Structural of vga_sync_reset is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk)
begin
if rising_edge(clk) then
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
|
library ieee;
use ieee.std_logic_1164.all;
package uart2BusTop_pkg is
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intReq : out std_logic;
intGnt : in std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
component uart2BusTop
generic
(
AW : integer := 8
);
port
(
clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
serOut : out std_logic;
intAccessReq : out std_logic;
intAccessGnt : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic
);
end component;
end uart2BusTop_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
package uart2BusTop_pkg is
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intReq : out std_logic;
intGnt : in std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
component uart2BusTop
generic
(
AW : integer := 8
);
port
(
clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
serOut : out std_logic;
intAccessReq : out std_logic;
intAccessGnt : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic
);
end component;
end uart2BusTop_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
use basic_library.very_common_pkg.all;
use work.package_with_constants;
entity clock_divider is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_output : out std_logic
);
end clock_divider;
architecture clock_divider of clock_divider is
signal counter : integer range 0 to DIVIDER - 1 := 0;
signal clk_internal : std_logic := '0';
signal clk_enable_unused : std_logic := '0';
begin
clk_output <= clk_internal;
useless_u : clk_en_generator
generic map (
DIVIDER => DIVIDER)
port map (
reset => reset,
clk_input => clk_input,
clk_en => open);
-- We read 'reset' signal asynchronously inside the process to force
-- msim issuing a synthesis warning
process(clk_input)
begin
if reset = '1' then
counter <= 0;
elsif clk_input'event and clk_input = '1' then
if counter < DIVIDER then
counter <= counter + 1;
else
counter <= 0;
clk_internal <= not clk_internal;
end if;
end if;
end process;
end clock_divider;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSR_tb IS
END PSR_tb;
ARCHITECTURE behavior OF PSR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std_logic;
rst : IN std_logic;
CWP : OUT std_logic;
icc: OUT STD_LOGIC_VECTOR(3 downto 0);
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal NZVC : std_logic_vector(3 downto 0) := (others => '0');
signal nCWP : std_logic := '0';
signal CLK : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal CWP : std_logic;
signal icc: std_logic_vector(3 downto 0);
signal C : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR PORT MAP (
NZVC => NZVC,
nCWP => nCWP,
CLK => CLK,
rst => rst,
CWP => CWP,
icc => icc,
C => C
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
NZVC<="1000";
wait for 40 ns;
NZVC<="0100";
wait for 40 ns;
NZVC<="1001";
nCWP<='1';
wait for 40 ns;
NZVC<="0000";
wait for 40 ns;
NZVC<="0011";
wait for 40 ns;
nCWP<='0';
wait for 40 ns;
rst<='1';
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc245.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00245ent IS
END c03s01b02x00p04n01i00245ent;
ARCHITECTURE c03s01b02x00p04n01i00245arch OF c03s01b02x00p04n01i00245ent IS
type I1 is range 1 to 9.0; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00245 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00245arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc245.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00245ent IS
END c03s01b02x00p04n01i00245ent;
ARCHITECTURE c03s01b02x00p04n01i00245arch OF c03s01b02x00p04n01i00245ent IS
type I1 is range 1 to 9.0; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00245 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00245arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc245.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00245ent IS
END c03s01b02x00p04n01i00245ent;
ARCHITECTURE c03s01b02x00p04n01i00245arch OF c03s01b02x00p04n01i00245ent IS
type I1 is range 1 to 9.0; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00245 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00245arch;
|
-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
|
-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_07_04 is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- end of code from book
end entity ch_07_04;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_07_04 is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- end of code from book
end entity ch_07_04;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_07_04 is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- end of code from book
end entity ch_07_04;
|
library ieee;
use ieee.std_logic_1164.all;
entity moving_average_filter is
port (
sin : in std_logic_vector (10 downto 0);
clk : in std_logic;
sout : out std_logic_vector (10 downto 0);
rst : in std_logic
);
end moving_average_filter;
architecture behavioral of moving_average_filter is
-- Registers
type tregisters is array (0 to 15) of std_logic_vector(14 downto 0);
signal r : tregisters;
-- Padded input value
signal first : std_logic_vector(14 downto 0);
-- First stage
signal s11 : std_logic_vector(14 downto 0);
signal s12 : std_logic_vector(14 downto 0);
signal s13 : std_logic_vector(14 downto 0);
signal s14 : std_logic_vector(14 downto 0);
signal c11 : std_logic_vector(14 downto 0);
signal c12 : std_logic_vector(14 downto 0);
signal c13 : std_logic_vector(14 downto 0);
signal c14 : std_logic_vector(14 downto 0);
-- Second stage
signal s21 : std_logic_vector(14 downto 0);
signal s22 : std_logic_vector(14 downto 0);
signal c21 : std_logic_vector(14 downto 0);
signal c22 : std_logic_vector(14 downto 0);
signal s22s : std_logic_vector(14 downto 0);
signal c21s : std_logic_vector(14 downto 0);
signal c22s : std_logic_vector(14 downto 0);
-- Third stage
signal s3 : std_logic_vector(14 downto 0);
signal c3 : std_logic_vector(14 downto 0);
signal c3s : std_logic_vector(14 downto 0);
-- Final sum
signal s : std_logic_vector(14 downto 0);
signal c : std_logic_vector(15 downto 0);
component counter42 is
Port ( a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
c : in std_logic_vector (14 downto 0);
d : in std_logic_vector (14 downto 0);
s : out std_logic_vector (14 downto 0);
co : out std_logic_vector (14 downto 0));
end component;
component carry_lookahead_adder is
Port ( a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic);
end component;
begin
process (sin, clk)
begin
if rst = '1' then
-- Reset register
for i in 0 to 15 loop
r(i) <= "000000000000000";
end loop;
elsif rising_edge(clk) then
-- Shift operands
for i in 15 downto 1 loop
r(i) <= r(i-1);
end loop;
-- Store first operand
r(0) <= first;
end if;
end process;
-- Sign extension
sign_extension_loop: for i in 14 downto 11 generate
first(i) <= sin(10);
end generate;
-- Connect lower 11-bits
input_loop: for i in 10 downto 0 generate
first(i) <= sin(i);
end generate;
-- First stage
stg11: counter42 port map(a=>first, b=>r( 0), c=>r( 1), d=>r( 2), s=>s11, co=>c11);
stg12: counter42 port map(a=>r( 3), b=>r( 4), c=>r( 5), d=>r( 6), s=>s12, co=>c12);
stg13: counter42 port map(a=>r( 7), b=>r( 8), c=>r( 9), d=>r(10), s=>s13, co=>c13);
stg14: counter42 port map(a=>r(11), b=>r(12), c=>r(13), d=>r(14), s=>s14, co=>c14);
-- Second stage: Sum shifted carries & sums
stg21: counter42 port map(a=>s11, b=>s12, c=>s13, d=>s14, s => s21, co => c21);
stg22: counter42 port map(a=>c11, b=>c12, c=>c13, d=>c14, s => s22, co => c22);
s22s <= s22(13 downto 0) & "0"; -- s22 is shifted by 1
c21s <= c21(13 downto 0) & "0"; -- c21 is shifted by 1
c22s <= c22(12 downto 0) & "00"; -- c22 is shifted by 2
-- Third stage
stg3: counter42 port map(a=>s21, b=>s22s, c=>c21s, d=>c22s, s=>s3, co => c3);
c3s <= c3(13 downto 0) & "0"; -- c3 is shifted by 1
-- Final addition
stg4: carry_lookahead_adder port map(a=>s3, b=>c3s, ci=>'0', s=>s);
-- Write output
division_loop: for i in 10 downto 0 generate
sout(i) <= s(i+4);
end generate;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real);
end entity gain;
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real);
end entity gain;
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real);
end entity gain;
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
-- system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_rgb565_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_rgb565_0_0 : entity is "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_rgb565_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_rgb565_0_0 : entity is "rgb888_to_rgb565,Vivado 2016.4";
end system_rgb888_to_rgb565_0_0;
architecture STRUCTURE of system_rgb888_to_rgb565_0_0 is
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\^rgb_888\(23 downto 19) <= rgb_888(23 downto 19);
\^rgb_888\(15 downto 10) <= rgb_888(15 downto 10);
\^rgb_888\(7 downto 3) <= rgb_888(7 downto 3);
rgb_565(15 downto 11) <= \^rgb_888\(23 downto 19);
rgb_565(10 downto 5) <= \^rgb_888\(15 downto 10);
rgb_565(4 downto 0) <= \^rgb_888\(7 downto 3);
end STRUCTURE;
|
architecture Rtl of I2SToAvalonST is
type aInputState is (Waiting, ReceivingSerData);
-- bclk set, for sync and delay
type aSyncSet is record
Meta : std_logic;
Sync : std_logic;
Dlyd : std_logic;
end record;
constant cInitValSync : aSyncSet := (
Meta => '0',
Sync => '0',
Dlyd => '0'
);
type aRegSet is record
State : aInputState; -- current state
D : std_logic_vector(gDataWidth-1 downto 0); -- data
BitIdx : unsigned(gDataWidthLen-1 downto 0); -- current bit index in data
Bclk : aSyncSet; -- bclk signals
Lrc : aSyncSet; -- left or rigth channel
LeftVal : std_logic; -- left channel valid
RightVal : std_logic; -- right channel valid
end record;
constant cInitValR : aRegSet := (
State => Waiting,
D => (others => '0'),
Bclk => cInitValSync,
Lrc => cInitValSync,
LeftVal => '0',
RightVal => '0',
BitIdx => (others => '0')
);
signal R, NxR : aRegSet;
begin -- architecture Rtl
-- register process
Reg : process(iClk, inReset)
begin
-- low active reset
if inReset = '0' then
R <= cInitValR;
-- rising clk edge
elsif rising_edge(iClk) then
R <= NxR;
end if;
end process;
Comb : process (R, iLRC, iBCLK, iDAT) is
begin -- process
-- default
NxR <= R;
-- reset valid flags
NxR.LeftVal <= '0';
NxR.RightVal <= '0';
-- sync input and delay
NxR.Bclk.Meta <= iBCLK;
NxR.Bclk.Sync <= R.Bclk.Meta;
NxR.Bclk.Dlyd <= R.Bclk.Sync;
NxR.Lrc.Meta <= iLRC;
NxR.Lrc.Sync <= R.Lrc.Meta;
NxR.Lrc.Dlyd <= R.Lrc.Sync;
case R.State is
-- waiting for input data
when Waiting =>
-- rising edge on LRC - Left Channel
if (R.Lrc.Dlyd = '0' and R.Lrc.Sync = '1')
-- falling edge on LRC - Right Channel
or (R.Lrc.Dlyd = '1' and R.Lrc.Sync = '0') then
NxR.BitIdx <= to_unsigned(gDataWidth-1, NxR.BitIdx'length);
NxR.State <= ReceivingSerData;
end if;
when ReceivingSerData =>
-- read input data
NxR.D(to_integer(R.BitIdx)) <= iDAT;
-- rising edge on BCLK
if R.Bclk.Dlyd = '0' and R.Bclk.Sync = '1' then
-- check bit index
if R.BitIdx = 0 then
-- end of frame
NxR.State <= Waiting;
if R.Lrc.Sync = '1' then
-- left channel valid
NxR.LeftVal <= '1';
else
-- right channel valid
NxR.RightVal <= '1';
end if;
else
-- decrease bit index
NxR.BitIdx <= R.BitIdx - 1;
end if;
end if;
end case;
end process;
-- output
oLeftData <= R.D;
oLeftValid <= R.LeftVal;
oRightData <= R.D;
oRightValid <= R.RightVal;
end architecture Rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type state_t is ( STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1,
STATE_NEEDED_READS_2,
STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION,
STATE_LOAD_BURST,
STATE_LOAD_READ_DECISION,
STATE_LOAD_READ,
STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION,
STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD,
STATE_LIKELIHOOD_DONE,
STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2
);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21"
);
constant decode : decode_t := (STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1,
STATE_NEEDED_READS_2,
STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION,
STATE_LOAD_BURST,
STATE_LOAD_READ_DECISION,
STATE_LOAD_READ,
STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION,
STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD,
STATE_LIKELIHOOD_DONE,
STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer := 128;
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"11111111");
resume_state_enc := (others => '0');
preempted := false;
done := false;
success := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- set flag, that thread was preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
-- CHANGE BACK (2 of 6) !!!
--state <= STATE_NEEDED_BURSTS;
end if;
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= STATE_NEEDED_BURSTS_2;
when STATE_NEEDED_BURSTS_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= STATE_NEEDED_READS_1;
when STATE_NEEDED_READS_1 =>
--! calculate number of reads (1 of 2)
-- change this back
-- old
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= STATE_NEEDED_READS_2;
when STATE_NEEDED_READS_2 =>
--! calculate number of reads (2 of 2)
number_of_reads_remember <= number_of_reads_remember / 4;
state <= STATE_READ_OBSERVATION_ADDRESS;
when STATE_READ_OBSERVATION_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_REF_DATA_ADDRESS;
end if;
-- -- CHANGE BACK (3 of 6) !!!
-- observation_array_start_address <= "00100000000000000000000000000000";
-- state <= STATE_READ_REF_DATA_ADDRESS;
when STATE_READ_REF_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
if preempted then
preempted := false;
enable <= '0';
init <= '1';
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
-- -- CHANGE BACK (4 of 6) !!!
-- -- ref data address = 10000040
-- reference_data_address <= "00010000000000000000000001000000";
-- state <= STATE_WAIT_FOR_MESSAGE;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= STATE_LOAD_OBSERVATION;
when STATE_LOAD_OBSERVATION =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= STATE_LOAD_BURST_DECISION;
when STATE_LOAD_BURST_DECISION =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= STATE_LOAD_BURST;
number_of_bursts <= number_of_bursts - 1;
else
state <= STATE_LOAD_READ_DECISION;
end if;
when STATE_LOAD_BURST =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= STATE_LOAD_BURST_DECISION;
end if;
when STATE_LOAD_READ_DECISION =>
--! decision if a read into local ram is needed
if (number_of_reads > 0) then
state <= STATE_LOAD_READ;
number_of_reads <= number_of_reads - 1;
elsif (second_run = '1') then
state <= STATE_LIKELIHOOD;
else
second_run <= '1';
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_LOAD_READ =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
state <= STATE_WRITE_TO_RAM;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= STATE_LOAD_READ_DECISION;
when STATE_LOAD_OBSERVATION_DATA_DECISION =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_2;
when STATE_LOAD_OBSERVATION_DATA_DECISION_2 =>
--! decide, if there is another observation to be handled, else post semaphore
o_RAMWEImportance <= '0';
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_3;
when STATE_LOAD_OBSERVATION_DATA_DECISION_3 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= STATE_LOAD_BURST_DECISION;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
when STATE_LIKELIHOOD =>
--! start and run likelihood user process
init <= '0';
enable <= '1';
observation_loaded <= '1';
state <= STATE_LIKELIHOOD_DONE;
when STATE_LIKELIHOOD_DONE =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
if (finished = '1') then
enable <= '0';
init <= '1';
state <= STATE_WRITE_LIKELIHOOD;
remaining_observations <= remaining_observations - 1;
end if;
when STATE_WRITE_LIKELIHOOD =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address, STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_dec_piso_seleccion IS
END tb_dec_piso_seleccion;
ARCHITECTURE behavior OF tb_dec_piso_seleccion IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec_piso_seleccion
PORT(
piso_code : IN std_logic_vector(1 downto 0);
piso0 : OUT std_logic;
piso1 : OUT std_logic;
piso2 : OUT std_logic
);
END COMPONENT;
--Inputs
signal piso_code : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal piso0 : std_logic;
signal piso1 : std_logic;
signal piso2 : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dec_piso_seleccion PORT MAP (
piso_code => piso_code,
piso0 => piso0,
piso1 => piso1,
piso2 => piso2
);
-- Stimulus process
stim_proc: process
begin
piso_code <= "01";
WAIT FOR 20 ns;
piso_code <= "10";
WAIT FOR 20 ns;
piso_code <= "11";
WAIT FOR 20 ns;
piso_code <= "00";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END; |
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