content stringlengths 1 1.04M ⌀ |
|---|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-- internal_flash.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_flash is
port (
clock : in std_logic := '0'; -- clk.clk
avmm_csr_addr : in std_logic ... |
-------------------------------------------------------------------------------
--! @file nf_rx_registers.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-22
--! @brief NanoFIP receiver registers.
------------------------------------------------... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Oct 16 23:04:57 2017
--Host : Juice-Laptop running 64-bit major release... |
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------... |
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------... |
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------... |
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------... |
--------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, eit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);... |
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without... |
entity e is
end entity;
architecture a of e is
signal a : boolean;
begin
process(a)
begin
case a is
when false => report "FALSE";
when true => report "TRUE";
when others => report "others";
end case;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_full of tb_elem is
for behav
... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
B : out std_logic;
C : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-------------------------------------------------------------------------------
--! @file xf.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-08
--! @brief Auxiliary FPGA communication.
-----------------------------------------------------------... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nor00 is
port(
clknr: in std_logic ;
codopnr: in std_logic_vector ( 3 downto 0 );
portAnr: in std_logic_vector ( 7 downto 0 );
portBnr: in std_logic_vector ( 7 downto 0 );
inFlagnr: in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
library std;
use std.env.all;
entity testbench_file is
generic(
constant period: time:= 20 ps
);
end entity;
architecture arch of testbench_file is
componen... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLROM_3_12.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------------... |
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capabili... |
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capabili... |
library ieee;
use ieee.std_logic_1164.all;
entity case02 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case02;
architecture behav of case02 is
begin
with a select o <=
'1' when "00011",
'1' when "00110" | "00111" | "10001",
'0' when "00100",
'1' when "01100",
'1' ... |
-- Author : Miguel Morales-Sandoval
-- Project : "Reconfigurable ECC
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo ... |
--
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
-- Rob Gaddi Highland Technology. Inspired SetAlertLog... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VC... |
package body b is
end b;
|
-------------------------------------------------------------------------------
--
-- The testbench for t8243 core.
--
-- $Id: tb_t8243-c.vhd,v 1.1 2006-07-14 01:02:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-----------------------------------------------... |
----------------------------------------------------------------------------
-- DPIMREF.VHD -- Digilent Parallel Interface Module Reference Design
----------------------------------------------------------------------------
-- Author: Gene Apperson
-- Copyright 2004 Digilent, Inc.
----------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop;
FOR_LABEL : for index in 4 to 23 loop
end loop;
For_label : for index in 4 to 23 loop
end loop;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BlockRamFaces is
Port (
Clock : in STD_LOGIC;
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (5 downto 0);
Column : in STD_LOGIC_VECTOR (5 downto 0);
DataOutPixel : out STD_LOGIC_VECTOR(11 downto... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use work.HMACSHA384_ISMAIL.all;
entity hmac_sha384 is
port ( clk: in std_logic;
salt : in std_logic_vector(383 downto 0);
pepper : in std_logic_vector(1023 downto 0);
small_msg: in std_logic_vector((6*4)-1 downto 0);
medium_msg... |
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
--
-- Simple RS232 sender with generic baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_sender is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- baudr... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00189
--
-- AUTHOR:
--
-- G. Tomi... |
-- Test case from Adam Barnes
--
package mycomp_pkg is
type int_array is array(natural range <>) of integer;
component mycomp is
generic (
mygen : int_array(1 to 6)
);
port (
i : in bit;
o : out bit
);
end component mycomp;
end package... |
entity tb_asgn01 is
end tb_asgn01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn01 is
signal a : std_logic_vector (2 downto 0);
signal s0 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn01
port map (a => a, s0 => s0, r => r);
process
begi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
--------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
--------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
--------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
package uart2BusTop_pkg is
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
... |
library ieee;
use ieee.std_logic_1164.all;
package uart2BusTop_pkg is
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
use basic_library.very_common_pkg.all;
use work.package_with_constants;
entity clock_divider is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSR_tb IS
END PSR_tb;
ARCHITECTURE behavior OF PSR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
entity moving_average_filter is
port (
sin : in std_logic_vector (10 downto 0);
clk : in std_logic;
sout : out std_logic_vector (10 downto 0);
rst : in std_logic
);
end moving_average_filter;
architecture behavioral of moving_ave... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major rel... |
architecture Rtl of I2SToAvalonST is
type aInputState is (Waiting, ReceivingSerData);
-- bclk set, for sync and delay
type aSyncSet is record
Meta : std_logic;
Sync : std_logic;
Dlyd : std_logic;
end record;
constant cInitValSync : aSyncSet := (
Meta => '0',
Sync => '0',
Dlyd => '0'... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
-------------------------------------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_dec_piso_seleccion IS
END tb_dec_piso_seleccion;
ARCHITECTURE behavior OF tb_dec_piso_seleccion IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec_piso_seleccion
PORT(
piso_code : IN std_logic_vector(1 downto 0);
... |
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