content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_rx_path - rtl
--
-- Description: This is the input port to the switch fabric
-- it consists of foll... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_rx_path - rtl
--
-- Description: This is the input port to the switch fabric
-- it consists of foll... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions:... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions:... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions:... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions:... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions:... |
entity e is end entity;
architecture a of e is
procedure f(x, y, z : integer);
signal x : bit;
begin
f(1, 2, 3 + 5);
assert x'active;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- company:
-- engineer:
--
-- vhdl test bench created by ise for module: random_number
--
-- dependencies:
--
-- revision:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_lo... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
--... |
-------------------------------------------------------------------------------
-- Ce module prends un fil en entrée, 1 si c'est un tick, 0 sinon
-- Sa sortie vaut successivement 0 puis 1 tous les 10 ticks
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_315;
architecture augh of add_315 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_315;
architecture augh of add_315 is
signal carry_inA : std_l... |
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; ... |
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; ... |
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; ... |
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; ... |
-- $Id: pdp11_aunit.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: a... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in st... |
------------------------------------------------------------------------------
-- Copyright (C) 2009 , Emmanuel Amadio
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must r... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_fwft_fifo is
end tb_fwft_fifo;
architecture test of tb_fwft_fifo is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- ... |
-- NEED RESULT: ARCH00110.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P3: Mu... |
architecture RTL of ENTITY1 is
begin
end architecture RTL;
architecture RTL of ENTITY1 is
begin
end;
architecture RTL of ENTITY1 is
begin
end architecture;
architecture
RTL
of
ENTITY1
is
begin
end
architecture
RTL
;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_NOT is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_NOT;
---------------------------------------------------------... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown_async is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
... |
------------------------------------------------------------------------------
-- Context register file
--
-- Project :
-- File : contextregfile.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Tec... |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is d... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** ... |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** ... |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** ... |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** ... |
package ffaccel_imem_mau is
-- created by generatebits
constant IMEMMAUWIDTH : positive := 43;
end ffaccel_imem_mau;
|
package ffaccel_imem_mau is
-- created by generatebits
constant IMEMMAUWIDTH : positive := 43;
end ffaccel_imem_mau;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:35 10/06/2016
-- Design Name:
-- Module Name: C:/Users/utp.CRIE/Desktop/sparcv8-monocicle/Test_alu.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versions:
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_version : unsigned(7 downto 0) := X"04" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release ... |
entity test is
type t is range 0 to 1e2;
end;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin
end block;
BLOCK_LABEL : block is begin
end block;
end architecture RTL;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, component, if-then-else, pro... |
-- This file is part of the ethernet_mac_test project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic(
-- 20 ms at 125 MHz clock
-- Minimum 88E1111 re... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity halfAdder is
-- Half, 1 bit adder
port(
a, b : in std_logic;
s, c : out std_logic
);
end entity halfAdder;
architecture rtl of halfAdder is
begin
s <= a xor b;
c <= a and b;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:56:37 06/19/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/git/ethernet/ethernet4b/control_unit_test1.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- ... |
-------------------------------------------------------------------------------
-- system_dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use... |
-- $Id: ib_intmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ib_intmap - syn
-- Description: pdp11: exter... |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failu... |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failu... |
architecture RTL of FIFO is
begin
a <= b;
a <= when c = '0' else '1';
block_label: block is
begin
a <= b;
a <= c;
end block;
a <= b;
a <= when c = '0' else '1';
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eab_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_1_v2
-- Module Name: Controller_Solving_Key_Equ... |
-- Quartus II VHDL Template
-- Binary Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity thirda is
port(
clk, enable : in std_logic;
reset: buffer std_logic;
q : out integer range 0 to 64
);
end entity;
architecture rtl of thirda is
component binary_counter_mod_16 is
port(
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
entity common_tb is
generic (
clock_period : time
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end common_tb;
architecture Behavioral of common_tb is
signal data_safe_8_b... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity decode_7seg is
port(
clk : in std_logic; -- Clock
reset : in std_logic; -- Reset
data_in : in std_logic_vector(15 downto 0);-- Number to be displayed 4 bits for each segements
segments : out std_logic_vector(... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Mon Aug 9 17:44:47 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $I... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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