content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
-- *********************************************************************
-- Copyright 2011, ON Semiconductor Corporation.
--
-- This software is owned by ON Semiconductor Corporation (ON)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this sof... |
library ieee;
use ieee.std_logic_1164.all;
entity system_timing is
generic (
TIMESTAMP_COUNTER_MAX: integer := 1000
);
port (
clock_50MHz : in std_logic;
reset : in std_logic;
time_base_50_ms_out: out std_logic;
elapsed_time_out: out integer range 0 to TIM... |
package pack is
type rec is record
x : integer;
y : bit_vector;
end record;
type rec_array is array (natural range <>) of rec;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i : in rec_arra... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
--------------------------------------------------------------------... |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
... |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
... |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:48:07 11/22/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Downloads/EPL221_FALL2013_MIPS32DSPprocessorID_948282/EPL221_FALL2013_MIPS32DSPprocessorID_948282/Control_Unit_tb_948... |
----------------------------------------
-- Sign Extender Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 8/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SE is
generic (
initial : integer; -- number of input std_logics
fina... |
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable... |
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable... |
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable... |
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable... |
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable... |
library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity tbs is
end entity tbs;
architecture sim of tbs is
constant period: time := 10 ns;
signal w_clk: std_logic := '0';
signal w_rst: std_logic := '0';
... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
package fifo_pkg is
end package;
package fifo_pkg is
END package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix_tb is
end entity;
architecture memory_matrix_tb_arq of memory_matrix_tb is
signal finished : boolean := false;
signal x_write: std_logic_vector(9 downto 0) := (others => '0');
signal y_write: std_logic_vector(9 downto 0) :=... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity AddrReg is
port(
AddrReg_in : in vl_logic_vector(31 downto 0);
AddrReg_write_en: in vl_logic;
Clk : in vl_logic;
AddrReg_out : out vl_logic_vector(31 downto 0)
);
end AddrReg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DIO_MOD is
generic (
-- IO-REQ: 2 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 ... |
--------------------------------------------------------------------------------
-- Baud Rate Counter --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
|
-------------------------------------------------------------------------------
--
-- Title : q
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\... |
-------------------------------------------------------------------------------
--
-- Title : q
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\... |
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
package mypack is
type MEM_CTL is record
act:... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:23 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity test is
package a is new b generic map(c => ((bar baz, qux zzz)) foo);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--translates the input Score Digits into SSD compatible format
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD2SSD is
Port ( Data_In1 : in STD_LOGIC_VECTOR (3 downto 0);
Data_In2 : in STD_LOGIC_VECTOR (3 downto 0);
Player_in : in STD_LOGIC_VECTOR (15 downto 0);
SSDisplay : out STD_LOGIC_VECT... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major relea... |
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_MPU6050_1 is
end tb_MPU6050_1;
architecture stimulus of tb_MP... |
entity test is
subtype t is foo(open);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY framer is
generic(N : integer := 16);
port(clk : in std_ulogic;
sin : in std_ulogic;
resetb : in std_ulogic;
SOUT : out std_ulogic;
clk_div_8 : out std_ulogic;
decode... |
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : i... |
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : i... |
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : i... |
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : i... |
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : i... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
library std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
USE std.textio.ALL;
PACKAGE my_package IS
function to_bstring(sl : std_logic) return string;
function to_bstring(slv : std_logic_vector) return string;
END PACKAGE;
PACKAGE BODY my_pa... |
LIBRARY ieee;
library std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
USE std.textio.ALL;
PACKAGE my_package IS
function to_bstring(sl : std_logic) return string;
function to_bstring(slv : std_logic_vector) return string;
END PACKAGE;
PACKAGE BODY my_pa... |
--------------------------------------------------------------------------------
--
-- register.vhd
--
-- This file contains the logic for a single register. The contents of the
-- register will always be output. The register will change its value to the
-- input on every rising edge of the clock, whenever the 'nLd... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.RWCACHE_PKG.all;
entity RWCACHE is
generic (
regaddrsize : integer
);
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE_EX : in std_logic;
READNOTWRITE_EX : in ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/ALU.sch - Fri Jun 8 12:08:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that ... |
package pack is
constant C : integer;
type rec is record
x : integer;
y : bit_vector(1 to C);
end record;
end package;
package body pack is
constant C : integer := 4;
end package body;
-------------------------------------------------------------------------------
entity issue549 is... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-- ----------------------------------------------------------------------------
-- Entity for conversion from binary state encoding to one hot encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.st... |
--4选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUXB41 IS
PORT(DATA0,DATA1,DATA2,DATA3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE ART OF MUXB41 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
SEL<=B&A;
PROCESS(SEL)
BEGIN
... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: udp_add_udp_header - Behavioral
--
-- Description: Add the UDP header to a data stream
--
-----------------------------------------------------------------------------... |
# For complete documentation of this file, please see Geany's main documentation
[styling]
# foreground;background;bold;italic
default=0x000000;0xffffff;false;false
comment=0xd00000;0xffffff;false;false
comment_line_bang=0x3f5fbf;0xffffff;false;false;
number=0x007f00;0xffffff;false;false
string=0xff901e;0xffffff;false;... |
--
-- This entity converts button states to the SNES communication protocol
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity snes_btn_ctrl is
port (
clk_i : in std_logic;
pause_o : out std_logic;
snes_js_btn_i : in snes_js... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------... |
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