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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
-- NEED RESULT: PKG00523.PkgProc: Declarative region direct visibility test passed
-- NEED RESULT: PKG00523.PkgProc: Declarative region direct visibility test passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00523
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (1)
-- 10.3 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00523
-- PKG00523/BODY
-- E00000(ARCH00523)
-- ENT00523_Test_Bench(ARCH00523_Test_Bench)
--
-- REVISION HISTORY:
--
-- 14-AUG-1987 - initial revision
-- 17-JUN-1988 - (KLM) changed host names of file objects
-- 28-NOV-1989 - (ESL) change files to be of mode out
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
package PKG00523 is
component PkgComp
generic ( G : boolean ) ;
port ( P : boolean ) ;
end component ;
subtype PkgSubtype is Bit_Vector (1 to 3) ;
type PkgType is record
f1 : boolean ;
f2 : PkgSubtype ;
end record ;
constant PkgCons : PkgType := (f1 => True,
f2 => PkgSubtype'(others => '1')) ;
signal PkgSig : PkgSubtype := (1 to 3 => PkgCons.f2(2)) ;
alias PkgAlias : bit is PkgSig(2) ;
type PkgFileType is file of boolean ;
file PkgFile : PkgFileType is out "ct00523.dat";
attribute PkgAttr : boolean ;
attribute PkgAttr of PkgFileType : type is PkgCons.f1 ;
procedure PkgProc (parm1 : boolean) ;
end PKG00523 ;
package body PKG00523 is
subtype PkgBSubtype is PkgSubtype ;
type PkgBType is record
f1 : boolean ;
f2 : PkgBSubtype ;
end record ;
constant PkgBCons : PkgBType := (f1 => PkgCons.f1,
f2 => PkgBSubtype'(PkgCons.f2)) ;
alias PkgBAlias : bit is PkgbCons.f2(2) ;
file PkgBFile : PkgFileType is out "ct00523.dat";
procedure PkgProc (parm1 : boolean) is
subtype SubpSubtype is PkgSubtype ;
type SubpType is record
f1 : boolean ;
f2 : SubpSubtype ;
end record ;
constant SubpCons : PkgType := (f1 => PkgCons.f1,
f2 => PkgCons.f2 ) ;
variable SubpVar : SubpSubtype := SubpCons.f2;
alias SubpAlias : bit is SubpVar(2) ;
file SubpFile : PkgFileType is out "ct00523.dat";
attribute PkgAttr of SubpLabel : label is PkgCons.f1 ;
variable correct : boolean ;
begin
SubpLabel : while True loop exit; end loop;
correct := PkgCons.f1 and (PkgCons.f2 = PkgSubtype'(others => '1')) and
(PkgSig(2) = PkgAlias) and
PkgFileType'PkgAttr and
PkgBCons.f1 and (PkgBCons.f2 = PkgBSubtype'(others => '1')) and
(PkgBAlias = PkgbCons.f2(2)) and
(SubpCons = PkgCons) and
(SubpVar(2) = SubpAlias) and
SubpLabel'Pkgattr ;
test_report ( "PKG00523.PkgProc" ,
"Declarative region direct visibility test" ,
correct ) ;
if parm1 then
PkgProc (Not parm1) ;
end if ;
end PkgProc ;
end PKG00523 ;
use WORK.STANDARD_TYPES.all, WORK.PKG00523.all ;
architecture ARCH00523 of E00000 is
begin
process
begin
PkgProc (True) ;
wait ;
end process ;
end ARCH00523 ;
entity ENT00523_Test_Bench is
end ENT00523_Test_Bench ;
architecture ARCH00523_Test_Bench of ENT00523_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00523 ) ;
begin
CIS1 : UUT;
end block L1 ;
end ARCH00523_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_580 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_580;
architecture augh of sub_580 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_580 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_580;
architecture augh of sub_580 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:00 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/num/num_stub.vhdl
-- Design : num
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity num is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end num;
architecture stub of num is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:00 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/num/num_stub.vhdl
-- Design : num
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity num is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end num;
architecture stub of num is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
package generic_queue_pkg is
generic (type t_generic_element;
scope : string := C_SCOPE;
GC_QUEUE_COUNT_MAX : natural := 1000;
GC_QUEUE_COUNT_THRESHOLD : natural := 950);
-- When find_* doesn't find a match, they return C_NO_MATCH.
constant C_NO_MATCH : integer := -1;
-- A generic queue for verification
type t_generic_queue is protected
procedure add(
constant instance : in integer;
constant element : in t_generic_element);
procedure add(
constant element : in t_generic_element);
procedure put(
constant instance : in integer;
constant element : in t_generic_element);
procedure put(
constant element : in t_generic_element);
impure function get(
constant instance : in integer)
return t_generic_element;
impure function get(
constant dummy : in t_void)
return t_generic_element;
impure function is_empty(
constant instance : in integer)
return boolean;
impure function is_empty(
constant dummy : in t_void)
return boolean;
procedure set_scope(
constant instance : in integer;
constant scope : in string);
procedure set_scope(
constant scope : in string);
procedure set_name(
constant name : in string);
impure function get_scope(
constant instance : in integer)
return string;
impure function get_scope(
constant dummy : in t_void)
return string;
impure function get_count(
constant instance : in integer)
return natural;
impure function get_count(
constant dummy : in t_void)
return natural;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural);
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural);
impure function get_queue_count_threshold(
constant instance : in integer) return natural;
impure function get_queue_count_threshold(
constant dummy : in t_void) return natural;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void) return t_alert_level;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level);
impure function get_queue_count_max(
constant instance : in integer) return natural;
impure function get_queue_count_max(
constant dummy : in t_void) return natural;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural);
procedure set_queue_count_max(
constant queue_count_max : in natural);
procedure flush(
constant instance : in integer);
procedure flush(
constant dummy : in t_void);
procedure reset(
constant instance : in integer);
procedure reset(
constant dummy : in t_void);
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
);
procedure delete(
constant element : in t_generic_element
);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant instance : in integer
) return t_generic_element;
impure function peek(
constant dummy : in t_void
) return t_generic_element;
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant instance : in integer
) return t_generic_element;
impure function fetch(
constant dummy : in t_void
) return t_generic_element;
impure function find_position(
constant element : in t_generic_element) return integer;
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean;
impure function exists(
constant element : in t_generic_element
) return boolean;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive) return integer;
impure function get_entry_num(
constant position_val : in positive) return integer;
procedure print_queue(
constant instance : in integer);
procedure print_queue(
constant dummy : in t_void);
end protected;
end package generic_queue_pkg;
package body generic_queue_pkg is
type t_generic_queue is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is record
entry_num : natural;
next_element : t_element_ptr;
element_data : t_generic_element;
end record;
type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr;
type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH);
variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry
variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry
variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0);
-- Scope variables
variable vr_scope : t_string_array := (others => (others => NUL));
variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
-- Name variables
variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL);
variable vr_name_is_defined : boolean := false;
variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX);
variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD);
variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING;
variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert
-- Fill level alert
type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY);
constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY;
variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
------------------------------------------------------------------------------------------------------
--
-- Helper methods (not visible from outside)
--
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- Helper method: Check if an Alert shall be triggered (to be called before adding another entry)
------------------------------------------------------------------------------------------------------
procedure perform_pre_add_checks (
constant instance : in integer
) is
begin
if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then
if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then
alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance));
vr_queue_count_threshold_triggered(instance) := true;
end if;
end if;
end procedure;
------------------------------------------------------------------------------------------------------
-- Helper method: Iterate through all entries, and match the one with element_data = element
-- This also works if the element is a record or array, whereas all entries/indexes must match
------------------------------------------------------------------------------------------------------
procedure match_element_data (
instance : in integer; -- Queue instance
element : in t_generic_element; -- Element to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr -- valid if found_match=true
) is
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
if vr_num_elements_in_queue(instance) > 0 then
-- Search from front to back element
v_element_ptr := vr_first_element(instance);
loop
if v_element_ptr.element_data = element then -- Element matched entry
found_match := true;
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else -- No match.
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop;
end if;
end procedure;
-- Find and return entry that matches the identifier
procedure match_identifier (
instance : in integer; -- Queue instance
identifier_option : in t_identifier_option; -- Determines what 'identifier' means
identifier : in positive; -- Identifier value to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr; -- valid if found_match=true
preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr
) is
-- Search from front to back element. Init pointers/counters to the first entry:
variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
preceding_element_ptr := null;
-- If queue is not empty and indentifier in valid range
if (vr_num_elements_in_queue(instance) > 0) and
((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or
(identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then
loop
-- For each element in queue:
-- Check if POSITION or ENTRY_NUM matches v_element_ptr
if (identifier_option = POSITION) and (v_position_ctr = identifier) then
found_match := true;
end if;
if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then
found_match := true;
end if;
if found_match then
-- This element matched. Done searching.
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else
-- No match.
if v_element_ptr.next_element = null then
-- report "last v_position_ctr = " & to_string(v_position_ctr);
exit; -- Last entry. All queue entries have been searched through.
end if;
preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop; -- for each element in queue
end if; -- Not empty
end procedure;
------------------------------------------------------------------------------------------------------
--
-- Public methods, visible from outside
--
------------------------------------------------------------------------------------------------------
-- add : Insert element in the back of queue, i.e. at the highest position
procedure add(
constant instance : in integer;
constant element : in t_generic_element
) is
constant proc_name : string := "add";
variable v_previous_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
-- Increment vr_entry_num
vr_entry_num(instance) := vr_entry_num(instance)+1;
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_queue(instance) > 0 then
v_previous_ptr := vr_last_element(instance);
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list
else -- List is empty
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list.
end if;
-- Increment number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1;
end procedure;
procedure add(
constant element : in t_generic_element
) is
begin
add(1, element);
end procedure;
procedure put(
constant instance : in integer;
constant element : in t_generic_element
) is
begin
add(instance, element);
end procedure;
procedure put(
constant element : in t_generic_element
) is
begin
put(1, element);
end procedure;
impure function get(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance);
end function;
impure function get(
constant dummy : in t_void
) return t_generic_element is
begin
return get(1);
end function;
procedure flush(
constant instance : in integer
) is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER);
-- Deallocate all entries in the list
-- Setting the last element to null and iterating over the queue until finding the null element
vr_last_element(instance) := null;
while vr_first_element(instance) /= null loop
v_to_be_deallocated_ptr := vr_first_element(instance);
vr_first_element(instance) := vr_first_element(instance).next_element;
DEALLOCATE(v_to_be_deallocated_ptr);
end loop;
-- Reset the queue counter
vr_num_elements_in_queue(instance) := 0;
vr_queue_count_threshold_triggered(instance) := false;
end procedure;
procedure flush(
constant dummy : in t_void
) is
begin
flush(1);
end procedure;
procedure reset(
constant instance : in integer) is
begin
flush(instance);
vr_entry_num(instance) := 0; -- Incremented before first insert
end procedure;
procedure reset(
constant dummy : in t_void) is
begin
reset(1);
end procedure;
impure function is_empty(
constant instance : in integer
) return boolean is
begin
if vr_num_elements_in_queue(instance) = 0 then
return true;
else
return false;
end if;
end function;
impure function is_empty(
constant dummy : in t_void
) return boolean is
begin
return is_empty(1);
end function;
procedure set_scope(
constant instance : in integer;
constant scope : in string) is
begin
if instance = ALL_INSTANCES then
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH));
else
for idx in vr_scope'range loop
vr_scope(idx) := (others => NUL);
vr_scope(idx)(1 to scope'length) := scope;
end loop;
end if;
vr_scope_is_defined := (others => true);
else
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH);
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined(instance) := true;
end if;
end procedure;
procedure set_scope(
constant scope : in string) is
begin
set_scope(1, scope);
end procedure;
procedure set_name(
constant name : in string) is
begin
vr_name(1 to name'length) := name;
vr_name_is_defined := true;
end procedure;
impure function get_scope(
constant instance : in integer
) return string is
begin
return to_string(vr_scope(instance));
end function;
impure function get_scope(
constant dummy : in t_void
) return string is
begin
return get_scope(1);
end function;
impure function get_count(
constant instance : in integer
) return natural is
begin
return vr_num_elements_in_queue(instance);
end function;
impure function get_count(
constant dummy : in t_void
) return natural is
begin
return get_count(1);
end function;
impure function get_queue_count_max(
constant instance : in integer
) return natural is
begin
return vr_queue_count_max(instance);
end function;
impure function get_queue_count_max(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_max(1);
end function;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural
) is
begin
vr_queue_count_max(instance) := queue_count_max;
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER);
end procedure;
procedure set_queue_count_max(
constant queue_count_max : in natural
) is
begin
set_queue_count_max(1, queue_count_max);
end procedure;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural
) is
begin
vr_queue_count_threshold(instance) := queue_count_alert_level;
end procedure;
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural
) is
begin
set_queue_count_threshold(1, queue_count_alert_level);
end procedure;
impure function get_queue_count_threshold(
constant instance : in integer
) return natural is
begin
return vr_queue_count_threshold(instance);
end function;
impure function get_queue_count_threshold(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_threshold(1);
end function;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void
) return t_alert_level is
begin
return vr_queue_count_threshold_severity;
end function;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level) is
begin
vr_queue_count_threshold_severity := alert_level;
end procedure;
----------------------------------------------------
-- Insert:
----------------------------------------------------
-- Inserts element into the queue after the matching entry with specified identifier:
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element)
is
constant proc_name : string := "insert";
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_found_match : boolean;
variable v_matched_position : integer;
begin
-- pre insert checks
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
if (identifier /= 1) then
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER);
else -- identifier_option /= POSITION
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER);
end if;
end if;
-- Search from front to back element.
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Make new element
vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num
-- POSITION: insert at matched position
if identifier_option = POSITION then
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr,
element_data => element);
-- if match is first element
if v_preceding_element_ptr = null then
vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list
else
v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
--ENTRY_NUM: insert at position after match
else
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr.next_element,
element_data => element);
v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements
elsif identifier_option = POSITION then -- v_found_match = false
if identifier = 1 then
add(instance, element);
end if;
elsif identifier_option = ENTRY_NUM then
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier) &
", element...", scope);
end if;
end if;
end procedure;
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element) is
begin
insert(1, identifier_option, identifier, element);
end procedure;
----------------------------------------------------
-- delete:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
constant proc_name : string := "delete";
variable v_matched_element_ptr : t_element_ptr; -- The element being deleted
variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
variable v_deletes_remaining : integer;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
-- delete based on POSITION :
-- Note that when deleting the first position, all above positions are decremented by one.
-- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- Find min position
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier_min,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first
while v_deletes_remaining > 0 loop
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
v_deletes_remaining := v_deletes_remaining - 1;
-- Prepare next iteration:
-- Next element to delete:
if v_deletes_remaining > 0 then
if (v_preceding_element_ptr = null) then
-- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry.
v_element_to_delete_ptr := vr_first_element(instance);
else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element
v_element_to_delete_ptr := v_preceding_element_ptr.next_element;
end if;
end if;
end loop;
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier_min), scope);
end if;
end if; -- v_found_match
-- delete based on ENTRY_NUM :
-- Unlike position, an entry's Entry_num is stable when deleting other entries
-- Entry_num is not necessarily increasing as we follow next_element pointers.
-- This means that we must do a complete search for each entry we want to delete
elsif (identifier_option = ENTRY_NUM) then
check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- For each entry to delete, find it based on entry_num , then delete it
for identifier in identifier_min to identifier_max loop
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier), scope);
end if;
end if; -- v_found_match
end loop;
end if; -- identifier_option
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
begin
delete(1, identifier_option, identifier_min, identifier_max);
end procedure;
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
) is
variable v_entry_num : integer:= find_entry_num(element);
begin
delete(instance, ENTRY_NUM, v_entry_num, v_entry_num);
end procedure;
procedure delete(
constant element : in t_generic_element
) is
begin
delete(1, element);
end procedure;
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
case range_option is
when SINGLE =>
delete(instance, identifier_option, identifier, identifier);
when AND_LOWER =>
delete(instance, identifier_option, 1, identifier);
when AND_HIGHER =>
if identifier_option = POSITION then
delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance));
elsif identifier_option = ENTRY_NUM then
delete(instance, identifier_option, identifier, vr_entry_num(instance));
end if;
end case;
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
delete(1, identifier_option, identifier, range_option);
end procedure;
----------------------------------------------------
-- peek:
----------------------------------------------------
-- Read the entry matching the identifier, but don't remove it.
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "peek";
variable v_matched_element_data : t_generic_element; -- Return value
variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_matched_element_data := v_matched_element_ptr.element_data;
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return peek(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function peek(
constant instance : in integer
) return t_generic_element is
begin
return peek(instance, POSITION, 1);
end function;
impure function peek(
constant dummy : in t_void
) return t_generic_element is
begin
return peek(1);
end function;
----------------------------------------------------
-- Fetch:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "fetch";
variable v_matched_element_ptr : t_element_ptr; -- The element being fetched
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Keep info about element before removing it from queue
v_matched_element_data := v_matched_element_ptr.element_data;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_matched_element_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_matched_element_ptr);
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return fetch(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function fetch(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance, POSITION, 1);
end function;
impure function fetch(
constant dummy : in t_void
) return t_generic_element is
begin
return fetch(1);
end function;
-- Returns position of entry if found, else C_NO_MATCH.
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element --
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
-- Don't include this check, because we may want to use exists() on an empty queue.
-- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_matched_position;
else
return C_NO_MATCH;
end if;
end function;
impure function find_position(
constant element : in t_generic_element
) return integer is
begin
return find_position(1, element);
end function;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean is
begin
return (find_position(instance, element) /= C_NO_MATCH);
end function;
impure function exists(
constant element : in t_generic_element
) return boolean is
begin
return exists(1, element);
end function;
-- Returns entry number or position to entry if found, else C_NO_MATCH.
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_element_ptr.entry_num;
else
return C_NO_MATCH;
end if;
end function;
impure function find_entry_num(
constant element : in t_generic_element
) return integer is
begin
return find_entry_num(1, element);
end function;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive
) return integer is
variable v_found_match : boolean;
variable v_matched_position : integer;
variable v_matched_element_ptr : t_element_ptr;
variable v_preceding_element_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => POSITION ,
identifier => position_val,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
return v_matched_element_ptr.entry_num;
else
return -1;
end if;
end function get_entry_num;
impure function get_entry_num(
constant position_val : in positive
) return integer is
begin
return get_entry_num(1, position_val);
end function get_entry_num;
-- for debugging:
-- print each entry's position and entry_num
procedure print_queue(
constant instance : in integer
)
is
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
-- Search from front to back element. Initalise pointers/counters to the first entry:
v_element_ptr := vr_first_element(instance);
if v_element_ptr = NULL then
return; -- Return if queue is empty
end if;
loop
log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope);
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end loop;
end procedure;
procedure print_queue(
constant dummy : in t_void) is
begin
print_queue(1);
end procedure;
end protected body;
end package body generic_queue_pkg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 0;
constant CFG_GRPCI2_TARGET : integer := 0;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#0#;
constant CFG_GRPCI2_DID : integer := 16#0#;
constant CFG_GRPCI2_CLASS : integer := 16#0#;
constant CFG_GRPCI2_RID : integer := 16#0#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#0#;
constant CFG_GRPCI2_BAR0 : integer := 0;
constant CFG_GRPCI2_BAR1 : integer := 0;
constant CFG_GRPCI2_BAR2 : integer := 0;
constant CFG_GRPCI2_BAR3 : integer := 0;
constant CFG_GRPCI2_BAR4 : integer := 0;
constant CFG_GRPCI2_BAR5 : integer := 0;
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2308.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02308ent IS
END c07s02b07x00p01n01i02308ent;
ARCHITECTURE c07s02b07x00p01n01i02308arch OF c07s02b07x00p01n01i02308ent IS
BEGIN
TESTING: PROCESS
constant x : real := abs 10.5;
BEGIN
assert NOT(x = 10.5)
report "***PASSED TEST: c07s02b07x00p01n01i02308"
severity NOTE;
assert (x = 10.5)
report "***FAILED TEST: c07s02b07x00p01n01i02308 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02308arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2308.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02308ent IS
END c07s02b07x00p01n01i02308ent;
ARCHITECTURE c07s02b07x00p01n01i02308arch OF c07s02b07x00p01n01i02308ent IS
BEGIN
TESTING: PROCESS
constant x : real := abs 10.5;
BEGIN
assert NOT(x = 10.5)
report "***PASSED TEST: c07s02b07x00p01n01i02308"
severity NOTE;
assert (x = 10.5)
report "***FAILED TEST: c07s02b07x00p01n01i02308 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02308arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2308.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02308ent IS
END c07s02b07x00p01n01i02308ent;
ARCHITECTURE c07s02b07x00p01n01i02308arch OF c07s02b07x00p01n01i02308ent IS
BEGIN
TESTING: PROCESS
constant x : real := abs 10.5;
BEGIN
assert NOT(x = 10.5)
report "***PASSED TEST: c07s02b07x00p01n01i02308"
severity NOTE;
assert (x = 10.5)
report "***FAILED TEST: c07s02b07x00p01n01i02308 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02308arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 60368)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Reorder Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library ee560;
use ee560.all;
-----------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_ROB of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden ROB)
signal Rob_Full_gold,Rob_TwoOrMoreVacant_gold,Rob_CommitMemWrite_gold,Rob_Commit_gold,Rob_CommitRegWrite_gold: std_logic ;
signal Rob_CommitPrePhyAddr_gold,Rob_CommitCurrPhyAddr_gold: std_logic_vector(5 downto 0);
signal Rob_SwAddr_gold: std_logic_vector(31 downto 0);
signal Rob_TopPtr_gold,Rob_BottomPtr_gold,Rob_CommitRdAddr_gold: std_logic_vector(4 downto 0);
signal Rob_Instruction_gold:std_logic_vector(31 downto 0);
-- Signals for the student's DUT (ROB)
signal Resetb: std_logic;
signal Cdb_Valid,Dis_InstSw,Dis_RegWrite,Dis_InstValid,Rob_Full,Rob_TwoOrMoreVacant,SB_Full,Rob_CommitMemWrite,Rob_Commit,Rob_CommitRegWrite,Cdb_Flush: std_logic ;
signal Dis_NewRdPhyAddr,Dis_PrevPhyAddr,Dis_SwRtPhyAddr,Rob_CommitPrePhyAddr,Rob_CommitCurrPhyAddr: std_logic_vector(5 downto 0);
signal Cdb_SwAddr,Rob_SwAddr: std_logic_vector(31 downto 0);
signal Dis_RobRdAddr,Cdb_RobTag,Rob_TopPtr,Rob_BottomPtr,Cfc_RobTag,Rob_CommitRdAddr: std_logic_vector(4 downto 0);
signal Rob_Instruction,Dis_instruction:std_logic_vector(31 downto 0);
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
--digi_address : in std_logic_vector(5 downto 0); -- input ID for the register we want to see
--digi_data : out std_logic_vector(31 downto 0); -- output data given by the register
Clk : in std_logic;
-- signals corresponding to Instruction memory
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component rob
port (
Clk :in std_logic;
Resetb :in std_logic;
Cdb_Valid : in std_logic; -- signal to tell that the values coming on CDB is valid
Cdb_RobTag : in std_logic_vector(4 downto 0); -- Tag of the instruction which the the CDB is broadcasting
Cdb_SwAddr : in std_logic_vector (31 downto 0); -- to give the store wordaddr
-- Interface with Dispatch unit
Dis_InstSw : in std_logic; -- signal that tells that the signal being dispatched is a store word
Dis_RegWrite : in std_logic; -- signal telling that the instruction is register writing instruction
Dis_InstValid : in std_logic; -- Signal telling that Dispatch unit is giving valid information
Dis_RobRdAddr : in std_logic_vector(4 downto 0); -- Actual Desitnation register number of the instruction being dispatched
Dis_NewRdPhyAddr : in std_logic_vector (5 downto 0); -- Current Physical Register number of dispatching instruction taken by the dispatch unit from the FRL
Dis_PrevPhyAddr : in std_logic_vector (5 downto 0); -- Previous Physical Register number of dispatch unit taken from CFC
Dis_SwRtPhyAddr : in std_logic_vector (5 downto 0); -- Physical Address number from where store word has to take the data
Rob_Full : out std_logic; -- Whether the ROB is Full or not
Rob_TwoOrMoreVacant : out std_logic; -- Whether there are two or more vacant spot in ROB. Useful because Dispatch is 2 stage and if there is
--only 1 vacant spot and second stage is dispatching the insturction first stage should not
-- dispatch any new Instruction
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
Rob_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with store buffer
SB_Full : in std_logic; -- Tells the ROB that the store buffer is full
Rob_SwAddr : out std_logic_vector (31 downto 0); -- The address in case of sw instruction
Rob_CommitMemWrite : out std_logic; -- Signal to enable the memory for writing purpose
-- Rob_FlushSw : out std_logic; -- for address buffer of lsq
-- Rob_FlushSwTag : out std_logic_vector (5 downto 0);
-- Takes care of flushing the address buffer
-- Interface with FRL and CFC
Rob_TopPtr : out std_logic_vector (4 downto 0); -- Gives the value of TopPtr pointer of ROB
Rob_BottomPtr : out std_logic_vector (4 downto 0); -- Gives the Bottom Pointer of ROB
Rob_Commit : out std_logic; -- FRL needs it to to add pre phy to free list cfc needs it to remove the latest cheackpointed copy
Rob_CommitRdAddr : out std_logic_vector(4 downto 0); -- Architectural register number of committing instruction
Rob_CommitRegWrite : out std_logic; --Indicates that the instruction that is being committed is a register wrtiting instruction
Rob_CommitPrePhyAddr : out std_logic_vector(5 downto 0); --pre physical addr of committing inst to be added to FRL
Rob_CommitCurrPhyAddr : out std_logic_vector (5 downto 0); -- Current Register Address of committing instruction to update retirment rat
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cfc_RobTag : in std_logic_vector (4 downto 0) -- Tag of the instruction that has the checkpoint
);
end component rob;
-----------------------------
for ROB_UUT: rob use entity work.rob(rob_arch);
-----------------------------
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
ROB_UUT: rob
port map (
Clk => Clk,
Resetb => Resetb,
Cdb_Valid => Cdb_Valid,
Cdb_RobTag => Cdb_RobTag,
Cdb_SwAddr => Cdb_SwAddr,
Dis_InstSw => Dis_InstSw,
Dis_RegWrite => Dis_RegWrite,
Dis_InstValid => Dis_InstValid,
Dis_RobRdAddr => Dis_RobRdAddr,
Dis_NewRdPhyAddr => Dis_NewRdPhyAddr,
Dis_PrevPhyAddr => Dis_PrevPhyAddr,
Dis_SwRtPhyAddr => Dis_SwRtPhyAddr,
Rob_Full => Rob_Full,
Rob_TwoOrMoreVacant => Rob_TwoOrMoreVacant,
Dis_instruction => Dis_instruction,
Rob_Instruction => Rob_Instruction,
SB_Full => SB_Full,
Rob_SwAddr => Rob_SwAddr,
Rob_CommitMemWrite => Rob_CommitMemWrite,
Rob_TopPtr => Rob_TopPtr,
Rob_BottomPtr => Rob_BottomPtr,
Rob_Commit => Rob_Commit,
Rob_CommitRdAddr => Rob_CommitRdAddr,
Rob_CommitRegWrite => Rob_CommitRegWrite,
Rob_CommitPrePhyAddr => Rob_CommitPrePhyAddr,
Rob_CommitCurrPhyAddr => Rob_CommitCurrPhyAddr,
Cdb_Flush => Cdb_Flush,
Cfc_RobTag => Cfc_RobTag
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of ROB only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Rob_Full_gold /= Rob_Full) then
write (my_outline, string'("ERROR! Rob_Full of TEST does not match Rob_Full_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_TwoOrMoreVacant_gold /= Rob_TwoOrMoreVacant) then
write (my_outline, string'("ERROR! Rob_TwoOrMoreVacant of TEST does not match Rob_TwoOrMoreVacant_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_Instruction_gold /= Rob_Instruction) then
write (my_outline, string'("ERROR! Rob_Instruction of TEST does not match Rob_Instruction_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_SwAddr_gold /= Rob_SwAddr) then
write (my_outline, string'("ERROR! Rob_SwAddr of TEST does not match Rob_SwAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_CommitMemWrite_gold /= Rob_CommitMemWrite) then
write (my_outline, string'("ERROR! Rob_CommitMemWrite of TEST does not match Rob_CommitMemWrite_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_TopPtr_gold /= Rob_TopPtr) then
write (my_outline, string'("ERROR! Rob_TopPtr of TEST does not match Rob_TopPtr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_BottomPtr_gold /= Rob_BottomPtr) then
write (my_outline, string'("ERROR! Rob_BottomPtr of TEST does not match Rob_BottomPtr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_Commit_gold /= Rob_Commit) then
write (my_outline, string'("ERROR! Rob_Commit of TEST does not match Rob_Commit_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_CommitRdAddr_gold /= Rob_CommitRdAddr) then
write (my_outline, string'("ERROR! Rob_CommitRdAddr of TEST does not match Rob_CommitRdAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_CommitRegWrite_gold /= Rob_CommitRegWrite) then
write (my_outline, string'("ERROR! Rob_CommitRegWrite of TEST does not match Rob_CommitRegWrite_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_CommitPrePhyAddr_gold /= Rob_CommitPrePhyAddr) then
write (my_outline, string'("ERROR! Rob_CommitPrePhyAddr of TEST does not match Rob_CommitPrePhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Rob_CommitCurrPhyAddr_gold /= Rob_CommitCurrPhyAddr) then
write (my_outline, string'("ERROR! Rob_CommitCurrPhyAddr of TEST does not match Rob_CommitCurrPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Cdb_Valid","Cdb_Valid",1,1);
enable_signal_spy("/UUT/Cdb_Valid","Cdb_Valid",0);
init_signal_spy("/UUT/Cdb_RobTag","Cdb_RobTag",1,1);
enable_signal_spy("/UUT/Cdb_RobTag","Cdb_RobTag",0);
init_signal_spy("/UUT/Cdb_SwAddr","Cdb_SwAddr",1,1);
enable_signal_spy("/UUT/Cdb_SwAddr","Cdb_SwAddr",0);
init_signal_spy("/UUT/Dis_InstSw","Dis_InstSw",1,1);
enable_signal_spy("/UUT/Dis_InstSw","Dis_InstSw",0);
init_signal_spy("/UUT/Dis_RegWrite","Dis_RegWrite",1,1);
enable_signal_spy("/UUT/Dis_RegWrite","Dis_RegWrite",0);
init_signal_spy("/UUT/Dis_InstValid","Dis_InstValid",1,1);
enable_signal_spy("/UUT/Dis_InstValid","Dis_InstValid",0);
init_signal_spy("/UUT/Dis_RobRdAddr","Dis_RobRdAddr",1,1);
enable_signal_spy("/UUT/Dis_RobRdAddr","Dis_RobRdAddr",0);
init_signal_spy("/UUT/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr",1,1);
enable_signal_spy("/UUT/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr",0);
init_signal_spy("/UUT/Dis_PrevPhyAddr","Dis_PrevPhyAddr",1,1);
enable_signal_spy("/UUT/Dis_PrevPhyAddr","Dis_PrevPhyAddr",0);
init_signal_spy("/UUT/Dis_SwRtPhyAddr","Dis_SwRtPhyAddr",1,1);
enable_signal_spy("/UUT/Dis_SwRtPhyAddr","Dis_SwRtPhyAddr",0);
init_signal_spy("/UUT/Dis_instruction","Dis_instruction",1,1);
enable_signal_spy("/UUT/Dis_instruction","Dis_instruction",0);
init_signal_spy("/UUT/SB_Full","SB_Full",1,1);
enable_signal_spy("/UUT/SB_Full","SB_Full",0);
init_signal_spy("/UUT/Cdb_Flush","Cdb_Flush",1,1);
enable_signal_spy("/UUT/Cdb_Flush","Cdb_Flush",0);
init_signal_spy("/UUT/Cfc_RobTag","Cfc_RobTag",1,1);
enable_signal_spy("/UUT/Cfc_RobTag","Cfc_RobTag",0);
--outputs--
init_signal_spy("/UUT/Rob_Full","Rob_Full_gold",1,1);
enable_signal_spy("/UUT/Rob_Full","Rob_Full_gold",0);
init_signal_spy("/UUT/Rob_TwoOrMoreVacant","Rob_TwoOrMoreVacant_gold",1,1);
enable_signal_spy("/UUT/Rob_TwoOrMoreVacant","Rob_TwoOrMoreVacant_gold",0);
init_signal_spy("/UUT/Rob_Instruction","Rob_Instruction_gold",1,1);
enable_signal_spy("/UUT/Rob_Instruction","Rob_Instruction_gold",0);
init_signal_spy("/UUT/Rob_SwAddr","Rob_SwAddr_gold",1,1);
enable_signal_spy("/UUT/Rob_SwAddr","Rob_SwAddr_gold",0);
init_signal_spy("/UUT/Rob_CommitMemWrite","Rob_CommitMemWrite_gold",1,1);
enable_signal_spy("/UUT/Rob_CommitMemWrite","Rob_CommitMemWrite_gold",0);
init_signal_spy("/UUT/Rob_TopPtr","Rob_TopPtr_gold",1,1);
enable_signal_spy("/UUT/Rob_TopPtr","Rob_TopPtr_gold",0);
init_signal_spy("/UUT/Rob_BottomPtr","Rob_BottomPtr_gold",1,1);
enable_signal_spy("/UUT/Rob_BottomPtr","Rob_BottomPtr_gold",0);
init_signal_spy("/UUT/Rob_Commit","Rob_Commit_gold",1,1);
enable_signal_spy("/UUT/Rob_Commit","Rob_Commit_gold",0);
init_signal_spy("/UUT/Rob_CommitRdAddr","Rob_CommitRdAddr_gold",1,1);
enable_signal_spy("/UUT/Rob_CommitRdAddr","Rob_CommitRdAddr_gold",0);
init_signal_spy("/UUT/Rob_CommitRegWrite","Rob_CommitRegWrite_gold",1,1);
enable_signal_spy("/UUT/Rob_CommitRegWrite","Rob_CommitRegWrite_gold",0);
init_signal_spy("/UUT/Rob_CommitPrePhyAddr","Rob_CommitPrePhyAddr_gold",1,1);
enable_signal_spy("/UUT/Rob_CommitPrePhyAddr","Rob_CommitPrePhyAddr_gold",0);
init_signal_spy("/UUT/Rob_CommitCurrPhyAddr","Rob_CommitCurrPhyAddr_gold",1,1);
enable_signal_spy("/UUT/Rob_CommitCurrPhyAddr","Rob_CommitCurrPhyAddr_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_ROB;
|
-- NEED RESULT: ARCH00280: Block statement with a guard expression passed
-- NEED RESULT: ARCH00280: Block statement without a guard expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00280
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00280)
-- ENT00280_Test_Bench(ARCH00280_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00280 of E00000 is
signal S : boolean := false ;
begin
B1 :
block ( S )
begin
B1_2 :
block ( Not S )
begin
process
begin
test_report ( "ARCH00280" ,
"Block statement with a guard expression" ,
True ) ;
wait ;
end process ;
end block B1_2 ;
end block B1 ;
B2 :
block ( S )
begin
B2_2 :
block
begin
process
begin
test_report ( "ARCH00280" ,
"Block statement without a guard expression" ,
True ) ;
wait ;
end process ;
end block B2_2 ;
end block B2 ;
end ARCH00280 ;
entity ENT00280_Test_Bench is
end ENT00280_Test_Bench ;
architecture ARCH00280_Test_Bench of ENT00280_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00280 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00280_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 05:17:03 PM
-- Design Name:
-- Module Name: MOV8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MOV8 is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end MOV8;
architecture Behavioral of MOV8 is
component SHL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SHL8Bit;
signal OutputSHL1 : BIT_VECTOR(7 downto 0);
signal OutputSHL2 : BIT_VECTOR(7 downto 0);
signal OutputSHL3 : BIT_VECTOR(7 downto 0);
signal OutputSHL4 : BIT_VECTOR(7 downto 0);
begin
-- Shift InputA 4 bits to the left
SHL_Impl1: SHL8Bit port map(InputA, OutputSHL1);
SHL_Impl2: SHL8Bit port map(OutputSHL1, OutputSHL2);
SHL_Impl3: SHL8Bit port map(OutputSHL2, OutputSHL3);
SHL_Impl4: SHL8Bit port map(OutputSHL3, OutputSHL4);
Output <= OutputSHL4 or InputB;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity network_interface;
architecture structural of network_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
type ni_states is (idle, sending);
signal state, next_state : ni_states;
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-- priority encoder to determine which vc to use
us_0: priority_encoder generic map(vc_sel_width)
port map(send_getNonFullVCs, selected_vc_enc);
process(clk, rst)
begin
if rst = '1' then
selected_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
state <= next_state;
end if;
end process;
selected_vc_d <= selected_vc_enc when state = idle else
selected_vc_q;
process(state, send_flit, set_tail_flit)
begin
next_state <= state;
if state = idle and send_flit = '1' then
next_state <= sending;
end if;
if state = sending and set_tail_flit = '1' then
next_state <= idle;
end if;
end process;
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc_q & send_data;
ready_to_send <= or_reduce(send_getNonFullVCs) when state = idle else
send_getNonFullVCs(0) when state = sending and selected_vc_q = "01" else
send_getNonFullVCs(1) when state = sending and selected_vc_q = "10";
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_sync_cell.vhd
--!
--! @brief fpgaMSP430 Generic synchronizer
--
--! @author Olivier Girard, olgirard@gmail.com
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_sync_cell is
generic (
SYNC_EN : boolean := true --! Synchronize input
);
port (
--! INPUTs
clk : in std_logic; --! Receiving clock
rst : in std_logic; --! Receiving reset (active high)
data_in : in std_logic; --! Asynchronous data input
--! OUTPUTs
data_out : out std_logic --! Synchronized data output
);
end entity fmsp_sync_cell;
architecture RTL of fmsp_sync_cell is
signal data_sync : std_logic_vector(1 downto 0);
begin
DATA_SYNC_REG : process(clk,rst)
begin
if (rst = '1') then
data_sync <= "00";
elsif rising_edge(clk) then
data_sync <= data_sync(0) & data_in;
end if;
end process DATA_SYNC_REG;
DATA_MUX : process(data_sync(1),data_in)
begin
if (SYNC_EN = true) then
data_out <= data_sync(1);
else
data_out <= data_in;
end if;
end process DATA_MUX;
end RTL; --! fmsp_sync_cell
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity log is
port(
inp : in unsigned;
outp : out unsigned
);
end;
architecture rtl of log is
constant c_val_bits : integer := 5;
type t_lut is array(natural range <>) of unsigned(c_val_bits-1 downto 0);
function map_log2(addr_bits, value_bits : integer) return t_lut is
variable step : real := 1.0/real(2**addr_bits);
variable tmp : real;
variable result : t_lut(0 to 2**addr_bits-1);
begin
for idx in result'range loop
tmp := 1.0 + real(idx)*step;
result(idx) := to_unsigned(integer(tmp), value_bits);
end loop;
return result;
end function;
constant lut : t_lut := map_log2(5, c_val_bits);
function find_msb(inp : unsigned) return integer is
variable result : integer := 0;
begin
for idx in inp'left downto inp'right loop
if inp(idx) = '1' then
result := idx;
exit;
end if;
end loop;
return result;
end;
begin
p_comb : process(inp)
variable msb : integer;
variable lsb : integer;
variable idx : unsigned(c_val_bits-1 downto 0);
begin
if inp = 0 then
outp <= (others => '0');
else
msb := find_msb(inp);
lsb := msb - c_val_bits;
if lsb >= 0 then
idx := inp(msb-1 downto lsb);
else
idx := shift_left(inp, abs(lsb))(c_val_bits-1 downto 0);
end if;
outp <= to_unsigned(2**c_val_bits * msb) +
lut(to_integer(idx));
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity log is
port(
inp : in unsigned;
outp : out unsigned
);
end;
architecture rtl of log is
constant c_val_bits : integer := 5;
type t_lut is array(natural range <>) of unsigned(c_val_bits-1 downto 0);
function map_log2(addr_bits, value_bits : integer) return t_lut is
variable step : real := 1.0/real(2**addr_bits);
variable tmp : real;
variable result : t_lut(0 to 2**addr_bits-1);
begin
for idx in result'range loop
tmp := 1.0 + real(idx)*step;
result(idx) := to_unsigned(integer(tmp), value_bits);
end loop;
return result;
end function;
constant lut : t_lut := map_log2(5, c_val_bits);
function find_msb(inp : unsigned) return integer is
variable result : integer := 0;
begin
for idx in inp'left downto inp'right loop
if inp(idx) = '1' then
result := idx;
exit;
end if;
end loop;
return result;
end;
begin
p_comb : process(inp)
variable msb : integer;
variable lsb : integer;
variable idx : unsigned(c_val_bits-1 downto 0);
begin
if inp = 0 then
outp <= (others => '0');
else
msb := find_msb(inp);
lsb := msb - c_val_bits;
if lsb >= 0 then
idx := inp(msb-1 downto lsb);
else
idx := shift_left(inp, abs(lsb))(c_val_bits-1 downto 0);
end if;
outp <= to_unsigned(2**c_val_bits * msb) +
lut(to_integer(idx));
end if;
end process;
end; |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
|
-------------------------------------------------------------------
-- System Generator version 10.1.00 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity warp_timer_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_DWIDTH: integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH: integer range 32 to 32 := 32;
C_SPLB_AWIDTH: integer := 0;
C_SPLB_P2P: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER_CONTROL_R: integer := 0;
C_MEMMAP_TIMER_CONTROL_R_N_BITS: integer := 0;
C_MEMMAP_TIMER_CONTROL_R_BIN_PT: integer := 0;
C_MEMMAP_TIMER_STATUS: integer := 0;
C_MEMMAP_TIMER_STATUS_N_BITS: integer := 0;
C_MEMMAP_TIMER_STATUS_BIN_PT: integer := 0;
C_MEMMAP_TIMER0_COUNTTO: integer := 0;
C_MEMMAP_TIMER0_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER0_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER1_COUNTTO: integer := 0;
C_MEMMAP_TIMER1_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER1_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER2_COUNTTO: integer := 0;
C_MEMMAP_TIMER2_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER2_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER3_COUNTTO: integer := 0;
C_MEMMAP_TIMER3_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER3_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER_CONTROL_W: integer := 0;
C_MEMMAP_TIMER_CONTROL_W_N_BITS: integer := 0;
C_MEMMAP_TIMER_CONTROL_W_BIN_PT: integer := 0
);
port (
ce: in std_logic;
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer_plbw;
architecture structural of warp_timer_plbw is
signal ce_x0: std_logic;
signal clk: std_logic;
signal idlefordifs_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal timer0_active_x0: std_logic;
signal timer1_active_x0: std_logic;
signal timer2_active_x0: std_logic;
signal timer3_active_x0: std_logic;
signal timerexpire_x0: std_logic;
begin
ce_x0 <= ce;
idlefordifs_x0 <= idlefordifs;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
clk <= splb_clk;
splb_rst_x0 <= splb_rst;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
timer0_active <= timer0_active_x0;
timer1_active <= timer1_active_x0;
timer2_active <= timer2_active_x0;
timer3_active <= timer3_active_x0;
timerexpire <= timerexpire_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.warp_timer_cw
port map (
ce => ce_x0,
clk => clk,
idlefordifs => idlefordifs_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
timer0_active => timer0_active_x0,
timer1_active => timer1_active_x0,
timer2_active => timer2_active_x0,
timer3_active => timer3_active_x0,
timerexpire => timerexpire_x0
);
end structural;
|
-------------------------------------------------------------------
-- System Generator version 10.1.00 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity warp_timer_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_DWIDTH: integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH: integer range 32 to 32 := 32;
C_SPLB_AWIDTH: integer := 0;
C_SPLB_P2P: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER0_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER1_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER2_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT_N_BITS: integer := 0;
C_MEMMAP_TIMER3_TIMELEFT_BIN_PT: integer := 0;
C_MEMMAP_TIMER_CONTROL_R: integer := 0;
C_MEMMAP_TIMER_CONTROL_R_N_BITS: integer := 0;
C_MEMMAP_TIMER_CONTROL_R_BIN_PT: integer := 0;
C_MEMMAP_TIMER_STATUS: integer := 0;
C_MEMMAP_TIMER_STATUS_N_BITS: integer := 0;
C_MEMMAP_TIMER_STATUS_BIN_PT: integer := 0;
C_MEMMAP_TIMER0_COUNTTO: integer := 0;
C_MEMMAP_TIMER0_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER0_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER1_COUNTTO: integer := 0;
C_MEMMAP_TIMER1_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER1_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER2_COUNTTO: integer := 0;
C_MEMMAP_TIMER2_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER2_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER3_COUNTTO: integer := 0;
C_MEMMAP_TIMER3_COUNTTO_N_BITS: integer := 0;
C_MEMMAP_TIMER3_COUNTTO_BIN_PT: integer := 0;
C_MEMMAP_TIMER_CONTROL_W: integer := 0;
C_MEMMAP_TIMER_CONTROL_W_N_BITS: integer := 0;
C_MEMMAP_TIMER_CONTROL_W_BIN_PT: integer := 0
);
port (
ce: in std_logic;
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer_plbw;
architecture structural of warp_timer_plbw is
signal ce_x0: std_logic;
signal clk: std_logic;
signal idlefordifs_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal timer0_active_x0: std_logic;
signal timer1_active_x0: std_logic;
signal timer2_active_x0: std_logic;
signal timer3_active_x0: std_logic;
signal timerexpire_x0: std_logic;
begin
ce_x0 <= ce;
idlefordifs_x0 <= idlefordifs;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
clk <= splb_clk;
splb_rst_x0 <= splb_rst;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
timer0_active <= timer0_active_x0;
timer1_active <= timer1_active_x0;
timer2_active <= timer2_active_x0;
timer3_active <= timer3_active_x0;
timerexpire <= timerexpire_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.warp_timer_cw
port map (
ce => ce_x0,
clk => clk,
idlefordifs => idlefordifs_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
timer0_active => timer0_active_x0,
timer1_active => timer1_active_x0,
timer2_active => timer2_active_x0,
timer3_active => timer3_active_x0,
timerexpire => timerexpire_x0
);
end structural;
|
-- Video_System.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:20
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Video_System is
port (
VGA_CLK_from_the_VGA_Controller : out std_logic; -- VGA_Controller_external_interface.CLK
VGA_HS_from_the_VGA_Controller : out std_logic; -- .HS
VGA_VS_from_the_VGA_Controller : out std_logic; -- .VS
VGA_BLANK_from_the_VGA_Controller : out std_logic; -- .BLANK
VGA_SYNC_from_the_VGA_Controller : out std_logic; -- .SYNC
VGA_R_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .R
VGA_G_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .G
VGA_B_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .B
clk_0 : in std_logic := '0'; -- clk_0_clk_in.clk
reset_n : in std_logic := '0'; -- clk_0_clk_in_reset.reset_n
I2C_SDAT_to_and_from_the_AV_Config : inout std_logic := '0'; -- AV_Config_external_interface.SDAT
I2C_SCLK_from_the_AV_Config : out std_logic; -- .SCLK
SRAM_DQ_to_and_from_the_Pixel_Buffer : inout std_logic_vector(15 downto 0) := (others => '0'); -- Pixel_Buffer_external_interface.DQ
SRAM_ADDR_from_the_Pixel_Buffer : out std_logic_vector(17 downto 0); -- .ADDR
SRAM_LB_N_from_the_Pixel_Buffer : out std_logic; -- .LB_N
SRAM_UB_N_from_the_Pixel_Buffer : out std_logic; -- .UB_N
SRAM_CE_N_from_the_Pixel_Buffer : out std_logic; -- .CE_N
SRAM_OE_N_from_the_Pixel_Buffer : out std_logic; -- .OE_N
SRAM_WE_N_from_the_Pixel_Buffer : out std_logic; -- .WE_N
TD_CLK27_to_the_Video_In_Decoder : in std_logic := '0'; -- Video_In_Decoder_external_interface.TD_CLK27
TD_DATA_to_the_Video_In_Decoder : in std_logic_vector(7 downto 0) := (others => '0'); -- .TD_DATA
TD_HS_to_the_Video_In_Decoder : in std_logic := '0'; -- .TD_HS
TD_VS_to_the_Video_In_Decoder : in std_logic := '0'; -- .TD_VS
TD_RESET_from_the_Video_In_Decoder : out std_logic; -- .TD_RESET
overflow_flag_from_the_Video_In_Decoder : out std_logic -- .overflow_flag
);
end entity Video_System;
architecture rtl of Video_System is
component Video_System_Onchip_Memory is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
clken : in std_logic := 'X'; -- clken
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X' -- reset
);
end component Video_System_Onchip_Memory;
component Video_System_Dual_Clock_FIFO is
port (
clk_stream_in : in std_logic := 'X'; -- clk
reset_stream_in : in std_logic := 'X'; -- reset
clk_stream_out : in std_logic := 'X'; -- clk
reset_stream_out : in std_logic := 'X'; -- reset
stream_in_ready : out std_logic; -- ready
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Dual_Clock_FIFO;
component Video_System_Pixel_Buffer is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component Video_System_Pixel_Buffer;
component Video_System_Pixel_Buffer_DMA is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_address : out std_logic_vector(31 downto 0); -- address
master_arbiterlock : out std_logic; -- lock
master_read : out std_logic; -- read
master_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
stream_ready : in std_logic := 'X'; -- ready
stream_startofpacket : out std_logic; -- startofpacket
stream_endofpacket : out std_logic; -- endofpacket
stream_valid : out std_logic; -- valid
stream_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Pixel_Buffer_DMA;
component Video_System_Pixel_RGB_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Pixel_RGB_Resampler;
component Video_System_Pixel_Scaler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Pixel_Scaler;
component Video_System_VGA_Controller is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
startofpacket : in std_logic := 'X'; -- startofpacket
endofpacket : in std_logic := 'X'; -- endofpacket
valid : in std_logic := 'X'; -- valid
ready : out std_logic; -- ready
VGA_CLK : out std_logic; -- export
VGA_HS : out std_logic; -- export
VGA_VS : out std_logic; -- export
VGA_BLANK : out std_logic; -- export
VGA_SYNC : out std_logic; -- export
VGA_R : out std_logic_vector(9 downto 0); -- export
VGA_G : out std_logic_vector(9 downto 0); -- export
VGA_B : out std_logic_vector(9 downto 0) -- export
);
end component Video_System_VGA_Controller;
component Video_System_Video_In_Decoder is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0); -- data
TD_CLK27 : in std_logic := 'X'; -- export
TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
TD_HS : in std_logic := 'X'; -- export
TD_VS : in std_logic := 'X'; -- export
TD_RESET : out std_logic; -- export
overflow_flag : out std_logic -- export
);
end component Video_System_Video_In_Decoder;
component Video_System_Chroma_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Video_System_Chroma_Resampler;
component Video_System_Color_Space_Converter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Video_System_Color_Space_Converter;
component Video_System_Video_RGB_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Video_RGB_Resampler;
component Video_System_Video_Clipper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_data : out std_logic_vector(15 downto 0); -- data
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic -- valid
);
end component Video_System_Video_Clipper;
component Video_System_Video_Scaler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Video_Scaler;
component Video_System_Video_DMA is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_startofpacket : in std_logic := 'X'; -- startofpacket
stream_endofpacket : in std_logic := 'X'; -- endofpacket
stream_valid : in std_logic := 'X'; -- valid
stream_ready : out std_logic; -- ready
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
master_address : out std_logic_vector(31 downto 0); -- address
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(15 downto 0) -- writedata
);
end component Video_System_Video_DMA;
component Video_System_AV_Config is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(31 downto 0); -- readdata
waitrequest : out std_logic; -- waitrequest
I2C_SDAT : inout std_logic := 'X'; -- export
I2C_SCLK : out std_logic -- export
);
end component Video_System_AV_Config;
component Video_System_CPU is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(19 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(19 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_begintransfer : in std_logic := 'X'; -- begintransfer
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_select : in std_logic := 'X'; -- chipselect
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component Video_System_CPU;
component Video_System_Clock_Signals is
port (
CLOCK_50 : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sys_clk : out std_logic; -- clk
sys_reset_n : out std_logic; -- reset_n
VGA_CLK : out std_logic -- clk
);
end component Video_System_Clock_Signals;
component Video_System_CPU_instruction_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component Video_System_CPU_instruction_master_translator;
component Video_System_CPU_data_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X' -- debugaccess
);
end component Video_System_CPU_data_master_translator;
component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X' -- lock
);
end component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator;
component Video_System_Video_DMA_avalon_dma_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X') -- writedata
);
end component Video_System_Video_DMA_avalon_dma_master_translator;
component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(104 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent;
component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(104 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent;
component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(86 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent;
component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(86 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent;
component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(105 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(86 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(87 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent;
component Video_System_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router;
component Video_System_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router_001;
component Video_System_addr_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router_002;
component Video_System_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router;
component Video_System_id_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router_002;
component Video_System_id_router_003 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router_003;
component Video_System_burst_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(86 downto 0); -- data
source0_channel : out std_logic_vector(5 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component Video_System_burst_adapter;
component Video_System_rst_controller is
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic -- reset
);
end component Video_System_rst_controller;
component Video_System_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(104 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux;
component Video_System_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(104 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(104 downto 0); -- data
src2_channel : out std_logic_vector(5 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(104 downto 0); -- data
src3_channel : out std_logic_vector(5 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(104 downto 0); -- data
src4_channel : out std_logic_vector(5 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(104 downto 0); -- data
src5_channel : out std_logic_vector(5 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux_001;
component Video_System_cmd_xbar_demux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(86 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux_002;
component Video_System_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_cmd_xbar_mux;
component Video_System_cmd_xbar_mux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_cmd_xbar_mux_002;
component Video_System_rsp_xbar_demux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(86 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(86 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(86 downto 0); -- data
src2_channel : out std_logic_vector(5 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic -- endofpacket
);
end component Video_System_rsp_xbar_demux_002;
component Video_System_rsp_xbar_demux_003 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component Video_System_rsp_xbar_demux_003;
component Video_System_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_rsp_xbar_mux;
component Video_System_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_rsp_xbar_mux_001;
component Video_System_width_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(86 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component Video_System_width_adapter;
component Video_System_width_adapter_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(104 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component Video_System_width_adapter_001;
component Video_System_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component Video_System_irq_mapper;
component video_system_cpu_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component video_system_cpu_jtag_debug_module_translator;
component video_system_onchip_memory_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_onchip_memory_s1_translator;
component video_system_pixel_buffer_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_pixel_buffer_avalon_sram_slave_translator;
component video_system_av_config_avalon_av_config_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_av_config_avalon_av_config_slave_translator;
signal pixel_scaler_avalon_scaler_source_endofpacket : std_logic; -- Pixel_Scaler:stream_out_endofpacket -> Dual_Clock_FIFO:stream_in_endofpacket
signal pixel_scaler_avalon_scaler_source_valid : std_logic; -- Pixel_Scaler:stream_out_valid -> Dual_Clock_FIFO:stream_in_valid
signal pixel_scaler_avalon_scaler_source_startofpacket : std_logic; -- Pixel_Scaler:stream_out_startofpacket -> Dual_Clock_FIFO:stream_in_startofpacket
signal pixel_scaler_avalon_scaler_source_data : std_logic_vector(29 downto 0); -- Pixel_Scaler:stream_out_data -> Dual_Clock_FIFO:stream_in_data
signal pixel_scaler_avalon_scaler_source_ready : std_logic; -- Dual_Clock_FIFO:stream_in_ready -> Pixel_Scaler:stream_out_ready
signal pixel_rgb_resampler_avalon_rgb_source_endofpacket : std_logic; -- Pixel_RGB_Resampler:stream_out_endofpacket -> Pixel_Scaler:stream_in_endofpacket
signal pixel_rgb_resampler_avalon_rgb_source_valid : std_logic; -- Pixel_RGB_Resampler:stream_out_valid -> Pixel_Scaler:stream_in_valid
signal pixel_rgb_resampler_avalon_rgb_source_startofpacket : std_logic; -- Pixel_RGB_Resampler:stream_out_startofpacket -> Pixel_Scaler:stream_in_startofpacket
signal pixel_rgb_resampler_avalon_rgb_source_data : std_logic_vector(29 downto 0); -- Pixel_RGB_Resampler:stream_out_data -> Pixel_Scaler:stream_in_data
signal pixel_rgb_resampler_avalon_rgb_source_ready : std_logic; -- Pixel_Scaler:stream_in_ready -> Pixel_RGB_Resampler:stream_out_ready
signal pixel_buffer_dma_avalon_pixel_source_endofpacket : std_logic; -- Pixel_Buffer_DMA:stream_endofpacket -> Pixel_RGB_Resampler:stream_in_endofpacket
signal pixel_buffer_dma_avalon_pixel_source_valid : std_logic; -- Pixel_Buffer_DMA:stream_valid -> Pixel_RGB_Resampler:stream_in_valid
signal pixel_buffer_dma_avalon_pixel_source_startofpacket : std_logic; -- Pixel_Buffer_DMA:stream_startofpacket -> Pixel_RGB_Resampler:stream_in_startofpacket
signal pixel_buffer_dma_avalon_pixel_source_data : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA:stream_data -> Pixel_RGB_Resampler:stream_in_data
signal pixel_buffer_dma_avalon_pixel_source_ready : std_logic; -- Pixel_RGB_Resampler:stream_in_ready -> Pixel_Buffer_DMA:stream_ready
signal dual_clock_fifo_avalon_dc_buffer_source_endofpacket : std_logic; -- Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
signal dual_clock_fifo_avalon_dc_buffer_source_valid : std_logic; -- Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
signal dual_clock_fifo_avalon_dc_buffer_source_startofpacket : std_logic; -- Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
signal dual_clock_fifo_avalon_dc_buffer_source_data : std_logic_vector(29 downto 0); -- Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
signal dual_clock_fifo_avalon_dc_buffer_source_ready : std_logic; -- VGA_Controller:ready -> Dual_Clock_FIFO:stream_out_ready
signal video_in_decoder_avalon_decoder_source_endofpacket : std_logic; -- Video_In_Decoder:stream_out_endofpacket -> Chroma_Resampler:stream_in_endofpacket
signal video_in_decoder_avalon_decoder_source_valid : std_logic; -- Video_In_Decoder:stream_out_valid -> Chroma_Resampler:stream_in_valid
signal video_in_decoder_avalon_decoder_source_startofpacket : std_logic; -- Video_In_Decoder:stream_out_startofpacket -> Chroma_Resampler:stream_in_startofpacket
signal video_in_decoder_avalon_decoder_source_data : std_logic_vector(15 downto 0); -- Video_In_Decoder:stream_out_data -> Chroma_Resampler:stream_in_data
signal video_in_decoder_avalon_decoder_source_ready : std_logic; -- Chroma_Resampler:stream_in_ready -> Video_In_Decoder:stream_out_ready
signal chroma_resampler_avalon_chroma_source_endofpacket : std_logic; -- Chroma_Resampler:stream_out_endofpacket -> Color_Space_Converter:stream_in_endofpacket
signal chroma_resampler_avalon_chroma_source_valid : std_logic; -- Chroma_Resampler:stream_out_valid -> Color_Space_Converter:stream_in_valid
signal chroma_resampler_avalon_chroma_source_startofpacket : std_logic; -- Chroma_Resampler:stream_out_startofpacket -> Color_Space_Converter:stream_in_startofpacket
signal chroma_resampler_avalon_chroma_source_data : std_logic_vector(23 downto 0); -- Chroma_Resampler:stream_out_data -> Color_Space_Converter:stream_in_data
signal chroma_resampler_avalon_chroma_source_ready : std_logic; -- Color_Space_Converter:stream_in_ready -> Chroma_Resampler:stream_out_ready
signal color_space_converter_avalon_csc_source_endofpacket : std_logic; -- Color_Space_Converter:stream_out_endofpacket -> Video_RGB_Resampler:stream_in_endofpacket
signal color_space_converter_avalon_csc_source_valid : std_logic; -- Color_Space_Converter:stream_out_valid -> Video_RGB_Resampler:stream_in_valid
signal color_space_converter_avalon_csc_source_startofpacket : std_logic; -- Color_Space_Converter:stream_out_startofpacket -> Video_RGB_Resampler:stream_in_startofpacket
signal color_space_converter_avalon_csc_source_data : std_logic_vector(23 downto 0); -- Color_Space_Converter:stream_out_data -> Video_RGB_Resampler:stream_in_data
signal color_space_converter_avalon_csc_source_ready : std_logic; -- Video_RGB_Resampler:stream_in_ready -> Color_Space_Converter:stream_out_ready
signal video_rgb_resampler_avalon_rgb_source_endofpacket : std_logic; -- Video_RGB_Resampler:stream_out_endofpacket -> Video_Clipper:stream_in_endofpacket
signal video_rgb_resampler_avalon_rgb_source_valid : std_logic; -- Video_RGB_Resampler:stream_out_valid -> Video_Clipper:stream_in_valid
signal video_rgb_resampler_avalon_rgb_source_startofpacket : std_logic; -- Video_RGB_Resampler:stream_out_startofpacket -> Video_Clipper:stream_in_startofpacket
signal video_rgb_resampler_avalon_rgb_source_data : std_logic_vector(15 downto 0); -- Video_RGB_Resampler:stream_out_data -> Video_Clipper:stream_in_data
signal video_rgb_resampler_avalon_rgb_source_ready : std_logic; -- Video_Clipper:stream_in_ready -> Video_RGB_Resampler:stream_out_ready
signal video_clipper_avalon_clipper_source_endofpacket : std_logic; -- Video_Clipper:stream_out_endofpacket -> Video_Scaler:stream_in_endofpacket
signal video_clipper_avalon_clipper_source_valid : std_logic; -- Video_Clipper:stream_out_valid -> Video_Scaler:stream_in_valid
signal video_clipper_avalon_clipper_source_startofpacket : std_logic; -- Video_Clipper:stream_out_startofpacket -> Video_Scaler:stream_in_startofpacket
signal video_clipper_avalon_clipper_source_data : std_logic_vector(15 downto 0); -- Video_Clipper:stream_out_data -> Video_Scaler:stream_in_data
signal video_clipper_avalon_clipper_source_ready : std_logic; -- Video_Scaler:stream_in_ready -> Video_Clipper:stream_out_ready
signal video_scaler_avalon_scaler_source_endofpacket : std_logic; -- Video_Scaler:stream_out_endofpacket -> Video_DMA:stream_endofpacket
signal video_scaler_avalon_scaler_source_valid : std_logic; -- Video_Scaler:stream_out_valid -> Video_DMA:stream_valid
signal video_scaler_avalon_scaler_source_startofpacket : std_logic; -- Video_Scaler:stream_out_startofpacket -> Video_DMA:stream_startofpacket
signal video_scaler_avalon_scaler_source_data : std_logic_vector(15 downto 0); -- Video_Scaler:stream_out_data -> Video_DMA:stream_data
signal video_scaler_avalon_scaler_source_ready : std_logic; -- Video_DMA:stream_ready -> Video_Scaler:stream_out_ready
signal clock_signals_sys_clk_clk : std_logic; -- Clock_Signals:sys_clk -> [AV_Config:clk, AV_Config_avalon_av_config_slave_translator:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, CPU:clk, CPU_data_master_translator:clk, CPU_data_master_translator_avalon_universal_master_0_agent:clk, CPU_instruction_master_translator:clk, CPU_instruction_master_translator_avalon_universal_master_0_agent:clk, CPU_jtag_debug_module_translator:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Chroma_Resampler:clk, Color_Space_Converter:clk, Dual_Clock_FIFO:clk_stream_in, Onchip_Memory:clk, Onchip_Memory_s1_translator:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer:clk, Pixel_Buffer_DMA:clk, Pixel_Buffer_DMA_avalon_control_slave_translator:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_RGB_Resampler:clk, Pixel_Scaler:clk, Video_Clipper:clk, Video_DMA:clk, Video_DMA_avalon_dma_control_slave_translator:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Video_DMA_avalon_dma_master_translator:clk, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:clk, Video_In_Decoder:clk, Video_RGB_Resampler:clk, Video_Scaler:clk, addr_router:clk, addr_router_001:clk, addr_router_002:clk, addr_router_003:clk, burst_adapter:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_demux_003:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, irq_mapper:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, width_adapter:clk, width_adapter_001:clk]
signal clock_signals_vga_clk_clk : std_logic; -- Clock_Signals:VGA_CLK -> [Dual_Clock_FIFO:clk_stream_out, VGA_Controller:clk, rst_controller_001:clk]
signal cpu_instruction_master_waitrequest : std_logic; -- CPU_instruction_master_translator:av_waitrequest -> CPU:i_waitrequest
signal cpu_instruction_master_address : std_logic_vector(19 downto 0); -- CPU:i_address -> CPU_instruction_master_translator:av_address
signal cpu_instruction_master_read : std_logic; -- CPU:i_read -> CPU_instruction_master_translator:av_read
signal cpu_instruction_master_readdata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:av_readdata -> CPU:i_readdata
signal cpu_data_master_waitrequest : std_logic; -- CPU_data_master_translator:av_waitrequest -> CPU:d_waitrequest
signal cpu_data_master_writedata : std_logic_vector(31 downto 0); -- CPU:d_writedata -> CPU_data_master_translator:av_writedata
signal cpu_data_master_address : std_logic_vector(19 downto 0); -- CPU:d_address -> CPU_data_master_translator:av_address
signal cpu_data_master_write : std_logic; -- CPU:d_write -> CPU_data_master_translator:av_write
signal cpu_data_master_read : std_logic; -- CPU:d_read -> CPU_data_master_translator:av_read
signal cpu_data_master_readdata : std_logic_vector(31 downto 0); -- CPU_data_master_translator:av_readdata -> CPU:d_readdata
signal cpu_data_master_debugaccess : std_logic; -- CPU:jtag_debug_module_debugaccess_to_roms -> CPU_data_master_translator:av_debugaccess
signal cpu_data_master_byteenable : std_logic_vector(3 downto 0); -- CPU:d_byteenable -> CPU_data_master_translator:av_byteenable
signal pixel_buffer_dma_avalon_pixel_dma_master_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_waitrequest -> Pixel_Buffer_DMA:master_waitrequest
signal pixel_buffer_dma_avalon_pixel_dma_master_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA:master_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_address
signal pixel_buffer_dma_avalon_pixel_dma_master_lock : std_logic; -- Pixel_Buffer_DMA:master_arbiterlock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_lock
signal pixel_buffer_dma_avalon_pixel_dma_master_read : std_logic; -- Pixel_Buffer_DMA:master_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_read
signal pixel_buffer_dma_avalon_pixel_dma_master_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdata -> Pixel_Buffer_DMA:master_readdata
signal pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdatavalid -> Pixel_Buffer_DMA:master_readdatavalid
signal video_dma_avalon_dma_master_waitrequest : std_logic; -- Video_DMA_avalon_dma_master_translator:av_waitrequest -> Video_DMA:master_waitrequest
signal video_dma_avalon_dma_master_writedata : std_logic_vector(15 downto 0); -- Video_DMA:master_writedata -> Video_DMA_avalon_dma_master_translator:av_writedata
signal video_dma_avalon_dma_master_address : std_logic_vector(31 downto 0); -- Video_DMA:master_address -> Video_DMA_avalon_dma_master_translator:av_address
signal video_dma_avalon_dma_master_write : std_logic; -- Video_DMA:master_write -> Video_DMA_avalon_dma_master_translator:av_write
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator:av_writedata -> CPU:jtag_debug_module_writedata
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- CPU_jtag_debug_module_translator:av_address -> CPU:jtag_debug_module_address
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect : std_logic; -- CPU_jtag_debug_module_translator:av_chipselect -> CPU:jtag_debug_module_select
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- CPU_jtag_debug_module_translator:av_write -> CPU:jtag_debug_module_write
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- CPU:jtag_debug_module_readdata -> CPU_jtag_debug_module_translator:av_readdata
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer : std_logic; -- CPU_jtag_debug_module_translator:av_begintransfer -> CPU:jtag_debug_module_begintransfer
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- CPU_jtag_debug_module_translator:av_debugaccess -> CPU:jtag_debug_module_debugaccess
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- CPU_jtag_debug_module_translator:av_byteenable -> CPU:jtag_debug_module_byteenable
signal onchip_memory_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator:av_writedata -> Onchip_Memory:writedata
signal onchip_memory_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- Onchip_Memory_s1_translator:av_address -> Onchip_Memory:address
signal onchip_memory_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- Onchip_Memory_s1_translator:av_chipselect -> Onchip_Memory:chipselect
signal onchip_memory_s1_translator_avalon_anti_slave_0_clken : std_logic; -- Onchip_Memory_s1_translator:av_clken -> Onchip_Memory:clken
signal onchip_memory_s1_translator_avalon_anti_slave_0_write : std_logic; -- Onchip_Memory_s1_translator:av_write -> Onchip_Memory:write
signal onchip_memory_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Onchip_Memory:readdata -> Onchip_Memory_s1_translator:av_readdata
signal onchip_memory_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Onchip_Memory_s1_translator:av_byteenable -> Onchip_Memory:byteenable
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_writedata -> Pixel_Buffer:writedata
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_address -> Pixel_Buffer:address
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:av_write -> Pixel_Buffer:write
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:av_read -> Pixel_Buffer:read
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer:readdata -> Pixel_Buffer_avalon_sram_slave_translator:av_readdata
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- Pixel_Buffer:readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator:av_readdatavalid
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_byteenable -> Pixel_Buffer:byteenable
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- AV_Config:waitrequest -> AV_Config_avalon_av_config_slave_translator:av_waitrequest
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_writedata -> AV_Config:writedata
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_address -> AV_Config:address
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write : std_logic; -- AV_Config_avalon_av_config_slave_translator:av_write -> AV_Config:write
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read : std_logic; -- AV_Config_avalon_av_config_slave_translator:av_read -> AV_Config:read
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- AV_Config:readdata -> AV_Config_avalon_av_config_slave_translator:av_readdata
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_byteenable -> AV_Config:byteenable
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_writedata -> Video_DMA:slave_writedata
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_address -> Video_DMA:slave_address
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:av_write -> Video_DMA:slave_write
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:av_read -> Video_DMA:slave_read
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Video_DMA:slave_readdata -> Video_DMA_avalon_dma_control_slave_translator:av_readdata
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_byteenable -> Video_DMA:slave_byteenable
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_writedata -> Pixel_Buffer_DMA:slave_writedata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_address -> Pixel_Buffer_DMA:slave_address
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_write -> Pixel_Buffer_DMA:slave_write
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_read -> Pixel_Buffer_DMA:slave_read
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA:slave_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator:av_readdata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_byteenable -> Pixel_Buffer_DMA:slave_byteenable
signal cpu_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_instruction_master_translator:uav_waitrequest
signal cpu_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- CPU_instruction_master_translator:uav_burstcount -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal cpu_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:uav_writedata -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal cpu_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:uav_address -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal cpu_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- CPU_instruction_master_translator:uav_lock -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal cpu_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- CPU_instruction_master_translator:uav_write -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal cpu_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- CPU_instruction_master_translator:uav_read -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal cpu_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_instruction_master_translator:uav_readdata
signal cpu_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- CPU_instruction_master_translator:uav_debugaccess -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal cpu_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- CPU_instruction_master_translator:uav_byteenable -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_instruction_master_translator:uav_readdatavalid
signal cpu_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_data_master_translator:uav_waitrequest
signal cpu_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- CPU_data_master_translator:uav_burstcount -> CPU_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal cpu_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- CPU_data_master_translator:uav_writedata -> CPU_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal cpu_data_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- CPU_data_master_translator:uav_address -> CPU_data_master_translator_avalon_universal_master_0_agent:av_address
signal cpu_data_master_translator_avalon_universal_master_0_lock : std_logic; -- CPU_data_master_translator:uav_lock -> CPU_data_master_translator_avalon_universal_master_0_agent:av_lock
signal cpu_data_master_translator_avalon_universal_master_0_write : std_logic; -- CPU_data_master_translator:uav_write -> CPU_data_master_translator_avalon_universal_master_0_agent:av_write
signal cpu_data_master_translator_avalon_universal_master_0_read : std_logic; -- CPU_data_master_translator:uav_read -> CPU_data_master_translator_avalon_universal_master_0_agent:av_read
signal cpu_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- CPU_data_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_data_master_translator:uav_readdata
signal cpu_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- CPU_data_master_translator:uav_debugaccess -> CPU_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal cpu_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- CPU_data_master_translator:uav_byteenable -> CPU_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal cpu_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_data_master_translator:uav_readdatavalid
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_waitrequest
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_burstcount -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_writedata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_writedata
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_address
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_lock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_lock
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_write -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_write
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_read
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdata
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_debugaccess -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_byteenable -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdatavalid
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Video_DMA_avalon_dma_master_translator:uav_waitrequest
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_burstcount -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_writedata -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_writedata
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_address -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_address
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_lock -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_lock
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_write : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_write -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_write
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_read : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_read -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_read
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Video_DMA_avalon_dma_master_translator:uav_readdata
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_debugaccess -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_byteenable -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Video_DMA_avalon_dma_master_translator:uav_readdatavalid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- CPU_jtag_debug_module_translator:uav_waitrequest -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> CPU_jtag_debug_module_translator:uav_burstcount
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> CPU_jtag_debug_module_translator:uav_writedata
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> CPU_jtag_debug_module_translator:uav_address
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> CPU_jtag_debug_module_translator:uav_write
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> CPU_jtag_debug_module_translator:uav_lock
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> CPU_jtag_debug_module_translator:uav_read
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator:uav_readdata -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- CPU_jtag_debug_module_translator:uav_readdatavalid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> CPU_jtag_debug_module_translator:uav_debugaccess
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> CPU_jtag_debug_module_translator:uav_byteenable
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Onchip_Memory_s1_translator:uav_waitrequest -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> Onchip_Memory_s1_translator:uav_burstcount
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> Onchip_Memory_s1_translator:uav_writedata
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> Onchip_Memory_s1_translator:uav_address
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> Onchip_Memory_s1_translator:uav_write
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> Onchip_Memory_s1_translator:uav_lock
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> Onchip_Memory_s1_translator:uav_read
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator:uav_readdata -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Onchip_Memory_s1_translator:uav_readdatavalid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Onchip_Memory_s1_translator:uav_debugaccess
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> Onchip_Memory_s1_translator:uav_byteenable
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:uav_waitrequest -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_avalon_sram_slave_translator:uav_burstcount
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_avalon_sram_slave_translator:uav_writedata
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_avalon_sram_slave_translator:uav_address
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_avalon_sram_slave_translator:uav_write
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_avalon_sram_slave_translator:uav_lock
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_avalon_sram_slave_translator:uav_read
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:uav_readdata -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:uav_readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_avalon_sram_slave_translator:uav_debugaccess
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_avalon_sram_slave_translator:uav_byteenable
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(87 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(87 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- AV_Config_avalon_av_config_slave_translator:uav_waitrequest -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> AV_Config_avalon_av_config_slave_translator:uav_burstcount
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> AV_Config_avalon_av_config_slave_translator:uav_writedata
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_address -> AV_Config_avalon_av_config_slave_translator:uav_address
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_write -> AV_Config_avalon_av_config_slave_translator:uav_write
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_lock -> AV_Config_avalon_av_config_slave_translator:uav_lock
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_read -> AV_Config_avalon_av_config_slave_translator:uav_read
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator:uav_readdata -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- AV_Config_avalon_av_config_slave_translator:uav_readdatavalid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> AV_Config_avalon_av_config_slave_translator:uav_debugaccess
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> AV_Config_avalon_av_config_slave_translator:uav_byteenable
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:uav_waitrequest -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Video_DMA_avalon_dma_control_slave_translator:uav_burstcount
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Video_DMA_avalon_dma_control_slave_translator:uav_writedata
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Video_DMA_avalon_dma_control_slave_translator:uav_address
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Video_DMA_avalon_dma_control_slave_translator:uav_write
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Video_DMA_avalon_dma_control_slave_translator:uav_lock
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Video_DMA_avalon_dma_control_slave_translator:uav_read
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:uav_readdata -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:uav_readdatavalid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Video_DMA_avalon_dma_control_slave_translator:uav_debugaccess
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Video_DMA_avalon_dma_control_slave_translator:uav_byteenable
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_waitrequest -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_burstcount
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_writedata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_address
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_write
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_lock
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_read
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdatavalid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_debugaccess
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_byteenable
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(104 downto 0); -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(104 downto 0); -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> CPU_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(86 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_002:sink_ready -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_ready
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(86 downto 0); -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_003:sink_ready -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(86 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(86 downto 0); -- burst_adapter:source0_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(5 downto 0); -- burst_adapter:source0_channel -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [AV_Config:reset, AV_Config_avalon_av_config_slave_translator:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, CPU_data_master_translator:reset, CPU_data_master_translator_avalon_universal_master_0_agent:reset, CPU_instruction_master_translator:reset, CPU_instruction_master_translator_avalon_universal_master_0_agent:reset, CPU_jtag_debug_module_translator:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Chroma_Resampler:reset, Color_Space_Converter:reset, Dual_Clock_FIFO:reset_stream_in, Onchip_Memory:reset, Onchip_Memory_s1_translator:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer:reset, Pixel_Buffer_DMA:reset, Pixel_Buffer_DMA_avalon_control_slave_translator:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_RGB_Resampler:reset, Pixel_Scaler:reset, Video_Clipper:reset, Video_DMA:reset, Video_DMA_avalon_dma_control_slave_translator:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Video_DMA_avalon_dma_master_translator:reset, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:reset, Video_In_Decoder:reset, Video_RGB_Resampler:reset, Video_Scaler:reset, addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, width_adapter:reset, width_adapter_001:reset]
signal cpu_jtag_debug_module_reset_reset : std_logic; -- CPU:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [Dual_Clock_FIFO:reset_stream_out, VGA_Controller:reset]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> Clock_Signals:reset
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src3_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src3_channel -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src4_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src4_channel -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src5_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src5_channel -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_002_src0_endofpacket : std_logic; -- cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_002_src0_valid : std_logic; -- cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_002_src0_startofpacket : std_logic; -- cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_002_src0_data : std_logic_vector(86 downto 0); -- cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_002_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_002_src0_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_002:src0_ready
signal cmd_xbar_demux_003_src0_endofpacket : std_logic; -- cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_002:sink2_endofpacket
signal cmd_xbar_demux_003_src0_valid : std_logic; -- cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_002:sink2_valid
signal cmd_xbar_demux_003_src0_startofpacket : std_logic; -- cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_002:sink2_startofpacket
signal cmd_xbar_demux_003_src0_data : std_logic_vector(86 downto 0); -- cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_002:sink2_data
signal cmd_xbar_demux_003_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_002:sink2_channel
signal cmd_xbar_demux_003_src0_ready : std_logic; -- cmd_xbar_mux_002:sink2_ready -> cmd_xbar_demux_003:src0_ready
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src1_data -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src1_channel -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_demux_002_src2_endofpacket : std_logic; -- rsp_xbar_demux_002:src2_endofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_demux_002_src2_valid : std_logic; -- rsp_xbar_demux_002:src2_valid -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_demux_002_src2_startofpacket : std_logic; -- rsp_xbar_demux_002:src2_startofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_demux_002_src2_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src2_data -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_demux_002_src2_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src2_channel -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(104 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(5 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(104 downto 0); -- rsp_xbar_mux:src_data -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(5 downto 0); -- rsp_xbar_mux:src_channel -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(104 downto 0); -- addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
signal addr_router_001_src_channel : std_logic_vector(5 downto 0); -- addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
signal addr_router_001_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(104 downto 0); -- rsp_xbar_mux_001:src_data -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(5 downto 0); -- rsp_xbar_mux_001:src_channel -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
signal addr_router_002_src_endofpacket : std_logic; -- addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
signal addr_router_002_src_valid : std_logic; -- addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
signal addr_router_002_src_startofpacket : std_logic; -- addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
signal addr_router_002_src_data : std_logic_vector(86 downto 0); -- addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
signal addr_router_002_src_channel : std_logic_vector(5 downto 0); -- addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
signal addr_router_002_src_ready : std_logic; -- cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
signal rsp_xbar_demux_002_src1_ready : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src1_ready
signal addr_router_003_src_endofpacket : std_logic; -- addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
signal addr_router_003_src_valid : std_logic; -- addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
signal addr_router_003_src_startofpacket : std_logic; -- addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
signal addr_router_003_src_data : std_logic_vector(86 downto 0); -- addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
signal addr_router_003_src_channel : std_logic_vector(5 downto 0); -- addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
signal addr_router_003_src_ready : std_logic; -- cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
signal rsp_xbar_demux_002_src2_ready : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src2_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(104 downto 0); -- cmd_xbar_mux:src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux:src_channel -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(104 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(5 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(104 downto 0); -- cmd_xbar_mux_001:src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux_001:src_channel -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal id_router_001_src_data : std_logic_vector(104 downto 0); -- id_router_001:src_data -> rsp_xbar_demux_001:sink_data
signal id_router_001_src_channel : std_logic_vector(5 downto 0); -- id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
signal id_router_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> burst_adapter:sink0_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> burst_adapter:sink0_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> burst_adapter:sink0_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(86 downto 0); -- cmd_xbar_mux_002:src_data -> burst_adapter:sink0_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux_002:src_channel -> burst_adapter:sink0_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- burst_adapter:sink0_ready -> cmd_xbar_mux_002:src_ready
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal id_router_002_src_data : std_logic_vector(86 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data
signal id_router_002_src_channel : std_logic_vector(5 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
signal cmd_xbar_demux_001_src3_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal id_router_003_src_data : std_logic_vector(104 downto 0); -- id_router_003:src_data -> rsp_xbar_demux_003:sink_data
signal id_router_003_src_channel : std_logic_vector(5 downto 0); -- id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
signal id_router_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
signal cmd_xbar_demux_001_src4_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal id_router_004_src_data : std_logic_vector(104 downto 0); -- id_router_004:src_data -> rsp_xbar_demux_004:sink_data
signal id_router_004_src_channel : std_logic_vector(5 downto 0); -- id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
signal id_router_004_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(104 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(5 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> width_adapter:in_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src2_data -> width_adapter:in_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src2_channel -> width_adapter:in_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_demux_001:src2_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> cmd_xbar_mux_002:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(86 downto 0); -- width_adapter:out_data -> cmd_xbar_mux_002:sink0_data
signal width_adapter_src_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(5 downto 0); -- width_adapter:out_channel -> cmd_xbar_mux_002:sink0_channel
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> width_adapter_001:in_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> width_adapter_001:in_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> width_adapter_001:in_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src0_data -> width_adapter_001:in_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src0_channel -> width_adapter_001:in_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- width_adapter_001:in_ready -> rsp_xbar_demux_002:src0_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_mux_001:sink2_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal width_adapter_001_src_data : std_logic_vector(104 downto 0); -- width_adapter_001:out_data -> rsp_xbar_mux_001:sink2_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(5 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_mux_001:sink2_channel
signal cpu_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> CPU:d_irq
signal reset_n_ports_inv : std_logic; -- reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> CPU:reset_n
begin
onchip_memory : component Video_System_Onchip_Memory
port map (
clk => clock_signals_sys_clk_clk, -- clk1.clk
address => onchip_memory_s1_translator_avalon_anti_slave_0_address, -- s1.address
chipselect => onchip_memory_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
clken => onchip_memory_s1_translator_avalon_anti_slave_0_clken, -- .clken
readdata => onchip_memory_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
write => onchip_memory_s1_translator_avalon_anti_slave_0_write, -- .write
writedata => onchip_memory_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset -- reset1.reset
);
dual_clock_fifo : component Video_System_Dual_Clock_FIFO
port map (
clk_stream_in => clock_signals_sys_clk_clk, -- clock_stream_in.clk
reset_stream_in => rst_controller_reset_out_reset, -- clock_stream_in_reset.reset
clk_stream_out => clock_signals_vga_clk_clk, -- clock_stream_out.clk
reset_stream_out => rst_controller_001_reset_out_reset, -- clock_stream_out_reset.reset
stream_in_ready => pixel_scaler_avalon_scaler_source_ready, -- avalon_dc_buffer_sink.ready
stream_in_startofpacket => pixel_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_in_endofpacket => pixel_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_scaler_avalon_scaler_source_valid, -- .valid
stream_in_data => pixel_scaler_avalon_scaler_source_data, -- .data
stream_out_ready => dual_clock_fifo_avalon_dc_buffer_source_ready, -- avalon_dc_buffer_source.ready
stream_out_startofpacket => dual_clock_fifo_avalon_dc_buffer_source_startofpacket, -- .startofpacket
stream_out_endofpacket => dual_clock_fifo_avalon_dc_buffer_source_endofpacket, -- .endofpacket
stream_out_valid => dual_clock_fifo_avalon_dc_buffer_source_valid, -- .valid
stream_out_data => dual_clock_fifo_avalon_dc_buffer_source_data -- .data
);
pixel_buffer : component Video_System_Pixel_Buffer
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => SRAM_DQ_to_and_from_the_Pixel_Buffer, -- external_interface.export
SRAM_ADDR => SRAM_ADDR_from_the_Pixel_Buffer, -- .export
SRAM_LB_N => SRAM_LB_N_from_the_Pixel_Buffer, -- .export
SRAM_UB_N => SRAM_UB_N_from_the_Pixel_Buffer, -- .export
SRAM_CE_N => SRAM_CE_N_from_the_Pixel_Buffer, -- .export
SRAM_OE_N => SRAM_OE_N_from_the_Pixel_Buffer, -- .export
SRAM_WE_N => SRAM_WE_N_from_the_Pixel_Buffer, -- .export
address => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
pixel_buffer_dma : component Video_System_Pixel_Buffer_DMA
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
master_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid, -- avalon_pixel_dma_master.readdatavalid
master_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_waitrequest, -- .waitrequest
master_address => pixel_buffer_dma_avalon_pixel_dma_master_address, -- .address
master_arbiterlock => pixel_buffer_dma_avalon_pixel_dma_master_lock, -- .lock
master_read => pixel_buffer_dma_avalon_pixel_dma_master_read, -- .read
master_readdata => pixel_buffer_dma_avalon_pixel_dma_master_readdata, -- .readdata
slave_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address, -- avalon_control_slave.address
slave_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
slave_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read, -- .read
slave_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write, -- .write
slave_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
slave_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
stream_ready => pixel_buffer_dma_avalon_pixel_source_ready, -- avalon_pixel_source.ready
stream_startofpacket => pixel_buffer_dma_avalon_pixel_source_startofpacket, -- .startofpacket
stream_endofpacket => pixel_buffer_dma_avalon_pixel_source_endofpacket, -- .endofpacket
stream_valid => pixel_buffer_dma_avalon_pixel_source_valid, -- .valid
stream_data => pixel_buffer_dma_avalon_pixel_source_data -- .data
);
pixel_rgb_resampler : component Video_System_Pixel_RGB_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => pixel_buffer_dma_avalon_pixel_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => pixel_buffer_dma_avalon_pixel_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_buffer_dma_avalon_pixel_source_valid, -- .valid
stream_in_ready => pixel_buffer_dma_avalon_pixel_source_ready, -- .ready
stream_in_data => pixel_buffer_dma_avalon_pixel_source_data, -- .data
stream_out_ready => pixel_rgb_resampler_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => pixel_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => pixel_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => pixel_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_out_data => pixel_rgb_resampler_avalon_rgb_source_data -- .data
);
pixel_scaler : component Video_System_Pixel_Scaler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => pixel_rgb_resampler_avalon_rgb_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => pixel_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_in_ready => pixel_rgb_resampler_avalon_rgb_source_ready, -- .ready
stream_in_data => pixel_rgb_resampler_avalon_rgb_source_data, -- .data
stream_out_ready => pixel_scaler_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => pixel_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => pixel_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => pixel_scaler_avalon_scaler_source_valid, -- .valid
stream_out_data => pixel_scaler_avalon_scaler_source_data -- .data
);
vga_controller : component Video_System_VGA_Controller
port map (
clk => clock_signals_vga_clk_clk, -- clock_reset.clk
reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
data => dual_clock_fifo_avalon_dc_buffer_source_data, -- avalon_vga_sink.data
startofpacket => dual_clock_fifo_avalon_dc_buffer_source_startofpacket, -- .startofpacket
endofpacket => dual_clock_fifo_avalon_dc_buffer_source_endofpacket, -- .endofpacket
valid => dual_clock_fifo_avalon_dc_buffer_source_valid, -- .valid
ready => dual_clock_fifo_avalon_dc_buffer_source_ready, -- .ready
VGA_CLK => VGA_CLK_from_the_VGA_Controller, -- external_interface.export
VGA_HS => VGA_HS_from_the_VGA_Controller, -- .export
VGA_VS => VGA_VS_from_the_VGA_Controller, -- .export
VGA_BLANK => VGA_BLANK_from_the_VGA_Controller, -- .export
VGA_SYNC => VGA_SYNC_from_the_VGA_Controller, -- .export
VGA_R => VGA_R_from_the_VGA_Controller, -- .export
VGA_G => VGA_G_from_the_VGA_Controller, -- .export
VGA_B => VGA_B_from_the_VGA_Controller -- .export
);
video_in_decoder : component Video_System_Video_In_Decoder
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_out_ready => video_in_decoder_avalon_decoder_source_ready, -- avalon_decoder_source.ready
stream_out_startofpacket => video_in_decoder_avalon_decoder_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_in_decoder_avalon_decoder_source_endofpacket, -- .endofpacket
stream_out_valid => video_in_decoder_avalon_decoder_source_valid, -- .valid
stream_out_data => video_in_decoder_avalon_decoder_source_data, -- .data
TD_CLK27 => TD_CLK27_to_the_Video_In_Decoder, -- external_interface.export
TD_DATA => TD_DATA_to_the_Video_In_Decoder, -- .export
TD_HS => TD_HS_to_the_Video_In_Decoder, -- .export
TD_VS => TD_VS_to_the_Video_In_Decoder, -- .export
TD_RESET => TD_RESET_from_the_Video_In_Decoder, -- .export
overflow_flag => overflow_flag_from_the_Video_In_Decoder -- .export
);
chroma_resampler : component Video_System_Chroma_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => video_in_decoder_avalon_decoder_source_startofpacket, -- avalon_chroma_sink.startofpacket
stream_in_endofpacket => video_in_decoder_avalon_decoder_source_endofpacket, -- .endofpacket
stream_in_valid => video_in_decoder_avalon_decoder_source_valid, -- .valid
stream_in_ready => video_in_decoder_avalon_decoder_source_ready, -- .ready
stream_in_data => video_in_decoder_avalon_decoder_source_data, -- .data
stream_out_ready => chroma_resampler_avalon_chroma_source_ready, -- avalon_chroma_source.ready
stream_out_startofpacket => chroma_resampler_avalon_chroma_source_startofpacket, -- .startofpacket
stream_out_endofpacket => chroma_resampler_avalon_chroma_source_endofpacket, -- .endofpacket
stream_out_valid => chroma_resampler_avalon_chroma_source_valid, -- .valid
stream_out_data => chroma_resampler_avalon_chroma_source_data -- .data
);
color_space_converter : component Video_System_Color_Space_Converter
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => chroma_resampler_avalon_chroma_source_startofpacket, -- avalon_csc_sink.startofpacket
stream_in_endofpacket => chroma_resampler_avalon_chroma_source_endofpacket, -- .endofpacket
stream_in_valid => chroma_resampler_avalon_chroma_source_valid, -- .valid
stream_in_ready => chroma_resampler_avalon_chroma_source_ready, -- .ready
stream_in_data => chroma_resampler_avalon_chroma_source_data, -- .data
stream_out_ready => color_space_converter_avalon_csc_source_ready, -- avalon_csc_source.ready
stream_out_startofpacket => color_space_converter_avalon_csc_source_startofpacket, -- .startofpacket
stream_out_endofpacket => color_space_converter_avalon_csc_source_endofpacket, -- .endofpacket
stream_out_valid => color_space_converter_avalon_csc_source_valid, -- .valid
stream_out_data => color_space_converter_avalon_csc_source_data -- .data
);
video_rgb_resampler : component Video_System_Video_RGB_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => color_space_converter_avalon_csc_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => color_space_converter_avalon_csc_source_endofpacket, -- .endofpacket
stream_in_valid => color_space_converter_avalon_csc_source_valid, -- .valid
stream_in_ready => color_space_converter_avalon_csc_source_ready, -- .ready
stream_in_data => color_space_converter_avalon_csc_source_data, -- .data
stream_out_ready => video_rgb_resampler_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => video_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => video_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_out_data => video_rgb_resampler_avalon_rgb_source_data -- .data
);
video_clipper : component Video_System_Video_Clipper
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_data => video_rgb_resampler_avalon_rgb_source_data, -- avalon_clipper_sink.data
stream_in_startofpacket => video_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_in_endofpacket => video_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => video_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_in_ready => video_rgb_resampler_avalon_rgb_source_ready, -- .ready
stream_out_ready => video_clipper_avalon_clipper_source_ready, -- avalon_clipper_source.ready
stream_out_data => video_clipper_avalon_clipper_source_data, -- .data
stream_out_startofpacket => video_clipper_avalon_clipper_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_clipper_avalon_clipper_source_endofpacket, -- .endofpacket
stream_out_valid => video_clipper_avalon_clipper_source_valid -- .valid
);
video_scaler : component Video_System_Video_Scaler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => video_clipper_avalon_clipper_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => video_clipper_avalon_clipper_source_endofpacket, -- .endofpacket
stream_in_valid => video_clipper_avalon_clipper_source_valid, -- .valid
stream_in_ready => video_clipper_avalon_clipper_source_ready, -- .ready
stream_in_data => video_clipper_avalon_clipper_source_data, -- .data
stream_out_ready => video_scaler_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => video_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => video_scaler_avalon_scaler_source_valid, -- .valid
stream_out_data => video_scaler_avalon_scaler_source_data -- .data
);
video_dma : component Video_System_Video_DMA
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_data => video_scaler_avalon_scaler_source_data, -- avalon_dma_sink.data
stream_startofpacket => video_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_endofpacket => video_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_valid => video_scaler_avalon_scaler_source_valid, -- .valid
stream_ready => video_scaler_avalon_scaler_source_ready, -- .ready
slave_address => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address, -- avalon_dma_control_slave.address
slave_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
slave_read => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read, -- .read
slave_write => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write, -- .write
slave_writedata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
slave_readdata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
master_address => video_dma_avalon_dma_master_address, -- avalon_dma_master.address
master_waitrequest => video_dma_avalon_dma_master_waitrequest, -- .waitrequest
master_write => video_dma_avalon_dma_master_write, -- .write
master_writedata => video_dma_avalon_dma_master_writedata -- .writedata
);
av_config : component Video_System_AV_Config
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address, -- avalon_av_config_slave.address
byteenable => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read, -- .read
write => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
waitrequest => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
I2C_SDAT => I2C_SDAT_to_and_from_the_AV_Config, -- external_interface.export
I2C_SCLK => I2C_SCLK_from_the_AV_Config -- .export
);
cpu : component Video_System_CPU
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => cpu_data_master_address, -- data_master.address
d_byteenable => cpu_data_master_byteenable, -- .byteenable
d_read => cpu_data_master_read, -- .read
d_readdata => cpu_data_master_readdata, -- .readdata
d_waitrequest => cpu_data_master_waitrequest, -- .waitrequest
d_write => cpu_data_master_write, -- .write
d_writedata => cpu_data_master_writedata, -- .writedata
jtag_debug_module_debugaccess_to_roms => cpu_data_master_debugaccess, -- .debugaccess
i_address => cpu_instruction_master_address, -- instruction_master.address
i_read => cpu_instruction_master_read, -- .read
i_readdata => cpu_instruction_master_readdata, -- .readdata
i_waitrequest => cpu_instruction_master_waitrequest, -- .waitrequest
d_irq => cpu_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => cpu_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => cpu_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_begintransfer => cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
jtag_debug_module_byteenable => cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_readdata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_select => cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
jtag_debug_module_write => cpu_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
clock_signals : component Video_System_Clock_Signals
port map (
CLOCK_50 => clk_0, -- clk_in_primary.clk
reset => rst_controller_002_reset_out_reset, -- clk_in_primary_reset.reset
sys_clk => clock_signals_sys_clk_clk, -- sys_clk.clk
sys_reset_n => open, -- sys_clk_reset.reset_n
VGA_CLK => clock_signals_vga_clk_clk -- vga_clk.clk
);
cpu_instruction_master_translator : component Video_System_CPU_instruction_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => cpu_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => cpu_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => cpu_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => cpu_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => cpu_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => cpu_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => cpu_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => cpu_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => cpu_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => cpu_instruction_master_waitrequest, -- .waitrequest
av_read => cpu_instruction_master_read, -- .read
av_readdata => cpu_instruction_master_readdata -- .readdata
);
cpu_data_master_translator : component Video_System_CPU_data_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => cpu_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => cpu_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => cpu_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => cpu_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => cpu_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => cpu_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => cpu_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => cpu_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => cpu_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => cpu_data_master_waitrequest, -- .waitrequest
av_byteenable => cpu_data_master_byteenable, -- .byteenable
av_read => cpu_data_master_read, -- .read
av_readdata => cpu_data_master_readdata, -- .readdata
av_write => cpu_data_master_write, -- .write
av_writedata => cpu_data_master_writedata, -- .writedata
av_debugaccess => cpu_data_master_debugaccess -- .debugaccess
);
pixel_buffer_dma_avalon_pixel_dma_master_translator : component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read, -- .read
uav_write => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => pixel_buffer_dma_avalon_pixel_dma_master_address, -- avalon_anti_master_0.address
av_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_waitrequest, -- .waitrequest
av_read => pixel_buffer_dma_avalon_pixel_dma_master_read, -- .read
av_readdata => pixel_buffer_dma_avalon_pixel_dma_master_readdata, -- .readdata
av_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid, -- .readdatavalid
av_lock => pixel_buffer_dma_avalon_pixel_dma_master_lock -- .lock
);
video_dma_avalon_dma_master_translator : component Video_System_Video_DMA_avalon_dma_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => video_dma_avalon_dma_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => video_dma_avalon_dma_master_translator_avalon_universal_master_0_read, -- .read
uav_write => video_dma_avalon_dma_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => video_dma_avalon_dma_master_address, -- avalon_anti_master_0.address
av_waitrequest => video_dma_avalon_dma_master_waitrequest, -- .waitrequest
av_write => video_dma_avalon_dma_master_write, -- .write
av_writedata => video_dma_avalon_dma_master_writedata -- .writedata
);
cpu_jtag_debug_module_translator : component video_system_cpu_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => cpu_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => cpu_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_readdata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
av_byteenable => cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_debugaccess => cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
onchip_memory_s1_translator : component video_system_onchip_memory_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
pixel_buffer_avalon_sram_slave_translator : component video_system_pixel_buffer_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
av_config_avalon_av_config_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
video_dma_avalon_dma_control_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
pixel_buffer_dma_avalon_control_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
cpu_instruction_master_translator_avalon_universal_master_0_agent : component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => cpu_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => cpu_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => cpu_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => cpu_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => cpu_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => cpu_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => cpu_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => cpu_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => cpu_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => cpu_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready -- .ready
);
cpu_data_master_translator_avalon_universal_master_0_agent : component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => cpu_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => cpu_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => cpu_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => cpu_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => cpu_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => cpu_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => cpu_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => cpu_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => cpu_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => cpu_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => cpu_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => cpu_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_001_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_001_src_data, -- .data
rp_channel => rsp_xbar_mux_001_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_001_src_ready -- .ready
);
pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent : component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address, -- av.address
av_write => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write, -- .write
av_read => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_demux_002_src1_valid, -- rp.valid
rp_data => rsp_xbar_demux_002_src1_data, -- .data
rp_channel => rsp_xbar_demux_002_src1_channel, -- .channel
rp_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_demux_002_src1_ready -- .ready
);
video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent : component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => video_dma_avalon_dma_master_translator_avalon_universal_master_0_address, -- av.address
av_write => video_dma_avalon_dma_master_translator_avalon_universal_master_0_write, -- .write
av_read => video_dma_avalon_dma_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_demux_002_src2_valid, -- rp.valid
rp_data => rsp_xbar_demux_002_src2_data, -- .data
rp_channel => rsp_xbar_demux_002_src2_channel, -- .channel
rp_startofpacket => rsp_xbar_demux_002_src2_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_demux_002_src2_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_demux_002_src2_ready -- .ready
);
cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
onchip_memory_s1_translator_avalon_universal_slave_0_agent : component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_001_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_001_src_valid, -- .valid
cp_data => cmd_xbar_mux_001_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_001_src_channel, -- .channel
rf_sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent : component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src3_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src3_valid, -- .valid
cp_data => cmd_xbar_demux_001_src3_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src3_channel, -- .channel
rf_sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent : component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src4_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src4_valid, -- .valid
cp_data => cmd_xbar_demux_001_src4_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src4_channel, -- .channel
rf_sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent : component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
addr_router : component Video_System_addr_router
port map (
sink_ready => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component Video_System_addr_router_001
port map (
sink_ready => cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => cpu_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
addr_router_002 : component Video_System_addr_router_002
port map (
sink_ready => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_002_src_ready, -- src.ready
src_valid => addr_router_002_src_valid, -- .valid
src_data => addr_router_002_src_data, -- .data
src_channel => addr_router_002_src_channel, -- .channel
src_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_002_src_endofpacket -- .endofpacket
);
addr_router_003 : component Video_System_addr_router_002
port map (
sink_ready => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_003_src_ready, -- src.ready
src_valid => addr_router_003_src_valid, -- .valid
src_data => addr_router_003_src_data, -- .data
src_channel => addr_router_003_src_channel, -- .channel
src_startofpacket => addr_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_003_src_endofpacket -- .endofpacket
);
id_router : component Video_System_id_router
port map (
sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component Video_System_id_router
port map (
sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component Video_System_id_router_002
port map (
sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component Video_System_id_router_003
port map (
sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component Video_System_id_router_003
port map (
sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component Video_System_id_router_003
port map (
sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
burst_adapter : component Video_System_burst_adapter
port map (
clk => clock_signals_sys_clk_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => cmd_xbar_mux_002_src_valid, -- sink0.valid
sink0_data => cmd_xbar_mux_002_src_data, -- .data
sink0_channel => cmd_xbar_mux_002_src_channel, -- .channel
sink0_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_mux_002_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
rst_controller : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clock_signals_sys_clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset -- reset_out.reset
);
rst_controller_001 : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clock_signals_vga_clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset -- reset_out.reset
);
rst_controller_002 : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_0, -- clk.clk
reset_out => rst_controller_002_reset_out_reset -- reset_out.reset
);
cmd_xbar_demux : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component Video_System_cmd_xbar_demux_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_001_src_ready, -- sink.ready
sink_channel => addr_router_001_src_channel, -- .channel
sink_data => addr_router_001_src_data, -- .data
sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_001_src_valid, -- .valid
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket -- .endofpacket
);
cmd_xbar_demux_002 : component Video_System_cmd_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_002_src_ready, -- sink.ready
sink_channel => addr_router_002_src_channel, -- .channel
sink_data => addr_router_002_src_data, -- .data
sink_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_002_src_valid, -- .valid
src0_ready => cmd_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_002_src0_valid, -- .valid
src0_data => cmd_xbar_demux_002_src0_data, -- .data
src0_channel => cmd_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_002_src0_endofpacket -- .endofpacket
);
cmd_xbar_demux_003 : component Video_System_cmd_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_003_src_ready, -- sink.ready
sink_channel => addr_router_003_src_channel, -- .channel
sink_data => addr_router_003_src_data, -- .data
sink_startofpacket => addr_router_003_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_003_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_003_src_valid, -- .valid
src0_ready => cmd_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_003_src0_valid, -- .valid
src0_data => cmd_xbar_demux_003_src0_data, -- .data
src0_channel => cmd_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_003_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux : component Video_System_cmd_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component Video_System_cmd_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component Video_System_cmd_xbar_mux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- sink0.ready
sink0_valid => width_adapter_src_valid, -- .valid
sink0_channel => width_adapter_src_channel, -- .channel
sink0_data => width_adapter_src_data, -- .data
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_002_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_002_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_002_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_002_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink2_ready => cmd_xbar_demux_003_src0_ready, -- sink2.ready
sink2_valid => cmd_xbar_demux_003_src0_valid, -- .valid
sink2_channel => cmd_xbar_demux_003_src0_channel, -- .channel
sink2_data => cmd_xbar_demux_003_src0_data, -- .data
sink2_startofpacket => cmd_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink2_endofpacket => cmd_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_001_src_ready, -- sink.ready
sink_channel => id_router_001_src_channel, -- .channel
sink_data => id_router_001_src_data, -- .data
sink_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component Video_System_rsp_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_002_src_ready, -- sink.ready
sink_channel => id_router_002_src_channel, -- .channel
sink_data => id_router_002_src_data, -- .data
sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_002_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
src2_ready => rsp_xbar_demux_002_src2_ready, -- src2.ready
src2_valid => rsp_xbar_demux_002_src2_valid, -- .valid
src2_data => rsp_xbar_demux_002_src2_data, -- .data
src2_channel => rsp_xbar_demux_002_src2_channel, -- .channel
src2_startofpacket => rsp_xbar_demux_002_src2_startofpacket, -- .startofpacket
src2_endofpacket => rsp_xbar_demux_002_src2_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_003_src_ready, -- sink.ready
sink_channel => id_router_003_src_channel, -- .channel
sink_data => id_router_003_src_data, -- .data
sink_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_004_src_ready, -- sink.ready
sink_channel => id_router_004_src_channel, -- .channel
sink_data => id_router_004_src_data, -- .data
sink_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_004_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component Video_System_rsp_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component Video_System_rsp_xbar_mux_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => width_adapter_001_src_ready, -- sink2.ready
sink2_valid => width_adapter_001_src_valid, -- .valid
sink2_channel => width_adapter_001_src_channel, -- .channel
sink2_data => width_adapter_001_src_data, -- .data
sink2_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink2_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
width_adapter : component Video_System_width_adapter
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src2_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src2_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src2_ready, -- .ready
in_data => cmd_xbar_demux_001_src2_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket -- .startofpacket
);
width_adapter_001 : component Video_System_width_adapter_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => rsp_xbar_demux_002_src0_valid, -- sink.valid
in_channel => rsp_xbar_demux_002_src0_channel, -- .channel
in_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
in_ready => rsp_xbar_demux_002_src0_ready, -- .ready
in_data => rsp_xbar_demux_002_src0_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket -- .startofpacket
);
irq_mapper : component Video_System_irq_mapper
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sender_irq => cpu_d_irq_irq -- sender.irq
);
reset_n_ports_inv <= not reset_n;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of Video_System
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a counter an its content. It exists to
/ circumvent the impossibility of reading the attributes of an unconstrained port signal inside the
/ port declaration of an entity. (e.g. to declare an output's size, which depends on an input's
/ size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.counter_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity counter is
generic(
UNSIGNED_2COMP_opt : boolean := true; --default
OVERFLOW_BEHAVIOR_opt : T_overflow_behavior := t_wrap; --default
COUNT_MODE_opt : T_count_mode := t_up; --default
COUNTER_WIDTH_dep : positive_exc := 0; --exception : value not set
TARGET_MODE : boolean; --compulsory
TARGET_dep : integer_exc := integer'low; --exception : value not set
TARGET_WITH_COUNT_opt : boolean_exc := t_exc; --default
TARGET_BLOCKING_opt : boolean_exc := t_exc; --default
USE_SET : boolean; --compulsory
SET_TO_dep : integer_exc := integer'low; --exception : value not set
USE_RESET : boolean; --compulsory
SET_RESET_PRIORITY_opt : T_set_reset_priority := t_reset; --default
USE_LOAD : boolean --compulsory
);
port(
clk : in std_ulogic;
enable : in std_ulogic;
set : in std_ulogic := 'U';
reset : in std_ulogic := 'U';
load : in std_ulogic := 'U';
count_mode_signal : in std_ulogic := 'U';
value_to_load : in std_ulogic_vector:= (counter_CIW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
USE_SET,
SET_TO_dep) downto 1
=> 'U');
count : out std_ulogic_vector;
count_is_target : out std_ulogic_vector
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture counter1 of counter is
constant CHECKS : integer := counter_CHECKS(UNSIGNED_2COMP_opt,
TARGET_MODE,
USE_SET,
USE_RESET,
USE_LOAD,
TARGET_BLOCKING_opt,
TARGET_dep,
SET_TO_dep,
COUNTER_WIDTH_dep);
begin
counter_core1:
entity work.counter_core
generic map(
UNSIGNED_2COMP_opt => UNSIGNED_2COMP_opt,
OVERFLOW_BEHAVIOR_opt => OVERFLOW_BEHAVIOR_opt,
COUNT_MODE_opt => COUNT_MODE_opt,
COUNTER_WIDTH_dep => COUNTER_WIDTH_dep,
TARGET_MODE => TARGET_MODE,
TARGET_dep => TARGET_dep,
TARGET_WITH_COUNT_opt => TARGET_WITH_COUNT_opt,
TARGET_BLOCKING_opt => TARGET_BLOCKING_opt,
USE_SET => USE_SET,
SET_TO_dep => SET_TO_dep,
USE_RESET => USE_RESET,
SET_RESET_PRIORITY_opt => SET_RESET_PRIORITY_opt,
USE_LOAD => USE_LOAD
)
port map(
clk => clk,
enable => enable,
count_mode_signal => count_mode_signal,
set => set,
reset => reset,
load => load,
value_to_load => value_to_load,
count => count,
count_is_target => count_is_target
);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity core is
end core;
architecture BEHAVIOR of core is
component clock is
port(
pulse : out std_logic
);
end component;
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end component;
component bB is
port(
S_GRB, S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0)
);
end component;
component bC is
port(
S_BUS_C : inout std_logic_vector(15 downto 0)
);
end component;
component busA is
port(
clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(15 downto 0)
);
end component;
component csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end component;
component fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end component;
component gr is
port(
clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(15 downto 0)
);
end component;
component inst is
port(
clock : in std_logic;
busA : in std_logic_vector(15 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end component;
component MAR is
port(
clk, lat : in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0)
);
end component;
component mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end component;
component mem is
port(
clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0)
);
end component;
component pr is
port(
clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0)
);
end component;
-- clock
signal pulse : std_logic;
-- alu
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
-- bB
signal busb_alu : std_logic_vector(15 downto 0);
-- bC
signal alu_busc_others : std_logic_vector(15 downto 0);
-- busA
signal busa_alu_ir: std_logic_vector(15 downto 0);
-- csgc
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
-- fr
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
-- gr
signal gr_busa : std_logic_vector(15 downto 0);
signal gr_busb : std_logic_vector(15 downto 0);
signal GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : std_logic_vector(15 downto 0);
-- inst
signal ir_csgc : std_logic_vector(15 downto 0);
-- MAR
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
-- mdr
signal mdr_busab_mem : std_logic_vector(15 downto 0);
-- memory
signal mem_mdr : std_logic_vector(15 downto 0);
-- pr
signal pr_busb : std_logic_vector(15 downto 0);
begin
clock_a : clock port map(
pulse => pulse
);
alu_a : alu port map(
func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others
);
bB_a : bB port map(
S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu
);
-- bC_a : bC port map(
-- S_BUS_C => alu_busc_others
-- );
busA_a : busA port map(
clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir
);
csgc_a : csgc port map(
clk => pulse,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView
);
fr_a : fr port map(
clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o
);
gr_a : gr port map(
clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View, GR1_View => GR1_View, GR2_View => GR2_View, GR3_View => GR3_View,
GR4_View => GR4_View, GR5_View => GR5_View, GR6_View => GR6_View, GR7_View => GR7_View,
GR8_View => GR8_View, GR9_View => GR9_View, GR10_View => GR10_View, GR11_View => GR11_View,
GR12_View => GR12_View, GR13_View => GR13_View, GR14_View => GR14_View, GR15_View => GR15_View
);
inst_a : inst port map(
clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc
);
MAR_a : MAR port map(
clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem
);
mdr_a : mdr port map(
clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem
);
mem_a : mem port map(
clk => pulse,
read => csgc_mem_read,
write => csgc_mem_write,
S_MAR_F => mar_mem,
S_MDR_F => mdr_busab_mem,
data => mem_mdr
);
pr_a : pr port map(
clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb
);
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port(
operand0: in unsigned(15 downto 0);
operand1: in unsigned(15 downto 0);
operation: in unsigned(3 downto 0);
alu_out: out unsigned(15 downto 0);
c_flag: out std_logic; --carry flag
z_flag: out std_logic; --zero flag
n_flag: out std_logic; --negative flag
lt_flag: out std_logic --overflow flag
);
end entity;
architecture a_alu of alu is
component mux4x1 is
port(
in0: in unsigned(15 downto 0);
in1: in unsigned(15 downto 0);
in2: in unsigned(15 downto 0);
in3: in unsigned(15 downto 0);
sel: in unsigned(3 downto 0);
out0: out unsigned(15 downto 0)
);
end component;
component arithmetic_circuit is
port(
a: in unsigned(15 downto 0);
b: in unsigned(15 downto 0);
sum: out unsigned(15 downto 0);
sub: out unsigned(15 downto 0);
slt: out unsigned(15 downto 0);
sneg: out unsigned(15 downto 0)
);
end component;
signal sum_sig, sub_sig, slt_sig, sneg_sig: unsigned(15 downto 0);
signal A_17bits_sig, B_17bits_sig,sum_17bits_sig: unsigned(16 downto 0);
signal alu_out_sig: unsigned(15 downto 0);
begin
A_17bits_sig <= "0"&operand0 when operand0(15)='0' else
"1"&operand0 when operand0(15)='1';
B_17bits_sig <= "0"&operand1 when operand1(15)='0' else
"1"&operand1 when operand1(15)='1';
sum_17bits_sig <= A_17bits_sig + B_17bits_sig;
c_flag <= sum_17bits_sig(16) when operation="0001" else
'1' when operation="0010" and operand1 <= operand0 else
'0';
z_flag <= '1' when alu_out_sig="0000000000000000" else '0';
n_flag <= '1' when alu_out_sig(15)='1' else '0';
lt_flag <= '1' when slt_sig="0000000000000001" else '0';
alu_out <= alu_out_sig;
alu_mux: mux4x1 port map(in0=>sum_sig,in1=>sub_sig,in2=>slt_sig,in3=>sneg_sig,sel=>operation,out0=>alu_out_sig);
alu_arithmetic_circuit: arithmetic_circuit port map(a=>operand0,b=>operand1,sum=>sum_sig,sub=>sub_sig,slt=>slt_sig,sneg=>sneg_sig);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
type t is (one, zero);
signal r : t;
begin
q <= '1' when r = one else '0';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= zero;
else
case r is
when zero => r <= one;
when others => r <= zero;
end case;
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
type t is (one, zero);
signal r : t;
begin
q <= '1' when r = one else '0';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= zero;
else
case r is
when zero => r <= one;
when others => r <= zero;
end case;
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
type t is (one, zero);
signal r : t;
begin
q <= '1' when r = one else '0';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= zero;
else
case r is
when zero => r <= one;
when others => r <= zero;
end case;
end if;
end if;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity fsm_timer_tb is
end entity fsm_timer_tb;
--------------------------------------
architecture circuit of fsm_timer_tb is
-- dut declaration
component simple_car_alarm is
port (
clk, rst, remote, sensors: in std_logic;
siren: out std_logic);
end component simple_car_alarm;
-- signal declaration
signal clk_tb: std_logic := '0';
signal rst_tb, remote_tb, sensors_tb: std_logic;
signal siren_tb: std_logic;
begin
-- dut instantiation
dut: simple_car_alarm port map (
clk => clk_tb,
rst => rst_tb,
remote => remote_tb,
sensors => sensors_tb,
siren => siren_tb
);
-- stimuli generation
-- clk
clk_tb <= not clk_tb after 20 ns;
-- rst
rst_tb <= '1', '0' after 40 ns;
-- remote
remote_tb <= '0', '1' after 160 ns, '0' after 200 ns, '1' after 240 ns, '0' after 320 ns, '1' after 400 ns, '0' after 480 ns, '1' after 680 ns, '0' after 800 ns;
-- sensors
sensors_tb <= '0', '1' after 560 ns, '0' after 640 ns;
-- output comparison check
--
-- process
-- --declarativepart
-- begin
--
-- -- 0 ns = disarmed
-- assert pr_state = disarmed
-- report "error initial state not disarmed"
-- severity failure;
--
--
-- -- 180 ns = armed
--
-- wait for 180 ns;
-- assert pr_state = armed
-- report "error state not armed"
-- severity failure;
--
--
-- -- 260 ns = disarmed
-- wait for 80 ns;
--
-- assert pr_state = disarmed
-- report "error state not disarmed"
-- severity failure;
--
--
-- -- 420 ns = armed
-- wait for 160 ns;
--
-- assert pr_state = armed
-- report "error state not armed"
-- severity failure;
--
-- -- 580 ns = intrusion
-- wait for 160 ns;
--
-- assert pr_state = intrusion
-- report "error state not intrusion"
-- severity failure;
--
-- -- 700 ns = intrusion
-- wait for 120 ns;
--
-- assert pr_state = disarmed
-- report "error state not intrusion"
-- severity failure;
--
--
-- -- testbench passed
-- assert false
-- report "testbench passed"
-- severity note;
--
-- -- wait forever
-- wait;
--
-- end process;
end architecture circuit;
|
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
clock_en : in std_logic; -- for counters and stuff
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"01AA";
signal pio_i : pio_t;
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_latch : std_logic_vector(7 downto 0) := latch_reset_pattern(7 downto 0);
signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal pb_latch_ready : std_logic := '0';
signal pa_latch_ready : std_logic := '0';
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d, ca2_d : std_logic;
signal cb1_d, cb2_d : std_logic;
signal set_ca2_low : std_logic;
signal set_cb2_low : std_logic;
begin
irq <= irq_out;
irq_out <= '0' when (irq_flags and irq_mask) = "0000000" else '1';
write_t1c_h <= '1' when addr = X"5" and wen='1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' else '0';
-- input latches
ira <= port_a_i when pa_latch_ready='0';
irb <= port_b_i when pb_latch_ready='0';
pa_latch_ready <= '1' when (ca1_event='1') and (pa_latch_en='1') and (pa_latch_ready='0') else
'0' when (pa_latch_en='0') or (ren='1' and addr=X"1");
pb_latch_ready <= '1' when (cb1_event='1') and (pb_latch_en='1') and (pb_latch_ready='0') else
'0' when (pb_latch_en='0') or (ren='1' and addr=X"0");
ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select);
ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select);
cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select);
cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d <= ca1_c;
ca2_d <= ca2_c;
cb1_d <= cb1_c;
cb2_d <= cb2_c;
-- CA2 output logic
case ca2_out_mode is
when "00" =>
if ca1_event='1' then
ca2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"1" then
ca2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
ca2_o <= not set_ca2_low;
set_ca2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"1" then
if clock_en='1' then
ca2_o <= '0';
else
set_ca2_low <= '1';
end if;
end if;
when "10" =>
ca2_o <= '0';
when "11" =>
ca2_o <= '1';
when others =>
null;
end case;
-- CB2 output logic
case cb2_out_mode is
when "00" =>
if cb1_event='1' then
hs_cb2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"0" then
hs_cb2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
hs_cb2_o <= not set_cb2_low;
set_cb2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"0" then
if clock_en='1' then
hs_cb2_o <= '0';
else
set_cb2_low <= '1';
end if;
end if;
when "10" =>
hs_cb2_o <= '0';
when "11" =>
hs_cb2_o <= '1';
when others =>
null;
end case;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' then
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads --
case addr is
when X"0" => -- ORB
--Port B reads its own output register for pins set to output.
data_out(0) <= (pio_i.prb(0) and pio_i.ddrb(0)) or (irb(0) and not pio_i.ddrb(0));
data_out(1) <= (pio_i.prb(1) and pio_i.ddrb(1)) or (irb(1) and not pio_i.ddrb(1));
data_out(2) <= (pio_i.prb(2) and pio_i.ddrb(2)) or (irb(2) and not pio_i.ddrb(2));
data_out(3) <= (pio_i.prb(3) and pio_i.ddrb(3)) or (irb(3) and not pio_i.ddrb(3));
data_out(4) <= (pio_i.prb(4) and pio_i.ddrb(4)) or (irb(4) and not pio_i.ddrb(4));
data_out(5) <= (pio_i.prb(5) and pio_i.ddrb(5)) or (irb(5) and not pio_i.ddrb(5));
data_out(6) <= (pio_i.prb(6) and pio_i.ddrb(6)) or (irb(6) and not pio_i.ddrb(6));
data_out(7) <= (pio_i.prb(7) and (pio_i.ddrb(7) or tmr_a_output_en)) or (irb(7) and not (pio_i.ddrb(7) or tmr_a_output_en));
if cb2_no_irq_clr='0' and ren='1' then
cb2_flag <= '0';
end if;
if ren='1' then
cb1_flag <= '0';
end if;
when X"1" => -- ORA
data_out <= ira;
if ca2_no_irq_clr='0' and ren='1' then
ca2_flag <= '0';
end if;
if ren='1' then
ca1_flag <= '0';
end if;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddrb;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
if ren='1' then
timer_a_flag <= '0';
end if;
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
if ren='1' then
timer_b_flag <= '0';
end if;
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
if ren='1' then
serial_flag <= '0';
end if;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= ira;
when others =>
null;
end case;
if reset='1' then
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_o <= '1';
hs_cb2_o <= '1';
set_ca2_low <= '0';
set_cb2_low <= '0';
timer_a_latch <= latch_reset_pattern;
timer_b_latch <= latch_reset_pattern(7 downto 0);
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_post_oneshot : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_a_event <= '0';
if clock_en='1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
timer_a_reload <= '0';
else
if timer_a_count = X"0000" then
-- generate an event if we were triggered
if tmr_a_freerun = '1' then
timer_a_event <= '1';
-- if in free running mode, set a flag to reload
timer_a_reload <= tmr_a_freerun;
else
if (timer_a_post_oneshot = '0') then
timer_a_post_oneshot <= '1';
timer_a_event <= '1';
end if;
end if;
-- toggle output
timer_a_out <= not timer_a_out;
end if;
--Timer coutinues to count in both free run and one shot.
timer_a_count <= timer_a_count - X"0001";
end if;
end if;
if write_t1c_h = '1' then
timer_a_out <= '0';
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_reload <= '0';
timer_a_post_oneshot <= '0';
end if;
if reset='1' then
timer_a_out <= '1';
timer_a_count <= latch_reset_pattern;
timer_a_reload <= '0';
timer_a_post_oneshot <= '0';
end if;
end if;
end process;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_reload : std_logic;
signal timer_b_post_oneshot : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
variable timer_b_decrement : std_logic;
begin
if rising_edge(clock) then
timer_b_event <= '0';
timer_b_tick <= '0';
pb6_c <= port_b_i(6);
timer_b_decrement := '0';
if clock_en='1' then
pb6_d <= pb6_c;
if timer_b_reload = '1' then
timer_b_count <= X"00" & timer_b_latch(7 downto 0);
timer_b_reload <= '0';
else
if tmr_b_count_mode = '1' then
if (pb6_d='0' and pb6_c='1') then
timer_b_decrement := '1';
end if;
else -- one shot or used for shirt register
timer_b_decrement := '1';
end if;
if timer_b_decrement = '1' then
if timer_b_count = X"0000" then
if (timer_b_post_oneshot = '0') then
timer_b_post_oneshot <= '1';
timer_b_event <= '1';
end if;
timer_b_tick <= '1';
case shift_mode_control is
when "001" | "101" | "100" =>
timer_b_reload <= '1';
when others =>
null;
end case;
end if;
timer_b_count <= timer_b_count - X"0001";
end if;
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_reload <= '0';
timer_b_post_oneshot <= '0';
end if;
if reset='1' then
timer_b_count <= latch_reset_pattern;
timer_b_reload <= '0';
timer_b_post_oneshot <= '0';
end if;
end if;
end process;
end block tmr_b;
ser: block
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal cb1_c, cb2_c : std_logic;
signal mpu_write : std_logic;
signal mpu_read : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_active : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
case shift_clk_sel is
when "10" =>
if shift_active='0' then
shift_clock <= '1';
elsif clock_en='1' then
shift_clock <= not shift_clock;
end if;
when "00"|"01" =>
if shift_active='0' then
shift_clock <= '1';
elsif timer_b_tick='1' then
shift_clock <= not shift_clock;
end if;
when others => -- "11"
shift_clock <= To_X01(cb1_i);
end case;
shift_clock_d <= shift_clock;
end if;
end process;
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
cb1_t <= '0' when shift_clk_sel="11" else serport_en;
cb1_o <= shift_clock;
mpu_write <= wen when addr=X"A" else '0';
mpu_read <= ren when addr=X"A" else '0';
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
process(clock)
begin
if rising_edge(clock) then
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
if shift_clk_sel = "00" then
bit_cnt <= 7;
if shift_dir='0' then -- disabled mode
shift_active <= '0';
end if;
end if;
if mpu_read='1' or mpu_write='1' then
bit_cnt <= 7;
shift_active <= '1';
if mpu_write='1' then
shift_reg <= data_in;
end if;
end if;
serial_event <= '0';
if shift_active='1' then
if shift_tick_f='1' then
ser_cb2_o <= shift_reg(7);
end if;
if shift_tick_r='1' then
if shift_dir='1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
else
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
if bit_cnt=0 then
serial_event <= '1';
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if reset='1' then
shift_reg <= (others => '1');
shift_active <= '0';
bit_cnt <= 0;
ser_cb2_o <= '1';
end if;
end if;
end process;
end block ser;
end Gideon;
|
-- CPU package of common definitions, types and constants
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cpu_defs is
--------------------------------------------------------------
--
-- Data types
--
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
subtype halfword is std_logic_vector(15 downto 0);
subtype byte is std_logic_vector(7 downto 0);
--------------------------------------------------------------
--
-- Slave/peripheral interfaces for memory mapping
--
-- For each slave interface, we have:
--
-- START/END: first and last address in the memory map of the
-- interface
-- MASKBIT: for masking the part of an address given to the
-- slave.
--
constant CORE_REG_ADDR_START: word := x"00000000";
constant CORE_REG_ADDR_END: word := x"00000FFF";
constant CORE_REG_ADDR_SIZE: natural := 12;
constant MEM_ADDR_START: word := x"00100000";
constant MEM_ADDR_END: word := x"0013FFFF";
constant MEM_ADDR_SIZE: natural := 18;
--------------------------------------------------------------
--
-- Core registers
--
constant NCORE_REGS_LOG2: natural := 4;
subtype core_reg_addr is std_logic_vector(11 downto 0);
subtype core_reg_sel is std_logic_vector(NCORE_REGS_LOG2 - 1 downto 0);
constant CORE_REG_EXCEPTION_VECTOR: natural := 1;
constant CORE_REG_CONTROL_1: natural := 5;
constant CORE_REG_EXCEPTION_CAUSE: natural := 7;
constant CORE_REG_EXCEPTION_RET_ADDR: natural := 8;
constant CORE_REG_INTERRUPT_ENABLE: natural := 11;
constant CORE_REG_INTERRUPT_PENDING: natural := 12;
constant ADDR_OF_EXCEPTION_VECTOR: core_reg_addr := x"004";
constant ADDR_OF_CONTROL_1: core_reg_addr := x"100";
constant ADDR_OF_EXCEPTION_CAUSE: core_reg_addr := x"108";
constant ADDR_OF_EXCEPTION_RET_ADDR: core_reg_addr := x"10C";
constant ADDR_OF_INTERRUPT_ENABLE: core_reg_addr := x"120";
constant ADDR_OF_INTERRUPT_PENDING: core_reg_addr := x"124";
function core_reg2addr_map (sel: core_reg_sel) return core_reg_addr;
function addr2core_reg_map (addr: core_reg_addr) return core_reg_sel;
--------------------------------------------------------------
--
-- Opcodes
--
subtype cpu_opcode is std_logic_vector(5 downto 0);
constant OP_ADD: cpu_opcode := "000000";
constant OP_SUB: cpu_opcode := "000001";
constant OP_MULU: cpu_opcode := "000010";
constant OP_MUL: cpu_opcode := "000011";
constant OP_DIVU: cpu_opcode := "000100";
constant OP_DIV: cpu_opcode := "000101";
constant OP_LUI: cpu_opcode := "000110";
constant OP_SLL: cpu_opcode := "000111";
constant OP_SRL: cpu_opcode := "001000";
constant OP_AND: cpu_opcode := "001001";
constant OP_OR: cpu_opcode := "001010";
constant OP_NOR: cpu_opcode := "001011";
constant OP_XOR: cpu_opcode := "001100";
constant OP_LB: cpu_opcode := "001101";
constant OP_LH: cpu_opcode := "001110";
constant OP_LW: cpu_opcode := "001111";
constant OP_LBU: cpu_opcode := "010000";
constant OP_LHU: cpu_opcode := "010001";
constant OP_SB: cpu_opcode := "010010";
constant OP_SH: cpu_opcode := "010011";
constant OP_SW: cpu_opcode := "010100";
constant OP_B: cpu_opcode := "010101";
constant OP_JR: cpu_opcode := "010110";
constant OP_BEQ: cpu_opcode := "010111";
constant OP_BNE: cpu_opcode := "011000";
constant OP_BGE: cpu_opcode := "011001";
constant OP_BGT: cpu_opcode := "011010";
constant OP_BLE: cpu_opcode := "011011";
constant OP_BLT: cpu_opcode := "011100";
constant OP_CALL: cpu_opcode := "011101";
constant OP_ADDI: cpu_opcode := "100000";
constant OP_SUBI: cpu_opcode := "100001";
constant OP_BGEU: cpu_opcode := "100010";
constant OP_BGTU: cpu_opcode := "100011";
constant OP_BLEU: cpu_opcode := "100100";
constant OP_BLTU: cpu_opcode := "100101";
constant OP_ANDI: cpu_opcode := "101001";
constant OP_ORI: cpu_opcode := "101010";
constant OP_SLLI: cpu_opcode := "101011";
constant OP_SRLI: cpu_opcode := "101100";
constant OP_ERET: cpu_opcode := "111110";
constant OP_HALT: cpu_opcode := "111111";
end cpu_defs;
package body cpu_defs is
function core_reg2addr_map (sel: core_reg_sel) return core_reg_addr is
begin
case to_integer(unsigned(sel)) is
when CORE_REG_EXCEPTION_VECTOR => return ADDR_OF_EXCEPTION_VECTOR;
when CORE_REG_CONTROL_1 => return ADDR_OF_CONTROL_1;
when CORE_REG_EXCEPTION_CAUSE => return ADDR_OF_EXCEPTION_CAUSE;
when CORE_REG_EXCEPTION_RET_ADDR => return ADDR_OF_EXCEPTION_RET_ADDR;
when CORE_REG_INTERRUPT_ENABLE => return ADDR_OF_INTERRUPT_ENABLE;
when CORE_REG_INTERRUPT_PENDING => return ADDR_OF_INTERRUPT_PENDING;
when others => return x"000";
end case;
end;
function addr2core_reg_map (addr: core_reg_addr) return core_reg_sel is
variable sel_integer: natural range 0 to 2**NCORE_REGS_LOG2 - 1;
begin
case addr is
when ADDR_OF_EXCEPTION_VECTOR => sel_integer := CORE_REG_EXCEPTION_VECTOR;
when ADDR_OF_CONTROL_1 => sel_integer := CORE_REG_CONTROL_1;
when ADDR_OF_EXCEPTION_CAUSE => sel_integer := CORE_REG_EXCEPTION_CAUSE;
when ADDR_OF_EXCEPTION_RET_ADDR => sel_integer := CORE_REG_EXCEPTION_RET_ADDR;
when ADDR_OF_INTERRUPT_ENABLE => sel_integer := CORE_REG_INTERRUPT_ENABLE;
when ADDR_OF_INTERRUPT_PENDING => sel_integer := CORE_REG_INTERRUPT_PENDING;
when others => sel_integer := 0;
end case;
return std_logic_vector(to_unsigned(sel_integer, NCORE_REGS_LOG2));
end;
end cpu_defs;
|
-- CPU package of common definitions, types and constants
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cpu_defs is
--------------------------------------------------------------
--
-- Data types
--
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
subtype halfword is std_logic_vector(15 downto 0);
subtype byte is std_logic_vector(7 downto 0);
--------------------------------------------------------------
--
-- Slave/peripheral interfaces for memory mapping
--
-- For each slave interface, we have:
--
-- START/END: first and last address in the memory map of the
-- interface
-- MASKBIT: for masking the part of an address given to the
-- slave.
--
constant CORE_REG_ADDR_START: word := x"00000000";
constant CORE_REG_ADDR_END: word := x"00000FFF";
constant CORE_REG_ADDR_SIZE: natural := 12;
constant MEM_ADDR_START: word := x"00100000";
constant MEM_ADDR_END: word := x"0013FFFF";
constant MEM_ADDR_SIZE: natural := 18;
--------------------------------------------------------------
--
-- Core registers
--
constant NCORE_REGS_LOG2: natural := 4;
subtype core_reg_addr is std_logic_vector(11 downto 0);
subtype core_reg_sel is std_logic_vector(NCORE_REGS_LOG2 - 1 downto 0);
constant CORE_REG_EXCEPTION_VECTOR: natural := 1;
constant CORE_REG_CONTROL_1: natural := 5;
constant CORE_REG_EXCEPTION_CAUSE: natural := 7;
constant CORE_REG_EXCEPTION_RET_ADDR: natural := 8;
constant CORE_REG_INTERRUPT_ENABLE: natural := 11;
constant CORE_REG_INTERRUPT_PENDING: natural := 12;
constant ADDR_OF_EXCEPTION_VECTOR: core_reg_addr := x"004";
constant ADDR_OF_CONTROL_1: core_reg_addr := x"100";
constant ADDR_OF_EXCEPTION_CAUSE: core_reg_addr := x"108";
constant ADDR_OF_EXCEPTION_RET_ADDR: core_reg_addr := x"10C";
constant ADDR_OF_INTERRUPT_ENABLE: core_reg_addr := x"120";
constant ADDR_OF_INTERRUPT_PENDING: core_reg_addr := x"124";
function core_reg2addr_map (sel: core_reg_sel) return core_reg_addr;
function addr2core_reg_map (addr: core_reg_addr) return core_reg_sel;
--------------------------------------------------------------
--
-- Opcodes
--
subtype cpu_opcode is std_logic_vector(5 downto 0);
constant OP_ADD: cpu_opcode := "000000";
constant OP_SUB: cpu_opcode := "000001";
constant OP_MULU: cpu_opcode := "000010";
constant OP_MUL: cpu_opcode := "000011";
constant OP_DIVU: cpu_opcode := "000100";
constant OP_DIV: cpu_opcode := "000101";
constant OP_LUI: cpu_opcode := "000110";
constant OP_SLL: cpu_opcode := "000111";
constant OP_SRL: cpu_opcode := "001000";
constant OP_AND: cpu_opcode := "001001";
constant OP_OR: cpu_opcode := "001010";
constant OP_NOR: cpu_opcode := "001011";
constant OP_XOR: cpu_opcode := "001100";
constant OP_LB: cpu_opcode := "001101";
constant OP_LH: cpu_opcode := "001110";
constant OP_LW: cpu_opcode := "001111";
constant OP_LBU: cpu_opcode := "010000";
constant OP_LHU: cpu_opcode := "010001";
constant OP_SB: cpu_opcode := "010010";
constant OP_SH: cpu_opcode := "010011";
constant OP_SW: cpu_opcode := "010100";
constant OP_B: cpu_opcode := "010101";
constant OP_JR: cpu_opcode := "010110";
constant OP_BEQ: cpu_opcode := "010111";
constant OP_BNE: cpu_opcode := "011000";
constant OP_BGE: cpu_opcode := "011001";
constant OP_BGT: cpu_opcode := "011010";
constant OP_BLE: cpu_opcode := "011011";
constant OP_BLT: cpu_opcode := "011100";
constant OP_CALL: cpu_opcode := "011101";
constant OP_ADDI: cpu_opcode := "100000";
constant OP_SUBI: cpu_opcode := "100001";
constant OP_BGEU: cpu_opcode := "100010";
constant OP_BGTU: cpu_opcode := "100011";
constant OP_BLEU: cpu_opcode := "100100";
constant OP_BLTU: cpu_opcode := "100101";
constant OP_ANDI: cpu_opcode := "101001";
constant OP_ORI: cpu_opcode := "101010";
constant OP_SLLI: cpu_opcode := "101011";
constant OP_SRLI: cpu_opcode := "101100";
constant OP_ERET: cpu_opcode := "111110";
constant OP_HALT: cpu_opcode := "111111";
end cpu_defs;
package body cpu_defs is
function core_reg2addr_map (sel: core_reg_sel) return core_reg_addr is
begin
case to_integer(unsigned(sel)) is
when CORE_REG_EXCEPTION_VECTOR => return ADDR_OF_EXCEPTION_VECTOR;
when CORE_REG_CONTROL_1 => return ADDR_OF_CONTROL_1;
when CORE_REG_EXCEPTION_CAUSE => return ADDR_OF_EXCEPTION_CAUSE;
when CORE_REG_EXCEPTION_RET_ADDR => return ADDR_OF_EXCEPTION_RET_ADDR;
when CORE_REG_INTERRUPT_ENABLE => return ADDR_OF_INTERRUPT_ENABLE;
when CORE_REG_INTERRUPT_PENDING => return ADDR_OF_INTERRUPT_PENDING;
when others => return x"000";
end case;
end;
function addr2core_reg_map (addr: core_reg_addr) return core_reg_sel is
variable sel_integer: natural range 0 to 2**NCORE_REGS_LOG2 - 1;
begin
case addr is
when ADDR_OF_EXCEPTION_VECTOR => sel_integer := CORE_REG_EXCEPTION_VECTOR;
when ADDR_OF_CONTROL_1 => sel_integer := CORE_REG_CONTROL_1;
when ADDR_OF_EXCEPTION_CAUSE => sel_integer := CORE_REG_EXCEPTION_CAUSE;
when ADDR_OF_EXCEPTION_RET_ADDR => sel_integer := CORE_REG_EXCEPTION_RET_ADDR;
when ADDR_OF_INTERRUPT_ENABLE => sel_integer := CORE_REG_INTERRUPT_ENABLE;
when ADDR_OF_INTERRUPT_PENDING => sel_integer := CORE_REG_INTERRUPT_PENDING;
when others => sel_integer := 0;
end case;
return std_logic_vector(to_unsigned(sel_integer, NCORE_REGS_LOG2));
end;
end cpu_defs;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY adder_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
sum_out: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_adder OF adder_n IS
SIGNAL sum_signed: SIGNED(Nb-1 DOWNTO 0);
BEGIN
--sum_signed <= SIGNED(in_a(Nb-1) & in_a) + SIGNED(in_b(Nb-1) & in_b);
sum_signed <= SIGNED(in_a) + SIGNED(in_b);
sum_out <= STD_LOGIC_VECTOR(sum_signed);
END beh_adder;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DS clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of clkpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DS clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of clkpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
|
-------------------------------------------------------------------------------
-- axi_vdma_sfifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sfifo.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
--use proc_common_v4_0.coregen_comp_defs.all;
--use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
ENTITY axi_vdma_sfifo IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_FAMILY : STRING := "virtex7"; --
C_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 0,1 ; Default 1
UW_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16
UW_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K
);
PORT (
-- Common signal
rst : in std_logic := '0';
sleep : in std_logic := '0';
wr_rst_busy : out std_logic := '0';
rd_rst_busy : out std_logic := '0';
-- Write Domain signals
clk : in std_logic := '0';
din : in std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
full : out std_logic := '0';
data_count : out std_logic_vector(clog2(uw_fifo_depth)-1 downto 0) := (others => '0');
-- Read Domain signals
rd_en : in std_logic := '0';
dout : out std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
empty : out std_logic := '1'
);
END ENTITY axi_vdma_sfifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
ARCHITECTURE xilinx OF axi_vdma_sfifo IS
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";
--CONSTANT GND : std_logic := '0';
CONSTANT VCC : std_logic := '1';
CONSTANT clog2_uw_fifo_depth : integer := clog2(uw_fifo_depth);
CONSTANT clog2_uw_fifo_depth_plus_1 : integer := clog2(uw_fifo_depth) + 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ZERO_pntr : std_logic_vector(clog2_uw_fifo_depth-1 downto 0) := (others => '0');
signal GND : std_logic := '0';
signal ALMOST_FULL : std_logic;
signal WR_ACK : std_logic;
signal OVERFLOW : std_logic;
signal ALMOST_EMPTY : std_logic;
signal VALID : std_logic;
signal UNDERFLOW : std_logic;
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RD_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal WR_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
signal sig_data_count : std_logic_vector(clog2(uw_fifo_depth) downto 0) := (others => '0');
begin
FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate
begin
wr_rst_busy <= wr_rst_busy_sig;
rd_rst_busy <= rd_rst_busy_sig;
end generate FAMILY_8;
FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate
begin
wr_rst_busy <= '0';
rd_rst_busy <= '0';
end generate FAMILY_NOT_8;
data_count <= sig_data_count(clog2(uw_fifo_depth)-1 downto 0);
ZERO_pntr <= (others => '0');
GND <= '0';
fg_inst : entity fifo_generator_v12_0.fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
-- C_COUNT_TYPE => C_COUNT_TYPE,
C_COUNT_TYPE => 0, --my
-- C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DATA_COUNT_WIDTH => clog2_uw_fifo_depth_plus_1, --my
-- C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => uw_data_width,
-- C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => uw_data_width,
-- C_ENABLE_RLOCS => C_ENABLE_RLOCS,
--C_FAMILY => "virtex7",
C_FAMILY => C_FAMILY, --my
--C_FULL_FLAGS_RST_VAL => uw_full_flags_rst_val,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, --my
-- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
-- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
-- C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => 1, --my
-- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
-- C_HAS_INT_CLK => C_HAS_INT_CLK,
-- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
-- C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => 0, --my
-- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
-- C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => 0,
C_HAS_SRST => 1,
-- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
-- C_HAS_VALID => C_HAS_VALID,
-- C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, --my
-- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
-- C_HAS_WR_RST => C_HAS_WR_RST,
--C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_IMPLEMENTATION_TYPE => 0, --my --Block RAM
-- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
--C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MEMORY_TYPE => 1, --my --Block RAM
-- C_MIF_FILE_NAME => C_MIF_FILE_NAME,
-- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
-- C_OVERFLOW_LOW => C_OVERFLOW_LOW,
--C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
--C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRELOAD_LATENCY => 0, --my
C_PRELOAD_REGS => 1, --my
--C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 10,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 9,
C_PROG_EMPTY_TYPE => 0,
--C_PROG_FULL_THRESH_ASSERT_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-150, 14), --my
--C_PROG_FULL_THRESH_NEGATE_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-160, 12), --my
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => uw_fifo_depth,
--C_RD_FREQ => C_RD_FREQ,
C_RD_FREQ => 1, --my
C_RD_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
-- C_USE_DOUT_RST => C_USE_DOUT_RST,
-- C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => 1, --my
-- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
-- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => 1, --my
-- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
-- C_VALID_LOW => C_VALID_LOW,
-- C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => uw_fifo_depth,
--C_WR_FREQ => C_WR_FREQ,
C_WR_FREQ => 1, --my
C_WR_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
-- C_MSGON_VAL => C_MSGON_VAL,
-- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
-- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => MTBF_STAGES,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
PORT MAP (
backup => GND,
backup_marker => GND,
clk => clk,
rst => GND,
srst => rst,
wr_clk => GND,
wr_rst => GND,
rd_clk => GND,
rd_rst => GND,
din => din,
wr_en => wr_en,
rd_en => rd_en,
sleep => sleep,
wr_rst_busy => wr_rst_busy_sig,
rd_rst_busy => rd_rst_busy_sig,
prog_empty_thresh => ZERO_pntr,
prog_empty_thresh_assert => ZERO_pntr,
prog_empty_thresh_negate => ZERO_pntr,
prog_full_thresh => ZERO_pntr,
prog_full_thresh_assert => ZERO_pntr,
prog_full_thresh_negate => ZERO_pntr,
int_clk => GND,
injectdbiterr => GND,
injectsbiterr => GND,
dout => dout,
full => full,
empty => empty,
almost_full => ALMOST_FULL,
wr_ack => WR_ACK,
overflow => OVERFLOW,
almost_empty => ALMOST_EMPTY,
valid => VALID,
underflow => UNDERFLOW,
data_count => sig_data_count,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
END ARCHITECTURE xilinx;
|
-------------------------------------------------------------------------------
-- axi_vdma_sfifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sfifo.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
--use proc_common_v4_0.coregen_comp_defs.all;
--use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
ENTITY axi_vdma_sfifo IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_FAMILY : STRING := "virtex7"; --
C_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 0,1 ; Default 1
UW_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16
UW_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K
);
PORT (
-- Common signal
rst : in std_logic := '0';
sleep : in std_logic := '0';
wr_rst_busy : out std_logic := '0';
rd_rst_busy : out std_logic := '0';
-- Write Domain signals
clk : in std_logic := '0';
din : in std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
full : out std_logic := '0';
data_count : out std_logic_vector(clog2(uw_fifo_depth)-1 downto 0) := (others => '0');
-- Read Domain signals
rd_en : in std_logic := '0';
dout : out std_logic_vector(UW_DATA_WIDTH-1 downto 0) := (others => '0');
empty : out std_logic := '1'
);
END ENTITY axi_vdma_sfifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
ARCHITECTURE xilinx OF axi_vdma_sfifo IS
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";
--CONSTANT GND : std_logic := '0';
CONSTANT VCC : std_logic := '1';
CONSTANT clog2_uw_fifo_depth : integer := clog2(uw_fifo_depth);
CONSTANT clog2_uw_fifo_depth_plus_1 : integer := clog2(uw_fifo_depth) + 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ZERO_pntr : std_logic_vector(clog2_uw_fifo_depth-1 downto 0) := (others => '0');
signal GND : std_logic := '0';
signal ALMOST_FULL : std_logic;
signal WR_ACK : std_logic;
signal OVERFLOW : std_logic;
signal ALMOST_EMPTY : std_logic;
signal VALID : std_logic;
signal UNDERFLOW : std_logic;
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RD_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal WR_DATA_COUNT : std_logic_vector(clog2_uw_fifo_depth-1 DOWNTO 0);
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
signal sig_data_count : std_logic_vector(clog2(uw_fifo_depth) downto 0) := (others => '0');
begin
FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate
begin
wr_rst_busy <= wr_rst_busy_sig;
rd_rst_busy <= rd_rst_busy_sig;
end generate FAMILY_8;
FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate
begin
wr_rst_busy <= '0';
rd_rst_busy <= '0';
end generate FAMILY_NOT_8;
data_count <= sig_data_count(clog2(uw_fifo_depth)-1 downto 0);
ZERO_pntr <= (others => '0');
GND <= '0';
fg_inst : entity fifo_generator_v12_0.fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
-- C_COUNT_TYPE => C_COUNT_TYPE,
C_COUNT_TYPE => 0, --my
-- C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DATA_COUNT_WIDTH => clog2_uw_fifo_depth_plus_1, --my
-- C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => uw_data_width,
-- C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => uw_data_width,
-- C_ENABLE_RLOCS => C_ENABLE_RLOCS,
--C_FAMILY => "virtex7",
C_FAMILY => C_FAMILY, --my
--C_FULL_FLAGS_RST_VAL => uw_full_flags_rst_val,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, --my
-- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
-- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
-- C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => 1, --my
-- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
-- C_HAS_INT_CLK => C_HAS_INT_CLK,
-- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
-- C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => 0, --my
-- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
-- C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => 0,
C_HAS_SRST => 1,
-- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
-- C_HAS_VALID => C_HAS_VALID,
-- C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, --my
-- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
-- C_HAS_WR_RST => C_HAS_WR_RST,
--C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_IMPLEMENTATION_TYPE => 0, --my --Block RAM
-- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
--C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MEMORY_TYPE => 1, --my --Block RAM
-- C_MIF_FILE_NAME => C_MIF_FILE_NAME,
-- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
-- C_OVERFLOW_LOW => C_OVERFLOW_LOW,
--C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
--C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRELOAD_LATENCY => 0, --my
C_PRELOAD_REGS => 1, --my
--C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 10,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 9,
C_PROG_EMPTY_TYPE => 0,
--C_PROG_FULL_THRESH_ASSERT_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-150, 14), --my
--C_PROG_FULL_THRESH_NEGATE_VAL => if_then_else((UW_FIFO_TYPE = "BUILT_IN"), UW_FIFO_DEPTH-160, 12), --my
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => uw_fifo_depth,
--C_RD_FREQ => C_RD_FREQ,
C_RD_FREQ => 1, --my
C_RD_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
-- C_USE_DOUT_RST => C_USE_DOUT_RST,
-- C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => 1, --my
-- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
-- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => 1, --my
-- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
-- C_VALID_LOW => C_VALID_LOW,
-- C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => clog2_uw_fifo_depth, --my
-- C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => uw_fifo_depth,
--C_WR_FREQ => C_WR_FREQ,
C_WR_FREQ => 1, --my
C_WR_PNTR_WIDTH => clog2_uw_fifo_depth,
-- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
-- C_MSGON_VAL => C_MSGON_VAL,
-- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
-- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => MTBF_STAGES,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
PORT MAP (
backup => GND,
backup_marker => GND,
clk => clk,
rst => GND,
srst => rst,
wr_clk => GND,
wr_rst => GND,
rd_clk => GND,
rd_rst => GND,
din => din,
wr_en => wr_en,
rd_en => rd_en,
sleep => sleep,
wr_rst_busy => wr_rst_busy_sig,
rd_rst_busy => rd_rst_busy_sig,
prog_empty_thresh => ZERO_pntr,
prog_empty_thresh_assert => ZERO_pntr,
prog_empty_thresh_negate => ZERO_pntr,
prog_full_thresh => ZERO_pntr,
prog_full_thresh_assert => ZERO_pntr,
prog_full_thresh_negate => ZERO_pntr,
int_clk => GND,
injectdbiterr => GND,
injectsbiterr => GND,
dout => dout,
full => full,
empty => empty,
almost_full => ALMOST_FULL,
wr_ack => WR_ACK,
overflow => OVERFLOW,
almost_empty => ALMOST_EMPTY,
valid => VALID,
underflow => UNDERFLOW,
data_count => sig_data_count,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
END ARCHITECTURE xilinx;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: Regs_Group - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
-- Revision 1.10 - Readability improved by FOR-LOOP used 19.03.2007
--
-- Revision 1.00 - File Created 06.02.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Regs_Group is
port (
-- Event Buffer status + reset
wb_FIFO_Rst : out std_logic;
-- Write interface
Regs_WrEnA : in std_logic;
Regs_WrMaskA : in std_logic_vector(2-1 downto 0);
Regs_WrAddrA : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEnB : in std_logic;
Regs_WrMaskB : in std_logic_vector(2-1 downto 0);
Regs_WrAddrB : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinB : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : in std_logic;
ds_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Downstream Engine
DMA_ds_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : out std_logic; -- obsolete
DMA_ds_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : in std_logic;
DMA_ds_Tout : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : out std_logic;
dsBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : out std_logic;
dsLeng_Lo7b_True : out std_logic;
-- Downstream Control Signals
dsDMA_Start : out std_logic;
dsDMA_Stop : out std_logic;
dsDMA_Start2 : out std_logic;
dsDMA_Stop2 : out std_logic;
dsDMA_Channel_Rst : out std_logic;
dsDMA_Cmd_Ack : in std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : in std_logic;
us_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Upstream Engine
DMA_us_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : out std_logic; -- obsolete
us_MWr_Param_Vec : out std_logic_vector(6-1 downto 0);
DMA_us_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : in std_logic;
DMA_us_Tout : in std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : out std_logic;
usBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : out std_logic;
usLeng_Lo7b_True : out std_logic;
-- Upstream Control Signals
usDMA_Start : out std_logic;
usDMA_Stop : out std_logic;
usDMA_Start2 : out std_logic;
usDMA_Stop2 : out std_logic;
usDMA_Channel_Rst : out std_logic;
usDMA_Cmd_Ack : in std_logic;
-- MRd Channel Reset
MRd_Channel_Rst : out std_logic;
-- Tx module reset
Tx_Reset : out std_logic;
-- to Interrupts Module
Sys_IRQ : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System error and info
Tx_TimeOut : in std_logic;
Tx_wb_TimeOut : in std_logic;
Msg_Routing : out std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
pcie_link_width : in std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : in std_logic_vector(16-1 downto 0);
ddr_sdram_ready : in std_logic;
-- Interrupt Generation Signals
IG_Reset : out std_logic;
IG_Host_Clear : out std_logic;
IG_Latency : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : in std_logic;
-- SDRAM and Wishbone paging registers
sdram_pg : out std_logic_vector(31 downto 0);
wb_pg : out std_logic_vector(31 downto 0);
-- Clock and reset
user_clk : in std_logic;
user_lnk_up : in std_logic;
user_reset : in std_logic
);
end Regs_Group;
architecture Behavioral of Regs_Group is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
------ Delay signals
signal Regs_WrEn_r1 : std_logic;
signal Regs_WrAddr_r1 : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_r1 : std_logic_vector(2-1 downto 0);
signal Regs_WrDin_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrEn_r2 : std_logic;
signal Regs_WrDin_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_Wr_dma_V_hi_r2 : std_logic;
signal Regs_Wr_dma_nV_hi_r2 : std_logic;
signal Regs_Wr_dma_V_nE_hi_r2 : std_logic;
signal Regs_Wr_dma_V_lo_r2 : std_logic;
signal Regs_Wr_dma_nV_lo_r2 : std_logic;
signal Regs_Wr_dma_V_nE_lo_r2 : std_logic;
signal WrDin_r1_not_Zero_Hi : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Hi : std_logic;
signal WrDin_r1_not_Zero_Lo : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Lo : std_logic;
-- Calculation in advance, just for better timing
signal Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_hq_r2 : std_logic;
signal Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_lq_r2 : std_logic;
signal Regs_WrEnA_r1 : std_logic;
signal Regs_WrEnB_r1 : std_logic;
signal Regs_WrEnA_r2 : std_logic;
signal Regs_WrEnB_r2 : std_logic;
-- Register write mux signals
signal Reg_WrMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_WrMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Signals for Tx reading
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdQout_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register read mux signals
signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Event Buffer
signal wb_FIFO_Rst_i : std_logic;
signal wb_FIFO_Rst_b1 : std_logic;
signal wb_FIFO_Rst_b2 : std_logic;
signal wb_FIFO_Rst_b3 : std_logic;
signal wb_FIFO_Rst_b4 : std_logic;
signal wb_FIFO_Rst_b5 : std_logic;
-- Downstream DMA registers
signal DMA_ds_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Upstream DMA registers
signal DMA_us_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System Interrupt Status/Control
signal Sys_IRQ_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- General Control and Status
signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal sdram_pg_i : std_logic_vector(32-1 downto 0);
signal sdram_pg_o_hi : std_logic_vector(32-1 downto 0);
signal sdram_pg_o_lo : std_logic_vector(32-1 downto 0);
signal wb_pg_i : std_logic_vector(32-1 downto 0);
signal wb_pg_o_hi : std_logic_vector(32-1 downto 0);
signal wb_pg_o_lo : std_logic_vector(32-1 downto 0);
-- Hardward version
signal HW_Version_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal HW_Version_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Signal as the source of interrupts
signal IG_Host_Clear_i : std_logic;
signal IG_Reset_i : std_logic;
-- Interrupt Generator Control
signal IG_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Latency
signal IG_Latency_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Assert number
signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Deassert number
signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- IntClr character is written
signal Command_is_Host_iClr_Hi : std_logic;
signal Command_is_Host_iClr_Lo : std_logic;
-- Downstream Registers
signal DMA_ds_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_ds : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal dsHA_is_64b_i : std_logic;
signal dsBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal dsLeng_Hi19b_True_i : std_logic;
signal dsLeng_Lo7b_True_i : std_logic;
-- Downstream Control Signals
signal dsDMA_Start_i : std_logic;
signal dsDMA_Stop_i : std_logic;
signal dsDMA_Start2_i : std_logic;
signal dsDMA_Start2_r1 : std_logic;
signal dsDMA_Stop2_i : std_logic;
signal dsDMA_Channel_Rst_i : std_logic;
signal ds_Param_Modified : std_logic;
-- Upstream Registers
signal DMA_us_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_us : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal usHA_is_64b_i : std_logic;
signal usBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal usLeng_Hi19b_True_i : std_logic;
signal usLeng_Lo7b_True_i : std_logic;
-- Upstream Control Signals
signal usDMA_Start_i : std_logic;
signal usDMA_Stop_i : std_logic;
signal usDMA_Start2_i : std_logic;
signal usDMA_Start2_r1 : std_logic;
signal usDMA_Stop2_i : std_logic;
signal usDMA_Channel_Rst_i : std_logic;
signal us_Param_Modified : std_logic;
-- Reset character is written
signal Command_is_Reset_Hi : std_logic;
signal Command_is_Reset_Lo : std_logic;
-- MRd channel reset
signal MRd_Channel_Rst_i : std_logic;
-- Tx module reset
signal Tx_Reset_i : std_logic;
begin
-- Event buffer reset
wb_FIFO_Rst <= wb_FIFO_Rst_i;
-- MRd channel reset
MRd_Channel_Rst <= MRd_Channel_Rst_i;
-- Tx module reset
Tx_Reset <= Tx_Reset_i;
-- Upstream DMA engine reset
usDMA_Channel_Rst <= usDMA_Channel_Rst_i;
-- Downstream DMA engine reset
dsDMA_Channel_Rst <= dsDMA_Channel_Rst_i;
sdram_pg <= sdram_pg_i;
wb_pg <= wb_pg_i;
-- Upstream DMA registers
DMA_us_PA <= DMA_us_PA_i;
DMA_us_HA <= DMA_us_HA_i;
DMA_us_BDA <= DMA_us_BDA_i;
DMA_us_Length <= DMA_us_Length_i;
DMA_us_Control <= DMA_us_Control_i;
usDMA_BDA_eq_Null <= '0';
DMA_us_Status_i <= DMA_us_Status;
usHA_is_64b <= usHA_is_64b_i;
usBDA_is_64b <= usBDA_is_64b_i;
usLeng_Hi19b_True <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True <= usLeng_Lo7b_True_i;
usDMA_Start <= usDMA_Start_i;
usDMA_Stop <= usDMA_Stop_i;
usDMA_Start2 <= usDMA_Start2_r1;
-- usDMA_Start2 <= usDMA_Start2_i;
usDMA_Stop2 <= usDMA_Stop2_i;
-- Downstream DMA registers
DMA_ds_PA <= DMA_ds_PA_i;
DMA_ds_HA <= DMA_ds_HA_i;
DMA_ds_BDA <= DMA_ds_BDA_i;
DMA_ds_Length <= DMA_ds_Length_i;
DMA_ds_Control <= DMA_ds_Control_i;
dsDMA_BDA_eq_Null <= '0';
DMA_ds_Status_i <= DMA_ds_Status;
dsHA_is_64b <= dsHA_is_64b_i;
dsBDA_is_64b <= dsBDA_is_64b_i;
dsLeng_Hi19b_True <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True <= dsLeng_Lo7b_True_i;
dsDMA_Start <= dsDMA_Start_i;
dsDMA_Stop <= dsDMA_Stop_i;
dsDMA_Start2 <= dsDMA_Start2_r1;
-- dsDMA_Start2 <= dsDMA_Start2_i;
dsDMA_Stop2 <= dsDMA_Stop2_i;
-- Register to Interrupt handler module
Sys_IRQ <= Sys_IRQ_i;
-- Message routing method
Msg_Routing <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
-- us_MWr_TLP_Param
us_MWr_Param_Vec <= General_Control_i(13 downto 8);
-- ------------- Interrupt generator generation ----------------------
Gen_IG : if IMP_INT_GENERATOR generate
IG_Reset <= IG_Reset_i;
IG_Host_Clear <= IG_Host_Clear_i; -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
IG_Latency <= IG_Latency_i;
IG_Num_Assert_i <= IG_Num_Assert;
IG_Num_Deassert_i <= IG_Num_Deassert;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Control_i <= (others => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Latency_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset_i = '1' then
IG_Latency_i <= (others => '0');
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
end generate;
NotGen_IG : if not IMP_INT_GENERATOR generate
IG_Reset <= '0';
IG_Host_Clear <= '0';
IG_Latency <= (others => '0');
IG_Num_Assert_i <= (others => '0');
IG_Num_Deassert_i <= (others => '0');
IG_Control_i <= (others => '0');
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
IG_Latency_i <= (others => '0');
end generate;
-- ----------------------------------------------
-- Synchronous Delay : Sys_IRQ_i
--
Synch_Delay_Sys_IRQ :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_IRQ_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
<= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
end if;
end process;
-- ----------------------------------------------
-- Registers writing
--
Regs_WrAddr_i <= Regs_WrAddrA and Regs_WrAddrB;
Regs_WrMask_i <= Regs_WrMaskA or Regs_WrMaskB;
Regs_WrDin_i <= Regs_WrDinA or
(Regs_WrDinB(C_DBUS_WIDTH/2-1 downto 0) & Regs_WrDinB(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2));
-- ----------------------------------------------
-- Registers reading
--
Regs_RdAddr_i <= Regs_RdAddr;
Regs_RdQout <= Regs_RdQout_i;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrEn
--
Synch_Delay_Regs_WrEn :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrEn_r1 <= Regs_WrEnA or Regs_WrEnB;
Regs_WrEn_r2 <= Regs_WrEn_r1;
Regs_WrEnA_r1 <= Regs_WrEnA;
Regs_WrEnA_r2 <= Regs_WrEnA_r1;
Regs_WrEnB_r1 <= Regs_WrEnB;
Regs_WrEnB_r2 <= Regs_WrEnB_r1;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrAddr
--
Synch_Delay_Regs_WrAddr :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrAddr_r1 <= Regs_WrAddr_i;
Regs_WrMask_r1 <= Regs_WrMask_i;
end if;
end process;
-- ----------------------------------------------------
-- Synchronous Delay : dsDMA_Start2
-- usDMA_Start2
-- (Special recipe for 64-bit successive descriptors)
--
Synch_Delay_DMA_Start2 :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
dsDMA_Start2_r1 <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
usDMA_Start2_r1 <= usDMA_Start2_i and not usDMA_Cmd_Ack;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrDin_i
--
Synch_Delay_Regs_WrDin :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrDin_r1 <= Regs_WrDin_i;
Regs_WrDin_r2 <= Regs_WrDin_r1;
if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
WrDin_r1_not_Zero_Hi(3) <= '0';
else
WrDin_r1_not_Zero_Hi(3) <= '1';
end if;
if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
WrDin_r1_not_Zero_Hi(2) <= '0';
else
WrDin_r1_not_Zero_Hi(2) <= '1';
end if;
if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
WrDin_r1_not_Zero_Hi(1) <= '0';
else
WrDin_r1_not_Zero_Hi(1) <= '1';
end if;
if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
WrDin_r1_not_Zero_Hi(0) <= '0';
else
WrDin_r1_not_Zero_Hi(0) <= '1';
end if;
if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Hi <= '0';
else
WrDin_r2_not_Zero_Hi <= '1';
end if;
if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
WrDin_r1_not_Zero_Lo(3) <= '0';
else
WrDin_r1_not_Zero_Lo(3) <= '1';
end if;
if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
WrDin_r1_not_Zero_Lo(2) <= '0';
else
WrDin_r1_not_Zero_Lo(2) <= '1';
end if;
if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
WrDin_r1_not_Zero_Lo(1) <= '0';
else
WrDin_r1_not_Zero_Lo(1) <= '1';
end if;
if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
WrDin_r1_not_Zero_Lo(0) <= '0';
else
WrDin_r1_not_Zero_Lo(0) <= '1';
end if;
if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Lo <= '0';
else
WrDin_r2_not_Zero_Lo <= '1';
end if;
end if;
end process;
-- -----------------------------------------------------------
-- Synchronous Delay : DMA Commands Write Valid and not End
--
Synch_Delay_dmaCmd_Wr_Valid_and_End :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_Wr_dma_V_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32);
Regs_Wr_dma_nV_hi_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32);
Regs_Wr_dma_V_nE_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32);
Regs_Wr_dma_V_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID);
Regs_Wr_dma_nV_lo_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID);
Regs_Wr_dma_V_nE_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END);
end if;
end process;
-- ------------------------------------------------
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
-- Regs_WrDin_Lo7b_True_r2 x2
--
Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
then
Regs_WrDin_Hi19b_True_hq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_hq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
= C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
then
Regs_WrDin_Hi19b_True_lq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_lq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_lq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_lq_r2 <= '1';
end if;
end if;
end process;
-- ---------------------------------------
--
Write_DMA_Registers_Mux :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Reg_WrMuxer_Hi <= (others => '0');
Reg_WrMuxer_Lo <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(0) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(0) <= '0';
end if;
for k in 1 to C_NUM_OF_ADDRESSES-1 loop
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(k) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(k) <= '0';
end if;
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Lo(k) <= not Regs_WrMask_r1(0);
else
Reg_WrMuxer_Lo(k) <= '0';
end if;
end loop;
end if;
end process;
-- -----------------------------------------------
-- System Interrupt Status Control
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: Sys_Int_Enable_i
SysReg_Sys_Int_Enable :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_Int_Enable_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN) = '1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN) = '1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
Sys_Int_Enable_i <= Sys_Int_Enable_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- DDR SDRAM address page
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: wb_pg
SDRAM_Addr_page :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
sdram_pg_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_SDRAM_PG) = '1'
then
sdram_pg_i <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_SDRAM_PG) = '1'
then
sdram_pg_i <= Regs_WrDin_r2(32-1 downto 0);
else
sdram_pg_i <= sdram_pg_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Wishbone endpoint address page
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: wb_pg_i
Wishbone_addr_page :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
wb_pg_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_WB_PG) = '1'
then
wb_pg_i <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_WB_PG) = '1'
then
wb_pg_i <= Regs_WrDin_r2(32-1 downto 0);
else
wb_pg_i <= wb_pg_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- System General Control Register
-- -----------------------------------------------
-- -----------------------------------------------
-- Synchronous Registered: General_Control
SysReg_General_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
General_Control_i <= (others => '0');
General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
<= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
downto C_TLP_TYPE_BIT_BOT);
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL) = '1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL) = '1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
General_Control_i <= General_Control_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Control_i <= (others => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Latency_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset_i = '1' then
IG_Latency_i <= (others => '0');
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Upstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_PA_i
RxTrn_DMA_us_PA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_PA_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_PA_i <= (others => '0');
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH) = '1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH) = '1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(32-1 downto 0) <= DMA_us_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_HA_i
RxTrn_DMA_us_HA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_HA_i <= (others => '1');
usHA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_HA_i <= (others => '1');
usHA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
usHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
usHA_is_64b_i <= usHA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_HA_i(32-1 downto 0) <= DMA_us_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_BDA_i
Syn_Output_DMA_us_BDA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_BDA_i <= (others => '0');
usBDA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_BDA_i <= (others => '0');
usBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= usBDA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_BDA_i(32-1 downto 0) <= DMA_us_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_Length_i
RxTrn_DMA_us_Length :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Length_i <= (others => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_Length_i <= (others => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_us_Length_i <= DMA_us_Length_i;
usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True_i <= usLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous us_Param_Modified
SynReg_us_Param_Modified :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
us_Param_Modified <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1'
or usDMA_Start_i = '1'
or usDMA_Start2_i = '1'
then
us_Param_Modified <= '0';
elsif Regs_WrEn_r2 = '1' and
(
Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1'
)
then
us_Param_Modified <= '1';
else
us_Param_Modified <= us_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Control_i
Syn_Output_DMA_us_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Control_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
elsif Regs_Wr_dma_nV_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
else
DMA_us_Control_i <= DMA_us_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_us
Hold_Last_Ctrl_Word_us :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start_Stop
Syn_Output_DMA_us_Start_Stop :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Start_i <= '0';
usDMA_Stop_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not usDMA_Stop_i
and not Command_is_Reset_Hi
and us_Param_Modified;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not usDMA_Stop_i
and not Command_is_Reset_Lo
and us_Param_Modified;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack = '1'
then
usDMA_Start_i <= '0';
usDMA_Stop_i <= usDMA_Stop_i;
else
usDMA_Start_i <= usDMA_Start_i;
usDMA_Stop_i <= usDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start2_Stop2
Syn_Output_DMA_us_Start2_Stop2 :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack = '1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= usDMA_Stop2_i;
else
usDMA_Start2_i <= usDMA_Start2_i;
usDMA_Stop2_i <= usDMA_Stop2_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Downstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_PA_i
RxTrn_DMA_ds_PA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_PA_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_PA_i <= (others => '0');
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH) = '1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH) = '1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(32-1 downto 0) <= DMA_ds_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_HA_i
RxTrn_DMA_ds_HA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_HA_i <= (others => '1');
dsHA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_HA_i <= (others => '1');
dsHA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= dsHA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_HA_i(32-1 downto 0) <= DMA_ds_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_BDA_i
Syn_Output_DMA_ds_BDA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_BDA_i <= (others => '0');
dsBDA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_BDA_i <= (others => '0');
dsBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= dsBDA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_BDA_i(32-1 downto 0) <= DMA_ds_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- Synchronous Registered: DMA_ds_Length_i
RxTrn_DMA_ds_Length :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Length_i <= (others => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_Length_i <= (others => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_ds_Length_i <= DMA_ds_Length_i;
dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True_i <= dsLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous ds_Param_Modified
SynReg_ds_Param_Modified :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
ds_Param_Modified <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1'
or dsDMA_Start_i = '1'
or dsDMA_Start2_i = '1'
then
ds_Param_Modified <= '0';
elsif Regs_WrEn_r2 = '1' and
(
-- Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
-- or
Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1'
)
then
ds_Param_Modified <= '1';
else
ds_Param_Modified <= ds_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Control_i
Syn_Output_DMA_ds_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Control_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2 = '1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1')
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_ds_Control_i <= Last_Ctrl_Word_ds;
else
DMA_ds_Control_i <= DMA_ds_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_ds
Hold_Last_Ctrl_Word_ds :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start_Stop
Syn_Output_DMA_ds_Start_Stop :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not dsDMA_Stop_i
and not Command_is_Reset_Hi
and ds_Param_Modified;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not dsDMA_Stop_i
and not Command_is_Reset_Lo
and ds_Param_Modified;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo;
elsif Regs_WrEnA_r2 = '1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1')
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
and ds_Param_Modified;
dsDMA_Stop_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack = '1'
then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= dsDMA_Stop_i;
else
dsDMA_Start_i <= dsDMA_Start_i;
dsDMA_Stop_i <= dsDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start2_Stop2
Syn_Output_DMA_ds_Start2_Stop2 :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack = '1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= dsDMA_Stop2_i;
else
dsDMA_Start2_i <= dsDMA_Start2_i;
dsDMA_Stop2_i <= dsDMA_Stop2_i;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Reset signals --
------------------------------------------------------------------------
-- --------------------------------------
-- Identification: Command_is_Reset
--
Synch_Capture_Command_is_Reset :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Command_is_Reset_Hi <= '0';
Command_is_Reset_Lo <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32) = C_CHANNEL_RST_BITS then
Command_is_Reset_Hi <= '1';
else
Command_is_Reset_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0) = C_CHANNEL_RST_BITS then
Command_is_Reset_Lo <= '1';
else
Command_is_Reset_Lo <= '0';
end if;
end if;
end process;
-- --------------------------------------
-- Identification: Command_is_Host_iClr
--
Synch_Capture_Command_is_Host_iClr :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Command_is_Host_iClr_Hi <= '0';
Command_is_Host_iClr_Lo <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32) = C_HOST_ICLR_BITS then
Command_is_Host_iClr_Hi <= '1';
else
Command_is_Host_iClr_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0) = C_HOST_ICLR_BITS then
Command_is_Host_iClr_Lo <= '1';
else
Command_is_Host_iClr_Lo <= '0';
end if;
end if;
end process;
-------------------------------------------
-- Synchronous output: usDMA_Channel_Rst_i
--
Syn_Output_usDMA_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or (Regs_Wr_dma_V_LO_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
);
end if;
end process;
-------------------------------------------
-- Synchronous output: dsDMA_Channel_Rst_i
--
Syn_Output_dsDMA_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or
(Regs_Wr_dma_V_Lo_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
);
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: MRd_Channel_Rst_i
--
Syn_Output_MRd_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
MRd_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
MRd_Channel_Rst_i <= Regs_WrEn_r2
and (
(Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Hi)
or
(Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Lo)
);
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: Tx_Reset_i
--
Syn_Output_Tx_Reset :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Tx_Reset_i <= '1';
elsif user_clk'event and user_clk = '1' then
Tx_Reset_i <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Lo));
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: wb_FIFO_Rst_i
--
Syn_Output_wb_FIFO_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
wb_FIFO_Rst_i <= '1';
wb_FIFO_Rst_b5 <= '1';
wb_FIFO_Rst_b4 <= '1';
wb_FIFO_Rst_b3 <= '1';
wb_FIFO_Rst_b2 <= '1';
wb_FIFO_Rst_b1 <= '1';
elsif user_clk'event and user_clk = '1' then
wb_FIFO_Rst_i <= wb_FIFO_Rst_b1 or wb_FIFO_Rst_b2 or wb_FIFO_Rst_b3 or wb_FIFO_Rst_b4 or wb_FIFO_Rst_b5;
wb_FIFO_Rst_b5 <= wb_FIFO_Rst_b4;
wb_FIFO_Rst_b4 <= wb_FIFO_Rst_b3;
wb_FIFO_Rst_b3 <= wb_FIFO_Rst_b2;
wb_FIFO_Rst_b2 <= wb_FIFO_Rst_b1;
wb_FIFO_Rst_b1 <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
and Command_is_Reset_Lo));
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_us_Transf_Bytes
--
Syn_Calc_DMA_us_Transf_Bytes :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Transf_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_Transf_Bytes_i <= (others => '0');
elsif us_DMA_Bytes_Add = '1' then
DMA_us_Transf_Bytes_i(32-1 downto 0) <= DMA_us_Transf_Bytes_i(32-1 downto 0) + us_DMA_Bytes;
else
DMA_us_Transf_Bytes_i <= DMA_us_Transf_Bytes_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_ds_Transf_Bytes
--
Syn_Calc_DMA_ds_Transf_Bytes :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Transf_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_Transf_Bytes_i <= (others => '0');
elsif ds_DMA_Bytes_Add = '1' then
DMA_ds_Transf_Bytes_i(32-1 downto 0) <= DMA_ds_Transf_Bytes_i(32-1 downto 0) + ds_DMA_Bytes;
else
DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i;
end if;
end if;
end process;
----------------------------------------------------------
--------------- Tx reading registers -------------------
----------------------------------------------------------
----------------------------------------------------------
-- Synch Register: Read Selection
--
Tx_DMA_Reg_RdMuxer :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Reg_RdMuxer_Hi <= (others => '0');
Reg_RdMuxer_Lo <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for k in 0 to C_NUM_OF_ADDRESSES-1 loop
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Hi(k) <= '1';
else
Reg_RdMuxer_Hi(k) <= '0';
end if;
end loop;
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Lo(0) <= '1';
else
Reg_RdMuxer_Lo(0) <= '0';
end if;
for k in 1 to C_NUM_OF_ADDRESSES-1 loop
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Lo(k) <= '1';
else
Reg_RdMuxer_Lo(k) <= '0';
end if;
end loop;
end if;
end process;
-- -------------------------------------------------------
--
Sys_Int_Status_i <= (
CINT_BIT_TX_DDR_TOUT_ISR => tx_timeout,
CINT_BIT_TX_WB_TOUT_ISR => tx_wb_timeout,
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout ,
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout ,
CINT_BIT_INTGEN_IN_ISR => IG_Asserting,
CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
others => '0'
);
--------------------------------------------------------------------------
-- Upstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH) = '1'
else (others => '0');
DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1'
else (others => '0');
DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1'
else (others => '0');
DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1'
else (others => '0');
-- Length
DMA_us_Length_o_Hi(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1'
else (others => '0');
-- Control word
DMA_us_Control_o_Hi(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_us_Status_o_Hi(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC) = '1'
else (others => '0');
-- Peripheral Address Start point
DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH) = '1'
else (others => '0');
DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1'
else (others => '0');
DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1'
else (others => '0');
DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1'
else (others => '0');
-- Length
DMA_us_Length_o_Lo(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1'
else (others => '0');
-- Control word
DMA_us_Control_o_Lo(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_us_Status_o_Lo(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Downstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH) = '1'
else (others => '0');
DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1'
else (others => '0');
DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1'
else (others => '0');
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1'
else (others => '0');
-- Length
DMA_ds_Length_o_Hi(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1'
else (others => '0');
-- Control word
DMA_ds_Control_o_Hi(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_ds_Status_o_Hi(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC) = '1'
else (others => '0');
-- Peripheral Address Start point
DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH) = '1'
else (others => '0');
DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1'
else (others => '0');
DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1'
else (others => '0');
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1'
else (others => '0');
-- Length
DMA_ds_Length_o_Lo(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1'
else (others => '0');
-- Control word
DMA_ds_Control_o_Lo(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_ds_Status_o_Lo(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- System Interrupt Status
--------------------------------------------------------------------------
Sys_Int_Status_o_Hi(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT) = '1'
else (others => '0');
Sys_Int_Enable_o_Hi(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN) = '1'
else (others => '0');
Sys_Int_Status_o_Lo(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT) = '1'
else (others => '0');
Sys_Int_Enable_o_Lo(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN) = '1'
else (others => '0');
-- ----------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------------
Gen_IG_Read : if IMP_INT_GENERATOR generate
--------------------------------------------------------------------------
-- Interrupt Generator Latency
--------------------------------------------------------------------------
IG_Latency_o_Hi(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
else (others => '0');
IG_Latency_o_Lo(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Interrupt Generator Statistics
--------------------------------------------------------------------------
IG_Num_Assert_o_Hi(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT) = '1'
else (others => '0');
IG_Num_Deassert_o_Hi(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT) = '1'
else (others => '0');
IG_Num_Assert_o_Lo(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT) = '1'
else (others => '0');
IG_Num_Deassert_o_Lo(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT) = '1'
else (others => '0');
end generate;
NotGen_IG_Read : if not IMP_INT_GENERATOR generate
IG_Latency_o_Hi(32-1 downto 0) <= (others => '0');
IG_Latency_o_Lo(32-1 downto 0) <= (others => '0');
IG_Num_Assert_o_Hi(32-1 downto 0) <= (others => '0');
IG_Num_Deassert_o_Hi(32-1 downto 0) <= (others => '0');
IG_Num_Assert_o_Lo(32-1 downto 0) <= (others => '0');
IG_Num_Deassert_o_Lo(32-1 downto 0) <= (others => '0');
end generate;
--------------------------------------------------------------------------
-- System Error
--------------------------------------------------------------------------
Synch_Sys_Error_i :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_Error_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER) <= Tx_TimeOut;
Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER) <= Tx_wb_TimeOut;
end if;
end process;
--------------------------------------------------------------------------
-- General Status and Control
--------------------------------------------------------------------------
Synch_General_Status_i :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
General_Status_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
General_Status_i(32-1 downto 32-16) <= cfg_dcommand;
General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT) <= pcie_link_width;
General_Status_i(CINT_BIT_DDR_RDY_GSR) <= ddr_sdram_ready;
end if;
end process;
Sys_Error_o_Hi(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR) = '1'
else (others => '0');
General_Status_o_Hi(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS) = '1'
else (others => '0');
General_Control_o_Hi(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL) = '1'
else (others => '0');
sdram_pg_o_hi
<= sdram_pg_i when Reg_RdMuxer_Hi(CINT_ADDR_SDRAM_PG) = '1'
else (others => '0');
wb_pg_o_hi
<= wb_pg_i when Reg_RdMuxer_Hi(CINT_ADDR_WB_PG) = '1'
else (others => '0');
Sys_Error_o_Lo(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR) = '1'
else (others => '0');
General_Status_o_Lo(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS) = '1'
else (others => '0');
General_Control_o_Lo(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL) = '1'
else (others => '0');
sdram_pg_o_lo
<= sdram_pg_i when Reg_RdMuxer_Lo(CINT_ADDR_SDRAM_PG) = '1'
else (others => '0');
wb_pg_o_lo
<= wb_pg_i when Reg_RdMuxer_Lo(CINT_ADDR_WB_PG) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Hardware version
--------------------------------------------------------------------------
HW_Version_o_Hi(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION) = '1'
else (others => '0');
HW_Version_o_Lo(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION) = '1'
else (others => '0');
-----------------------------------------------------
-- Sequential : Regs_RdQout_i
--
Synch_Regs_RdQout :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Regs_RdQout_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Regs_RdQout_i(64-1 downto 32) <=
HW_Version_o_Hi (32-1 downto 0)
or Sys_Error_o_Hi (32-1 downto 0)
or General_Status_o_Hi (32-1 downto 0)
or General_Control_o_Hi(32-1 downto 0)
or sdram_pg_o_hi(32-1 downto 0)
or wb_pg_o_hi(32-1 downto 0)
or Sys_Int_Status_o_Hi (32-1 downto 0)
or Sys_Int_Enable_o_Hi (32-1 downto 0)
-- or DMA_us_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Hi (32-1 downto 0)
or DMA_us_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Hi (32-1 downto 0)
or DMA_us_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Hi (32-1 downto 0)
or DMA_us_Length_o_Hi (32-1 downto 0)
or DMA_us_Control_o_Hi (32-1 downto 0)
or DMA_us_Status_o_Hi (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Hi (32-1 downto 0)
-- or DMA_ds_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Hi (32-1 downto 0)
or DMA_ds_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Hi (32-1 downto 0)
or DMA_ds_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Hi (32-1 downto 0)
or DMA_ds_Length_o_Hi (32-1 downto 0)
or DMA_ds_Control_o_Hi (32-1 downto 0)
or DMA_ds_Status_o_Hi (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Hi (32-1 downto 0)
or IG_Latency_o_Hi (32-1 downto 0)
or IG_Num_Assert_o_Hi (32-1 downto 0)
or IG_Num_Deassert_o_Hi(32-1 downto 0);
Regs_RdQout_i(32-1 downto 0) <=
HW_Version_o_Lo (32-1 downto 0)
or Sys_Error_o_Lo (32-1 downto 0)
or General_Status_o_Lo (32-1 downto 0)
or General_Control_o_Lo(32-1 downto 0)
or sdram_pg_o_lo(32-1 downto 0)
or wb_pg_o_lo(32-1 downto 0)
or Sys_Int_Status_o_Lo (32-1 downto 0)
or Sys_Int_Enable_o_Lo (32-1 downto 0)
-- or DMA_us_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Lo (32-1 downto 0)
or DMA_us_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Lo (32-1 downto 0)
or DMA_us_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Lo (32-1 downto 0)
or DMA_us_Length_o_Lo (32-1 downto 0)
or DMA_us_Control_o_Lo (32-1 downto 0)
or DMA_us_Status_o_Lo (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Lo (32-1 downto 0)
-- or DMA_ds_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Lo (32-1 downto 0)
or DMA_ds_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Lo (32-1 downto 0)
or DMA_ds_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Lo (32-1 downto 0)
or DMA_ds_Length_o_Lo (32-1 downto 0)
or DMA_ds_Control_o_Lo (32-1 downto 0)
or DMA_ds_Status_o_Lo (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Lo (32-1 downto 0)
or IG_Latency_o_Lo (32-1 downto 0)
or IG_Num_Assert_o_Lo (32-1 downto 0)
or IG_Num_Deassert_o_Lo(32-1 downto 0);
end if;
end process;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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arxhQ0C9zg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26080)
`protect data_block
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51sDMa9VJbej2XbZsuPAOqnyLQLfyXuRAVwckEOWYQ==
`protect end_protected
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bytefifoFPGA.vhd when simulating
-- the core, bytefifoFPGA. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE bytefifoFPGA_a OF bytefifoFPGA IS
-- synthesis translate_off
COMPONENT wrapped_bytefifoFPGA
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bytefifoFPGA USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 1,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32256,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32255,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bytefifoFPGA
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
underflow => underflow,
prog_full => prog_full
);
-- synthesis translate_on
END bytefifoFPGA_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bytefifoFPGA.vhd when simulating
-- the core, bytefifoFPGA. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE bytefifoFPGA_a OF bytefifoFPGA IS
-- synthesis translate_off
COMPONENT wrapped_bytefifoFPGA
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bytefifoFPGA USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 1,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32256,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32255,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bytefifoFPGA
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
underflow => underflow,
prog_full => prog_full
);
-- synthesis translate_on
END bytefifoFPGA_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bytefifoFPGA.vhd when simulating
-- the core, bytefifoFPGA. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE bytefifoFPGA_a OF bytefifoFPGA IS
-- synthesis translate_off
COMPONENT wrapped_bytefifoFPGA
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bytefifoFPGA USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 1,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32256,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32255,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bytefifoFPGA
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
underflow => underflow,
prog_full => prog_full
);
-- synthesis translate_on
END bytefifoFPGA_a;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - sawtooth.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Sawtooth wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity sawtooth is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end sawtooth;
architecture Behavioral of sawtooth is
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
saw <= x;
CALC_SAW : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
x <= x + incr;
if x > upper then
x <= lower;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_deglitcher |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_deglitcher.vhd |
-- |
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. |
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.03 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content |
-- 23/08/2010 v0.02 EG code cleaned-up+commented |
-- 14/02/2011 v0.03 EG complete change, no dependency on osc; |
-- fd_rxd deglitched right at reception |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deglitcher
--=================================================================================================
entity wf_rx_deglitcher is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; -- receiver data
-- OUTPUTS
-- Signals to the wf_rx_deserializer unit
fd_rxd_filt_o : out std_logic; -- filtered output signal
fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal
fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal
end wf_rx_deglitcher;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_deglitcher is
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic;
signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic;
signal s_filt_c : unsigned (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_RXD synchronization --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
-- FD_RXD to the uclk, using a set of 2 registers.
FD_RXD_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_rxd_synch <= (others => '0');
else
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Deglitching --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only
-- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits.
-- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
FD_RXD_deglitcher: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
s_fd_rxd_filt <= '0';
s_fd_rxd_filt_d1 <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if s_fd_rxd_synch(1) = '0' then -- arrival of a '0'
if s_filt_c /= 0 then -- counter updated
s_filt_c <= s_filt_c - 1;
else
s_fd_rxd_filt <= '0'; -- output updated
end if; -- if counter = 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1'
if s_filt_c /= c_DEGLITCH_THRESHOLD then
s_filt_c <= s_filt_c + 1; -- counter updated
else
s_fd_rxd_filt <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD
end if;
s_fd_rxd_filt_d1 <= s_fd_rxd_filt; -- used for the edges detection
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
s_fd_rxd_filt_r_edge_p <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection
-- of a falling edge
s_fd_rxd_filt_f_edge_p <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection
-- of a rising edge
fd_rxd_filt_edge_p_o <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p;
fd_rxd_filt_f_edge_p_o <= s_fd_rxd_filt_f_edge_p;
fd_rxd_filt_o <= s_fd_rxd_filt;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- |
-- this is use to initilize the I2C pass through configuration need to communicate with remote I2C devices.
-- this runs on the host PC side.
-- by: Jie (Jack) Zhang MWL-MIT
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity i2c_master_init is
port (
clk : in std_logic; --same clock for the i2c interface
reset : in std_logic;
busy : in std_logic;
ack_error : in std_logic;
i2c_ena_o : out std_logic;
rw_o : out std_logic;
device_id_o : out std_logic_vector(6 downto 0);
addr_o : out std_logic_vector(7 downto 0);
value_o : out std_logic_vector(7 downto 0);
user_rw : in std_logic;
user_device_id : in std_logic_vector(6 downto 0);
user_addr : in std_logic_vector(7 downto 0);
user_value : in std_logic_vector(7 downto 0)
);
end i2c_master_init;
architecture Behavioral of i2c_master_init is
--state machine
type init_sm_type is (IDLE, CONF, TX, ACKERR, CONFBUSY, TXBUSY);
signal init_sm, init_sm_next : init_sm_type;
--signals
signal addr, addr_next : std_logic_vector(7 downto 0);
signal value, value_next : std_logic_vector(7 downto 0);
signal device_id, device_id_next : std_logic_vector(6 downto 0);
signal i2c_ena, i2c_ena_next : std_logic;
signal rw, rw_next : std_logic;
--counters
signal confcnt, confcnt_next : unsigned(3 downto 0); --state counter
constant CONF_SIZE : integer := 6;
type addr_value_rom_type is array (0 to CONF_SIZE - 1) of std_logic_vector(7 downto 0);
type deviceid_rom_type is array (0 to CONF_SIZE - 1) of std_logic_vector(6 downto 0);
constant ADDR_ROM : addr_value_rom_type := (
"00100001", --0x21 (des)
"00000111", --0x7 (des) (serializer alias)
"00001000", --0x8 (des)
"00010000", --0x10 (des)
"00010001", --0x11 (ser)
"00010010" --0x12 (ser)
);
constant VALUE_ROM : addr_value_rom_type := (
"00010111", --7: I2C passthrough (1) 6:4 I2C SDA hold (001) 3:0 I2C filter depth (0111)
"10110000", --0x58<<1 ser alias
"10100000", --0x50<<1 slave device ID
"10100000", --0x50<<1 slave device alias
"01100100", --0x64 for 100KHz SCL rate (high time)
"01100100" --0x64 for 100KHz SCL rate (low time)
);
constant DEVICEID_ROM : deviceid_rom_type := (
"1100000", --"1100000": DES ID "1011000": SER ID
"1100000", --des
"1100000", --des
"1100000", --des
"1011000", --ser
"1011000" --ser
);
begin
device_id_o <= device_id;
addr_o <= addr;
value_o <= value;
i2c_ena_o <= i2c_ena;
rw_o <= rw;
init_proc : process (clk, reset)
begin
if (reset = '1') then
init_sm <= IDLE;
confcnt <= (others => '0');
addr <= (others => '0');
value <= (others => '0');
device_id <= (others => '0');
i2c_ena <= '0';
rw <= '0';
elsif (rising_edge(clk)) then
init_sm <= init_sm_next;
confcnt <= confcnt_next;
addr <= addr_next;
value <= value_next;
device_id <= device_id_next;
i2c_ena <= i2c_ena_next;
rw <= rw_next;
end if;
end process;
init_proc_next : process (clk, reset, rw, user_rw, init_sm, confcnt, i2c_ena, busy, ack_error, value, addr, device_id, user_addr, user_value, user_device_id)
begin
case init_sm is
when IDLE =>
if busy = '0' then
init_sm_next <= CONF;
else
init_sm_next <= IDLE;
end if;
i2c_ena_next <= '0';
confcnt_next <= (others => '0');
addr_next <= (others => '0');
value_next <= (others => '0');
device_id_next <= (others => '0');
rw_next <= '0';
when CONF =>
i2c_ena_next <= '1'; --assert i2c enable signal
rw_next <= '0'; --this is a write
confcnt_next <= confcnt;
if busy = '1' then
init_sm_next <= CONFBUSY;
else
init_sm_next <= CONF;
end if;
addr_next <= ADDR_ROM(to_integer(confcnt));
value_next <= VALUE_ROM(to_integer(confcnt));
device_id_next <= DEVICEID_ROM(to_integer(confcnt));
when CONFBUSY =>
i2c_ena_next <= '0'; --disable enable pin
rw_next <= rw;
if ack_error = '1' then
init_sm_next <= ACKERR;
confcnt_next <= confcnt; --do not increment this
elsif busy = '0' then --wait for busy go to low
if (confcnt = CONF_SIZE - 1) then
init_sm_next <= TX; --configuration is done
confcnt_next <= confcnt;
else
init_sm_next <= CONF; --continue other configuration
confcnt_next <= confcnt + 1; --increment the conf counter
end if;
else
init_sm_next <= CONFBUSY;
confcnt_next <= confcnt;
end if;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
when ACKERR =>
if busy = '0' then
init_sm_next <= CONF;
else
init_sm_next <= ACKERR;
end if;
confcnt_next <= confcnt;
i2c_ena_next <= i2c_ena;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
rw_next <= rw;
when TX =>
i2c_ena_next <= '1'; --assert i2c enable signal
confcnt_next <= confcnt;
if busy = '1' then
init_sm_next <= TXBUSY;
else
init_sm_next <= TX;
end if;
rw_next <= user_rw;
addr_next <= user_addr;
value_next <= user_value;
device_id_next <= user_device_id;
when TXBUSY =>
i2c_ena_next <= '0';
if busy = '0' then --wait for busy to drop low
init_sm_next <= TX;
else
init_sm_next <= TXBUSY;
end if;
rw_next <= rw;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
confcnt_next <= confcnt;
end case;
end process;
end Behavioral; |
--------------------------------------------------------------------------------------------------
-- Count Generator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package count_gen_pkg is
component count_gen is
generic( INIT_VAL : integer := 0;
STEP_VAL : integer := 1);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
count : out integer);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count_gen is
generic( INIT_VAL : integer := 0;
STEP_VAL : integer := 1);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
count : out integer);
end count_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of count_gen is
signal count_reg : integer := INIT_VAL;
begin
-- increment the count value when enabled.
counter : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
count_reg <= INIT_VAL;
elsif(en = '1') then
count_reg <= count_reg + STEP_VAL;
end if;
end if;
end process;
count <= count_reg;
end rtl;
|
-- Vhdl test bench created from schematic C:\Users\Carlo\Documents\documentos carlo\universidad de los andes\3er semestre\trabajos\Sistemas Digitales\practica4\estructural.sch - Tue Sep 13 14:11:02 2011
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY estructural_estructural_sch_tb IS
END estructural_estructural_sch_tb;
ARCHITECTURE behavioral OF estructural_estructural_sch_tb IS
COMPONENT estructural
PORT( boton_habilitador : IN STD_LOGIC;
led1 : IN STD_LOGIC;
led2 : IN STD_LOGIC;
led3 : IN STD_LOGIC;
led4 : IN STD_LOGIC;
led5 : IN STD_LOGIC;
led6 : IN STD_LOGIC;
led7 : IN STD_LOGIC;
D1A2 : OUT STD_LOGIC;
D1A1 : OUT STD_LOGIC;
D1A0 : OUT STD_LOGIC;
D2A0 : OUT STD_LOGIC;
D2A1 : OUT STD_LOGIC;
D2A2 : OUT STD_LOGIC;
RBO : OUT STD_LOGIC;
RBI : OUT STD_LOGIC;
D3A0 : OUT STD_LOGIC;
D3A1 : OUT STD_LOGIC;
D3A2 : OUT STD_LOGIC;
LED_TEST : OUT STD_LOGIC;
switch11 : IN STD_LOGIC;
switch12 : IN STD_LOGIC;
switch13 : IN STD_LOGIC;
switch21 : IN STD_LOGIC;
switch22 : IN STD_LOGIC;
switch23 : IN STD_LOGIC;
switch31 : IN STD_LOGIC;
switch32 : IN STD_LOGIC;
switch33 : IN STD_LOGIC);
END COMPONENT;
-- Entradas
SIGNAL boton_habilitador : STD_LOGIC :='0';
SIGNAL led1 : STD_LOGIC:='0';
SIGNAL led2 : STD_LOGIC:='0';
SIGNAL led3 : STD_LOGIC:='0';
SIGNAL led4 : STD_LOGIC:='0';
SIGNAL led5 : STD_LOGIC:='0';
SIGNAL led6 : STD_LOGIC:='0';
SIGNAL led7 : STD_LOGIC:='0';
SIGNAL switch11 : STD_LOGIC:='0';
SIGNAL switch12 : STD_LOGIC:='0';
SIGNAL switch13 : STD_LOGIC:='0';
SIGNAL switch21 : STD_LOGIC:='0';
SIGNAL switch22 : STD_LOGIC:='0';
SIGNAL switch23 : STD_LOGIC:='0';
SIGNAL switch31 : STD_LOGIC:='0';
SIGNAL switch32 : STD_LOGIC:='0';
SIGNAL switch33 : STD_LOGIC:='0';
-- Salidas
SIGNAL D1A2 : STD_LOGIC;
SIGNAL D1A1 : STD_LOGIC;
SIGNAL D1A0 : STD_LOGIC;
SIGNAL D2A0 : STD_LOGIC;
SIGNAL D2A1 : STD_LOGIC;
SIGNAL D2A2 : STD_LOGIC;
SIGNAL RBO : STD_LOGIC;
SIGNAL RBI : STD_LOGIC;
SIGNAL D3A0 : STD_LOGIC;
SIGNAL D3A1 : STD_LOGIC;
SIGNAL D3A2 : STD_LOGIC;
SIGNAL LED_TEST : STD_LOGIC;
BEGIN
UUT: estructural PORT MAP(
boton_habilitador => boton_habilitador,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4,
led5 => led5,
led6 => led6,
led7 => led7,
D1A2 => D1A2,
D1A1 => D1A1,
D1A0 => D1A0,
D2A0 => D2A0,
D2A1 => D2A1,
D2A2 => D2A2,
RBO => RBO,
RBI => RBI,
D3A0 => D3A0,
D3A1 => D3A1,
D3A2 => D3A2,
LED_TEST => LED_TEST,
switch11 => switch11,
switch12 => switch12,
switch13 => switch13,
switch21 => switch21,
switch22 => switch22,
switch23 => switch23,
switch31 => switch31,
switch32 => switch32,
switch33 => switch33
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
WAIT FOR 10 NS;
report "Entradas del dado (0101001)";
boton_habilitador <= '0';
led1 <= '0';
led2 <= '1';
led3 <= '0';
led4 <= '1';
led5 <= '0';
led6 <= '0';
led7 <= '1';
report "Num Oculto 231";
--**-- TURNO 1
report "Entradas jugador";
switch11 <= '0';
switch12 <= '1';
switch13 <= '0';
switch21 <= '1';
switch22 <= '1';
switch23 <= '0';
switch31 <= '0';
switch32 <= '1';
switch33 <= '1';
wait for 10 ns;
report "Num ingresado (263) -> 1 pica, 1 fija";
report "Probando funcionamiento display";
assert D1A2 = switch11 report "Display D1A2 no representa la entrada del jugador" severity WARNING;
assert D1A1 = switch12 report "Display D1A1 no representa la entrada del jugador" severity WARNING;
assert D1A0 = switch13 report "Display D1A0 no representa la entrada del jugador" severity WARNING;
assert D2A2 = switch21 report "Display D2A2 no representa la entrada del jugador" severity WARNING;
assert D2A1 = switch22 report "Display D2A1 no representa la entrada del jugador" severity WARNING;
assert D2A0 = switch23 report "Display D2A0 no representa la entrada del jugador" severity WARNING;
assert D3A2 = switch31 report "Display D3A2 no representa la entrada del jugador" severity WARNING;
assert D3A1 = switch32 report "Display D3A1 no representa la entrada del jugador" severity WARNING;
assert D3A0 = switch33 report "Display D3A0 no representa la entrada del jugador" severity WARNING;
assert RBO ='1' report "RBO debía ser 1" severity WARNING;
assert RBI ='1' report "RBI debía ser 1" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '1' report "El LED debía estar apagado";
report "Jugador pulsa boton habilitador (turno 1)";
WAIT FOR 10 NS;
boton_habilitador <= '1';
wait for 10 NS;
report "Probando resultados de picas y fijas";
assert D1A2 = '0' report "Display D1A2 debía mostrar 1 fijas" severity WARNING;
assert D1A1 = '0' report "Display D1A1 debía mostrar 1 fijas" severity WARNING;
assert D1A0 = '1' report "Display D1A0 debía mostrar 1 fijas" severity WARNING;
assert D2A2 = '0' report "Display D2A2 debía mostrar 1 picas" severity WARNING;
assert D2A1 = '0' report "Display D2A1 debía mostrar 1 picas" severity WARNING;
assert D2A0 = '1' report "Display D2A0 debía mostrar 1 picas" severity WARNING;
assert D3A2 = '0' report "Display D3A2 debía estar apagado" severity WARNING;
assert D3A1 = '0' report "Display D3A1 debía estar apagado" severity WARNING;
assert D3A0 = '0' report "Display D3A0 debía estar apagado" severity WARNING;
assert RBO ='0' report "RBO debía ser 0" severity WARNING;
assert RBI ='0' report "RBI debía ser 0" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '1' report "El LED debía estar apagado";
report "Jugador libera boton habilitador (fin turno 1)";
wait FOR 10 NS;
boton_habilitador <= '0';
wait for 10 NS;
--**-- TURNO 2
report "Jugador cambia las entradas";
switch11 <= '0';
switch12 <= '1';
switch13 <= '0';
switch21 <= '0';
switch22 <= '1';
switch23 <= '1';
switch31 <= '1';
switch32 <= '0';
switch33 <= '0';
wait for 10 ns;
report "Num ingresado (234) -> 0 picas, 2 fijas";
report "Probando funcionamiento display";
assert D1A2 = switch11 report "Display D1A2 no representa la entrada del jugador" severity WARNING;
assert D1A1 = switch12 report "Display D1A1 no representa la entrada del jugador" severity WARNING;
assert D1A0 = switch13 report "Display D1A0 no representa la entrada del jugador" severity WARNING;
assert D2A2 = switch21 report "Display D2A2 no representa la entrada del jugador" severity WARNING;
assert D2A1 = switch22 report "Display D2A1 no representa la entrada del jugador" severity WARNING;
assert D2A0 = switch23 report "Display D2A0 no representa la entrada del jugador" severity WARNING;
assert D3A2 = switch31 report "Display D3A2 no representa la entrada del jugador" severity WARNING;
assert D3A1 = switch32 report "Display D3A1 no representa la entrada del jugador" severity WARNING;
assert D3A0 = switch33 report "Display D3A0 no representa la entrada del jugador" severity WARNING;
assert RBO ='1' report "RBO debía ser 1" severity WARNING;
assert RBI ='1' report "RBI debía ser 1" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '1' report "El LED debía estar apagado";
report "Jugador pulsa boton habilitador (turno 2)";
WAIT FOR 10 NS;
boton_habilitador <= '1';
wait for 10 NS;
report "Probando resultados de picas y fijas";
assert D1A2 = '0' report "Display D1A2 debía mostrar 2 fijas" severity WARNING;
assert D1A1 = '1' report "Display D1A1 debía mostrar 2 fijas" severity WARNING;
assert D1A0 = '0' report "Display D1A0 debía mostrar 2 fijas" severity WARNING;
assert D2A2 = '0' report "Display D2A2 debía mostrar 0 picas" severity WARNING;
assert D2A1 = '0' report "Display D2A1 debía mostrar 0 picas" severity WARNING;
assert D2A0 = '0' report "Display D2A0 debía mostrar 0 picas" severity WARNING;
assert D3A2 = '0' report "Display D3A2 debía estar apagado" severity WARNING;
assert D3A1 = '0' report "Display D3A1 debía estar apagado" severity WARNING;
assert D3A0 = '0' report "Display D3A0 debía estar apagado" severity WARNING;
assert RBO ='0' report "RBO debía ser 0" severity WARNING;
assert RBI ='0' report "RBI debía ser 0" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '1' report "El LED debía estar apagado";
report "Jugador libera boton habilitador (fin turno 2)";
wait FOR 10 NS;
boton_habilitador <= '0';
wait for 10 NS;
--**-- TURNO 3 -- FIN DEL JUEGO
report "Jugador cambia las entradas";
switch11 <= '0';
switch12 <= '1';
switch13 <= '0';
switch21 <= '0';
switch22 <= '1';
switch23 <= '1';
switch31 <= '0';
switch32 <= '0';
switch33 <= '1';
wait for 10 ns;
report "Num ingresado (231) -> 0 picas, 3 fijas";
report "Probando funcionamiento display";
assert D1A2 = switch11 report "Display D1A2 no representa la entrada del jugador" severity WARNING;
assert D1A1 = switch12 report "Display D1A1 no representa la entrada del jugador" severity WARNING;
assert D1A0 = switch13 report "Display D1A0 no representa la entrada del jugador" severity WARNING;
assert D2A2 = switch21 report "Display D2A2 no representa la entrada del jugador" severity WARNING;
assert D2A1 = switch22 report "Display D2A1 no representa la entrada del jugador" severity WARNING;
assert D2A0 = switch23 report "Display D2A0 no representa la entrada del jugador" severity WARNING;
assert D3A2 = switch31 report "Display D3A2 no representa la entrada del jugador" severity WARNING;
assert D3A1 = switch32 report "Display D3A1 no representa la entrada del jugador" severity WARNING;
assert D3A0 = switch33 report "Display D3A0 no representa la entrada del jugador" severity WARNING;
assert RBO ='1' report "RBO debía ser 1" severity WARNING;
assert RBI ='1' report "RBI debía ser 1" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '0' report "El LED debía estar encendido";
report "Jugador pulsa boton habilitador (turno 3 -- FIN DEL JUEGO)";
WAIT FOR 10 NS;
boton_habilitador <= '1';
wait for 10 NS;
report "Probando resultados de picas y fijas";
assert D1A2 = '0' report "Display D1A2 debía mostrar 3 fijas" severity WARNING;
assert D1A1 = '1' report "Display D1A1 debía mostrar 3 fijas" severity WARNING;
assert D1A0 = '1' report "Display D1A0 debía mostrar 3 fijas" severity WARNING;
assert D2A2 = '0' report "Display D2A2 debía mostrar 0 picas" severity WARNING;
assert D2A1 = '0' report "Display D2A1 debía mostrar 0 picas" severity WARNING;
assert D2A0 = '0' report "Display D2A0 debía mostrar 0 picas" severity WARNING;
assert D3A2 = '0' report "Display D3A2 debía estar apagado" severity WARNING;
assert D3A1 = '0' report "Display D3A1 debía estar apagado" severity WARNING;
assert D3A0 = '0' report "Display D3A0 debía estar apagado" severity WARNING;
assert RBO ='0' report "RBO debía ser 0" severity WARNING;
assert RBI ='0' report "RBI debía ser 0" severity WARNING;
report "Probando funcionamiento LED";
assert LED_TEST = '0' report "El LED debía estar encendido";
report "Jugador libera boton habilitador (FIN DEL JUEGO)";
wait FOR 10 NS;
boton_habilitador <= '0';
wait for 10 NS;
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
entity test is
end entity test;
architecture beh of test is
type t_vvc_config is
record
clock_name : string(1 to 30);
end record;
signal vvc_config : t_vvc_config;
alias clock_name : string is vvc_config.clock_name;
begin
process
begin
vvc_config.clock_name <= (others => NUL);
clock_name <= (others => NUL);
wait;
end process;
end architecture beh;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity com1_pkg1_lib3 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com1_pkg1_lib3;
architecture RTL of com1_pkg1_lib3 is
begin
data_o <= data_i;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0ECC000"; -- multiple of 16K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
ethernet_enable : in std_logic := '1';
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
cart_logic : in std_logic_vector(3 downto 0); -- 1 out of 16 logic emulations
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ram_select : std_logic;
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal eth_addr : boolean;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(3 downto 0) := "0000";
constant c_8k : std_logic_vector(3 downto 0) := "0001";
constant c_16k : std_logic_vector(3 downto 0) := "0010";
constant c_16k_umax : std_logic_vector(3 downto 0) := "0011";
constant c_fc3 : std_logic_vector(3 downto 0) := "0100";
constant c_ss5 : std_logic_vector(3 downto 0) := "0101";
constant c_retro : std_logic_vector(3 downto 0) := "0110";
constant c_action : std_logic_vector(3 downto 0) := "0111";
constant c_system3 : std_logic_vector(3 downto 0) := "1000";
constant c_domark : std_logic_vector(3 downto 0) := "1001";
constant c_ocean128 : std_logic_vector(3 downto 0) := "1010";
constant c_ocean256 : std_logic_vector(3 downto 0) := "1011";
constant c_easy_flash : std_logic_vector(3 downto 0) := "1100";
constant c_epyx : std_logic_vector(3 downto 0) := "1110";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
begin
serve_enable <= cart_en or kernal_enable;
slot_addr <= std_logic_vector(slot_req.bus_address);
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
allow_bank <= '0';
ram_select <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
ram_select <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_retro | c_action =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(1)='0' then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
else -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
-- if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
-- cart_en <= '0'; -- permanent off
-- end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- decode address DE02-DE0F
eth_addr <= slot_addr(15 downto 4) = X"DE0" and slot_addr(3 downto 1) /= "000" and ethernet_enable='1';
-- determine address
-- process(cart_logic_d, cart_base_d, slot_addr, mode_bits, bank_bits, do_io2, allow_bank, eth_addr)
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank, eth_addr, kernal_area)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 32K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
when c_fc3 =>
mem_addr_i(15 downto 0) <= bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when others =>
null;
end case;
if kernal_area='1' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
end if;
-- if eth_addr then
-- mem_addr_i(25 downto 21) <= eth_base(25 downto 21);
-- mem_addr_i(20) <= '1'; -- indicate it is a slot access
-- allow_write <= '1'; -- we should also be able to write to the ethernet chip
-- -- invert bit 3
-- mem_addr_i(3) <= not slot_addr(3);
-- -- leave other bits in tact
-- end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
slot_resp.irq <= '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0ECC000"; -- multiple of 16K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
ethernet_enable : in std_logic := '1';
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
cart_logic : in std_logic_vector(3 downto 0); -- 1 out of 16 logic emulations
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ram_select : std_logic;
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal eth_addr : boolean;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(3 downto 0) := "0000";
constant c_8k : std_logic_vector(3 downto 0) := "0001";
constant c_16k : std_logic_vector(3 downto 0) := "0010";
constant c_16k_umax : std_logic_vector(3 downto 0) := "0011";
constant c_fc3 : std_logic_vector(3 downto 0) := "0100";
constant c_ss5 : std_logic_vector(3 downto 0) := "0101";
constant c_retro : std_logic_vector(3 downto 0) := "0110";
constant c_action : std_logic_vector(3 downto 0) := "0111";
constant c_system3 : std_logic_vector(3 downto 0) := "1000";
constant c_domark : std_logic_vector(3 downto 0) := "1001";
constant c_ocean128 : std_logic_vector(3 downto 0) := "1010";
constant c_ocean256 : std_logic_vector(3 downto 0) := "1011";
constant c_easy_flash : std_logic_vector(3 downto 0) := "1100";
constant c_epyx : std_logic_vector(3 downto 0) := "1110";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
begin
serve_enable <= cart_en or kernal_enable;
slot_addr <= std_logic_vector(slot_req.bus_address);
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
allow_bank <= '0';
ram_select <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
ram_select <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_retro | c_action =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(1)='0' then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
else -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
-- if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
-- cart_en <= '0'; -- permanent off
-- end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- decode address DE02-DE0F
eth_addr <= slot_addr(15 downto 4) = X"DE0" and slot_addr(3 downto 1) /= "000" and ethernet_enable='1';
-- determine address
-- process(cart_logic_d, cart_base_d, slot_addr, mode_bits, bank_bits, do_io2, allow_bank, eth_addr)
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank, eth_addr, kernal_area)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 32K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
when c_fc3 =>
mem_addr_i(15 downto 0) <= bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when others =>
null;
end case;
if kernal_area='1' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
end if;
-- if eth_addr then
-- mem_addr_i(25 downto 21) <= eth_base(25 downto 21);
-- mem_addr_i(20) <= '1'; -- indicate it is a slot access
-- allow_write <= '1'; -- we should also be able to write to the ethernet chip
-- -- invert bit 3
-- mem_addr_i(3) <= not slot_addr(3);
-- -- leave other bits in tact
-- end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
slot_resp.irq <= '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0ECC000"; -- multiple of 16K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
ethernet_enable : in std_logic := '1';
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
cart_logic : in std_logic_vector(3 downto 0); -- 1 out of 16 logic emulations
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ram_select : std_logic;
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal eth_addr : boolean;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(3 downto 0) := "0000";
constant c_8k : std_logic_vector(3 downto 0) := "0001";
constant c_16k : std_logic_vector(3 downto 0) := "0010";
constant c_16k_umax : std_logic_vector(3 downto 0) := "0011";
constant c_fc3 : std_logic_vector(3 downto 0) := "0100";
constant c_ss5 : std_logic_vector(3 downto 0) := "0101";
constant c_retro : std_logic_vector(3 downto 0) := "0110";
constant c_action : std_logic_vector(3 downto 0) := "0111";
constant c_system3 : std_logic_vector(3 downto 0) := "1000";
constant c_domark : std_logic_vector(3 downto 0) := "1001";
constant c_ocean128 : std_logic_vector(3 downto 0) := "1010";
constant c_ocean256 : std_logic_vector(3 downto 0) := "1011";
constant c_easy_flash : std_logic_vector(3 downto 0) := "1100";
constant c_epyx : std_logic_vector(3 downto 0) := "1110";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
begin
serve_enable <= cart_en or kernal_enable;
slot_addr <= std_logic_vector(slot_req.bus_address);
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
allow_bank <= '0';
ram_select <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
ram_select <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_retro | c_action =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(1)='0' then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
else -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
-- if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
-- cart_en <= '0'; -- permanent off
-- end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- decode address DE02-DE0F
eth_addr <= slot_addr(15 downto 4) = X"DE0" and slot_addr(3 downto 1) /= "000" and ethernet_enable='1';
-- determine address
-- process(cart_logic_d, cart_base_d, slot_addr, mode_bits, bank_bits, do_io2, allow_bank, eth_addr)
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank, eth_addr, kernal_area)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 32K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
when c_fc3 =>
mem_addr_i(15 downto 0) <= bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when others =>
null;
end case;
if kernal_area='1' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
end if;
-- if eth_addr then
-- mem_addr_i(25 downto 21) <= eth_base(25 downto 21);
-- mem_addr_i(20) <= '1'; -- indicate it is a slot access
-- allow_write <= '1'; -- we should also be able to write to the ethernet chip
-- -- invert bit 3
-- mem_addr_i(3) <= not slot_addr(3);
-- -- leave other bits in tact
-- end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
slot_resp.irq <= '0';
end gideon;
|
-------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
library verilog;
use verilog.vl_types.all;
entity ama_multiplier_function is
generic(
width_data_in_a : integer := 1;
width_data_in_b : integer := 1;
width_data_out : integer := 1;
number_of_multipliers: integer := 1;
multiplier_input_representation_a: string := "UNSIGNED";
multiplier_input_representation_b: string := "UNSIGNED";
multiplier_register0: string := "UNREGISTERED";
multiplier_register1: string := "UNREGISTERED";
multiplier_register2: string := "UNREGISTERED";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_aclr1: string := "NONE";
multiplier_aclr2: string := "NONE";
multiplier_aclr3: string := "NONE";
width_data_in_a_msb: vl_notype;
width_data_in_b_msb: vl_notype;
width_data_out_msb: vl_notype;
width_mult_input_a: vl_notype;
width_mult_input_a_msb: vl_notype;
width_mult_input_b: vl_notype;
width_mult_input_b_msb: vl_notype;
width_mult_output: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in_a0 : in vl_logic_vector;
data_in_a1 : in vl_logic_vector;
data_in_a2 : in vl_logic_vector;
data_in_a3 : in vl_logic_vector;
data_in_b0 : in vl_logic_vector;
data_in_b1 : in vl_logic_vector;
data_in_b2 : in vl_logic_vector;
data_in_b3 : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in_a : constant is 1;
attribute mti_svvh_generic_type of width_data_in_b : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_output : constant is 3;
end ama_multiplier_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_multiplier_function is
generic(
width_data_in_a : integer := 1;
width_data_in_b : integer := 1;
width_data_out : integer := 1;
number_of_multipliers: integer := 1;
multiplier_input_representation_a: string := "UNSIGNED";
multiplier_input_representation_b: string := "UNSIGNED";
multiplier_register0: string := "UNREGISTERED";
multiplier_register1: string := "UNREGISTERED";
multiplier_register2: string := "UNREGISTERED";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_aclr1: string := "NONE";
multiplier_aclr2: string := "NONE";
multiplier_aclr3: string := "NONE";
width_data_in_a_msb: vl_notype;
width_data_in_b_msb: vl_notype;
width_data_out_msb: vl_notype;
width_mult_input_a: vl_notype;
width_mult_input_a_msb: vl_notype;
width_mult_input_b: vl_notype;
width_mult_input_b_msb: vl_notype;
width_mult_output: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in_a0 : in vl_logic_vector;
data_in_a1 : in vl_logic_vector;
data_in_a2 : in vl_logic_vector;
data_in_a3 : in vl_logic_vector;
data_in_b0 : in vl_logic_vector;
data_in_b1 : in vl_logic_vector;
data_in_b2 : in vl_logic_vector;
data_in_b3 : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in_a : constant is 1;
attribute mti_svvh_generic_type of width_data_in_b : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_output : constant is 3;
end ama_multiplier_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_multiplier_function is
generic(
width_data_in_a : integer := 1;
width_data_in_b : integer := 1;
width_data_out : integer := 1;
number_of_multipliers: integer := 1;
multiplier_input_representation_a: string := "UNSIGNED";
multiplier_input_representation_b: string := "UNSIGNED";
multiplier_register0: string := "UNREGISTERED";
multiplier_register1: string := "UNREGISTERED";
multiplier_register2: string := "UNREGISTERED";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_aclr1: string := "NONE";
multiplier_aclr2: string := "NONE";
multiplier_aclr3: string := "NONE";
width_data_in_a_msb: vl_notype;
width_data_in_b_msb: vl_notype;
width_data_out_msb: vl_notype;
width_mult_input_a: vl_notype;
width_mult_input_a_msb: vl_notype;
width_mult_input_b: vl_notype;
width_mult_input_b_msb: vl_notype;
width_mult_output: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in_a0 : in vl_logic_vector;
data_in_a1 : in vl_logic_vector;
data_in_a2 : in vl_logic_vector;
data_in_a3 : in vl_logic_vector;
data_in_b0 : in vl_logic_vector;
data_in_b1 : in vl_logic_vector;
data_in_b2 : in vl_logic_vector;
data_in_b3 : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in_a : constant is 1;
attribute mti_svvh_generic_type of width_data_in_b : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_output : constant is 3;
end ama_multiplier_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_multiplier_function is
generic(
width_data_in_a : integer := 1;
width_data_in_b : integer := 1;
width_data_out : integer := 1;
number_of_multipliers: integer := 1;
multiplier_input_representation_a: string := "UNSIGNED";
multiplier_input_representation_b: string := "UNSIGNED";
multiplier_register0: string := "UNREGISTERED";
multiplier_register1: string := "UNREGISTERED";
multiplier_register2: string := "UNREGISTERED";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_aclr1: string := "NONE";
multiplier_aclr2: string := "NONE";
multiplier_aclr3: string := "NONE";
width_data_in_a_msb: vl_notype;
width_data_in_b_msb: vl_notype;
width_data_out_msb: vl_notype;
width_mult_input_a: vl_notype;
width_mult_input_a_msb: vl_notype;
width_mult_input_b: vl_notype;
width_mult_input_b_msb: vl_notype;
width_mult_output: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in_a0 : in vl_logic_vector;
data_in_a1 : in vl_logic_vector;
data_in_a2 : in vl_logic_vector;
data_in_a3 : in vl_logic_vector;
data_in_b0 : in vl_logic_vector;
data_in_b1 : in vl_logic_vector;
data_in_b2 : in vl_logic_vector;
data_in_b3 : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in_a : constant is 1;
attribute mti_svvh_generic_type of width_data_in_b : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_output : constant is 3;
end ama_multiplier_function;
|
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