content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use IEEE.std_logic_arith.conv_unsigned;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.macro.all;
use work.tech_map.all;
use work.amba.all;
entity mctrl is
port (
rst : in rst_type;
clk : in clk_type;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
pioo : in pio_out_type;
wpo : in wprot_out_type;
mctrlo : out mctrl_out_type
);
end;
architecture rtl of mctrl is
type areatype is (rom, io, ram);
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
extlatch : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
wren : std_logic;
bdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(3 downto 0);
ramoen : std_logic_vector(3 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
psel : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : areatype;
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
rmw : std_logic;
brmw : std_logic;
hsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal promdata : std_logic_vector(31 downto 0); -- data from boot-prom
begin
ctrl : process(rst, ahbsi, apbi, memi, r, pioo, promdata, wpo
)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(3 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : areatype;
variable bdrive, ramsn : std_logic_vector(3 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bpsel : std_logic;
variable psel : std_logic;
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.wren := '0'; v.echeck := '0'; bpsel := '0';
v.rmw := '0'; merrtype := "---"; bready := '1';
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((not r.brdyn) or not r.mcfg1.brdyen) = '1') or (r.area /= io) then
bready := '1';
else bready := '0'; end if;
v.hresp := HRESP_OKAY;
-- decode memory area parameters
case ahbsi.haddr(30 downto 28) is
when "000" | "001" => area := rom;
when "010" | "011" => area := io;
when others => area := ram;
end case;
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
case area is
when rom =>
busw := r.mcfg1.romwidth;
when ram =>
adec := genmux(r.mcfg2.rambanksz, ahbsi.haddr(29 downto 14)) &
genmux(r.mcfg2.rambanksz, ahbsi.haddr(28 downto 13));
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and ahbsi.hwrite) = '1') and
((BUS16EN and (busw = "01") and (ahbsi.hsize(1 downto 0) = "00")) or
((busw(1) = '1') and (ahbsi.hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
when io =>
leadin := '1';
busw := r.mcfg1.iowidth;
when others =>
end case;
-- decode waitstates and illegal access
case r.area is
when rom =>
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
when ram =>
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
when io =>
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
when others => null;
end case;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := decode(adec);
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
psel := '1'; v.psel(1) := r.psel(0);
case area is
when rom =>
if ((BOOTOPT = memory) or ((BOOTOPT = dual) and (pioo.io8lsb(4) = '0'))) then
romsn(0) := ahbsi.haddr(28);
else psel := ahbsi.haddr(28); end if;
romsn(1) := not ahbsi.haddr(28);
when ram => ramsn := not rams;
when io => iosn := '0';
when others => null;
end case;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area = ram) then wrn := not bdrive; end if;
if ((ahbsi.hready and ahbsi.hsel) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.area := area;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
v.address := ahbsi.haddr; v.psel(0) := psel;
if (busw = "00") and (ahbsi.hwrite = '0') and (area /= io) and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (ahbsi.hwrite = '0') and (area /= io) and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not ahbsi.hwrite; end if;
v.hwrite := ahbsi.hwrite;
v.busw := busw; v.brmw := brmw;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '0' then
if r.busw(1) = '1' then v.writedata := writedata;
else
v.writedata(31 downto 16) := writedata(31 downto 16);
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if r.hsel = '1' then
wprothitx := wpo.wprothit and not r.read;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr;
elsif r.read = '0' then
if (r.busw = "00") and (r.area /= io) and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area /= io) and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area /= io) and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area /= io) and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; v.hsel := '0'; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.psel(0) := '1';
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or (r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.hsel := '0'; v.psel(0) := '1';
else v.echeck := '1'; end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
v.psel(0) := '1';
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
-- v.writedata(31 downto 8) := r.writedata(23 downto 0);
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
v.psel(0) := '1';
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '0'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel;
v.psel(0) := '1';
elsif ahbsi.hsel = '1' then
v.romsn := romsn; v.ramsn := ramsn; v.iosn := iosn & '1'; v.hsel := '1';
v.psel(0) := psel;
if v.read = '1' then v.ramoen := ramsn; v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR;
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
r.mcfg1.extlatch &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
regsd(12 downto 0) := r.mcfg2.rambanksz & "00" & r.mcfg2.rmw &
r.mcfg2.ramwidth & r.mcfg2.ramwws & r.mcfg2.ramrws;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.extlatch := apbi.pwdata(18);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
when others => null;
end case;
end if;
-- select appropriate data during reads
case r.area is
when rom | ram =>
dataout := memdata;
if (r.area = rom) and (BOOTOPT /= memory) then
if (r.psel(0) = '0') then v.readdata := promdata; end if;
if r.psel(1) = '0' then dataout := r.readdata; end if;
end if;
when others =>
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end case;
v.ready := ready;
-- generate memory address
if RAWADDR and (r.mcfg1.extlatch = '1') then
memo.address <= v.address(27 downto 0);
else
memo.address <= r.address(27 downto 0);
end if;
-- use d(15:0) as I/O ports (only usefull in 8/16-bit mode)
if BUS8EN or BUS16EN then
mctrlo.pioh <= r.data(15 downto 0);
if (r.mcfg1.romwidth(1) or r.mcfg1.iowidth(1) or r.mcfg2.ramwidth(1)) = '0' then
v.writedata(15 downto 0) := r.writedata(15 downto 0);
if pioo.wrio = '1' then
v.writedata(15 downto 0) := pioo.piol(31 downto 16);
end if;
v.wrn(3 downto 2) := "11";
v.bdrive(3 downto 2) := not pioo.piodir(17 downto 16);
end if;
else mctrlo.pioh <= (others => '0'); end if;
-- reset
if rst.syncrst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.extlatch := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
if ((BOOTOPT = memory) or ((BOOTOPT = dual) and (pioo.io8lsb(4) = '0')))
then
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := pioo.io8lsb(1 downto 0);
else
v.mcfg2.ramrws := std_logic_vector(BRAMRWS(1 downto 0));
v.mcfg2.ramwws := std_logic_vector(BRAMWWS(1 downto 0));
v.mcfg1.romrws := "0001";
v.mcfg1.romwws := "0001";
v.mcfg1.romwidth := "11";
end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- drive various register inputs and external outputs
ri <= v;
memo.ramsn <= r.ramsn;
memo.ramoen <= r.ramoen;
memo.romsn <= r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.bdrive <= (not r.bdrive) and memi.wrn;
memo.data <= r.writedata;
ahbso.hrdata <= dataout;
ahbso.hready <= r.ready and noerror;
ahbso.hresp <= r.hresp;
ahbso.hsplit <= (others => '0');
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; end if;
if rst.rawrst = '0' then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.bdrive <= (others => '0');
r.iosn <= "11"; r.ramoen <= (others => '1');
end if;
end process;
-- optional boot-prom
promgen : if (BOOTOPT /= memory) generate
bprom0 : bprom port map
(clk => clk, cs => r.psel(0), addr => r.address, data => promdata);
end generate;
end;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
READ_ARGS_4,
READ_ARGS_5,
WHILE_1,
WHILE_2,
WHILE_3,
DO_1,
DO_2,
DO_3,
DO_4,
DO_5,
DO_6,
DONE_1,
DONE_2,
DONE_3,
DONE_4,
MUL_A1,
MUL_A2,
MUL_A3,
MUL_B1,
MUL_B2,
MUL_B3,
MUL_C1,
MUL_C2,
MUL_C3,
MUL_D1,
MUL_D2,
MUL_D3,
MUL_E1,
MUL_E2,
MUL_E3,
MUL_F1,
MUL_F2,
MUL_F3,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant Z16 : std_logic_vector(0 to 15) := (others => '0');
constant ROUNDS: std_logic_vector(0 to 15) := x"0008";
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal inPtr, inPtr_next : std_logic_vector(0 to 31);
signal outPtr, outPtr_next : std_logic_vector(0 to 31);
signal zPtr, zPtr_next : std_logic_vector(0 to 31);
signal origZPtr, origZPtr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
signal t32, t32_next : std_logic_vector(0 to 31);
signal x1, x1_next : std_logic_vector(0 to 15);
signal x2, x2_next : std_logic_vector(0 to 15);
signal x3, x3_next : std_logic_vector(0 to 15);
signal x4, x4_next : std_logic_vector(0 to 15);
signal t1, t1_next : std_logic_vector(0 to 15);
signal t2, t2_next : std_logic_vector(0 to 15);
signal r, r_next : std_logic_vector(0 to 15);
signal a, a_next : std_logic_vector(0 to 15);
signal b, b_next : std_logic_vector(0 to 15);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
inPtr <= inPtr_next;
outPtr <= outPtr_next;
zPtr <= zPtr_next;
origZPtr <= origZPtr_next;
count <= count_next;
t32 <= t32_next;
x1 <= x1_next;
x2 <= x2_next;
x3 <= x3_next;
x4 <= x4_next;
t1 <= t1_next;
t2 <= t2_next;
r <= r_next;
a <= a_next;
b <= b_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
inPtr_next <= inPtr;
outPtr_next <= outPtr;
zPtr_next <= zPtr;
origZPtr_next <= origZPtr;
count_next <= count;
t32_next <= t32;
x1_next <= x1;
x2_next <= x2;
x3_next <= x3;
x4_next <= x4;
t1_next <= t1;
t2_next <= t2;
r_next <= r;
a_next <= a;
b_next <= b;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
inPtr_next <= Z32;
outPtr_next <= Z32;
zPtr_next <= Z32;
origZPtr_next <= Z32;
count_next <= count;
t32_next <= Z32;
x1_next <= Z16;
x2_next <= Z16;
x3_next <= Z16;
x4_next <= Z16;
t1_next <= Z16;
t2_next <= Z16;
r_next <= Z16;
a_next <= Z16;
b_next <= Z16;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Read the inPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
when READ_ARGS_2 =>
inPtr_next <= toUser_value;
-- Read the outPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
when READ_ARGS_3 =>
outPtr_next <= toUser_value;
-- Read count
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
return_state_next <= READ_ARGS_4;
next_state <= WAIT_STATE;
when READ_ARGS_4 =>
count_next <= toUser_value;
-- Read address of z
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
return_state_next <= READ_ARGS_5;
next_state <= WAIT_STATE;
when READ_ARGS_5 =>
origZPtr_next <= toUser_value;
next_state <= WHILE_1;
-- while ( count > 0 ) {
-- Z = origZ;
-- r = ROUNDS;
-- count--;
-- x1 = *inPtr++;
-- x2 = *inPtr++;
when WHILE_1 =>
case count is
when x"00000000" =>
next_state <= EXIT_THREAD;
when others =>
count_next <= count - x"00000001";
r_next <= ROUNDS;
zPtr_next <= origZPtr;
-- Read first 32 bits of inPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inPtr;
-- increment inPtr
inPtr_next <= inPtr + x"00000004";
return_state_next <= WHILE_2;
next_state <= WAIT_STATE;
end case;
-- x3 = *inPtr++;
-- x4 = *inPtr;
when WHILE_2 =>
x1_next <= toUser_value(0 to 15);
x2_next <= toUser_value(16 to 31);
-- Read second 32 bits of inPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inPtr;
-- increment inPtr
inPtr_next <= inPtr + x"00000004";
return_state_next <= WHILE_3;
next_state <= WAIT_STATE;
when WHILE_3 =>
x3_next <= toUser_value(0 to 15);
x4_next <= toUser_value(16 to 31);
next_state <= DO_1;
when DO_1 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_A1;
next_state <= WAIT_STATE;
-- MUL(x1, *Z++)
-- x2 += *Z++
when MUL_A1 =>
a_next <= x1;
b_next <= toUser_value(0 to 15);
x2_next <= x2 + toUser_value(16 to 31);
next_state <= MUL_A2;
when MUL_A2 =>
case a is
when x"0000" =>
x1_next <= x"0001" - b;
next_state <= DO_2;
when others =>
case b is
when x"0000" =>
x1_next <= x"0001" - a;
next_state <= DO_2;
when others =>
t32_next <= a * b;
next_state <= MUL_A3;
end case;
end case;
when MUL_A3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_2;
else
x1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_2;
end if;
-- x3 += *Z++
-- MUL(x4, *Z++ );
when DO_2 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_B1;
next_state <= WAIT_STATE;
when MUL_B1 =>
x3_next <= x3 + toUser_value(0 to 15);
a_next <= x4;
b_next <= toUser_value(16 to 31);
next_state <= MUL_B2;
when MUL_B2 =>
case a is
when x"0000" =>
x4_next <= x"0001" - b;
next_state <= DO_3;
when others =>
case b is
when x"0000" =>
x4_next <= x"0001" - a;
next_state <= DO_3;
when others =>
t32_next <= a * b;
next_state <= MUL_B3;
end case;
end case;
when MUL_B3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x4_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_3;
else
x4_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_3;
end if;
-- t2 = x1^x3;
-- MUL( t2, *Z++ );
-- t1 = t2 + ( x2^x4 );
-- MUL( t1, *Z++ );
when DO_3 =>
t2_next <= x1 xor x3;
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_C1;
next_state <= WAIT_STATE;
when MUL_C1 =>
a_next <= t2;
b_next <= toUser_value(0 to 15);
next_state <= MUL_C2;
when MUL_C2 =>
case a is
when x"0000" =>
t2_next <= x"0001" - b;
next_state <= MUL_D1;
when others =>
case b is
when x"0000" =>
t2_next <= x"0001" - a;
next_state <= MUL_D1;
when others =>
t32_next <= a * b;
next_state <= MUL_C3;
end case;
end case;
when MUL_C3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
t2_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= MUL_D1;
else
t2_next <= t32(16 to 31) - t32(0 to 15);
next_state <= MUL_D1;
end if;
when MUL_D1 =>
a_next <= t2 + (x2 xor x4);
b_next <= toUser_value(16 to 31);
next_state <= MUL_D2;
when MUL_D2 =>
case a is
when x"0000" =>
t1_next <= x"0001" - b;
next_state <= DO_4;
when others =>
case b is
when x"0000" =>
t1_next <= x"0001" - a;
next_state <= DO_4;
when others =>
t32_next <= a * b;
next_state <= MUL_D3;
end case;
end case;
when MUL_D3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
t1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_4;
else
t1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_4;
end if;
-- t2 = t1+t2;
-- x1 ^= t1;
when DO_4 =>
t2_next <= t1 + t2;
x1_next <= x1 xor t1;
next_state <= DO_5;
-- x4 ^= t2;
-- t2 ^= x2;
when DO_5 =>
x4_next <= x4 xor t2;
t2_next <= t2 xor x2;
next_state <= DO_6;
-- x2 = x3^t1;
-- x3 = t2;
-- while (--r);
when DO_6 =>
x2_next <= x3 xor t1;
x3_next <= t2;
case r is
when x"0001" =>
next_state <= DONE_1;
when others =>
r_next <= r - x"0001";
next_state <= DO_1;
end case;
-- MUL(x1, *Z++);
-- out++ = x1;
-- out++ = x3 + *Z++;
when DONE_1 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_E1;
next_state <= WAIT_STATE;
when MUL_E1 =>
a_next <= x1;
b_next <= toUser_value(0 to 15);
next_state <= MUL_E2;
when MUL_E2 =>
case a is
when x"0000" =>
x1_next <= x"0001" - b;
next_state <= DONE_2;
when others =>
case b is
when x"0000" =>
x1_next <= x"0001" - a;
next_state <= DONE_2;
when others =>
t32_next <= a * b;
next_state <= MUL_E3;
end case;
end case;
when MUL_E3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DONE_2;
else
x1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DONE_2;
end if;
when DONE_2 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= outPtr;
thrd2intrfc_value <= x1 & (x3 + toUser_value(16 to 31));
outPtr_next <= outPtr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= DONE_3;
-- *out++ = x2 + *Z++;
-- MUL(x4, *Z);
-- *out = x4;
when DONE_3 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
return_state_next <= MUL_F1;
next_state <= WAIT_STATE;
when MUL_F1 =>
a_next <= x4;
b_next <= toUser_value(16 to 31);
next_state <= MUL_F2;
when MUL_F2 =>
case a is
when x"0000" =>
x4_next <= x"0001" - b;
next_state <= DONE_4;
when others =>
case b is
when x"0000" =>
x4_next <= x"0001" - a;
next_state <= DONE_4;
when others =>
t32_next <= a * b;
next_state <= MUL_F3;
end case;
end case;
when MUL_F3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x4_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DONE_4;
else
x4_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DONE_4;
end if;
when DONE_4 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= outPtr;
thrd2intrfc_value <= (x2 + toUser_value(0 to 15)) & x4;
outPtr_next <= outPtr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_1;
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2019-01-27
-- Author: Gideon
-- Description: Testcase 8 for USB host
-- This testcase verfies the correct behavior of the short packets
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano8 is
generic (
g_report_file_name : string := "work/usb_test_nano8.rpt"
);
end entity;
architecture arch of usb_test_nano8 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
signal nyet_count : natural := 2;
signal ack_on_ping : boolean := true;
signal transfer_size : natural := 256;
signal packet_size : natural := 256;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
ack_on_ping => ack_on_ping,
nyet_count => nyet_count,
interrupt => interrupt,
transfer_size => transfer_size,
packet_size => packet_size,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable data, remain, newcmd : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable pipe : integer;
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0); timeout : time; new_cmd, remain : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
variable cmd : std_logic_vector(15 downto 0);
variable res : std_logic_vector(15 downto 0);
variable len : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1' for timeout;
if interrupt = '0' then
sctb_trace("Timeout waiting for interrupt.");
result := X"FFFF";
return;
end if;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
io_read_word(addr => Command, word => cmd);
io_read_word(addr => Command_Result, word => res);
io_read_word(addr => Command_Length, word => len);
sctb_trace("Fifo read: " & hstr(data) & ", Command: " & hstr(cmd) & ", Result: " & hstr(res) & ", Remaining: " & hstr(len));
result := res;
new_cmd := cmd;
remain := len;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path:path", g_report_file_name);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
sctb_open_region("Testing an in packet in high speed, transfer size = packet_size", 0);
transfer_size <= 16;
packet_size <= 16;
write_memory_8(mem, X"00050000", X"11");
write_memory_8(mem, X"00050001", X"22");
write_memory_8(mem, X"00050002", X"33");
write_memory_8(mem, X"00050003", X"44");
write_memory_8(mem, X"00050004", X"55");
write_memory_8(mem, X"00050005", X"66");
write_memory_8(mem, X"00050006", X"77");
write_memory_8(mem, X"00050007", X"88");
io_write_word(Command_SplitCtl, X"8131"); -- Hub Address 1, Port 2, Speed = FS, EP = control
--io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_DevEP, X"0004");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Length, X"0010");
io_write_word(Command_MemHi, X"0005");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_Interval, X"0000");
io_write_word(Command_Timeout, X"001A");
io_write_word(c_nano_numpipes, X"0001" ); -- Set active pipes to 1
--io_write_word(Command, X"8041"); -- output
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 02 = IN
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"8010", "Unexpected result. Expected data packet of 16 bytes.");
sctb_check(remain, X"0000", "Expected all data to be transferred.");
sctb_check(newcmd, X"4A42", "Expected toggle bit to be set.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet in high speed, transfer size < packet_size. Note, we start with DATA 1!", 0);
--io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
transfer_size <= 8;
packet_size <= 16;
io_write_word(Command_MaxTrans, X"0008");
io_write_word(Command_Length, X"0011");
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4842"); -- 4000 = write to memory, 40 = Do Data, 02 = IN, 800 = toggle is 1
read_attr_fifo(data, 2.5 ms, newcmd, remain);
sctb_check(data and X"F7FF", X"8400", "Unexpected result. Expected data packet of 0 bytes in the last transfer.");
sctb_check(remain, X"0001", "Expected one data byte to be left.");
sctb_check(newcmd, X"4242", "Expected toggle bit to be cleared.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet in high speed, transfer size > packet_size. Note, we start with DATA 0!", 0);
--io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
transfer_size <= 32;
packet_size <= 22;
io_write_word(Command_MaxTrans, X"0020");
io_write_word(Command_Length, X"0020");
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 02 = IN,
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data and X"F7FF", X"8016", "Unexpected result. Expected data packet of 16 bytes in the last transfer.");
sctb_check(remain, X"000A", "Expected 10 bytes to be left.");
sctb_check(newcmd, X"4A42", "Expected toggle bit to be set.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
-- restart; mem load -infile nano_code.hex -format hex /usb_test_nano7/i_harness/i_host/i_nano/i_buf_ram/mem; run 20 ms |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AND3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end AND3;
architecture AND3 of AND3 is
begin
Z<= A and B and C;
end AND3; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AND3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end AND3;
architecture AND3 of AND3 is
begin
Z<= A and B and C;
end AND3; |
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: sigport-c.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: sigport-c.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_a_RTL_CONF / ent_a
--
configuration ent_a_RTL_CONF of ent_a is
for rtl
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_RTL_CONF;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_RTL_CONF;
end for;
for inst_ac : ent_ac
use configuration work.ent_ac_RTL_CONF;
end for;
for inst_ad : ent_ad
use configuration work.ent_ad_RTL_CONF;
end for;
for inst_ae : ent_ae
use configuration work.ent_ae_RTL_CONF;
end for;
end for;
end ent_a_RTL_CONF;
--
-- End of Generated Configuration ent_a_RTL_CONF
--
--
-- Start of Generated Configuration ent_aa_RTL_CONF / ent_aa
--
configuration ent_aa_RTL_CONF of ent_aa is
for rtl
-- Generated Configuration
end for;
end ent_aa_RTL_CONF;
--
-- End of Generated Configuration ent_aa_RTL_CONF
--
--
-- Start of Generated Configuration ent_ab_RTL_CONF / ent_ab
--
configuration ent_ab_RTL_CONF of ent_ab is
for rtl
-- Generated Configuration
end for;
end ent_ab_RTL_CONF;
--
-- End of Generated Configuration ent_ab_RTL_CONF
--
--
-- Start of Generated Configuration ent_ac_RTL_CONF / ent_ac
--
configuration ent_ac_RTL_CONF of ent_ac is
for rtl
-- Generated Configuration
end for;
end ent_ac_RTL_CONF;
--
-- End of Generated Configuration ent_ac_RTL_CONF
--
--
-- Start of Generated Configuration ent_ad_RTL_CONF / ent_ad
--
configuration ent_ad_RTL_CONF of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_RTL_CONF;
--
-- End of Generated Configuration ent_ad_RTL_CONF
--
--
-- Start of Generated Configuration ent_ae_RTL_CONF / ent_ae
--
configuration ent_ae_RTL_CONF of ent_ae is
for rtl
-- Generated Configuration
end for;
end ent_ae_RTL_CONF;
--
-- End of Generated Configuration ent_ae_RTL_CONF
--
--
-- Start of Generated Configuration ent_b_RTL_CONF / ent_b
--
configuration ent_b_RTL_CONF of ent_b is
for rtl
-- Generated Configuration
// __I_NO_CONFIG_VERILOG //for inst_ba : ent_ba
// __I_NO_CONFIG_VERILOG // use configuration work.ent_ba_RTL_CONF;
// __I_NO_CONFIG_VERILOG //end for;
// __I_NO_CONFIG_VERILOG //for inst_bb : ent_bb
// __I_NO_CONFIG_VERILOG // use configuration work.ent_bb_RTL_CONF;
// __I_NO_CONFIG_VERILOG //end for;
end for;
end ent_b_RTL_CONF;
--
-- End of Generated Configuration ent_b_RTL_CONF
--
--
-- Start of Generated Configuration ent_ba_RTL_CONF / ent_ba
--
configuration ent_ba_RTL_CONF of ent_ba is
for rtl
-- Generated Configuration
end for;
end ent_ba_RTL_CONF;
--
-- End of Generated Configuration ent_ba_RTL_CONF
--
--
-- Start of Generated Configuration ent_bb_RTL_CONF / ent_bb
--
configuration ent_bb_RTL_CONF of ent_bb is
for rtl
-- Generated Configuration
end for;
end ent_bb_RTL_CONF;
--
-- End of Generated Configuration ent_bb_RTL_CONF
--
--
-- Start of Generated Configuration ent_t_RTL_CONF / ent_t
--
configuration ent_t_RTL_CONF of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_RTL_CONF;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_b : ent_b
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_b_RTL_CONF;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_t_RTL_CONF;
--
-- End of Generated Configuration ent_t_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal Switch : std_logic_vector(3 downto 0);
signal LED : std_logic_vector(7 downto 0);
constant SIM_CF : natural := CF/10; -- 50 MHz/10 for simulation
begin
-- instantiate MUT
MUT : entity work.mcu
generic map(CLK_FRQ => SIM_CF)
port map(
rst => rst,
clk => clk,
LED => LED,
Switch => Switch
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / SIM_CF/2;
clk <= not clk;
end process;
end TB;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and FIFO Generator when XST elaborated the client core
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-- |
-- |--- XilinxCoreLib.fifo_generator_v9_2
-- |--- XilinxCoreLib.fifo_generator_v9_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v7_1
-- |--- XilinxCoreLib.blk_mem_gen_v7_3
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/01/2008 Initial Version
--
-- DET 2/01/2008 for proc_common_v4_0
-- ~~~~~~
-- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create
-- this file.
-- - Changed instance of sync fifo to use new wrapper file that will adapt
-- to FIFO Generator primitive.
-- - Replaced "edk_generatecore" with "generatecore" utility call
-- - Removed the CAM component
-- ^^^^^^
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 4.3
-- - Added Block Memory Generator Component Version 2.7
-- ^^^^^^
--
-- MSH 2/26/2009 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 5.1
-- - Added Block Memory Generator Component Version 3.1
-- ^^^^^^
--
-- DET 3/2/2009 for EDK 11.1
-- ~~~~~~
-- - Added new Parameters and ports for Fifo Generatore 5.1.
-- ^^^^^^
--
-- DET 3/30/2009 EDK 11.2
-- ~~~~~~
-- - Had to reorder parameter list of FIFO Generator 4.3 component to match
-- the corresponding Verilog model due to NCSIM positional order
-- dependancy of parameters in vhdl/verilog use case.
-- ^^^^^^
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Added fifo_generator_v5_2
-- ^^^^^^
--
-- DET 2/9/2010 For EDK 12.1
-- ~~~~~~
-- - Added fifo_generator_v5_3
-- - Added blk_mem_gen_v3_3
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Added fifo_generator_v6_1
-- - Added blk_mem_gen_v4_1
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 10/04/2010 EDK 13.1
-- ~~~~~~
-- - Added fifo_generator_v7_3
-- - Added blk_mem_gen_v5_2
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Replaced fifo_generator v7.3 with v8.1
-- - Added blk_mem_gen_v6_1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Removed blk_mem_gen v6_1
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- - Update to use blk_mem_gen_v6_2
-- - Remove out of date components.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the component decalarion
-- ^^^^^^
--
-- DET 3/7/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR596052
-- - Added removed fifo generator and Blk Mem Gen components back into
-- coregen_comp_defs.
-- ^^^^^^
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
PACKAGE coregen_comp_defs IS
--------------------------------------------------------
-- Declare general attributes used in this file
-- for defining each component being used with
-- the generatecore utility
attribute box_type: string;
attribute GENERATOR_DEFAULT: string;
-------------------------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v12_0
-- The Component declaration for fifo_generator_v12_0 pulled from the
-- Coregen version of
-- file: fifo_generator_v12_0_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V10.0 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v12_0
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex6";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3
C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
backup : in std_logic := '0';
backup_marker : in std_logic := '0';
clk : in std_logic := '0';
rst : in std_logic := '0';
srst : in std_logic := '0';
wr_clk : in std_logic := '0';
wr_rst : in std_logic := '0';
rd_clk : in std_logic := '0';
rd_rst : in std_logic := '0';
din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
rd_en : in std_logic := '0';
-- optional inputs
prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
int_clk : in std_logic := '0';
injectdbiterr : in std_logic := '0';
injectsbiterr : in std_logic := '0';
sleep : in std_logic := '0';
dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0');
full : out std_logic := '0';
almost_full : out std_logic := '0';
wr_ack : out std_logic := '0';
overflow : out std_logic := '0';
empty : out std_logic := '1';
almost_empty : out std_logic := '1';
valid : out std_logic := '0';
underflow : out std_logic := '0';
data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
prog_full : out std_logic := '0';
prog_empty : out std_logic := '1';
sbiterr : out std_logic := '0';
dbiterr : out std_logic := '0';
wr_rst_busy : out std_logic := '0';
rd_rst_busy : out std_logic := '0';
-- axi global signal
m_aclk : in std_logic := '0';
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1
m_aclk_en : in std_logic := '0';
s_aclk_en : in std_logic := '0';
-- axi full/lite slave write channel (write side)
s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic := '0';
s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic := '0';
s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_bvalid : out std_logic := '0';
s_axi_bready : in std_logic := '0';
-- axi full/lite master write channel (read side)
m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_awvalid : out std_logic := '0';
m_axi_awready : in std_logic := '0';
m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
m_axi_wlast : out std_logic := '0';
m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_wvalid : out std_logic := '0';
m_axi_wready : in std_logic := '0';
m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_bvalid : in std_logic := '0';
m_axi_bready : out std_logic := '0';
-- axi full/lite slave read channel (write side)
s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic := '0';
s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_rlast : out std_logic := '0';
s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_rvalid : out std_logic := '0';
s_axi_rready : in std_logic := '0';
-- axi full/lite master read channel (read side)
m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_arvalid : out std_logic := '0';
m_axi_arready : in std_logic := '0';
m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_rlast : in std_logic := '0';
m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_rvalid : in std_logic := '0';
m_axi_rready : out std_logic := '0';
-- axi streaming slave signals (write side)
s_axis_tvalid : in std_logic := '0';
s_axis_tready : out std_logic := '0';
s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
s_axis_tlast : in std_logic := '0';
s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi streaming master signals (read side)
m_axis_tvalid : out std_logic := '0';
m_axis_tready : in std_logic := '0';
m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
m_axis_tlast : out std_logic := '0';
m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi full/lite write address channel signals
axi_aw_injectsbiterr : in std_logic := '0';
axi_aw_injectdbiterr : in std_logic := '0';
axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_sbiterr : out std_logic := '0';
axi_aw_dbiterr : out std_logic := '0';
axi_aw_overflow : out std_logic := '0';
axi_aw_underflow : out std_logic := '0';
axi_aw_prog_full : out std_logic := '0';
axi_aw_prog_empty : out std_logic := '1';
-- axi_aw_almost_full : out std_logic := '0';
-- axi_aw_almost_empty : out std_logic := '1';
-- axi full/lite write data channel signals
axi_w_injectsbiterr : in std_logic := '0';
axi_w_injectdbiterr : in std_logic := '0';
axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_sbiterr : out std_logic := '0';
axi_w_dbiterr : out std_logic := '0';
axi_w_overflow : out std_logic := '0';
axi_w_underflow : out std_logic := '0';
axi_w_prog_full : out std_logic := '0';
axi_w_prog_empty : out std_logic := '1';
-- axi_w_almost_full : out std_logic := '0';
-- axi_w_almost_empty : out std_logic := '1';
-- axi full/lite write response channel signals
axi_b_injectsbiterr : in std_logic := '0';
axi_b_injectdbiterr : in std_logic := '0';
axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_sbiterr : out std_logic := '0';
axi_b_dbiterr : out std_logic := '0';
axi_b_overflow : out std_logic := '0';
axi_b_underflow : out std_logic := '0';
axi_b_prog_full : out std_logic := '0';
axi_b_prog_empty : out std_logic := '1';
-- axi_b_almost_full : out std_logic := '0';
-- axi_b_almost_empty : out std_logic := '1';
-- axi full/lite read address channel signals
axi_ar_injectsbiterr : in std_logic := '0';
axi_ar_injectdbiterr : in std_logic := '0';
axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_sbiterr : out std_logic := '0';
axi_ar_dbiterr : out std_logic := '0';
axi_ar_overflow : out std_logic := '0';
axi_ar_underflow : out std_logic := '0';
axi_ar_prog_full : out std_logic := '0';
axi_ar_prog_empty : out std_logic := '1';
-- axi_ar_almost_full : out std_logic := '0';
-- axi_ar_almost_empty : out std_logic := '1';
-- axi full/lite read data channel signals
axi_r_injectsbiterr : in std_logic := '0';
axi_r_injectdbiterr : in std_logic := '0';
axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_sbiterr : out std_logic := '0';
axi_r_dbiterr : out std_logic := '0';
axi_r_overflow : out std_logic := '0';
axi_r_underflow : out std_logic := '0';
axi_r_prog_full : out std_logic := '0';
axi_r_prog_empty : out std_logic := '1';
-- axi_r_almost_full : out std_logic := '0';
-- axi_r_almost_empty : out std_logic := '1';
-- axi streaming fifo related signals
axis_injectsbiterr : in std_logic := '0';
axis_injectdbiterr : in std_logic := '0';
axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_sbiterr : out std_logic := '0';
axis_dbiterr : out std_logic := '0';
axis_overflow : out std_logic := '0';
axis_underflow : out std_logic := '0';
axis_prog_full : out std_logic := '0';
axis_prog_empty : out std_logic := '1'
-- axis_almost_full : out std_logic := '0';
-- axis_almost_empty : out std_logic := '1'
);
END COMPONENT;
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_2
-- Component declaration for blk_mem_gen_v8_2 pulled from the
-- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib
-- file: blk_mem_gen_v8_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC"; -- Removed in version v8_2
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC := '0';
DBITERR : OUT STD_LOGIC := '0';
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC := '0';
SLEEP : IN STD_LOGIC := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC := '0';
S_AXI_DBITERR : OUT STD_LOGIC := '0';
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT; --blk_mem_gen_v8_1
-- The following tells XST that blk_mem_gen_v8_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
-- ATTRIBUTE box_type OF blk_mem_gen_v8_1 : COMPONENT IS "black_box";
-- ATTRIBUTE generator_default OF blk_mem_gen_v8_1 : COMPONENT IS
-- "generatecore com.xilinx.ip.blk_mem_gen_v8_1.blk_mem_gen_v8_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
END coregen_comp_defs;
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumberTb is
end RandomNumberTb;
-- Testes funcionais à entidade RandomNumber
architecture Stimulus of RandomNumberTb is
signal s_clock, s_stop, s_reseti, s_resetO, s_counter : std_logic;
begin
uut: entity work.RandomNumber(Behavioral)
port map(clock => s_clock,
stop_signal => s_stop,
reset => s_reseti,
resetOut => s_resetO,
count => s_counter);
clk_process:process
begin
s_clock <= '1';
wait for 20 ns;
s_clock <= '0';
wait for 20 ns;
end process;
comb_process:process
begin
s_stop <= '0';
s_reseti <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 50 ns;
s_stop <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 50 ns;
s_reseti <= '1';
wait for 50 ns;
end process;
end Stimulus; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZrbubDlN4D7iuGXASr8bjj6AOz2q/Nb57f4SldOibP6bhd6UBs3Eb/4sj4ay55vW641jk4Ta/URs
Zug6y8FJEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MNObpmwHm4iGZ9YNtCKbmOKCx0Tj5nMCmrTRycw7AdgguSBpM/HVk2rsYRt84IxwyDXnjVhMOJ0U
DoyfQkeS/MNTE1lPjToh6e2AMZMy/EF3PWN5jSbnEXLUUKSzoDvj/JoJoLc8tg38/m/oBbl7TaPV
oFITFYzqwpBbDVhCuRk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mmABCk2JD2TZOwnhghCPum49XNgGlVuSOYATXVavQ5dXh3mLpHesfQMUwIiSjrXAbSx7yOMd5pQe
GVXRayu25GF8jVy4MCSwTs0wQduu4FyxrNIGi5/wugpyIINGe0OrfkCDFLNiLXw8oYrfvKl6kTTN
17pkUT1mtfJZxORtX6UbyAYSuMJ80aqOwM86eM2i0c8bgpLgjLgZixs8vhnDrmUC33HqwIyGIGty
nN7r7C+pyniratw2IVzSped+eLslbwgqEKyjpZ+w5G/8hc/R8W3s8mVcKTt0FH4JqCoplFvB2TDr
oQxg0pBecl/po8DwI1Sp8LzsthokjIqZ1UBs/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RNdVWR8FapCjA6A1Wvas6UxlPnswdC1Q0oMM85te8PL/bNhgtJGFavXygo4o80rZ6a7vy5SY2/U5
DPEUquK/4v2O0o1dPv46namWJtc3OTwD+p5JMrVAieKWYSFYuq6/pvNjZp2ip/YO0HBGkdH1uy5m
C7rziCHZEha+Q7MCAFw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
k5x7H6MYGgsgOJZYts6B8Jg+yrFC/kh256ksQBoescVtzNQXQsHnI1ecDTY/vc8XwqLjeulNHj5p
RCM4qfBYiuL9jj6OpibOGEvKRPli3U0be8i3WpUcjIXylE5fZPULb88LItQK+jo7sFRVH7MPx9LP
R5ZpXoiv06lnsI73v0H/rxRCCJ573C6YyNyKEaJdF/t9n1Nu/vgYJewuehPQ4vs6Z+2wqe89uKQE
SnO3T65W9yfG7smSQWsnrWGAVjbkn6cgLWY3ac+otPmrkq6A0BLP0ASl3anfFKgG70aZ0kHyAMG8
8fdN0xjLpA3l9EM8pG/395eeSWX0cgsP932o8g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4944)
`protect data_block
/XgPhy9icX+DmDXKlhQ5s4OMi97hVZAnw58nijbh8YMFViStg1d8kwdVLWwmFdgcl8645CKp8VbI
mSZxT+MGJRaoYIPk6igS9Oggoo4oGVd1vRijllXGnmopORszkbps8Es8c/KmyslIIwBWUqUQHQfZ
x5j2ATjvntl2DFPNqj+3t71IzJUX27lHsAtWWw9WP6ySmVLNjI7g7SZPVPTB+X7TfCF3WPBDdiDd
YFUESW+L1UAWOcaiZ/dfFHK3SaodGL0wqlkPmCSvx1jug2l6W3VrC9RF8WBqqeHfLvs/ZkirMIPq
2iYUI/dnO+1K+li0LLArU29PWwNdUQaFkbbTfo9ksGGZrsgGTwgmBbGpYcpvdesJUaQFeAX9Rklk
/STJOZG2Im2D8JqkgJHo4hlSOTTEAaJFObXJYYc84x1MD2enkcNWyvOnaz54ZvMYfcKdEdvmK/TD
iv4lQqmJmHFpzi5YJ1QG4G4c01Ylwj3sgIuvsAOWFQtB70DQp3yxrp2sQMGTpuUoEp2Qln4lB199
1heUTbFosMIN+vgXM6RdqpEMC+13njI9AmuFj0MtVccCgGwoQbSteoF7X7did+sBwi3arQWWKHuk
5rJWZtfabKCpFBYGJV4NjPqorjHAaamr9VXGXErFa/aZWIAiNUrAo07JBpB4P7t5I4PRWLeUPboC
a7+klZDXI36cHMn4RWDKrabjFORJLrqhkciAVQaT0nffsMAk2G+b6Uz8Tu+2vh1ibHb4m94Om6Op
DGo4MFBTixHdoMPg/jKqdHccmwABOUGn5P2nN7POsTqpIh0h1AxRfsV8Sa4LAsZZmo1Os+gR+I9o
EBOlRQR1x5/f5omSg42ZEs+RQ67f7Zkg6qIYtSBemfUGkUeCsGM3bj72WYbcktNUh1M++7beqZoB
XLbeeXGIn2mYWS+vQAe6JbSY+jh5xUZZsJ8dSFzrx9PpCGoFTRyW3YDzB0Q4GGIxQH5Z9tKzxSpj
S2m+sXAYhVoJhkXRuU0mq1Rhf3IuqoyE/PfJ/Calb2Y3O1ngIpKUDQWF+RKQe/K34GJa6zm5hjmb
BJKcf/o6iEqocCdj7m1fbfvHg8T3GOPzK+Uw0DX17/md/cfb/XtoXcz1hLHNygGWAfwTpHT9kuQa
M6BcHE5HWnjnHRaYfsTMQnh4+H7fY367iIGZkYZsVZh7d2WyykDeeykJktptlGnSbeeDcLyL9lEK
CHZHSq5krWiHbeR2q2ANE3NX0cmf0M5TiUGJEHyQc2xMpEdAN6DPCdz2YPwBotGlOmI1oG21pkmt
tJK2FYD0QT3tR7WaLyikXQGaoSPdO4w9szh21LTW9zt/OKPuBpTwXBJJZF9v6xvS/qJDCpkIHD3D
Xtf6uLilitUvB9bZJIIstfqtu0AiD3kx1Gna76gKGxR6NW1iJz7H+rzcEcyC9QRnPwqLCcQLpsvE
q6xriiQw2MljbbxSIPwJ1ip/wp+y7BcTY/+M6fNBkufoufXucaGsbl40mbOGMDgayLhSQNvHgrDz
unNb9zQXLu71k1dJYVhj40ndlwsN0RlLUqoa/L6L8TYHEsjd+Up5Jg56lVxU7ZMo1UUsZ6xVOoO9
Cb0PZw+iD1VK7FToTnoIxx10ixVjEnNWe0qwCPQTBRz2bKmX1Ll2h85U60gp5DS3SnVA33LQnsZg
Y4OZ5cm3ukf7dzaXM0xJ3BeLPuxfcYbmM05BRdd3mMHqWBPBRlRpvdpPle/9Wjcj2/AWW3zjObwD
IhcR1c3cFohV8srL3DqV9+BegW9eVH4MgjgkDEfSRLUqC8DEE26j1et32MWqGXCc31xMGiRW3Kc7
KHB6HD8YckBht80QpHaiZcM7hrqTJnvseXAGm0M1X1UcugCJrXycPIrVovit7KAJh3hf7L0rx5qh
BI+tlUhaZB18ZLPhRLMF4VW5sx6I+/ze64kQMW12F8XmALl/O5jbE24ZMzrpc4pZ4AMAXZPltpfi
4XVbqWMqkIqTHmVrHNIrykL0OZ0KOrVztJxcm+YMRbBFiiBhUlgy+ADCYAeBg3WhYQcZkcrAow8n
6gS5CWGyWR523mNnpg/PCsfA0hBv/jUo/lSAmngojOm5e45DEr0030Fj1XQVFmHveSwwkBNT5JpK
UExV9vu6G9QB5rO8NEZIgybjQKSIunqk8kZ7C0rJkqmCLcZUmfw3utRUtFFlhxigCcJSLrp/B3Ca
ibRaEsHtbuPH/9MTtF/fMxM0k3JZqJBtgZ5/FZfWqSxFbZwF2IZm1sSncQ1yc6Nq297yi1lmNO7c
YeXSGJIY/DhAHoC5vLt36wX43aD+8X/Y088lXtDKh3FSFtu2Gx2DsubgQB4idik7jRqi91e1E8FU
po3aXZqnf+OHozuBHP45vMOEXGPFtDR95L5x7APGKvLKUYxr0cIBx3CQymxdWa+b8icVvLo0iVqW
U/UCB+JqAi5n88AaugRCu5N5BNacfwWudwespHpujQsfGPi79JnGb2ck0/LTbCrRMdp28CQs/0MQ
4l8uZEzMYi+kKBH/B9iloRvHPOl+9BjAKzxIxcKcLsXsz1sNnJ2mQByG9iA/zkAr+qJ5Nk6wYATR
hWaDjkf3xs58t07u0hCnJz4A1VrFzrAZoD5E4+00YOBFkjdB5kscNuZJI2RXbyBM/oAUah9CvQ33
bf+/B6gK+tIYrwTYnHEnX7dV4/TD8NWF5SjuGyFHNecfkJOVqIol4yzqMbzzNpIJCY8CpdftHdvH
gi+Dm6wh2ZzAj0TWPPh4hqAAKBiNp9zcSgKtF8XnX3kemtAWTq1HqTZxVRBCYx+Bdo/AgX2iVxH2
EtzoEuwcoY0m9gqyhvgsEV67e6wkpmUZgYjydw/XeRMQGkHK5C02Fe+qz8Aeqig8lEU7JT+6YQO5
hs2H8vEZ0K/Xtrn4b8AwA3ulwc4a38lbRk1kcdPbBxldehq54FI9tSc3GtxDQ2DM6/yjuO6tgtVT
HP8zwWeUW8QrrqfymURFmY1HdU5E5p8pxcwn+pLUQUYDwRD5tsVMKWVEHxQ5ONISWyGqwUPnv2EM
P/ylCTEzanpvnYy4kb6vYVR3tjO1Frnim5s9OTFvGX/phTcZHhNeJJnHGXw7jPFy/GdWFMhi3erL
OXqeTJPYfwDSoP0/umaoRk1wdsDpUj4PcXQ42xAOJwaBAMGVGJanUhio5mpHdeTyIksL1cDNFIo2
GuzJN2hOMk/pQsDs6Lz8uCjWdcMTqxzw0Ke4HW+wPvUtPoYuZW/Eq0bkJ3Neus5lGKlAKqYwbRmB
nnTepSOsgCWzZUEM6DCc1myE6mDnSaZYbaTu8EX9T2Dbv73bPAIcqHlg5myBhGJ9stCLBSy02Xxq
+aRMZyXmkL7+KvoktjxSOpMR7EGMzpJObqx+78BxrDmmZKGw+EmPxsn4yNL9f9MtrWN0YnHp3V6c
CL/sMJv7ycKAWirgf5wNxBB+Eo0J+nc4eDN8ysUbSnSYna0hdSKcUNxyNLY6Bvyl/LZMKnMLk5Y1
cO2ejo4G/cBwwIk2+hMn/mUoguB6d+2zNr7Wp3XWq/raX4QtAAQ2tramNCjbi/zvXGDoPidC9Y6r
mJfAHOLEVPiKUXTEIpI0UnK57Bh4fslf2zCeVswXP/VbgPEA0I2aR5gimCFv4tixBrConniePEpX
xhLInR63b48fd5fMxufarksOWoIbIFSNEdkGtsS0gFtTiKP+kHdS6QzjLIWhEr7afHSlLyCUTsIp
gGPbPhefnDrSBlfyj0S8NcZxrG+8eLcZqwk19jf8VvmqFY6/mFAIl84b3YCNzHHfwHNehX9m4K6F
xk0D4IPPm31Oy1kKNr13solUY5llTKRdfuIqGf5FkR50QmzHIac3uq+cS7NNf9MVaNP4i9S724eE
ySPtlmOyuJrL9SFJzNbDT3KzkpbT5roVh7km13cWvcxYXHYikkTwwrTe8+wEmmEeegdAVeqwZpLx
ADQqImcmW+EyMcNAn+siXXUqWjQe1wjPvB1so/vviZBQZOyVcrpTwxaF4Q8r6/Aipx/vuxO4zCVR
DY8DetlbMpTMpveel1KKKsqWPsVI8iLHOxVh23zLIyeR45PilQ7jmPp2ubyo2IDPvINqhTgBCD3G
PKD2fT4irKWZwWfP/DRXjlBRqmfUgaf5CHQocrz/E7ksfucxvqvtHWalLUJx1c0zVVxCRZyhLKoq
zaB5B5WovRxpx2aQ/scyYEg73qzQSZmWiIlH7ZJCm9OmeXCTC9HkVBSMVqWqqbXxpPqns6lvKtTK
EKSt4SdN4PviWqAB3QmNDGR2yVEsVd3KB0VuDtH2I1oT84v5l8MVaTTJS7IUmCLeWRrJ1U6FPtM+
T324vheQWEicU6SebkNYSBd1OO/Uqejv6oS/1qIdLLz8WGBPd4P0YAmCjHpLGsudxzJafZxS1BDW
+FsKA5DpPyZJi7VmYRlquRN5eYOcqdetbFQLSl+MwZaBDq8UjVXdlrg+PYrv2Zfq66hccZSys/VA
wnagUp0EYJ4A/YrZHPLvEd4mgS2J/NZtWjOOsZrro8xViKuUV96eLJRIKcIJZgUoM3rUZ1pnBKxR
qr11Emcd/e4R1+1/Xkv9sluN0cp2b/6rT+uYGXCRPqKqKtI33jC2BmAqKae/dzfmWzga8M0Xo2st
huuQkSIcRgihATt4XXWeXhzAMGC5mIdWOciW+OdbYYXMSbaSBgp/3ol9C+Mrv4rjTYvXitrOF5Y9
CKo/XAX8tKW6784RCIvwt1HOc/4SBPHG+J+pWLUNdECp6ockcyFMyGwhBW/My16hEJ9ZE0/906B9
5vNZNZfHamWNx/amMPRa862j+T5f1L2QYSbmioqsuE1OwBEyT+BYfw6IJ7dwEXEFgFpcNh8kKQXy
UORnvS6bw2yQUhMSstD9JwT5BA7Q5EWKs2S8qif6y4Vm8VX1gjjVmxwTD1V9qdePefSJZuPBgvqT
p/PotcDtTmvMHpj/QMwDp8iU5HxvuxUkqBbs7+PdYXXjzWNWCaVMnBBS8qkAtkEvy3drhnNYyRzH
aGvwlGqckdb0Uw0wO10Jq7Ci+gvF0lX6OrvEsJ/GMaAJNR5lejPBOhcMr3jpJfhhIwxxhzCh9hw5
EYNRnte36C1EM12u1r6SpA3ArkaCI9kNXCYij5loV/6NYU7SQ2sDs96mkGcirr22g1AbnvHjhWBM
yGduEk/z0pJyvhDKkblWrPfjgaHAk8iPW9oV5d8WoZl/rn0HVmh3OJ03U3uuiCpPOkochS/MGm2X
2j/YbaUTr1FS7cYHyBb1E/DIqZgqGYKLSzfz4qir2cQ3xH39sKflWnlk9ZHuPHAqT7cF/vrN/46R
WCJVjoUpQr+b2uTeI9T1ZwnnCVrfjxhVrDQejF8M+9CcxH/Qq0YQGcYY27x5fQGyJAlK/QFeUHdW
Cd3PJcJbjAKrx44SXKrK5I6srvWC06YFPp5AotK+6TiZ850Ir0kPLZzM72e5xyQbbfgJB7CeDnxW
wy91bM1wUoLPSenCORf3lIpE6o1m6QsUuOElhu9onccpvUxrPIu2PpgFCfx7eCZojSuF32hkIQPG
szdDEmsdTq6YqyUMPtG7VM352mlnFx3j8rF9svdqM3WYa3kcPQOVKUs/894U6wfWJenOLGDeF6UW
WqNHFD6KQ1EUfEQa+YCvKVdq+DShAjosYd6RjthGEvHaaiNlRGfr1hE8/3qlgT/+alN2CSiTCzvg
AANIZtJYzqU2GlFuN1XyUnnMNRCC0TXNDeqzQ7l1bx+umwG/rVKc6/VbTojgWi4zXIuvnYpOEbmI
zRla9h2uPkX91iGFlZTvBX8u4+zNYG2N9GBrRYO67c0fsAdL8ZZ/KVKU4xmf35ftxWag5ppemj9p
zlFZ6u3kqNPDryujA52aJVcLvD2V4hggJaMTbqq3AsFBDFmYA6lNrc842WyI8gKCn48Eb+xZTqQZ
Q9o34zZwZGuXj/i2PZkk51BOrcAbxou5nNCvMUjwYHeyCc1fm9QK0ofRFw/Xjgeu+/nOE5KYxWN0
S2Nt00vhAYSy2herp0FmuKQxQ0/7QcypRKMTku3JPi3rcOYfcLjjbPUV5T2yuuQG0a8vyuahb+0A
1c2NCG5ezuRGor7OcZ7YqbYRWNWHAMtj8Q1loiuF+uxic6DYDUI6JGAXj2zD7ZYdo1k8gP201eNj
4Cgkw4D2R2mwtASM0psPxuUqdZtFvxOBTECqZkWMnYfZ+3TUj51hQMWRdLNFDt174YoXqtRZlQaX
Phkyqe+ISgw8QCxlzfLyTdQaYqu0XoqlJZyutfEg1jvTj0CrKOoQbUMAVU0UT0leczqqBmboSlYy
dLH634BopNavZnXbpj1SZudSqI/ua12os59WyHq/mAA2bYXRD95yFPyY2Gg1csGw7inm1N9YYq+a
i2zKAVGd6xOA0/tiZ/iABFMkgGgrTmlSMrDPFtp3u7lQ3fcA/46DoXSLwKbUKzFcpoHszZ5oBlAm
oKEwzh2sA9ZXg3QS8401RsRl/M7PCMFV15YVUgpRkt0qGHQr4QBhIdNfe9zOdQsgnzZUAxDM6Q0c
lDRVhefeFLLFIkHNZQS+BLVcda1OtxCH9u/jtYbfxMGO6b1kD3k3bU4f
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2575.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p02n02i02575ent IS
END c13s02b00x00p02n02i02575ent;
ARCHITECTURE c13s02b00x00p02n02i02575arch OF c13s02b00x00p02n02i02575ent IS
type MEM is range 4 to 5; -- Space is a separator except in this comment section
type M1 is range 2 to 4; -- End of line is a separator between the
-- earlier comment section and this type.
BEGIN
TESTING: PROCESS
variable j : MEM := 4;
variable n : M1 := 2;
BEGIN
assert NOT(j=4 and n=2)
report "***PASSED TEST: c13s02b00x00p02n02i02575"
severity NOTE;
assert (j=4 and n=2)
report "***FAILED TEST: c13s02b00x00p02n02i02575 - Lexical test failed."
severity NOTE;
wait;
END PROCESS TESTING;
END c13s02b00x00p02n02i02575arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2575.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p02n02i02575ent IS
END c13s02b00x00p02n02i02575ent;
ARCHITECTURE c13s02b00x00p02n02i02575arch OF c13s02b00x00p02n02i02575ent IS
type MEM is range 4 to 5; -- Space is a separator except in this comment section
type M1 is range 2 to 4; -- End of line is a separator between the
-- earlier comment section and this type.
BEGIN
TESTING: PROCESS
variable j : MEM := 4;
variable n : M1 := 2;
BEGIN
assert NOT(j=4 and n=2)
report "***PASSED TEST: c13s02b00x00p02n02i02575"
severity NOTE;
assert (j=4 and n=2)
report "***FAILED TEST: c13s02b00x00p02n02i02575 - Lexical test failed."
severity NOTE;
wait;
END PROCESS TESTING;
END c13s02b00x00p02n02i02575arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2575.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p02n02i02575ent IS
END c13s02b00x00p02n02i02575ent;
ARCHITECTURE c13s02b00x00p02n02i02575arch OF c13s02b00x00p02n02i02575ent IS
type MEM is range 4 to 5; -- Space is a separator except in this comment section
type M1 is range 2 to 4; -- End of line is a separator between the
-- earlier comment section and this type.
BEGIN
TESTING: PROCESS
variable j : MEM := 4;
variable n : M1 := 2;
BEGIN
assert NOT(j=4 and n=2)
report "***PASSED TEST: c13s02b00x00p02n02i02575"
severity NOTE;
assert (j=4 and n=2)
report "***FAILED TEST: c13s02b00x00p02n02i02575 - Lexical test failed."
severity NOTE;
wait;
END PROCESS TESTING;
END c13s02b00x00p02n02i02575arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_180 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_180;
architecture augh of add_180 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_180 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_180;
architecture augh of add_180 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_50Mhz : IN STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
SIGNAL clock_1Mhz_reg, clock_100Khz_reg, clock_10Khz_reg, clock_1Khz_reg: STD_LOGIC;
SIGNAL clock_100hz_reg, clock_10Hz_reg, clock_1Hz_reg : STD_LOGIC;
BEGIN
PROCESS
BEGIN
clock_1Mhz <= clock_1Mhz_reg;
clock_100Khz <= clock_100Khz_reg;
clock_10Khz <= clock_10Khz_reg;
clock_1Khz <= clock_1Khz_reg;
clock_100hz <= clock_100hz_reg;
clock_10hz <= clock_10hz_reg;
clock_1hz <= clock_1hz_reg;
-- Divide by 50
WAIT UNTIL clock_50Mhz'EVENT and clock_50Mhz = '1';
IF count_1Mhz < 49 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "0000000";
END IF;
IF count_1Mhz < 25 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
clock_1Mhz_reg <= clock_1Mhz_int;
clock_100Khz_reg <= clock_100Khz_int;
clock_10Khz_reg <= clock_10Khz_int;
clock_1Khz_reg <= clock_1Khz_int;
clock_100hz_reg <= clock_100hz_int;
clock_10hz_reg <= clock_10hz_int;
clock_1hz_reg <= clock_1hz_int;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_reg'EVENT and clock_1Mhz_reg = '1';
IF count_100Khz /= 4 THEN
count_100Khz <= count_100Khz + 1;
ELSE
count_100khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_reg'EVENT and clock_100Khz_reg = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_reg'EVENT and clock_10Khz_reg = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_reg'EVENT and clock_1Khz_reg = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_reg'EVENT and clock_100hz_reg = '1';
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_reg'EVENT and clock_10hz_reg = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1913.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01913ent IS
END c07s02b01x00p01n01i01913ent;
ARCHITECTURE c07s02b01x00p01n01i01913arch OF c07s02b01x00p01n01i01913ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x and y) and (y or z)) then
end if; -- logical operators defined only for BIT and BOOLEAN.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n01i01913 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01913arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1913.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01913ent IS
END c07s02b01x00p01n01i01913ent;
ARCHITECTURE c07s02b01x00p01n01i01913arch OF c07s02b01x00p01n01i01913ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x and y) and (y or z)) then
end if; -- logical operators defined only for BIT and BOOLEAN.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n01i01913 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01913arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1913.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01913ent IS
END c07s02b01x00p01n01i01913ent;
ARCHITECTURE c07s02b01x00p01n01i01913arch OF c07s02b01x00p01n01i01913ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x and y) and (y or z)) then
end if; -- logical operators defined only for BIT and BOOLEAN.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n01i01913 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01913arch;
|
----------------------------------------------------------------------------------
-- Company: *
-- Engineer: Andres Gamboa
--
-- Create Date: 08:52:16 10/15/2013
-- Design Name:
-- Module Name: four7seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mod_7segments is
port ( clk_8KHz, reset : in std_logic; -- Entrada clk 8 KHZ, reset
dig0, dig1, dig2, dig3, dig4, dig5, dig6, dig7 : in std_logic_vector(3 downto 0); -- Entrada digitos binario
g : in std_logic_vector(7 downto 0); -- Entrada habilitar 7 segmentos
an : out std_logic_vector(7 downto 0); -- Salida seleccion 7 segmentos
segments : out std_logic_vector(6 downto 0) -- Salida 7 segmentos
);
end mod_7segments;
architecture Behavioral of mod_7segments is
component mod_bcd
port ( bcd : in std_logic_vector(3 downto 0);
g : in std_logic;
segment7 : out std_logic_vector(6 downto 0));
end component;
signal seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7 : std_logic_vector(6 downto 0);
signal estado, estado_sig : std_logic_vector(2 downto 0);
begin
bcd0: mod_bcd port map( bcd => dig0, g => g(0), segment7 => seg0);
bcd1: mod_bcd port map( bcd => dig1, g => g(1), segment7 => seg1);
bcd2: mod_bcd port map( bcd => dig2, g => g(2), segment7 => seg2);
bcd3: mod_bcd port map( bcd => dig3, g => g(3), segment7 => seg3);
bcd4: mod_bcd port map( bcd => dig4, g => g(4), segment7 => seg4);
bcd5: mod_bcd port map( bcd => dig5, g => g(5), segment7 => seg5);
bcd6: mod_bcd port map( bcd => dig6, g => g(6), segment7 => seg6);
bcd7: mod_bcd port map( bcd => dig7, g => g(7), segment7 => seg7);
process (clk, reset, seg1, seg2, seg3, seg4)
begin
if reset='0' then
segments <= "0111111";
an <= "00000000";
estado <= "000";
estado_sig <= "000";
elsif clk'event and clk = '1' then
estado <= estado_sig;
case estado is
when "000" =>
estado_sig <= "001";
an <= "11111110";
segments <= seg0;
when "001" =>
estado_sig <= "010";
an <= "11111101";
segments <= seg1;
when "010" =>
estado_sig <= "011";
an <= "11111011";
segments <= seg2;
when "011" =>
estado_sig <= "100";
an <= "11110111";
segments <= seg3;
when "100" =>
estado_sig <= "101";
an <= "11101111";
segments <= seg4;
when "101" =>
estado_sig <= "110";
an <= "11011111";
segments <= seg5;
when "110" =>
estado_sig <= "111";
an <= "10111111";
segments <= seg6;
when "111" =>
estado_sig <= "000";
an <= "01111111";
segments <= seg7;
when others =>
estado_sig <= "000";
an <= "00000000";
segments <= "0111111";
end case;
end if;
end process;
end Behavioral;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
|
library IEEE;
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VOut is
port (
CLK : in STD_LOGIC;
TM : in STD_LOGIC := '1'; -- Negative
HS : out STD_LOGIC; -- Negative
VS : out STD_LOGIC; -- Negative
RCH : out STD_LOGIC_VECTOR(3 downto 0);
GCH : out STD_LOGIC_VECTOR(3 downto 0);
BCH : out STD_LOGIC_VECTOR(3 downto 0)
);
end entity;
architecture Behavioral of VOut is
-- 1024x768 @ 60Hz, 65mHz pixel clock - params from tinyvga.com/vga-timing
constant HorVisArea : INTEGER := 1024;
constant HorFrPArea : INTEGER := 24;
constant HorSyPArea : INTEGER := 136;
constant HorBkPArea : INTEGER := 160;
constant HorTotArea : INTEGER := HorVisArea + HorFrPArea + HorSyPArea + HorBkPArea;
constant VerVisArea : INTEGER := 768;
constant VerFrPArea : INTEGER := 3;
constant VerSyPArea : INTEGER := 6;
constant VerBkPArea : INTEGER := 29;
constant VerTotArea : INTEGER := VerVisArea + VerFrPArea + VerSyPArea + VerBkPArea;
signal color : STD_LOGIC;
signal VTest : STD_LOGIC;
signal mpos : INTEGER range 0 to 8979;
signal CCNT : INTEGER range 0 to HorTotArea;
signal RCNT : INTEGER range 0 to VerTotArea;
signal cctmp : INTEGER range 0 to VerVisArea;
signal picv : STD_LOGIC_VECTOR (7 downto 0);
component thpic is
port (
CLK : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
begin
TPic: thpic port map (
adr => conv_std_logic_vector(mpos,14),
clk => CLK,
q => picv
);
process(CLK)
begin
if rising_edge(CLK) then
-- Video test mode control
VTest <= not TM;
-- Video output
if CCNT < HorVisArea and RCNT < VerVisArea
then
if VTest = '0' then
-- Visible area control
if color = '1'
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Grid for display test
elsif conv_std_logic_vector(CCNT,1) = b"0" and conv_std_logic_vector(RCNT,1) = b"0" and
CCNT /= 2 and RCNT /= 2 and CCNT /= HorVisArea - 4 and RCNT /= VerVisArea - 4
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
else
RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Overflow control
if (CCNT = HorTotArea - 1) then
CCNT <= 0;
if RCNT = VerTotArea - 1 then
RCNT <= 0;
else
RCNT <= RCNT + 1;
end if;
else
CCNT <= CCNT + 1;
end if;
-- Sync pulse generation - negative polarity
if (CCNT >= HorVisArea + HorFrPArea) and (CCNT < HorTotArea - HorBkPArea) then
HS <= '0';
else
HS <= '1';
end if;
if (RCNT >= VerVisArea + VerFrPArea) and (RCNT < VerTotArea - VerBkPArea) then
VS <= '0';
else
VS <= '1';
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
-- Fetch new pixel value
if (cctmp < HorVisArea) and (CCNT = cctmp) then
cctmp <= cctmp + conv_integer(picv(6 downto 0));
color <= picv(7);
mpos <= mpos + 1;
end if;
-- Fetch the new row
if CCNT = HorTotArea - 1 then
cctmp <= 0;
end if;
-- Clear memory position each new frame
if (CCNT = HorTotArea - 2) and (RCNT = VerTotArea - 1) then
mpos <= 1;
end if;
end if;
end process;
end Behavioral;
library IEEE, ALTERA;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ALTERA.ALTERA_SYN_ATTRIBUTES.ALL;
entity thpic is
port (
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end thpic;
architecture rtl of thpic is
type mem_t is array (8979 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal rom: mem_t;
attribute ram_init_file: string;
attribute ram_init_file of rom: signal is "TPic.mif";
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(conv_integer(adr));
end if;
end process;
end rtl; |
library IEEE;
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VOut is
port (
CLK : in STD_LOGIC;
TM : in STD_LOGIC := '1'; -- Negative
HS : out STD_LOGIC; -- Negative
VS : out STD_LOGIC; -- Negative
RCH : out STD_LOGIC_VECTOR(3 downto 0);
GCH : out STD_LOGIC_VECTOR(3 downto 0);
BCH : out STD_LOGIC_VECTOR(3 downto 0)
);
end entity;
architecture Behavioral of VOut is
-- 1024x768 @ 60Hz, 65mHz pixel clock - params from tinyvga.com/vga-timing
constant HorVisArea : INTEGER := 1024;
constant HorFrPArea : INTEGER := 24;
constant HorSyPArea : INTEGER := 136;
constant HorBkPArea : INTEGER := 160;
constant HorTotArea : INTEGER := HorVisArea + HorFrPArea + HorSyPArea + HorBkPArea;
constant VerVisArea : INTEGER := 768;
constant VerFrPArea : INTEGER := 3;
constant VerSyPArea : INTEGER := 6;
constant VerBkPArea : INTEGER := 29;
constant VerTotArea : INTEGER := VerVisArea + VerFrPArea + VerSyPArea + VerBkPArea;
signal color : STD_LOGIC;
signal VTest : STD_LOGIC;
signal mpos : INTEGER range 0 to 8979;
signal CCNT : INTEGER range 0 to HorTotArea;
signal RCNT : INTEGER range 0 to VerTotArea;
signal cctmp : INTEGER range 0 to VerVisArea;
signal picv : STD_LOGIC_VECTOR (7 downto 0);
component thpic is
port (
CLK : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
begin
TPic: thpic port map (
adr => conv_std_logic_vector(mpos,14),
clk => CLK,
q => picv
);
process(CLK)
begin
if rising_edge(CLK) then
-- Video test mode control
VTest <= not TM;
-- Video output
if CCNT < HorVisArea and RCNT < VerVisArea
then
if VTest = '0' then
-- Visible area control
if color = '1'
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Grid for display test
elsif conv_std_logic_vector(CCNT,1) = b"0" and conv_std_logic_vector(RCNT,1) = b"0" and
CCNT /= 2 and RCNT /= 2 and CCNT /= HorVisArea - 4 and RCNT /= VerVisArea - 4
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
else
RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Overflow control
if (CCNT = HorTotArea - 1) then
CCNT <= 0;
if RCNT = VerTotArea - 1 then
RCNT <= 0;
else
RCNT <= RCNT + 1;
end if;
else
CCNT <= CCNT + 1;
end if;
-- Sync pulse generation - negative polarity
if (CCNT >= HorVisArea + HorFrPArea) and (CCNT < HorTotArea - HorBkPArea) then
HS <= '0';
else
HS <= '1';
end if;
if (RCNT >= VerVisArea + VerFrPArea) and (RCNT < VerTotArea - VerBkPArea) then
VS <= '0';
else
VS <= '1';
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
-- Fetch new pixel value
if (cctmp < HorVisArea) and (CCNT = cctmp) then
cctmp <= cctmp + conv_integer(picv(6 downto 0));
color <= picv(7);
mpos <= mpos + 1;
end if;
-- Fetch the new row
if CCNT = HorTotArea - 1 then
cctmp <= 0;
end if;
-- Clear memory position each new frame
if (CCNT = HorTotArea - 2) and (RCNT = VerTotArea - 1) then
mpos <= 1;
end if;
end if;
end process;
end Behavioral;
library IEEE, ALTERA;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ALTERA.ALTERA_SYN_ATTRIBUTES.ALL;
entity thpic is
port (
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end thpic;
architecture rtl of thpic is
type mem_t is array (8979 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal rom: mem_t;
attribute ram_init_file: string;
attribute ram_init_file of rom: signal is "TPic.mif";
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(conv_integer(adr));
end if;
end process;
end rtl; |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
ELSIF c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
ELSIF x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
ELSIF c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
ELSIF x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Main is
port(
modo : in std_logic := '0'; -- Gera / Valida. [sel 1]
k : in std_logic_vector (3 downto 0) := "1000"; -- Seleciona um grupo de até 16 bits. [sel 2~5]
s : in std_logic_vector (3 downto 0) := "0000"; -- Seleciona um valor. [sel 6~9]
hab_clk : in std_logic := '1'; -- Habilitador de clock. [sel 10]
but_clk : in std_logic := '0'; -- Botão pra trabalhar como clock. [sel 11]
clk : in std_logic := '0'; -- Clock do circuito.
display : out std_logic_vector (6 to 0); -- Display usado para mostrar estatisticas.
leds : out std_logic_vector (15 downto 0) -- LEDs de saída do circuito.
);
end Main;
architecture Behavioral of Main is
-- Vetor usado para deslocamento de bits.
signal vetor : std_logic_vector (15 downto 0) := "0000000000000010";
-- Guarda quantas vezes o valor de 'S' aparece.
signal estatistica : std_logic_vector (3 downto 0) := "0000";
-- Sinal para conectar estatística com display.
signal bcd : std_logic_vector (6 to 0);
-- Conta quantas vezes o valor de 'S' aparece no vetor.
signal conta_s : integer range 0 to 15;
begin
process (vetor, clk, modo)
-- Transforma o valor binário do grupo 'k' em inteiro.
variable grupo : integer range 0 to 15;
begin
-- Função GERA e VALIDA implementadas juntas.
if (modo = '0') then
-- Variável que contém tamanho do grupo.
grupo := to_integer(unsigned(k));
-- Aplica a geração aleatória.
vetor(grupo) <= vetor(0) xor vetor(1);
-- Da o shift nos bits em borda de subida.
if (clk'event and clk = '1' and hab_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
elsif (but_clk'event and but_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
end if;
-- VALIDA
-- Se os 4 últimos digitos do vetor foram iguais ao valor de 'S' então conta.
if (vetor(0) = s(0) and vetor(1) = s(1) and vetor(2) = s(2) and vetor(3) = s(3)) then
conta_s <= conta_s + 1;
end if;
end if;
end process;
-- Atribui valor inteiro da contagem para sinal.
estatistica <= std_logic_vector(to_unsigned(conta_s, 4));
-- BCD.
process (estatistica, clk)
begin
if (estatistica = "0000") then -- 0
bcd <= "1111110";
elsif (estatistica = "0001") then -- 1
bcd <= "0110000";
elsif (estatistica = "0010") then -- 2
bcd <= "1101101";
elsif (estatistica = "0011") then -- 3
bcd <= "1111001";
elsif (estatistica = "0100") then -- 4
bcd <= "0110010";
elsif (estatistica = "0101") then -- 5
bcd <= "1011010";
elsif (estatistica = "0110") then -- 6
bcd <= "1011111";
elsif (estatistica = "0111") then -- 7
bcd <= "1110000";
elsif (estatistica = "1000") then -- 8
bcd <= "1111111";
elsif (estatistica = "1001") then -- 9
bcd <= "1111011";
elsif (estatistica = "1010") then -- A
bcd <= "1110111";
elsif (estatistica = "1011") then -- B
bcd <= "0011111";
elsif (estatistica = "1100") then -- C
bcd <= "1001110";
elsif (estatistica = "1101") then -- D
bcd <= "0111101";
elsif (estatistica = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Inverte os valores do display pois é anodo.
display <= not bcd;
-- Atribui o valor do vetor deslocado aos LEDs de saida.
leds <= vetor;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AwWbkafRpmUgr8V92aHEZ2sY97/tHJvETsM1hSGphQtxrQq/xYaEsMaIXwwIvNrsNqxAJaVsvRvn
JMezsz7KyA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hq7YGrjuSDXZDCwYl5lV4kV1UuWYLCUEpnqnkQMEJAIC682Z5TUa0P809XfzdZeZw1MaF4Vc1NTx
E6ECjowP8EjtZeAbczyq7rEitVSULP+P4HXfxdy1uBiRfy387pIjihUCPJo8F1EK6Pr18BnW4UFA
z5m5S+Zjb35YdVVlvZ0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
J8z0ebrW8RdhwtS+c3+yPkwDpT9bxR90BFVWq4BuC7ZCtTRNs5gJ78QUtPbGYYc6lMHulIHX3Olk
Uk5QYrVS2ruhe0vDjJ8oAWj3jtIdRhE7qk5zNEwYcs7UqxZLtwhp+iVK5tkcsM8T/h2S6icKkUoU
4WL+LwFYG5AwBUW5aSkMRcejAOXf9e1BB0YZ7XaNi+Q06conYt4i5JKg++dFLNYJQfL9vQaFF8t4
JibkWrzEEOrlLoSR0jtqLvCaF8fNssW3ksYb/K3sqRCy6Q1uiBl2mFiZdbbfvufHl2+s9ozqn8KB
HzW8coY1ZgOdltmzg2pWNj6NHJFP9eRfVW9tTQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
djyuBIY5lgB9Uah20g7An2w3eBIDkloASAR/7QYa3ADm6slTzhRhNLKiMQbhYssniSYzEU0NpSS3
u7TRZQgLVqTBRl9WE019cm7QmiwOrZYXaKpoNl/O1nkiwyUY39dlYBPhtQx9t+neH5MAeuBRFnxg
kwXgCqZsJJw7WPq8dVM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GYo3RT7lBroRGVFGSAVwtqGNouH5bPbzrA3cFwK81BiaEmyyuWtTT2RJ2W+EAy3bVWR+pGUnEvSX
+fSQUpVwxaNVk4MhOz6vAEt0Xy9vBe54e7bOYB0bV5BnrKNIN3K10ipZSOSaImlVVQfNj8BQx0BO
ttkRmfedmZpVm+hWOLhtlW4L3bUeW86pm5MhoVtyWf3NOgGk1SO5bAkF761GXDhL0IrsoHAbT6DF
dQz0U22yj1f8bDS5bG2Sy3oxiHmYIZT3QNUvwx7rjUhlmZZIxF6mtpWUP83x9N6i9qf0uiloQ7z9
+7Y6KZ9G20JjYodcnBkWdgbus7Wp+iW57er5JA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
6gGn+h571+YsuilMHPBJbr73+Q6FWgUD5B1TM3cuivdUulxEdMqnG9Wpy/PpETE7slHiQIMRtv+0
/mgRZcxzg3xSxjPCIhEWQqzaM/IRFODjEVABeip5KK6cd4q8pbxlS+i85z6lA/zQonBc6sSif1dd
d4PNW5Jasn6A9kzHYbufQC6Q9lM2+DAAWTY8pB42ThtMzPEz4weaIomzy98EECmbQsI0rimWvFQH
YK74RGZcfPKcR/WZH4L4COC1AbP64+GtsJxH7/3K78+udbHK/gUaazya0pN956+h5dQfJeGGZNRB
k5h3y6L0YnQhdm4Qi8gKwnh8k6mUG+KUqNv1ilSa/hgPN/VRHKe47a39534rQ6Mkx1zkInPPdmcs
PtUF/IpWp4FGn8Qp2Eq8qScRFsFHRUaIXag1TMik8IDWCHKBaazWTZYpSDZgX4mPutgd4askcx5Q
ky4rvN9GGQfrlIGTREWBm1RxhuLxvOvbqhNQFhufsoPTFTXPfJv7cNYWnZZan+FB2dk4ryHKznGO
gvzue3XqNTQTSw+B/XfZC1owxcGXMqvh4FLv/uZ8gXv+N4RRyAoY5aYPlDmzRimkYWwrFM8c621n
fuJ6Byyrdbjuz6acIz5G1WpsNmFF1ITxG2AsfV+74qDcWt9g04flZ4tuikInk9xfUH9CS9Gj9oee
6AMwbYg7rkNsQ4xMIcV6jf4Fmov9BZyKwrDYaWQ6R4t31ETDzHSG0AceXwViNSzjRu6AeorzFm5c
0Di0S6jmiYn7RzqT+SntD+RriLTJl75AfnqcARgZPRbyjwuU1274AJKcAZmSHTVfduJ8lau5woFp
2Q0v3+A42MGwc1iXjkAqTg2c6/un0pUEyfGdIpXNv0Hu3kS3/rZt9AHtOYVii2rFAuB1GXagQ53I
/1Wp1H7QJ7bQqJRmGaSGyA1gg8NdFwg9CvGqWwTtE3rp+yDNv6bu5Ekwc0kDecx/WTC6ACOKRNZH
pkOU0pr9mfDns0HqSKbpmSOs2ny4nPWUwEt1euTXEPS618pitaa/t26S9l1RLGV+D3EZr4g+odzu
fWgl5Lo9J7ZXpldxyt7CteqDbjREsaPgqRWCpbHLBrgCi65UgzuiaFVDHEwBSLPmerdolHGaS9I8
2azHYYkXW9pph/XmgMUPQ//pOK3gm4gpjnWm/RaJDNcB0pHw5WZVa+aI52BM3xHYzEAL2b3ElhIn
LJS9gqU29t/Y2FXrdwxoG4X1MVMdTnYBQyZ5SXzZmTQWQmG01YUcCyTTpsIQyP3HW+ekuKHIj5/v
Nr3mpruey98UTyUz67dCDG5BqmPqTybXHdzPUlU7XMhDQOcltrz5D7p7lq0N1Z1Pw/hPA/vmsKVM
FFAxyQ1UhYNh5DI3gT794SK62uFgeJVWUfNzRUSexgVSQACps023pe8J7cHLBuhOlwn9MQ2CDtSx
u7xX5dPzayOzYx0dVxnfoAtHuobe/52EylxFLPYg4kW6I8okcXwhYSbfzkZU1ypKHzeX1ARjW19G
YUWIqXEaovGiHOf9YCHmUg0iuA/mOcZhwQaJz/iNEkukX75nXiSMbclC3zQQcrLVmbTioJrDpPXO
3/Wu7uwY3LMtx/WEq2RlcrPts3J0gpDB20OmyPnprG00byZLfyWw66wOaTq+T1vVq1SPgzrGpwnX
dXI+62ovEYBf3slre/2BbUtHeqUUCx+AcWYxkisuMgsDuyju0MoRWLYeTY/CHkiEAtWl6cVLpqOP
la+gK1iQCTZqcrta3wAAGssrjWTcHU7VzLpsbMCcO8U2y1yQEWF532f7OOuqa0hIJwbY/CAI8eq5
L5Kbkt2xxN5eH5ciSg7FxRFUzfJW6vRSrOCDI6JZ7D06L9zkrCNCy3Sg1Hqn9EyDnPOGXWonKx9j
2nSrp19CpkrIhp3ql154p41iVcePbh1dxxxdha1te2jjUhygfriqm85DKkfb8pQnkkQwosWoKJwE
roQss+J6LymbGgkDYyGj3a2l1UHKg7tWUkRzmq5lDuw9yqJdhR7tEc8yrH1ox6zLFIP+YmoEcQQZ
yal2gdkh5h5avU++pozGddPX6lQQXGD2ocN531alzDsAspxB1ZAXPjJzN/rUf0RMEEhmaeJO84V7
9PhHKTIPBy1Yr4w77XFaBSyly6Qcf8IBGDJawyy02Zy9ZvZoxqyR09OIuWENklyLHsSdEJzVFe0p
1HUPgBa4NeBG5pPt0Jc+M+eedCqei09/MReoLiNWJ31JbS940cWfFD3FI6OPfhM+umxHajOlm+oZ
LJyOv/6AtCH4zXxO6+oalNFF33Si3Ew+j4NOYxtVxu+jUY8sE1ylryjyvHzaBUaw63RZ9d73eVEs
qrM2tAIAS9XG6n4gwCvG9IMkDCs55X70omqoIAnZ4AdfovtSoU0Un5UaANAcycqujrnF/MWtmGgr
NpGJFh0XhHGT4fmHEnNWoLxwqfcK+2d6Xof58FQTnzlXok5o5l/UtpQG5WFWcMF56GiwbidAVeif
K/twAggsD1bkuza/lW74DFMmP0ffZ/2Z1Mm+OTtmJLcHESTVuumqnwaGJzJa79Bylhi/H2VCHhXe
evEpQPOOjHmkOJedTkvTEBztvOf/i7BH5KUSwfon3hgzVfPAJMDc0pbqUmPbhEbbYvzF6DeWY6Hc
K8usDf/e/rqbMbwwt7xlv/hszdMJ9DRcxng5ar4Yel184qmX5W9QXQ3MeDmARbJGKDWzzHkX3EDV
Z83he9RU0HKbwjlTrsJf1LWoPXcPPyUADnnTsQv85C7pyJ/XFtIVUqPbSpsNRsfVRyV2EngJuvsE
KuxsNcz5Hr0PawIzgtxmPuBrjpF7ZwQSidUlqdnRTWhobiR+Rel48yFkfgQX4ovIjkI3NB2+HaKv
sNYsC04wiRujHE1hiZptpzrdNjeKApWfgoh8JMU6HornWdYTWeJ+ABBz9PI01dXLaVWf5lW3InL0
LUIUPmV2MrBdsRq0OQoUfH5xRqCSbDikzsfE4CAhteDHQjusLs7X31E8Nu2QBdFwcK85I3+qry0o
uO+m2JrW11CzFGWCKgcXE50oYKsRgOoOTS+ndC7ZLMuJ0aYA2mjEo7MrP3FAqLyMbodrOLyqAzFy
mcvo4o7TzHqA742vb3hJT+jQKBcqNEYOL1OmW8m4q29SlRPcPKDSjY0nDymFRhZAc6lL71+7HVAm
O2GoZ2GmO7FI+bqa2HEZAvqaOMkXI/ywjYSAMRiRJ8rFnMHSdiD/23FPQJ0xeatSLfSMWU9ktrx/
JddGAay1QW9I9gCl/9gfR53siy0tLVU84IybK7PU0ByfL7mz/x6myWSJRCmrFqlBNrYAQS8BftNd
zIJn04TZZsPGusyn6WwwjsydqxVqAQchRiPlJN0Y1Oi7J+gmGZ4vfl4ZT+jnnWHHwOUJPTVkaJly
omC1uL7c+WjYGMqQQq2aShcje6Rg9+Vv+jurN2kPv9kvtXl2Le3vuzQhH+tIM/xJAiPa7ZZPnNdV
IzVImMHPBaiXFJHwFwIwHB6T/4pD4iF6C41xryBJa2aJwO7ZkS9joK/Vq8XtbcY4hCFQxRXYCH+K
fjAAi05t9wsTnTqtNMYzElKkwNczcInCDMpIioF3llSEzcof/AKQJH2bcBRJXFYdF6+CVebelYRs
6kJIDeRdSyWFQcaQU8lpho/KYk8kQ+UwGXFLC8GLLF3VVC+6XFoluv362dkIvslbdOkkY8nTuLom
fHlDgsTZk78sQaHyOb4C91+Fo396YYL25k2JV8SiC/bVdb5BFYQvnEf6uPb9E0Rd8G2evA2O9UVH
UPjSCPokP9jAuRVLgd6O6lZKBcyAIoM1Bjn59AywXxo4jIhk11ENccEu9XpugUcOH78g3WgtvvBS
Mv1z/4FmDAgWBzW4nxiwgS0QHM9pttdjeya9fCUcT9p9AkqNyXv3HuxmKVmLKd1KihK1xFxOuoiF
OXfd1mYK7b+AT7wDp77pAM585ZlIdY97O+YgFxBz/vs88xD/wWKp/lqdCOWk0a9eeigXUtWVsY7q
oIyqeJHuCxSUrznjX0KWGjl5QjaQkjK5i3xcGHcGKXm38hkwEFkOAEmhbCGbEQzwHGfD1WIYh0hE
W7ai96GcAvr0BUU72XCum1U1J32L/ch7BfGVGEtYXuPbGlY31MXx4yxK75e6NR4HnHB4InZaYrEn
TzIGYIP7QDQnDoZ0TjUsQpskUzVUHDuGW3bj0adV/0QYEbGd+HIOGsB6NnkjQ2ZiRpPbLZi9VsQc
8IUFLTApzlZovXY2GrGUKQdXtqRbNPWCTSi8hfcFAmAb1qIq4C2k4iZy0ntkjcELUVK/3C6KiXgt
/t/dziZkmIfiYGHXGUsCxhK6K/E2k3CLE7WFHN8R1yj7+s9H5EdBbKeuNhaM1nrmxo5a8Mc5xmCi
Sfu3vySMTfP1zKHbXjAv/5fjGJk/olR7KAZvYOkF5rHiLHWDTZBR58oRYsqHAeNkQQJrsH1LpsA6
paSvrNAbHIQOTvsQcm/z14QDpolPPNOuNm2YLnEA0lId2KMsV9H66fATCzA2fITFAYSU+/CczsyY
87F6l+quK9VqwSJSHFgEkVGz3nR4H7D+j29AZBvq4IgAGrkvY1KR1QoP/wNPhpZYIWxn/ojemlqh
C6S3K+HI1M+G+tXJ1iG0G2rDtPq6CW3Gz57q0X6lu+7GFpGL+DAsmiLCFng2+O6ki6WOD7KbpOy5
vRqNE3QJIAmLrsiQ28Mppdf5Aos/ydrvZnvfUoojKQcsO1pCIJSxQREz40pEWoFr518D6lUwj3rw
oQjzdiE8Ksi5mtVLAR6eXmlUn3gS4BSO6WhelegI0U/Yx6Dfjxfyso2COr8vKfLrzj082OHyzBZL
FcH1rsU7hzbpIXpbeQ9XZ62ZA38spjibk8uGyKqMrE5N3Y0VDYjNZMHHx9KWXZ2gtWN+81UnULfO
WO2WXfDCUFa4W2NMwPSkup/WuYfeRYyG2lb8iKWHir+PRuLM3+0dle2s5FX6k2uPbDCy9e7zlMnH
DLeeS2crb6h7ATxr0yf+FWno2/H+1tAau5hfaETKoC1VR3geuE0KuNtO6DzIaGL/HB37++KYh5AL
332L1qCOMil8Xihru4PWZ67fvI3b96G1VWALYtLdOno/olJpIBY/gdZws4/RDJUi0CAUcAk+KTgd
t1oUJk+mprcZ7ecQXKOs5DWjiE4caZHQgpswgHszz+eHs0P4jcjt1YsfMUUOAEkKTg/dmfle5H1R
/PvWH5+a+QFep+6Dr1+a7pJyuNI+bkWNmZk+p0Kvoai0AbTHmRc79HFwvMLumB8zgf04ZNEXPNG9
Xmw4Rtfc2x8uL4yONhYgxWV+aN9yMZu6R4pfFLi2Tf+RoCj+zqugu2zCcc5lghBWN+Uu3OO8x6KT
caNc+Lh5IyhYdy+lIVwJahcJcLM/8GFvK/3nraIn423NNKrQrsQIDXw77AtXjhbgpYkcbg4kZmLq
qJF4xrapXmY=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AwWbkafRpmUgr8V92aHEZ2sY97/tHJvETsM1hSGphQtxrQq/xYaEsMaIXwwIvNrsNqxAJaVsvRvn
JMezsz7KyA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hq7YGrjuSDXZDCwYl5lV4kV1UuWYLCUEpnqnkQMEJAIC682Z5TUa0P809XfzdZeZw1MaF4Vc1NTx
E6ECjowP8EjtZeAbczyq7rEitVSULP+P4HXfxdy1uBiRfy387pIjihUCPJo8F1EK6Pr18BnW4UFA
z5m5S+Zjb35YdVVlvZ0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
J8z0ebrW8RdhwtS+c3+yPkwDpT9bxR90BFVWq4BuC7ZCtTRNs5gJ78QUtPbGYYc6lMHulIHX3Olk
Uk5QYrVS2ruhe0vDjJ8oAWj3jtIdRhE7qk5zNEwYcs7UqxZLtwhp+iVK5tkcsM8T/h2S6icKkUoU
4WL+LwFYG5AwBUW5aSkMRcejAOXf9e1BB0YZ7XaNi+Q06conYt4i5JKg++dFLNYJQfL9vQaFF8t4
JibkWrzEEOrlLoSR0jtqLvCaF8fNssW3ksYb/K3sqRCy6Q1uiBl2mFiZdbbfvufHl2+s9ozqn8KB
HzW8coY1ZgOdltmzg2pWNj6NHJFP9eRfVW9tTQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
djyuBIY5lgB9Uah20g7An2w3eBIDkloASAR/7QYa3ADm6slTzhRhNLKiMQbhYssniSYzEU0NpSS3
u7TRZQgLVqTBRl9WE019cm7QmiwOrZYXaKpoNl/O1nkiwyUY39dlYBPhtQx9t+neH5MAeuBRFnxg
kwXgCqZsJJw7WPq8dVM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GYo3RT7lBroRGVFGSAVwtqGNouH5bPbzrA3cFwK81BiaEmyyuWtTT2RJ2W+EAy3bVWR+pGUnEvSX
+fSQUpVwxaNVk4MhOz6vAEt0Xy9vBe54e7bOYB0bV5BnrKNIN3K10ipZSOSaImlVVQfNj8BQx0BO
ttkRmfedmZpVm+hWOLhtlW4L3bUeW86pm5MhoVtyWf3NOgGk1SO5bAkF761GXDhL0IrsoHAbT6DF
dQz0U22yj1f8bDS5bG2Sy3oxiHmYIZT3QNUvwx7rjUhlmZZIxF6mtpWUP83x9N6i9qf0uiloQ7z9
+7Y6KZ9G20JjYodcnBkWdgbus7Wp+iW57er5JA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
6gGn+h571+YsuilMHPBJbr73+Q6FWgUD5B1TM3cuivdUulxEdMqnG9Wpy/PpETE7slHiQIMRtv+0
/mgRZcxzg3xSxjPCIhEWQqzaM/IRFODjEVABeip5KK6cd4q8pbxlS+i85z6lA/zQonBc6sSif1dd
d4PNW5Jasn6A9kzHYbufQC6Q9lM2+DAAWTY8pB42ThtMzPEz4weaIomzy98EECmbQsI0rimWvFQH
YK74RGZcfPKcR/WZH4L4COC1AbP64+GtsJxH7/3K78+udbHK/gUaazya0pN956+h5dQfJeGGZNRB
k5h3y6L0YnQhdm4Qi8gKwnh8k6mUG+KUqNv1ilSa/hgPN/VRHKe47a39534rQ6Mkx1zkInPPdmcs
PtUF/IpWp4FGn8Qp2Eq8qScRFsFHRUaIXag1TMik8IDWCHKBaazWTZYpSDZgX4mPutgd4askcx5Q
ky4rvN9GGQfrlIGTREWBm1RxhuLxvOvbqhNQFhufsoPTFTXPfJv7cNYWnZZan+FB2dk4ryHKznGO
gvzue3XqNTQTSw+B/XfZC1owxcGXMqvh4FLv/uZ8gXv+N4RRyAoY5aYPlDmzRimkYWwrFM8c621n
fuJ6Byyrdbjuz6acIz5G1WpsNmFF1ITxG2AsfV+74qDcWt9g04flZ4tuikInk9xfUH9CS9Gj9oee
6AMwbYg7rkNsQ4xMIcV6jf4Fmov9BZyKwrDYaWQ6R4t31ETDzHSG0AceXwViNSzjRu6AeorzFm5c
0Di0S6jmiYn7RzqT+SntD+RriLTJl75AfnqcARgZPRbyjwuU1274AJKcAZmSHTVfduJ8lau5woFp
2Q0v3+A42MGwc1iXjkAqTg2c6/un0pUEyfGdIpXNv0Hu3kS3/rZt9AHtOYVii2rFAuB1GXagQ53I
/1Wp1H7QJ7bQqJRmGaSGyA1gg8NdFwg9CvGqWwTtE3rp+yDNv6bu5Ekwc0kDecx/WTC6ACOKRNZH
pkOU0pr9mfDns0HqSKbpmSOs2ny4nPWUwEt1euTXEPS618pitaa/t26S9l1RLGV+D3EZr4g+odzu
fWgl5Lo9J7ZXpldxyt7CteqDbjREsaPgqRWCpbHLBrgCi65UgzuiaFVDHEwBSLPmerdolHGaS9I8
2azHYYkXW9pph/XmgMUPQ//pOK3gm4gpjnWm/RaJDNcB0pHw5WZVa+aI52BM3xHYzEAL2b3ElhIn
LJS9gqU29t/Y2FXrdwxoG4X1MVMdTnYBQyZ5SXzZmTQWQmG01YUcCyTTpsIQyP3HW+ekuKHIj5/v
Nr3mpruey98UTyUz67dCDG5BqmPqTybXHdzPUlU7XMhDQOcltrz5D7p7lq0N1Z1Pw/hPA/vmsKVM
FFAxyQ1UhYNh5DI3gT794SK62uFgeJVWUfNzRUSexgVSQACps023pe8J7cHLBuhOlwn9MQ2CDtSx
u7xX5dPzayOzYx0dVxnfoAtHuobe/52EylxFLPYg4kW6I8okcXwhYSbfzkZU1ypKHzeX1ARjW19G
YUWIqXEaovGiHOf9YCHmUg0iuA/mOcZhwQaJz/iNEkukX75nXiSMbclC3zQQcrLVmbTioJrDpPXO
3/Wu7uwY3LMtx/WEq2RlcrPts3J0gpDB20OmyPnprG00byZLfyWw66wOaTq+T1vVq1SPgzrGpwnX
dXI+62ovEYBf3slre/2BbUtHeqUUCx+AcWYxkisuMgsDuyju0MoRWLYeTY/CHkiEAtWl6cVLpqOP
la+gK1iQCTZqcrta3wAAGssrjWTcHU7VzLpsbMCcO8U2y1yQEWF532f7OOuqa0hIJwbY/CAI8eq5
L5Kbkt2xxN5eH5ciSg7FxRFUzfJW6vRSrOCDI6JZ7D06L9zkrCNCy3Sg1Hqn9EyDnPOGXWonKx9j
2nSrp19CpkrIhp3ql154p41iVcePbh1dxxxdha1te2jjUhygfriqm85DKkfb8pQnkkQwosWoKJwE
roQss+J6LymbGgkDYyGj3a2l1UHKg7tWUkRzmq5lDuw9yqJdhR7tEc8yrH1ox6zLFIP+YmoEcQQZ
yal2gdkh5h5avU++pozGddPX6lQQXGD2ocN531alzDsAspxB1ZAXPjJzN/rUf0RMEEhmaeJO84V7
9PhHKTIPBy1Yr4w77XFaBSyly6Qcf8IBGDJawyy02Zy9ZvZoxqyR09OIuWENklyLHsSdEJzVFe0p
1HUPgBa4NeBG5pPt0Jc+M+eedCqei09/MReoLiNWJ31JbS940cWfFD3FI6OPfhM+umxHajOlm+oZ
LJyOv/6AtCH4zXxO6+oalNFF33Si3Ew+j4NOYxtVxu+jUY8sE1ylryjyvHzaBUaw63RZ9d73eVEs
qrM2tAIAS9XG6n4gwCvG9IMkDCs55X70omqoIAnZ4AdfovtSoU0Un5UaANAcycqujrnF/MWtmGgr
NpGJFh0XhHGT4fmHEnNWoLxwqfcK+2d6Xof58FQTnzlXok5o5l/UtpQG5WFWcMF56GiwbidAVeif
K/twAggsD1bkuza/lW74DFMmP0ffZ/2Z1Mm+OTtmJLcHESTVuumqnwaGJzJa79Bylhi/H2VCHhXe
evEpQPOOjHmkOJedTkvTEBztvOf/i7BH5KUSwfon3hgzVfPAJMDc0pbqUmPbhEbbYvzF6DeWY6Hc
K8usDf/e/rqbMbwwt7xlv/hszdMJ9DRcxng5ar4Yel184qmX5W9QXQ3MeDmARbJGKDWzzHkX3EDV
Z83he9RU0HKbwjlTrsJf1LWoPXcPPyUADnnTsQv85C7pyJ/XFtIVUqPbSpsNRsfVRyV2EngJuvsE
KuxsNcz5Hr0PawIzgtxmPuBrjpF7ZwQSidUlqdnRTWhobiR+Rel48yFkfgQX4ovIjkI3NB2+HaKv
sNYsC04wiRujHE1hiZptpzrdNjeKApWfgoh8JMU6HornWdYTWeJ+ABBz9PI01dXLaVWf5lW3InL0
LUIUPmV2MrBdsRq0OQoUfH5xRqCSbDikzsfE4CAhteDHQjusLs7X31E8Nu2QBdFwcK85I3+qry0o
uO+m2JrW11CzFGWCKgcXE50oYKsRgOoOTS+ndC7ZLMuJ0aYA2mjEo7MrP3FAqLyMbodrOLyqAzFy
mcvo4o7TzHqA742vb3hJT+jQKBcqNEYOL1OmW8m4q29SlRPcPKDSjY0nDymFRhZAc6lL71+7HVAm
O2GoZ2GmO7FI+bqa2HEZAvqaOMkXI/ywjYSAMRiRJ8rFnMHSdiD/23FPQJ0xeatSLfSMWU9ktrx/
JddGAay1QW9I9gCl/9gfR53siy0tLVU84IybK7PU0ByfL7mz/x6myWSJRCmrFqlBNrYAQS8BftNd
zIJn04TZZsPGusyn6WwwjsydqxVqAQchRiPlJN0Y1Oi7J+gmGZ4vfl4ZT+jnnWHHwOUJPTVkaJly
omC1uL7c+WjYGMqQQq2aShcje6Rg9+Vv+jurN2kPv9kvtXl2Le3vuzQhH+tIM/xJAiPa7ZZPnNdV
IzVImMHPBaiXFJHwFwIwHB6T/4pD4iF6C41xryBJa2aJwO7ZkS9joK/Vq8XtbcY4hCFQxRXYCH+K
fjAAi05t9wsTnTqtNMYzElKkwNczcInCDMpIioF3llSEzcof/AKQJH2bcBRJXFYdF6+CVebelYRs
6kJIDeRdSyWFQcaQU8lpho/KYk8kQ+UwGXFLC8GLLF3VVC+6XFoluv362dkIvslbdOkkY8nTuLom
fHlDgsTZk78sQaHyOb4C91+Fo396YYL25k2JV8SiC/bVdb5BFYQvnEf6uPb9E0Rd8G2evA2O9UVH
UPjSCPokP9jAuRVLgd6O6lZKBcyAIoM1Bjn59AywXxo4jIhk11ENccEu9XpugUcOH78g3WgtvvBS
Mv1z/4FmDAgWBzW4nxiwgS0QHM9pttdjeya9fCUcT9p9AkqNyXv3HuxmKVmLKd1KihK1xFxOuoiF
OXfd1mYK7b+AT7wDp77pAM585ZlIdY97O+YgFxBz/vs88xD/wWKp/lqdCOWk0a9eeigXUtWVsY7q
oIyqeJHuCxSUrznjX0KWGjl5QjaQkjK5i3xcGHcGKXm38hkwEFkOAEmhbCGbEQzwHGfD1WIYh0hE
W7ai96GcAvr0BUU72XCum1U1J32L/ch7BfGVGEtYXuPbGlY31MXx4yxK75e6NR4HnHB4InZaYrEn
TzIGYIP7QDQnDoZ0TjUsQpskUzVUHDuGW3bj0adV/0QYEbGd+HIOGsB6NnkjQ2ZiRpPbLZi9VsQc
8IUFLTApzlZovXY2GrGUKQdXtqRbNPWCTSi8hfcFAmAb1qIq4C2k4iZy0ntkjcELUVK/3C6KiXgt
/t/dziZkmIfiYGHXGUsCxhK6K/E2k3CLE7WFHN8R1yj7+s9H5EdBbKeuNhaM1nrmxo5a8Mc5xmCi
Sfu3vySMTfP1zKHbXjAv/5fjGJk/olR7KAZvYOkF5rHiLHWDTZBR58oRYsqHAeNkQQJrsH1LpsA6
paSvrNAbHIQOTvsQcm/z14QDpolPPNOuNm2YLnEA0lId2KMsV9H66fATCzA2fITFAYSU+/CczsyY
87F6l+quK9VqwSJSHFgEkVGz3nR4H7D+j29AZBvq4IgAGrkvY1KR1QoP/wNPhpZYIWxn/ojemlqh
C6S3K+HI1M+G+tXJ1iG0G2rDtPq6CW3Gz57q0X6lu+7GFpGL+DAsmiLCFng2+O6ki6WOD7KbpOy5
vRqNE3QJIAmLrsiQ28Mppdf5Aos/ydrvZnvfUoojKQcsO1pCIJSxQREz40pEWoFr518D6lUwj3rw
oQjzdiE8Ksi5mtVLAR6eXmlUn3gS4BSO6WhelegI0U/Yx6Dfjxfyso2COr8vKfLrzj082OHyzBZL
FcH1rsU7hzbpIXpbeQ9XZ62ZA38spjibk8uGyKqMrE5N3Y0VDYjNZMHHx9KWXZ2gtWN+81UnULfO
WO2WXfDCUFa4W2NMwPSkup/WuYfeRYyG2lb8iKWHir+PRuLM3+0dle2s5FX6k2uPbDCy9e7zlMnH
DLeeS2crb6h7ATxr0yf+FWno2/H+1tAau5hfaETKoC1VR3geuE0KuNtO6DzIaGL/HB37++KYh5AL
332L1qCOMil8Xihru4PWZ67fvI3b96G1VWALYtLdOno/olJpIBY/gdZws4/RDJUi0CAUcAk+KTgd
t1oUJk+mprcZ7ecQXKOs5DWjiE4caZHQgpswgHszz+eHs0P4jcjt1YsfMUUOAEkKTg/dmfle5H1R
/PvWH5+a+QFep+6Dr1+a7pJyuNI+bkWNmZk+p0Kvoai0AbTHmRc79HFwvMLumB8zgf04ZNEXPNG9
Xmw4Rtfc2x8uL4yONhYgxWV+aN9yMZu6R4pfFLi2Tf+RoCj+zqugu2zCcc5lghBWN+Uu3OO8x6KT
caNc+Lh5IyhYdy+lIVwJahcJcLM/8GFvK/3nraIn423NNKrQrsQIDXw77AtXjhbgpYkcbg4kZmLq
qJF4xrapXmY=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AwWbkafRpmUgr8V92aHEZ2sY97/tHJvETsM1hSGphQtxrQq/xYaEsMaIXwwIvNrsNqxAJaVsvRvn
JMezsz7KyA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hq7YGrjuSDXZDCwYl5lV4kV1UuWYLCUEpnqnkQMEJAIC682Z5TUa0P809XfzdZeZw1MaF4Vc1NTx
E6ECjowP8EjtZeAbczyq7rEitVSULP+P4HXfxdy1uBiRfy387pIjihUCPJo8F1EK6Pr18BnW4UFA
z5m5S+Zjb35YdVVlvZ0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
J8z0ebrW8RdhwtS+c3+yPkwDpT9bxR90BFVWq4BuC7ZCtTRNs5gJ78QUtPbGYYc6lMHulIHX3Olk
Uk5QYrVS2ruhe0vDjJ8oAWj3jtIdRhE7qk5zNEwYcs7UqxZLtwhp+iVK5tkcsM8T/h2S6icKkUoU
4WL+LwFYG5AwBUW5aSkMRcejAOXf9e1BB0YZ7XaNi+Q06conYt4i5JKg++dFLNYJQfL9vQaFF8t4
JibkWrzEEOrlLoSR0jtqLvCaF8fNssW3ksYb/K3sqRCy6Q1uiBl2mFiZdbbfvufHl2+s9ozqn8KB
HzW8coY1ZgOdltmzg2pWNj6NHJFP9eRfVW9tTQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
djyuBIY5lgB9Uah20g7An2w3eBIDkloASAR/7QYa3ADm6slTzhRhNLKiMQbhYssniSYzEU0NpSS3
u7TRZQgLVqTBRl9WE019cm7QmiwOrZYXaKpoNl/O1nkiwyUY39dlYBPhtQx9t+neH5MAeuBRFnxg
kwXgCqZsJJw7WPq8dVM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GYo3RT7lBroRGVFGSAVwtqGNouH5bPbzrA3cFwK81BiaEmyyuWtTT2RJ2W+EAy3bVWR+pGUnEvSX
+fSQUpVwxaNVk4MhOz6vAEt0Xy9vBe54e7bOYB0bV5BnrKNIN3K10ipZSOSaImlVVQfNj8BQx0BO
ttkRmfedmZpVm+hWOLhtlW4L3bUeW86pm5MhoVtyWf3NOgGk1SO5bAkF761GXDhL0IrsoHAbT6DF
dQz0U22yj1f8bDS5bG2Sy3oxiHmYIZT3QNUvwx7rjUhlmZZIxF6mtpWUP83x9N6i9qf0uiloQ7z9
+7Y6KZ9G20JjYodcnBkWdgbus7Wp+iW57er5JA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
6gGn+h571+YsuilMHPBJbr73+Q6FWgUD5B1TM3cuivdUulxEdMqnG9Wpy/PpETE7slHiQIMRtv+0
/mgRZcxzg3xSxjPCIhEWQqzaM/IRFODjEVABeip5KK6cd4q8pbxlS+i85z6lA/zQonBc6sSif1dd
d4PNW5Jasn6A9kzHYbufQC6Q9lM2+DAAWTY8pB42ThtMzPEz4weaIomzy98EECmbQsI0rimWvFQH
YK74RGZcfPKcR/WZH4L4COC1AbP64+GtsJxH7/3K78+udbHK/gUaazya0pN956+h5dQfJeGGZNRB
k5h3y6L0YnQhdm4Qi8gKwnh8k6mUG+KUqNv1ilSa/hgPN/VRHKe47a39534rQ6Mkx1zkInPPdmcs
PtUF/IpWp4FGn8Qp2Eq8qScRFsFHRUaIXag1TMik8IDWCHKBaazWTZYpSDZgX4mPutgd4askcx5Q
ky4rvN9GGQfrlIGTREWBm1RxhuLxvOvbqhNQFhufsoPTFTXPfJv7cNYWnZZan+FB2dk4ryHKznGO
gvzue3XqNTQTSw+B/XfZC1owxcGXMqvh4FLv/uZ8gXv+N4RRyAoY5aYPlDmzRimkYWwrFM8c621n
fuJ6Byyrdbjuz6acIz5G1WpsNmFF1ITxG2AsfV+74qDcWt9g04flZ4tuikInk9xfUH9CS9Gj9oee
6AMwbYg7rkNsQ4xMIcV6jf4Fmov9BZyKwrDYaWQ6R4t31ETDzHSG0AceXwViNSzjRu6AeorzFm5c
0Di0S6jmiYn7RzqT+SntD+RriLTJl75AfnqcARgZPRbyjwuU1274AJKcAZmSHTVfduJ8lau5woFp
2Q0v3+A42MGwc1iXjkAqTg2c6/un0pUEyfGdIpXNv0Hu3kS3/rZt9AHtOYVii2rFAuB1GXagQ53I
/1Wp1H7QJ7bQqJRmGaSGyA1gg8NdFwg9CvGqWwTtE3rp+yDNv6bu5Ekwc0kDecx/WTC6ACOKRNZH
pkOU0pr9mfDns0HqSKbpmSOs2ny4nPWUwEt1euTXEPS618pitaa/t26S9l1RLGV+D3EZr4g+odzu
fWgl5Lo9J7ZXpldxyt7CteqDbjREsaPgqRWCpbHLBrgCi65UgzuiaFVDHEwBSLPmerdolHGaS9I8
2azHYYkXW9pph/XmgMUPQ//pOK3gm4gpjnWm/RaJDNcB0pHw5WZVa+aI52BM3xHYzEAL2b3ElhIn
LJS9gqU29t/Y2FXrdwxoG4X1MVMdTnYBQyZ5SXzZmTQWQmG01YUcCyTTpsIQyP3HW+ekuKHIj5/v
Nr3mpruey98UTyUz67dCDG5BqmPqTybXHdzPUlU7XMhDQOcltrz5D7p7lq0N1Z1Pw/hPA/vmsKVM
FFAxyQ1UhYNh5DI3gT794SK62uFgeJVWUfNzRUSexgVSQACps023pe8J7cHLBuhOlwn9MQ2CDtSx
u7xX5dPzayOzYx0dVxnfoAtHuobe/52EylxFLPYg4kW6I8okcXwhYSbfzkZU1ypKHzeX1ARjW19G
YUWIqXEaovGiHOf9YCHmUg0iuA/mOcZhwQaJz/iNEkukX75nXiSMbclC3zQQcrLVmbTioJrDpPXO
3/Wu7uwY3LMtx/WEq2RlcrPts3J0gpDB20OmyPnprG00byZLfyWw66wOaTq+T1vVq1SPgzrGpwnX
dXI+62ovEYBf3slre/2BbUtHeqUUCx+AcWYxkisuMgsDuyju0MoRWLYeTY/CHkiEAtWl6cVLpqOP
la+gK1iQCTZqcrta3wAAGssrjWTcHU7VzLpsbMCcO8U2y1yQEWF532f7OOuqa0hIJwbY/CAI8eq5
L5Kbkt2xxN5eH5ciSg7FxRFUzfJW6vRSrOCDI6JZ7D06L9zkrCNCy3Sg1Hqn9EyDnPOGXWonKx9j
2nSrp19CpkrIhp3ql154p41iVcePbh1dxxxdha1te2jjUhygfriqm85DKkfb8pQnkkQwosWoKJwE
roQss+J6LymbGgkDYyGj3a2l1UHKg7tWUkRzmq5lDuw9yqJdhR7tEc8yrH1ox6zLFIP+YmoEcQQZ
yal2gdkh5h5avU++pozGddPX6lQQXGD2ocN531alzDsAspxB1ZAXPjJzN/rUf0RMEEhmaeJO84V7
9PhHKTIPBy1Yr4w77XFaBSyly6Qcf8IBGDJawyy02Zy9ZvZoxqyR09OIuWENklyLHsSdEJzVFe0p
1HUPgBa4NeBG5pPt0Jc+M+eedCqei09/MReoLiNWJ31JbS940cWfFD3FI6OPfhM+umxHajOlm+oZ
LJyOv/6AtCH4zXxO6+oalNFF33Si3Ew+j4NOYxtVxu+jUY8sE1ylryjyvHzaBUaw63RZ9d73eVEs
qrM2tAIAS9XG6n4gwCvG9IMkDCs55X70omqoIAnZ4AdfovtSoU0Un5UaANAcycqujrnF/MWtmGgr
NpGJFh0XhHGT4fmHEnNWoLxwqfcK+2d6Xof58FQTnzlXok5o5l/UtpQG5WFWcMF56GiwbidAVeif
K/twAggsD1bkuza/lW74DFMmP0ffZ/2Z1Mm+OTtmJLcHESTVuumqnwaGJzJa79Bylhi/H2VCHhXe
evEpQPOOjHmkOJedTkvTEBztvOf/i7BH5KUSwfon3hgzVfPAJMDc0pbqUmPbhEbbYvzF6DeWY6Hc
K8usDf/e/rqbMbwwt7xlv/hszdMJ9DRcxng5ar4Yel184qmX5W9QXQ3MeDmARbJGKDWzzHkX3EDV
Z83he9RU0HKbwjlTrsJf1LWoPXcPPyUADnnTsQv85C7pyJ/XFtIVUqPbSpsNRsfVRyV2EngJuvsE
KuxsNcz5Hr0PawIzgtxmPuBrjpF7ZwQSidUlqdnRTWhobiR+Rel48yFkfgQX4ovIjkI3NB2+HaKv
sNYsC04wiRujHE1hiZptpzrdNjeKApWfgoh8JMU6HornWdYTWeJ+ABBz9PI01dXLaVWf5lW3InL0
LUIUPmV2MrBdsRq0OQoUfH5xRqCSbDikzsfE4CAhteDHQjusLs7X31E8Nu2QBdFwcK85I3+qry0o
uO+m2JrW11CzFGWCKgcXE50oYKsRgOoOTS+ndC7ZLMuJ0aYA2mjEo7MrP3FAqLyMbodrOLyqAzFy
mcvo4o7TzHqA742vb3hJT+jQKBcqNEYOL1OmW8m4q29SlRPcPKDSjY0nDymFRhZAc6lL71+7HVAm
O2GoZ2GmO7FI+bqa2HEZAvqaOMkXI/ywjYSAMRiRJ8rFnMHSdiD/23FPQJ0xeatSLfSMWU9ktrx/
JddGAay1QW9I9gCl/9gfR53siy0tLVU84IybK7PU0ByfL7mz/x6myWSJRCmrFqlBNrYAQS8BftNd
zIJn04TZZsPGusyn6WwwjsydqxVqAQchRiPlJN0Y1Oi7J+gmGZ4vfl4ZT+jnnWHHwOUJPTVkaJly
omC1uL7c+WjYGMqQQq2aShcje6Rg9+Vv+jurN2kPv9kvtXl2Le3vuzQhH+tIM/xJAiPa7ZZPnNdV
IzVImMHPBaiXFJHwFwIwHB6T/4pD4iF6C41xryBJa2aJwO7ZkS9joK/Vq8XtbcY4hCFQxRXYCH+K
fjAAi05t9wsTnTqtNMYzElKkwNczcInCDMpIioF3llSEzcof/AKQJH2bcBRJXFYdF6+CVebelYRs
6kJIDeRdSyWFQcaQU8lpho/KYk8kQ+UwGXFLC8GLLF3VVC+6XFoluv362dkIvslbdOkkY8nTuLom
fHlDgsTZk78sQaHyOb4C91+Fo396YYL25k2JV8SiC/bVdb5BFYQvnEf6uPb9E0Rd8G2evA2O9UVH
UPjSCPokP9jAuRVLgd6O6lZKBcyAIoM1Bjn59AywXxo4jIhk11ENccEu9XpugUcOH78g3WgtvvBS
Mv1z/4FmDAgWBzW4nxiwgS0QHM9pttdjeya9fCUcT9p9AkqNyXv3HuxmKVmLKd1KihK1xFxOuoiF
OXfd1mYK7b+AT7wDp77pAM585ZlIdY97O+YgFxBz/vs88xD/wWKp/lqdCOWk0a9eeigXUtWVsY7q
oIyqeJHuCxSUrznjX0KWGjl5QjaQkjK5i3xcGHcGKXm38hkwEFkOAEmhbCGbEQzwHGfD1WIYh0hE
W7ai96GcAvr0BUU72XCum1U1J32L/ch7BfGVGEtYXuPbGlY31MXx4yxK75e6NR4HnHB4InZaYrEn
TzIGYIP7QDQnDoZ0TjUsQpskUzVUHDuGW3bj0adV/0QYEbGd+HIOGsB6NnkjQ2ZiRpPbLZi9VsQc
8IUFLTApzlZovXY2GrGUKQdXtqRbNPWCTSi8hfcFAmAb1qIq4C2k4iZy0ntkjcELUVK/3C6KiXgt
/t/dziZkmIfiYGHXGUsCxhK6K/E2k3CLE7WFHN8R1yj7+s9H5EdBbKeuNhaM1nrmxo5a8Mc5xmCi
Sfu3vySMTfP1zKHbXjAv/5fjGJk/olR7KAZvYOkF5rHiLHWDTZBR58oRYsqHAeNkQQJrsH1LpsA6
paSvrNAbHIQOTvsQcm/z14QDpolPPNOuNm2YLnEA0lId2KMsV9H66fATCzA2fITFAYSU+/CczsyY
87F6l+quK9VqwSJSHFgEkVGz3nR4H7D+j29AZBvq4IgAGrkvY1KR1QoP/wNPhpZYIWxn/ojemlqh
C6S3K+HI1M+G+tXJ1iG0G2rDtPq6CW3Gz57q0X6lu+7GFpGL+DAsmiLCFng2+O6ki6WOD7KbpOy5
vRqNE3QJIAmLrsiQ28Mppdf5Aos/ydrvZnvfUoojKQcsO1pCIJSxQREz40pEWoFr518D6lUwj3rw
oQjzdiE8Ksi5mtVLAR6eXmlUn3gS4BSO6WhelegI0U/Yx6Dfjxfyso2COr8vKfLrzj082OHyzBZL
FcH1rsU7hzbpIXpbeQ9XZ62ZA38spjibk8uGyKqMrE5N3Y0VDYjNZMHHx9KWXZ2gtWN+81UnULfO
WO2WXfDCUFa4W2NMwPSkup/WuYfeRYyG2lb8iKWHir+PRuLM3+0dle2s5FX6k2uPbDCy9e7zlMnH
DLeeS2crb6h7ATxr0yf+FWno2/H+1tAau5hfaETKoC1VR3geuE0KuNtO6DzIaGL/HB37++KYh5AL
332L1qCOMil8Xihru4PWZ67fvI3b96G1VWALYtLdOno/olJpIBY/gdZws4/RDJUi0CAUcAk+KTgd
t1oUJk+mprcZ7ecQXKOs5DWjiE4caZHQgpswgHszz+eHs0P4jcjt1YsfMUUOAEkKTg/dmfle5H1R
/PvWH5+a+QFep+6Dr1+a7pJyuNI+bkWNmZk+p0Kvoai0AbTHmRc79HFwvMLumB8zgf04ZNEXPNG9
Xmw4Rtfc2x8uL4yONhYgxWV+aN9yMZu6R4pfFLi2Tf+RoCj+zqugu2zCcc5lghBWN+Uu3OO8x6KT
caNc+Lh5IyhYdy+lIVwJahcJcLM/8GFvK/3nraIn423NNKrQrsQIDXw77AtXjhbgpYkcbg4kZmLq
qJF4xrapXmY=
`protect end_protected
|
-----------------------------------------------------------------------------
-- LEON Xilinx AC701 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0);
sdcard_spi_miso : in std_logic;
sdcard_spi_mosi : out std_logic;
sdcard_spi_cs_b : out std_logic;
sdcard_spi_clk : out std_logic
);
end;
architecture rtl of leon3mp is
component ahb2mig_7series
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
----- component STARTUPE2 -----
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal mig_ahbsi : ahb_slv_in_type;
signal mig_ahbso : ahb_slv_out_type;
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_7SERIES = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs, devid => XILINX_AC701)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => CFG_NCPU, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => CFG_NCPU-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#900#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 13, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc,
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(13), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(1), syso.proc_error);
sysi.dsu_enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (button(0), sysi.dsu_break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(0), ndsuact);
ndsuact <= not syso.dsu_active;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 0, hirq => 1, faddr => 16#100#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
-- To output SPI clock use Xilinx STARTUPE2 primitive
--sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE",
SIM_CCLK_FREQ => 10.0
)
port map (
CFGCLK => open ,
CFGMCLK => open ,
EOS => open ,
PREQ => open ,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '0',
PACK => '0',
USRCCLKO => spmo.sck,
USRCCLKTS => '0',
USRDONEO => '1',
USRDONETS => '1'
);
end generate;
nospimc: if CFG_SPIMCTRL = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, '1');
--sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, '0');
end generate;
-----------------------------------------------------------------------------
-- L2 cache, optionally covering DDR3 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 4, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(4),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(0) <= mig_ahbso;
mig_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(4) <= mig_ahbso;
mig_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series generic map (
hindex => 4*(1-CFG_L2_EN), haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => mig_ahbsi,
ahbso => mig_ahbso,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4*(1-CFG_L2_EN),
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => mig_ahbsi,
ahbso => mig_ahbso
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
calib_done <= '1';
clkm <= not clkm after 5.0 ns;
-- pragma translate_on
end generate gen_mig_model;
end generate;
no_mig_gen : if (CFG_MIG_7SERIES = 0) generate
ahbram0 : ahbram
generic map (hindex => 4*(1-CFG_L2_EN), haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, mig_ahbsi, mig_ahbso);
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate no_mig_gen;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 3, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 0, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
rgmiii.mdint <= '0'; -- No interrupt on Marvell 88E1116R PHY
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rstraw);
sfp_clock_mux_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 2)
port map (sfp_clock_mux, "00");
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 4, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- SPI Controller --------------------------------------------------
----------------------------------------------------------------------
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(12), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_miso, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_mosi, spio.mosi);
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_clk, spio.sck);
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (sdcard_spi_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_miso, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_mosi, '1');
sck_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_clk, '0');
slvsel_pad : outpad generic map (level => cmos, voltage => x25v,tech => padtech)
port map (sdcard_spi_cs_b, '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx AC701 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity agito is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
output_loc : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of agito is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"agito,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7vx485tffg1761-2,HLS_INPUT_CLOCK=2.390000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.390000,HLS_SYN_LAT=210,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1458,HLS_SYN_LUT=1472}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (53 downto 0) := "000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (53 downto 0) := "000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (53 downto 0) := "000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (53 downto 0) := "000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (53 downto 0) := "000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (53 downto 0) := "000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (53 downto 0) := "000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (53 downto 0) := "000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (53 downto 0) := "000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (53 downto 0) := "000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (53 downto 0) := "001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (53 downto 0) := "010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (53 downto 0) := "100000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
signal ap_CS_fsm : STD_LOGIC_VECTOR (53 downto 0) := "000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_70 : BOOLEAN;
signal halt_flag : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal pc_V : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal zero_flag : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal memory_V_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal memory_V_ce0 : STD_LOGIC;
signal memory_V_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal memory_V_address1 : STD_LOGIC_VECTOR (4 downto 0);
signal memory_V_ce1 : STD_LOGIC;
signal memory_V_we1 : STD_LOGIC;
signal memory_V_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal registers_V_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal registers_V_ce0 : STD_LOGIC;
signal registers_V_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal registers_V_address1 : STD_LOGIC_VECTOR (3 downto 0);
signal registers_V_ce1 : STD_LOGIC;
signal registers_V_we1 : STD_LOGIC;
signal registers_V_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_660_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal opcode_V_reg_1449 : STD_LOGIC_VECTOR (4 downto 0);
signal reg_698 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_138 : BOOLEAN;
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_152 : BOOLEAN;
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_160 : BOOLEAN;
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_168 : BOOLEAN;
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_184 : BOOLEAN;
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_215 : BOOLEAN;
signal grp_agito_bit_serial_add_fu_607_ap_done : STD_LOGIC;
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_243 : BOOLEAN;
signal ap_sig_cseq_ST_st36_fsm_35 : STD_LOGIC;
signal ap_sig_bdd_251 : BOOLEAN;
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_259 : BOOLEAN;
signal ap_sig_cseq_ST_st43_fsm_42 : STD_LOGIC;
signal ap_sig_bdd_274 : BOOLEAN;
signal ap_sig_cseq_ST_st45_fsm_44 : STD_LOGIC;
signal ap_sig_bdd_288 : BOOLEAN;
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_296 : BOOLEAN;
signal grp_fu_666_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_705 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_306 : BOOLEAN;
signal exitcond_i_i2_fu_943_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_317 : BOOLEAN;
signal exitcond_i_i1_fu_987_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_329 : BOOLEAN;
signal exitcond_i_i_fu_1050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal reg_709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_342 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_349 : BOOLEAN;
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_357 : BOOLEAN;
signal ap_sig_cseq_ST_st37_fsm_36 : STD_LOGIC;
signal ap_sig_bdd_376 : BOOLEAN;
signal grp_agito_bit_serial_and_fu_632_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal reg_715 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_386 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_393 : BOOLEAN;
signal grp_fu_671_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_720 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st52_fsm_51 : STD_LOGIC;
signal ap_sig_bdd_413 : BOOLEAN;
signal grp_agito_bit_serial_add_fu_607_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal reg_724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st33_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_423 : BOOLEAN;
signal ap_sig_cseq_ST_st39_fsm_38 : STD_LOGIC;
signal ap_sig_bdd_432 : BOOLEAN;
signal ap_sig_cseq_ST_st49_fsm_48 : STD_LOGIC;
signal ap_sig_bdd_444 : BOOLEAN;
signal grp_fu_688_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_729 : STD_LOGIC_VECTOR (31 downto 0);
signal t_V_reg_1407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_462 : BOOLEAN;
signal halt_flag_load_load_fu_769_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal inst_V_reg_1423 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_479 : BOOLEAN;
signal operands_V_fu_798_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal operands_V_reg_1453 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_i12_fu_924_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i12_reg_1554 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i11_fu_931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i11_reg_1559 : STD_LOGIC_VECTOR (63 downto 0);
signal r_V_71_cast_fu_935_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_71_cast_reg_1564 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_fu_949_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal p_Result_2_fu_973_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_fu_993_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal p_Result_1_fu_1024_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i10_fu_1042_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i10_reg_1600 : STD_LOGIC_VECTOR (63 downto 0);
signal i_fu_1056_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal p_Result_s_fu_1088_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_fu_1131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_reg_1623 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_593 : BOOLEAN;
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_614 : BOOLEAN;
signal tmp_150_reg_1673 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_148_reg_1678 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_144_reg_1683 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_142_reg_1688 : STD_LOGIC_VECTOR (0 downto 0);
signal storemerge_fu_1214_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal storemerge_reg_1693 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_635 : BOOLEAN;
signal storemerge5_fu_1227_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal storemerge5_reg_1698 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_79_tmp_s_fu_1239_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_79_tmp_s_reg_1703 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_78_tmp_s_fu_1247_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_78_tmp_s_reg_1708 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_r_V_s_fu_1259_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_r_V_s_reg_1713 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_r_V_s_fu_1266_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_r_V_s_reg_1718 : STD_LOGIC_VECTOR (31 downto 0);
signal val_assign_fu_1312_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal val_assign_reg_1723 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st31_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_660 : BOOLEAN;
signal r_V_22_cast_fu_1339_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_22_cast_reg_1733 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_671 : BOOLEAN;
signal r_V_18_cast_fu_1347_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_18_cast_reg_1738 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_13_cast_fu_1384_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_13_cast_reg_1748 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st48_fsm_47 : STD_LOGIC;
signal ap_sig_bdd_686 : BOOLEAN;
signal ap_sig_cseq_ST_st50_fsm_49 : STD_LOGIC;
signal ap_sig_bdd_695 : BOOLEAN;
signal grp_fu_651_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_13_reg_1758 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st51_fsm_50 : STD_LOGIC;
signal ap_sig_bdd_704 : BOOLEAN;
signal memory_V_load_1_reg_1763 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_reg_1768 : STD_LOGIC_VECTOR (31 downto 0);
signal memory_V_load_reg_1773 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_bit_serial_add_fu_607_ap_start : STD_LOGIC;
signal grp_agito_bit_serial_add_fu_607_ap_idle : STD_LOGIC;
signal grp_agito_bit_serial_add_fu_607_ap_ready : STD_LOGIC;
signal grp_agito_bit_serial_add_fu_607_arg1_V : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_bit_serial_add_fu_607_arg2_V : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_bit_serial_add_fu_607_sub_flag : STD_LOGIC_VECTOR (0 downto 0);
signal grp_agito_bit_serial_add_fu_607_zero_flag : STD_LOGIC_VECTOR (0 downto 0);
signal grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld : STD_LOGIC;
signal grp_agito_shift_fu_619_ap_start : STD_LOGIC;
signal grp_agito_shift_fu_619_ap_done : STD_LOGIC;
signal grp_agito_shift_fu_619_ap_idle : STD_LOGIC;
signal grp_agito_shift_fu_619_ap_ready : STD_LOGIC;
signal grp_agito_shift_fu_619_operands_V : STD_LOGIC_VECTOR (26 downto 0);
signal grp_agito_shift_fu_619_right_flag : STD_LOGIC;
signal grp_agito_shift_fu_619_arithmetic_flag : STD_LOGIC;
signal grp_agito_shift_fu_619_registers_V_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_agito_shift_fu_619_registers_V_ce0 : STD_LOGIC;
signal grp_agito_shift_fu_619_registers_V_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_shift_fu_619_registers_V_address1 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_agito_shift_fu_619_registers_V_ce1 : STD_LOGIC;
signal grp_agito_shift_fu_619_registers_V_we1 : STD_LOGIC;
signal grp_agito_shift_fu_619_registers_V_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_bit_serial_and_fu_632_arg1_V : STD_LOGIC_VECTOR (31 downto 0);
signal grp_agito_bit_serial_and_fu_632_arg2_V : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_11_reg_538 : STD_LOGIC_VECTOR (31 downto 0);
signal bvh_d_index_2_reg_550 : STD_LOGIC_VECTOR (5 downto 0);
signal p_Val2_9_reg_561 : STD_LOGIC_VECTOR (31 downto 0);
signal bvh_d_index_1_reg_573 : STD_LOGIC_VECTOR (5 downto 0);
signal p_Val2_6_reg_584 : STD_LOGIC_VECTOR (31 downto 0);
signal bvh_d_index_reg_596 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st32_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_767 : BOOLEAN;
signal ap_sig_cseq_ST_st38_fsm_37 : STD_LOGIC;
signal ap_sig_bdd_775 : BOOLEAN;
signal grp_agito_shift_fu_619_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st35_fsm_34 : STD_LOGIC;
signal ap_sig_bdd_853 : BOOLEAN;
signal r_V_56_cast_fu_1101_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_fu_779_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_784_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i9_44_fu_805_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i8_43_fu_810_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i7_42_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i6_41_fu_820_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i5_40_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i7_fu_839_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_30_fu_844_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_28_fu_849_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_fu_854_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_fu_859_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_17_fu_864_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_869_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i6_fu_877_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i3_38_fu_882_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i2_37_fu_887_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i3_fu_892_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_i_fu_900_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i1_fu_905_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_35_fu_913_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_i1_fu_1037_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i9_fu_1106_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_898 : BOOLEAN;
signal tmp_7_i_fu_1114_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i8_fu_1119_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_908 : BOOLEAN;
signal tmp_31_fu_1145_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_29_fu_1153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_25_fu_1161_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_22_fu_1169_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_1177_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_15_fu_1185_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_27_fu_1190_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_20_fu_1195_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_fu_1200_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i1_36_fu_1303_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_926 : BOOLEAN;
signal tmp_i4_39_fu_1318_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st34_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_936 : BOOLEAN;
signal tmp_39_i_fu_1326_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i5_fu_1331_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st40_fsm_39 : STD_LOGIC;
signal ap_sig_bdd_946 : BOOLEAN;
signal tmp_4_i_fu_1352_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i4_fu_1357_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st44_fsm_43 : STD_LOGIC;
signal ap_sig_bdd_956 : BOOLEAN;
signal tmp_3_i_fu_1362_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i2_fu_1376_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_969 : BOOLEAN;
signal tmp_2_i_fu_1389_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_fu_1394_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st53_fsm_52 : STD_LOGIC;
signal ap_sig_bdd_979 : BOOLEAN;
signal lhs_V_fu_830_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_994 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_1001 : BOOLEAN;
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_1009 : BOOLEAN;
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_1018 : BOOLEAN;
signal r_V_60_fu_802_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_fu_642_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_24_fu_874_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal r_V_12_fu_897_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_8_fu_910_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal r_V_64_fu_928_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal index_assign_2_cast5_fu_939_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_163_fu_955_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i2_fu_963_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Repl2_2_fu_969_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal index_assign_1_cast7_fu_983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_161_fu_1007_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_160_fu_999_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i1_fu_1014_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Repl2_1_fu_1020_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal r_V_55_fu_1034_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal index_assign_cast9_fu_1046_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_158_fu_1070_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_157_fu_1062_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i_fu_1078_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Repl2_s_fu_1084_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal r_V_52_fu_1098_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_49_fu_1111_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_45_fu_1124_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal r_V_49_cast_fu_1127_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_43_fu_1142_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_40_fu_1150_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_37_fu_1158_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_34_fu_1166_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_30_fu_1174_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_28_fu_1182_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sel_tmp3_fu_1209_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_70_cast_fu_1205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp_fu_1222_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_68_cast_fu_1235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_66_cast_fu_1255_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_23_fu_1323_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_20_fu_1336_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_17_fu_1344_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_14_fu_1367_p4 : STD_LOGIC_VECTOR (17 downto 0);
signal r_V_11_fu_1381_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st54_fsm_53 : STD_LOGIC;
signal ap_sig_bdd_1508 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (53 downto 0);
component agito_bit_serial_add IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
arg1_V : IN STD_LOGIC_VECTOR (31 downto 0);
arg2_V : IN STD_LOGIC_VECTOR (31 downto 0);
sub_flag : IN STD_LOGIC_VECTOR (0 downto 0);
zero_flag : OUT STD_LOGIC_VECTOR (0 downto 0);
zero_flag_ap_vld : OUT STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component agito_shift IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
operands_V : IN STD_LOGIC_VECTOR (26 downto 0);
right_flag : IN STD_LOGIC;
arithmetic_flag : IN STD_LOGIC;
registers_V_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce0 : OUT STD_LOGIC;
registers_V_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
registers_V_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce1 : OUT STD_LOGIC;
registers_V_we1 : OUT STD_LOGIC;
registers_V_d1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component agito_bit_serial_and IS
port (
arg1_V : IN STD_LOGIC_VECTOR (31 downto 0);
arg2_V : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component agito_memory_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (4 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (4 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component agito_registers_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (3 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
memory_V_U : component agito_memory_V
generic map (
DataWidth => 32,
AddressRange => 30,
AddressWidth => 5)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => memory_V_address0,
ce0 => memory_V_ce0,
q0 => memory_V_q0,
address1 => memory_V_address1,
ce1 => memory_V_ce1,
we1 => memory_V_we1,
d1 => memory_V_d1);
registers_V_U : component agito_registers_V
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => registers_V_address0,
ce0 => registers_V_ce0,
q0 => registers_V_q0,
address1 => registers_V_address1,
ce1 => registers_V_ce1,
we1 => registers_V_we1,
d1 => registers_V_d1);
grp_agito_bit_serial_add_fu_607 : component agito_bit_serial_add
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_agito_bit_serial_add_fu_607_ap_start,
ap_done => grp_agito_bit_serial_add_fu_607_ap_done,
ap_idle => grp_agito_bit_serial_add_fu_607_ap_idle,
ap_ready => grp_agito_bit_serial_add_fu_607_ap_ready,
arg1_V => grp_agito_bit_serial_add_fu_607_arg1_V,
arg2_V => grp_agito_bit_serial_add_fu_607_arg2_V,
sub_flag => grp_agito_bit_serial_add_fu_607_sub_flag,
zero_flag => grp_agito_bit_serial_add_fu_607_zero_flag,
zero_flag_ap_vld => grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld,
ap_return => grp_agito_bit_serial_add_fu_607_ap_return);
grp_agito_shift_fu_619 : component agito_shift
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_agito_shift_fu_619_ap_start,
ap_done => grp_agito_shift_fu_619_ap_done,
ap_idle => grp_agito_shift_fu_619_ap_idle,
ap_ready => grp_agito_shift_fu_619_ap_ready,
operands_V => grp_agito_shift_fu_619_operands_V,
right_flag => grp_agito_shift_fu_619_right_flag,
arithmetic_flag => grp_agito_shift_fu_619_arithmetic_flag,
registers_V_address0 => grp_agito_shift_fu_619_registers_V_address0,
registers_V_ce0 => grp_agito_shift_fu_619_registers_V_ce0,
registers_V_q0 => grp_agito_shift_fu_619_registers_V_q0,
registers_V_address1 => grp_agito_shift_fu_619_registers_V_address1,
registers_V_ce1 => grp_agito_shift_fu_619_registers_V_ce1,
registers_V_we1 => grp_agito_shift_fu_619_registers_V_we1,
registers_V_d1 => grp_agito_shift_fu_619_registers_V_d1);
grp_agito_bit_serial_and_fu_632 : component agito_bit_serial_and
port map (
arg1_V => grp_agito_bit_serial_and_fu_632_arg1_V,
arg2_V => grp_agito_bit_serial_and_fu_632_arg2_V,
ap_return => grp_agito_bit_serial_and_fu_632_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg assign process. --
grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) or (ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) or (ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37))) then
grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_ap_ready)) then
grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_agito_shift_fu_619_ap_start_ap_start_reg assign process. --
grp_agito_shift_fu_619_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_agito_shift_fu_619_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_A)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_9)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_8)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_7)))) then
grp_agito_shift_fu_619_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_agito_shift_fu_619_ap_ready)) then
grp_agito_shift_fu_619_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- bvh_d_index_1_reg_573 assign process. --
bvh_d_index_1_reg_573_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = exitcond_i_i1_fu_987_p2))) then
bvh_d_index_1_reg_573 <= i_2_fu_993_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_17))) then
bvh_d_index_1_reg_573 <= ap_const_lv6_0;
end if;
end if;
end process;
-- bvh_d_index_2_reg_550 assign process. --
bvh_d_index_2_reg_550_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = exitcond_i_i2_fu_943_p2))) then
bvh_d_index_2_reg_550 <= i_3_fu_949_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_18))) then
bvh_d_index_2_reg_550 <= ap_const_lv6_0;
end if;
end if;
end process;
-- bvh_d_index_reg_596 assign process. --
bvh_d_index_reg_596_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = exitcond_i_i_fu_1050_p2))) then
bvh_d_index_reg_596 <= i_fu_1056_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
bvh_d_index_reg_596 <= ap_const_lv6_0;
end if;
end if;
end process;
-- halt_flag assign process. --
halt_flag_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_0))) then
halt_flag <= ap_const_lv1_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
halt_flag <= ap_const_lv1_0;
end if;
end if;
end process;
-- p_Val2_11_reg_538 assign process. --
p_Val2_11_reg_538_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = exitcond_i_i2_fu_943_p2))) then
p_Val2_11_reg_538 <= p_Result_2_fu_973_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_18))) then
p_Val2_11_reg_538 <= ap_const_lv32_0;
end if;
end if;
end process;
-- p_Val2_6_reg_584 assign process. --
p_Val2_6_reg_584_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = exitcond_i_i_fu_1050_p2))) then
p_Val2_6_reg_584 <= p_Result_s_fu_1088_p4;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_Val2_6_reg_584 <= ap_const_lv32_0;
end if;
end if;
end process;
-- p_Val2_9_reg_561 assign process. --
p_Val2_9_reg_561_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = exitcond_i_i1_fu_987_p2))) then
p_Val2_9_reg_561 <= p_Result_1_fu_1024_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_17))) then
p_Val2_9_reg_561 <= ap_const_lv32_0;
end if;
end if;
end process;
-- pc_V assign process. --
pc_V_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34) and not((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34) and not((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34) and not((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34) and not((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done))))))) then
pc_V <= reg_694;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)))) then
pc_V <= reg_729;
elsif (((opcode_V_reg_1449 = ap_const_lv5_2) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= tmp_2_reg_1768;
elsif (((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= tmp_45_r_V_s_reg_1718;
elsif (((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= tmp_46_r_V_s_reg_1713;
elsif (((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= r_V_78_tmp_s_reg_1708;
elsif (((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= r_V_79_tmp_s_reg_1703;
elsif (((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= storemerge5_reg_1698;
elsif (((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
pc_V <= storemerge_reg_1693;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
pc_V <= tmp_1_i_reg_1623;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45) or (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52))) then
pc_V <= reg_720;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12))) then
pc_V <= reg_705;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_13))) then
pc_V <= lhs_V_fu_830_p1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
pc_V <= ap_const_lv32_0;
end if;
end if;
end process;
-- zero_flag assign process. --
zero_flag_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = halt_flag_load_load_fu_769_p1))) then
zero_flag <= ap_const_lv1_0;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48) and (ap_const_logic_1 = grp_agito_bit_serial_add_fu_607_zero_flag_ap_vld)))) then
zero_flag <= grp_agito_bit_serial_add_fu_607_zero_flag;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
inst_V_reg_1423 <= memory_V_q0;
opcode_V_reg_1449 <= memory_V_q0(31 downto 27);
operands_V_reg_1453 <= operands_V_fu_798_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st51_fsm_50)) then
memory_V_load_1_reg_1763 <= memory_V_q0;
r_V_13_reg_1758 <= inst_V_reg_1423(26 downto 18);
tmp_2_reg_1768 <= grp_fu_688_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51)) then
memory_V_load_reg_1773 <= memory_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47)) then
r_V_13_cast_reg_1748(8 downto 0) <= r_V_13_cast_fu_1384_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41))) then
r_V_18_cast_reg_1738(8 downto 0) <= r_V_18_cast_fu_1347_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41))) then
r_V_22_cast_reg_1733(8 downto 0) <= r_V_22_cast_fu_1339_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_17))) then
r_V_71_cast_reg_1564(8 downto 0) <= r_V_71_cast_fu_935_p1(8 downto 0);
tmp_i11_reg_1559(8 downto 0) <= tmp_i11_fu_931_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
r_V_78_tmp_s_reg_1708 <= r_V_78_tmp_s_fu_1247_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
r_V_79_tmp_s_reg_1703 <= r_V_79_tmp_s_fu_1239_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_A)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_9)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_8)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_7)))) then
reg_694 <= grp_fu_660_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_18)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_17)) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_11)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_10)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_F)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_E)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_D)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_C)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35) or ((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) and (opcode_V_reg_1449 = ap_const_lv5_4)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4))))) or (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44) or (ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46))) then
reg_698 <= registers_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = exitcond_i_i2_fu_943_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = exitcond_i_i1_fu_987_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = exitcond_i_i_fu_1050_p2))))) then
reg_705 <= grp_fu_666_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or (ap_const_logic_1 = ap_sig_cseq_ST_st37_fsm_36))) then
reg_709 <= registers_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
reg_715 <= grp_agito_bit_serial_and_fu_632_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))))) or (ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51))) then
reg_720 <= grp_fu_671_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4))))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32) and not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))) or (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4))))) or (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48)))) then
reg_724 <= grp_agito_bit_serial_add_fu_607_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4))))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32) and not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))) or (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42) and not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4))))))) then
reg_729 <= grp_fu_688_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
storemerge5_reg_1698 <= storemerge5_fu_1227_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
storemerge_reg_1693 <= storemerge_fu_1214_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = halt_flag_load_load_fu_769_p1))) then
t_V_reg_1407 <= pc_V;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)))))) then
tmp_142_reg_1688 <= grp_agito_bit_serial_add_fu_607_ap_return(31 downto 31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)))))) then
tmp_144_reg_1683 <= grp_agito_bit_serial_add_fu_607_ap_return(31 downto 31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)))))) then
tmp_148_reg_1678 <= grp_agito_bit_serial_add_fu_607_ap_return(31 downto 31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) and not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)))))) then
tmp_150_reg_1673 <= grp_agito_bit_serial_add_fu_607_ap_return(31 downto 31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then
tmp_1_i_reg_1623 <= tmp_1_i_fu_1131_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
tmp_45_r_V_s_reg_1718 <= tmp_45_r_V_s_fu_1266_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
tmp_46_r_V_s_reg_1713 <= tmp_46_r_V_s_fu_1259_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
tmp_i10_reg_1600(8 downto 0) <= tmp_i10_fu_1042_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (opcode_V_reg_1449 = ap_const_lv5_18))) then
tmp_i12_reg_1554(8 downto 0) <= tmp_i12_fu_924_p1(8 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) then
val_assign_reg_1723 <= val_assign_fu_1312_p2;
end if;
end if;
end process;
tmp_i12_reg_1554(63 downto 9) <= "0000000000000000000000000000000000000000000000000000000";
tmp_i11_reg_1559(63 downto 9) <= "0000000000000000000000000000000000000000000000000000000";
r_V_71_cast_reg_1564(31 downto 9) <= "00000000000000000000000";
tmp_i10_reg_1600(63 downto 9) <= "0000000000000000000000000000000000000000000000000000000";
r_V_22_cast_reg_1733(31 downto 9) <= "00000000000000000000000";
r_V_18_cast_reg_1738(31 downto 9) <= "00000000000000000000000";
r_V_13_cast_reg_1748(31 downto 9) <= "00000000000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, opcode_V_reg_1449, grp_agito_bit_serial_add_fu_607_ap_done, exitcond_i_i2_fu_943_p2, exitcond_i_i1_fu_987_p2, exitcond_i_i_fu_1050_p2, halt_flag_load_load_fu_769_p1, grp_agito_shift_fu_619_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = halt_flag_load_load_fu_769_p1))) then
ap_NS_fsm <= ap_ST_st54_fsm_53;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if ((opcode_V_reg_1449 = ap_const_lv5_1)) then
ap_NS_fsm <= ap_ST_st52_fsm_51;
elsif ((opcode_V_reg_1449 = ap_const_lv5_2)) then
ap_NS_fsm <= ap_ST_st47_fsm_46;
elsif ((opcode_V_reg_1449 = ap_const_lv5_3)) then
ap_NS_fsm <= ap_ST_st45_fsm_44;
elsif (((opcode_V_reg_1449 = ap_const_lv5_5) or (opcode_V_reg_1449 = ap_const_lv5_4))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
elsif ((opcode_V_reg_1449 = ap_const_lv5_6)) then
ap_NS_fsm <= ap_ST_st36_fsm_35;
elsif (((opcode_V_reg_1449 = ap_const_lv5_A) or (opcode_V_reg_1449 = ap_const_lv5_9) or (opcode_V_reg_1449 = ap_const_lv5_8) or (opcode_V_reg_1449 = ap_const_lv5_7))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
elsif ((opcode_V_reg_1449 = ap_const_lv5_B)) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
elsif (((opcode_V_reg_1449 = ap_const_lv5_0) or (opcode_V_reg_1449 = ap_const_lv5_13) or (not((opcode_V_reg_1449 = ap_const_lv5_18)) and not((opcode_V_reg_1449 = ap_const_lv5_17)) and not((opcode_V_reg_1449 = ap_const_lv5_16)) and not((opcode_V_reg_1449 = ap_const_lv5_15)) and not((opcode_V_reg_1449 = ap_const_lv5_14)) and not((opcode_V_reg_1449 = ap_const_lv5_12)) and not((opcode_V_reg_1449 = ap_const_lv5_11)) and not((opcode_V_reg_1449 = ap_const_lv5_10)) and not((opcode_V_reg_1449 = ap_const_lv5_F)) and not((opcode_V_reg_1449 = ap_const_lv5_E)) and not((opcode_V_reg_1449 = ap_const_lv5_D)) and not((opcode_V_reg_1449 = ap_const_lv5_C)) and not((opcode_V_reg_1449 = ap_const_lv5_B)) and not((opcode_V_reg_1449 = ap_const_lv5_A)) and not((opcode_V_reg_1449 = ap_const_lv5_9)) and not((opcode_V_reg_1449 = ap_const_lv5_8)) and not((opcode_V_reg_1449 = ap_const_lv5_7)) and not((opcode_V_reg_1449 = ap_const_lv5_6)) and not((opcode_V_reg_1449 = ap_const_lv5_5)) and not((opcode_V_reg_1449 = ap_const_lv5_4)) and not((opcode_V_reg_1449 = ap_const_lv5_3)) and not((opcode_V_reg_1449 = ap_const_lv5_2)) and not((opcode_V_reg_1449 = ap_const_lv5_1))))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
elsif (((opcode_V_reg_1449 = ap_const_lv5_11) or (opcode_V_reg_1449 = ap_const_lv5_10) or (opcode_V_reg_1449 = ap_const_lv5_F) or (opcode_V_reg_1449 = ap_const_lv5_E) or (opcode_V_reg_1449 = ap_const_lv5_D) or (opcode_V_reg_1449 = ap_const_lv5_C))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
elsif ((opcode_V_reg_1449 = ap_const_lv5_12)) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
elsif ((opcode_V_reg_1449 = ap_const_lv5_14)) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
elsif ((opcode_V_reg_1449 = ap_const_lv5_15)) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
elsif ((opcode_V_reg_1449 = ap_const_lv5_16)) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if ((opcode_V_reg_1449 = ap_const_lv5_17)) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = exitcond_i_i2_fu_943_p2)) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st8_fsm_7 =>
if ((ap_const_lv1_0 = exitcond_i_i1_fu_987_p2)) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
if ((ap_const_lv1_0 = exitcond_i_i_fu_1050_p2)) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
if ((not((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done)))) and ((opcode_V_reg_1449 = ap_const_lv5_11) or (opcode_V_reg_1449 = ap_const_lv5_10) or (opcode_V_reg_1449 = ap_const_lv5_F) or (opcode_V_reg_1449 = ap_const_lv5_E) or (opcode_V_reg_1449 = ap_const_lv5_D) or (opcode_V_reg_1449 = ap_const_lv5_C)))) then
ap_NS_fsm <= ap_ST_st28_fsm_27;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
if (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
else
ap_NS_fsm <= ap_ST_st33_fsm_32;
end if;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st35_fsm_34 =>
if ((not((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_0 = grp_agito_shift_fu_619_ap_done)))) and ((opcode_V_reg_1449 = ap_const_lv5_A) or (opcode_V_reg_1449 = ap_const_lv5_9) or (opcode_V_reg_1449 = ap_const_lv5_8) or (opcode_V_reg_1449 = ap_const_lv5_7)))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
else
ap_NS_fsm <= ap_ST_st35_fsm_34;
end if;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
if (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
if ((not((((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done) and (opcode_V_reg_1449 = ap_const_lv5_4)))) and ((opcode_V_reg_1449 = ap_const_lv5_5) or (opcode_V_reg_1449 = ap_const_lv5_4)))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st43_fsm_42;
end if;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
if (not((ap_const_logic_0 = grp_agito_bit_serial_add_fu_607_ap_done))) then
ap_NS_fsm <= ap_ST_st50_fsm_49;
else
ap_NS_fsm <= ap_ST_st49_fsm_48;
end if;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st54_fsm_53)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st54_fsm_53)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= registers_V_q0;
-- ap_sig_bdd_1001 assign process. --
ap_sig_bdd_1001_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1001 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_1009 assign process. --
ap_sig_bdd_1009_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1009 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_1018 assign process. --
ap_sig_bdd_1018_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1018 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_138 assign process. --
ap_sig_bdd_138_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_138 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_1508 assign process. --
ap_sig_bdd_1508_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1508 <= (ap_const_lv1_1 = ap_CS_fsm(53 downto 53));
end process;
-- ap_sig_bdd_152 assign process. --
ap_sig_bdd_152_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_152 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_160 assign process. --
ap_sig_bdd_160_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_160 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_168 assign process. --
ap_sig_bdd_168_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_168 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_184 assign process. --
ap_sig_bdd_184_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_184 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_215 assign process. --
ap_sig_bdd_215_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_215 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_243 assign process. --
ap_sig_bdd_243_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_243 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_251 assign process. --
ap_sig_bdd_251_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_251 <= (ap_const_lv1_1 = ap_CS_fsm(35 downto 35));
end process;
-- ap_sig_bdd_259 assign process. --
ap_sig_bdd_259_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_259 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_274 assign process. --
ap_sig_bdd_274_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_274 <= (ap_const_lv1_1 = ap_CS_fsm(42 downto 42));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_288 <= (ap_const_lv1_1 = ap_CS_fsm(44 downto 44));
end process;
-- ap_sig_bdd_296 assign process. --
ap_sig_bdd_296_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_296 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_306 assign process. --
ap_sig_bdd_306_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_306 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_317 assign process. --
ap_sig_bdd_317_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_317 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_329 assign process. --
ap_sig_bdd_329_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_329 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_342 assign process. --
ap_sig_bdd_342_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_342 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_349 assign process. --
ap_sig_bdd_349_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_349 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_357 assign process. --
ap_sig_bdd_357_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_357 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_376 assign process. --
ap_sig_bdd_376_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_376 <= (ap_const_lv1_1 = ap_CS_fsm(36 downto 36));
end process;
-- ap_sig_bdd_386 assign process. --
ap_sig_bdd_386_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_386 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_393 assign process. --
ap_sig_bdd_393_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_393 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_413 assign process. --
ap_sig_bdd_413_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_413 <= (ap_const_lv1_1 = ap_CS_fsm(51 downto 51));
end process;
-- ap_sig_bdd_423 assign process. --
ap_sig_bdd_423_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_423 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_432 assign process. --
ap_sig_bdd_432_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_432 <= (ap_const_lv1_1 = ap_CS_fsm(38 downto 38));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_444 <= (ap_const_lv1_1 = ap_CS_fsm(48 downto 48));
end process;
-- ap_sig_bdd_462 assign process. --
ap_sig_bdd_462_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_462 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_479 assign process. --
ap_sig_bdd_479_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_479 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_593 assign process. --
ap_sig_bdd_593_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_593 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_614 assign process. --
ap_sig_bdd_614_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_614 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_635 assign process. --
ap_sig_bdd_635_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_635 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_660 assign process. --
ap_sig_bdd_660_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_660 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_671 assign process. --
ap_sig_bdd_671_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_671 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_686 assign process. --
ap_sig_bdd_686_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_686 <= (ap_const_lv1_1 = ap_CS_fsm(47 downto 47));
end process;
-- ap_sig_bdd_695 assign process. --
ap_sig_bdd_695_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_695 <= (ap_const_lv1_1 = ap_CS_fsm(49 downto 49));
end process;
-- ap_sig_bdd_70 assign process. --
ap_sig_bdd_70_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_70 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_704 assign process. --
ap_sig_bdd_704_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_704 <= (ap_const_lv1_1 = ap_CS_fsm(50 downto 50));
end process;
-- ap_sig_bdd_767 assign process. --
ap_sig_bdd_767_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_767 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_775 assign process. --
ap_sig_bdd_775_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_775 <= (ap_const_lv1_1 = ap_CS_fsm(37 downto 37));
end process;
-- ap_sig_bdd_853 assign process. --
ap_sig_bdd_853_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_853 <= (ap_const_lv1_1 = ap_CS_fsm(34 downto 34));
end process;
-- ap_sig_bdd_898 assign process. --
ap_sig_bdd_898_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_898 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_908 assign process. --
ap_sig_bdd_908_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_908 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_926 assign process. --
ap_sig_bdd_926_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_926 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_936 assign process. --
ap_sig_bdd_936_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_936 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_946 assign process. --
ap_sig_bdd_946_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_946 <= (ap_const_lv1_1 = ap_CS_fsm(39 downto 39));
end process;
-- ap_sig_bdd_956 assign process. --
ap_sig_bdd_956_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_956 <= (ap_const_lv1_1 = ap_CS_fsm(43 downto 43));
end process;
-- ap_sig_bdd_969 assign process. --
ap_sig_bdd_969_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_969 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_979 assign process. --
ap_sig_bdd_979_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_979 <= (ap_const_lv1_1 = ap_CS_fsm(52 downto 52));
end process;
-- ap_sig_bdd_994 assign process. --
ap_sig_bdd_994_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_994 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_152)
begin
if (ap_sig_bdd_152) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_342)
begin
if (ap_sig_bdd_342) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_329)
begin
if (ap_sig_bdd_329) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_1009)
begin
if (ap_sig_bdd_1009) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_160)
begin
if (ap_sig_bdd_160) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_386)
begin
if (ap_sig_bdd_386) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_898)
begin
if (ap_sig_bdd_898) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_168)
begin
if (ap_sig_bdd_168) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_349)
begin
if (ap_sig_bdd_349) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_393)
begin
if (ap_sig_bdd_393) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_70)
begin
if (ap_sig_bdd_70) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_908)
begin
if (ap_sig_bdd_908) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_593)
begin
if (ap_sig_bdd_593) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_1018)
begin
if (ap_sig_bdd_1018) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_184)
begin
if (ap_sig_bdd_184) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_357)
begin
if (ap_sig_bdd_357) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_614)
begin
if (ap_sig_bdd_614) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_215)
begin
if (ap_sig_bdd_215) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_926)
begin
if (ap_sig_bdd_926) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_462)
begin
if (ap_sig_bdd_462) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_243)
begin
if (ap_sig_bdd_243) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st31_fsm_30 assign process. --
ap_sig_cseq_ST_st31_fsm_30_assign_proc : process(ap_sig_bdd_660)
begin
if (ap_sig_bdd_660) then
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st32_fsm_31 assign process. --
ap_sig_cseq_ST_st32_fsm_31_assign_proc : process(ap_sig_bdd_767)
begin
if (ap_sig_bdd_767) then
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st33_fsm_32 assign process. --
ap_sig_cseq_ST_st33_fsm_32_assign_proc : process(ap_sig_bdd_423)
begin
if (ap_sig_bdd_423) then
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st34_fsm_33 assign process. --
ap_sig_cseq_ST_st34_fsm_33_assign_proc : process(ap_sig_bdd_936)
begin
if (ap_sig_bdd_936) then
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st35_fsm_34 assign process. --
ap_sig_cseq_ST_st35_fsm_34_assign_proc : process(ap_sig_bdd_853)
begin
if (ap_sig_bdd_853) then
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st36_fsm_35 assign process. --
ap_sig_cseq_ST_st36_fsm_35_assign_proc : process(ap_sig_bdd_251)
begin
if (ap_sig_bdd_251) then
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st37_fsm_36 assign process. --
ap_sig_cseq_ST_st37_fsm_36_assign_proc : process(ap_sig_bdd_376)
begin
if (ap_sig_bdd_376) then
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st38_fsm_37 assign process. --
ap_sig_cseq_ST_st38_fsm_37_assign_proc : process(ap_sig_bdd_775)
begin
if (ap_sig_bdd_775) then
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_38 assign process. --
ap_sig_cseq_ST_st39_fsm_38_assign_proc : process(ap_sig_bdd_432)
begin
if (ap_sig_bdd_432) then
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_479)
begin
if (ap_sig_bdd_479) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st40_fsm_39 assign process. --
ap_sig_cseq_ST_st40_fsm_39_assign_proc : process(ap_sig_bdd_946)
begin
if (ap_sig_bdd_946) then
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_259)
begin
if (ap_sig_bdd_259) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_671)
begin
if (ap_sig_bdd_671) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st43_fsm_42 assign process. --
ap_sig_cseq_ST_st43_fsm_42_assign_proc : process(ap_sig_bdd_274)
begin
if (ap_sig_bdd_274) then
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st44_fsm_43 assign process. --
ap_sig_cseq_ST_st44_fsm_43_assign_proc : process(ap_sig_bdd_956)
begin
if (ap_sig_bdd_956) then
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st45_fsm_44 assign process. --
ap_sig_cseq_ST_st45_fsm_44_assign_proc : process(ap_sig_bdd_288)
begin
if (ap_sig_bdd_288) then
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_969)
begin
if (ap_sig_bdd_969) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_296)
begin
if (ap_sig_bdd_296) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st48_fsm_47 assign process. --
ap_sig_cseq_ST_st48_fsm_47_assign_proc : process(ap_sig_bdd_686)
begin
if (ap_sig_bdd_686) then
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st49_fsm_48 assign process. --
ap_sig_cseq_ST_st49_fsm_48_assign_proc : process(ap_sig_bdd_444)
begin
if (ap_sig_bdd_444) then
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st50_fsm_49 assign process. --
ap_sig_cseq_ST_st50_fsm_49_assign_proc : process(ap_sig_bdd_695)
begin
if (ap_sig_bdd_695) then
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st51_fsm_50 assign process. --
ap_sig_cseq_ST_st51_fsm_50_assign_proc : process(ap_sig_bdd_704)
begin
if (ap_sig_bdd_704) then
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st52_fsm_51 assign process. --
ap_sig_cseq_ST_st52_fsm_51_assign_proc : process(ap_sig_bdd_413)
begin
if (ap_sig_bdd_413) then
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st53_fsm_52 assign process. --
ap_sig_cseq_ST_st53_fsm_52_assign_proc : process(ap_sig_bdd_979)
begin
if (ap_sig_bdd_979) then
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st54_fsm_53 assign process. --
ap_sig_cseq_ST_st54_fsm_53_assign_proc : process(ap_sig_bdd_1508)
begin
if (ap_sig_bdd_1508) then
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_138)
begin
if (ap_sig_bdd_138) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_306)
begin
if (ap_sig_bdd_306) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_994)
begin
if (ap_sig_bdd_994) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_317)
begin
if (ap_sig_bdd_317) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_1001)
begin
if (ap_sig_bdd_1001) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
exitcond_i_i1_fu_987_p2 <= "1" when (bvh_d_index_1_reg_573 = ap_const_lv6_20) else "0";
exitcond_i_i2_fu_943_p2 <= "1" when (bvh_d_index_2_reg_550 = ap_const_lv6_20) else "0";
exitcond_i_i_fu_1050_p2 <= "1" when (bvh_d_index_reg_596 = ap_const_lv6_20) else "0";
grp_agito_bit_serial_add_fu_607_ap_start <= grp_agito_bit_serial_add_fu_607_ap_start_ap_start_reg;
-- grp_agito_bit_serial_add_fu_607_arg1_V assign process. --
grp_agito_bit_serial_add_fu_607_arg1_V_assign_proc : process(opcode_V_reg_1449, reg_698, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st43_fsm_42, ap_sig_cseq_ST_st33_fsm_32, ap_sig_cseq_ST_st39_fsm_38, ap_sig_cseq_ST_st49_fsm_48, val_assign_reg_1723)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) then
grp_agito_bit_serial_add_fu_607_arg1_V <= val_assign_reg_1723;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) or (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)))) then
grp_agito_bit_serial_add_fu_607_arg1_V <= reg_698;
else
grp_agito_bit_serial_add_fu_607_arg1_V <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_agito_bit_serial_add_fu_607_arg2_V assign process. --
grp_agito_bit_serial_add_fu_607_arg2_V_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st43_fsm_42, reg_709, ap_sig_cseq_ST_st33_fsm_32, ap_sig_cseq_ST_st39_fsm_38, ap_sig_cseq_ST_st49_fsm_48, r_V_22_cast_reg_1733, r_V_18_cast_reg_1738, r_V_13_cast_reg_1748)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48)) then
grp_agito_bit_serial_add_fu_607_arg2_V <= r_V_13_cast_reg_1748;
elsif (((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42))) then
grp_agito_bit_serial_add_fu_607_arg2_V <= r_V_18_cast_reg_1738;
elsif (((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42))) then
grp_agito_bit_serial_add_fu_607_arg2_V <= r_V_22_cast_reg_1733;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) then
grp_agito_bit_serial_add_fu_607_arg2_V <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) or ((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)))) then
grp_agito_bit_serial_add_fu_607_arg2_V <= reg_709;
else
grp_agito_bit_serial_add_fu_607_arg2_V <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_agito_bit_serial_add_fu_607_sub_flag assign process. --
grp_agito_bit_serial_add_fu_607_sub_flag_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st43_fsm_42, ap_sig_cseq_ST_st33_fsm_32, ap_sig_cseq_ST_st39_fsm_38, ap_sig_cseq_ST_st49_fsm_48)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32) or (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) or (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)) or ((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)))) then
grp_agito_bit_serial_add_fu_607_sub_flag <= ap_const_lv1_0;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_11) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_F) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_D) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)))) then
grp_agito_bit_serial_add_fu_607_sub_flag <= ap_const_lv1_1;
else
grp_agito_bit_serial_add_fu_607_sub_flag <= "X";
end if;
end process;
grp_agito_bit_serial_and_fu_632_arg1_V <= reg_698;
-- grp_agito_bit_serial_and_fu_632_arg2_V assign process. --
grp_agito_bit_serial_and_fu_632_arg2_V_assign_proc : process(reg_709, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, r_V_56_cast_fu_1101_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then
grp_agito_bit_serial_and_fu_632_arg2_V <= reg_709;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
grp_agito_bit_serial_and_fu_632_arg2_V <= r_V_56_cast_fu_1101_p1;
else
grp_agito_bit_serial_and_fu_632_arg2_V <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_agito_shift_fu_619_ap_start <= grp_agito_shift_fu_619_ap_start_ap_start_reg;
-- grp_agito_shift_fu_619_arithmetic_flag assign process. --
grp_agito_shift_fu_619_arithmetic_flag_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st35_fsm_34)
begin
if ((((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
grp_agito_shift_fu_619_arithmetic_flag <= ap_const_logic_1;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
grp_agito_shift_fu_619_arithmetic_flag <= ap_const_logic_0;
else
grp_agito_shift_fu_619_arithmetic_flag <= 'X';
end if;
end process;
grp_agito_shift_fu_619_operands_V <= operands_V_reg_1453;
grp_agito_shift_fu_619_registers_V_q0 <= registers_V_q0;
-- grp_agito_shift_fu_619_right_flag assign process. --
grp_agito_shift_fu_619_right_flag_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st35_fsm_34)
begin
if ((((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
grp_agito_shift_fu_619_right_flag <= ap_const_logic_1;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
grp_agito_shift_fu_619_right_flag <= ap_const_logic_0;
else
grp_agito_shift_fu_619_right_flag <= 'X';
end if;
end process;
grp_fu_642_p4 <= inst_V_reg_1423(17 downto 9);
grp_fu_651_p4 <= inst_V_reg_1423(26 downto 18);
grp_fu_660_p2 <= std_logic_vector(unsigned(pc_V) + unsigned(ap_const_lv32_1));
grp_fu_666_p2 <= std_logic_vector(unsigned(t_V_reg_1407) + unsigned(ap_const_lv32_1));
grp_fu_671_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(t_V_reg_1407));
grp_fu_688_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pc_V));
halt_flag_load_load_fu_769_p1 <= halt_flag;
i_2_fu_993_p2 <= std_logic_vector(unsigned(bvh_d_index_1_reg_573) + unsigned(ap_const_lv6_1));
i_3_fu_949_p2 <= std_logic_vector(unsigned(bvh_d_index_2_reg_550) + unsigned(ap_const_lv6_1));
i_fu_1056_p2 <= std_logic_vector(unsigned(bvh_d_index_reg_596) + unsigned(ap_const_lv6_1));
index_assign_1_cast7_fu_983_p1 <= std_logic_vector(resize(unsigned(bvh_d_index_1_reg_573),32));
index_assign_2_cast5_fu_939_p1 <= std_logic_vector(resize(unsigned(bvh_d_index_2_reg_550),32));
index_assign_cast9_fu_1046_p1 <= std_logic_vector(resize(unsigned(bvh_d_index_reg_596),32));
lhs_V_fu_830_p1 <= std_logic_vector(resize(unsigned(operands_V_reg_1453),32));
-- memory_V_address0 assign process. --
memory_V_address0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st50_fsm_49, tmp_s_fu_779_p1, tmp_i_35_fu_913_p1, tmp_2_i_fu_1389_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49)) then
memory_V_address0 <= tmp_2_i_fu_1389_p1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
memory_V_address0 <= tmp_i_35_fu_913_p1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
memory_V_address0 <= tmp_s_fu_779_p1(5 - 1 downto 0);
else
memory_V_address0 <= "XXXXX";
end if;
end process;
-- memory_V_address1 assign process. --
memory_V_address1_assign_proc : process(ap_sig_cseq_ST_st44_fsm_43, tmp_3_i_fu_1362_p1, tmp_i2_fu_1376_p1, ap_sig_cseq_ST_st46_fsm_45)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) then
memory_V_address1 <= tmp_i2_fu_1376_p1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) then
memory_V_address1 <= tmp_3_i_fu_1362_p1(5 - 1 downto 0);
else
memory_V_address1 <= "XXXXX";
end if;
end process;
-- memory_V_ce0 assign process. --
memory_V_ce0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st50_fsm_49)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49))) then
memory_V_ce0 <= ap_const_logic_1;
else
memory_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- memory_V_ce1 assign process. --
memory_V_ce1_assign_proc : process(ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st46_fsm_45)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43) or (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45))) then
memory_V_ce1 <= ap_const_logic_1;
else
memory_V_ce1 <= ap_const_logic_0;
end if;
end process;
memory_V_d1 <= reg_698;
-- memory_V_we1 assign process. --
memory_V_we1_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st46_fsm_45)
begin
if ((((opcode_V_reg_1449 = ap_const_lv5_4) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) or (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45))) then
memory_V_we1 <= ap_const_logic_1;
else
memory_V_we1 <= ap_const_logic_0;
end if;
end process;
operands_V_fu_798_p1 <= memory_V_q0(27 - 1 downto 0);
p_Repl2_1_fu_1020_p1 <= std_logic_vector(resize(unsigned(tmp_i_i1_fu_1014_p2),64));
p_Repl2_2_fu_969_p1 <= std_logic_vector(resize(unsigned(tmp_i_i2_fu_963_p2),64));
p_Repl2_s_fu_1084_p1 <= std_logic_vector(resize(unsigned(tmp_i_i_fu_1078_p2),64));
p_Result_1_fu_1024_p4_proc : process(p_Val2_9_reg_561, index_assign_1_cast7_fu_983_p1, p_Repl2_1_fu_1020_p1)
variable result: std_logic_vector(0 downto 0);
begin
p_Result_1_fu_1024_p4 <= p_Val2_9_reg_561;
if to_integer(unsigned(index_assign_1_cast7_fu_983_p1)) >= p_Val2_9_reg_561'low and to_integer(unsigned(index_assign_1_cast7_fu_983_p1)) <= p_Val2_9_reg_561'high then
result(0) := '0';
for i in p_Repl2_1_fu_1020_p1'range loop
result(0) := result(0) or p_Repl2_1_fu_1020_p1(i);
end loop;
p_Result_1_fu_1024_p4(to_integer(unsigned(index_assign_1_cast7_fu_983_p1))) <= result(0);
end if;
end process;
p_Result_2_fu_973_p4_proc : process(p_Val2_11_reg_538, index_assign_2_cast5_fu_939_p1, p_Repl2_2_fu_969_p1)
variable result: std_logic_vector(0 downto 0);
begin
p_Result_2_fu_973_p4 <= p_Val2_11_reg_538;
if to_integer(unsigned(index_assign_2_cast5_fu_939_p1)) >= p_Val2_11_reg_538'low and to_integer(unsigned(index_assign_2_cast5_fu_939_p1)) <= p_Val2_11_reg_538'high then
result(0) := '0';
for i in p_Repl2_2_fu_969_p1'range loop
result(0) := result(0) or p_Repl2_2_fu_969_p1(i);
end loop;
p_Result_2_fu_973_p4(to_integer(unsigned(index_assign_2_cast5_fu_939_p1))) <= result(0);
end if;
end process;
p_Result_s_fu_1088_p4_proc : process(p_Val2_6_reg_584, index_assign_cast9_fu_1046_p1, p_Repl2_s_fu_1084_p1)
variable result: std_logic_vector(0 downto 0);
begin
p_Result_s_fu_1088_p4 <= p_Val2_6_reg_584;
if to_integer(unsigned(index_assign_cast9_fu_1046_p1)) >= p_Val2_6_reg_584'low and to_integer(unsigned(index_assign_cast9_fu_1046_p1)) <= p_Val2_6_reg_584'high then
result(0) := '0';
for i in p_Repl2_s_fu_1084_p1'range loop
result(0) := result(0) or p_Repl2_s_fu_1084_p1(i);
end loop;
p_Result_s_fu_1088_p4(to_integer(unsigned(index_assign_cast9_fu_1046_p1))) <= result(0);
end if;
end process;
r_V_11_fu_1381_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_12_fu_897_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_13_cast_fu_1384_p1 <= std_logic_vector(resize(unsigned(r_V_11_fu_1381_p1),32));
r_V_14_fu_1367_p4 <= inst_V_reg_1423(26 downto 9);
r_V_17_fu_1344_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_18_cast_fu_1347_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),32));
r_V_20_fu_1336_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_22_cast_fu_1339_p1 <= std_logic_vector(resize(unsigned(r_V_20_fu_1336_p1),32));
r_V_23_fu_1323_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_24_fu_874_p1 <= inst_V_reg_1423(18 - 1 downto 0);
r_V_28_fu_1182_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_30_fu_1174_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_34_fu_1166_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_37_fu_1158_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_40_fu_1150_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_43_fu_1142_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_45_fu_1124_p1 <= inst_V_reg_1423(18 - 1 downto 0);
r_V_49_cast_fu_1127_p1 <= std_logic_vector(resize(unsigned(r_V_45_fu_1124_p1),32));
r_V_49_fu_1111_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_52_fu_1098_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_55_fu_1034_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_56_cast_fu_1101_p1 <= std_logic_vector(resize(unsigned(r_V_52_fu_1098_p1),32));
r_V_60_fu_802_p1 <= inst_V_reg_1423(18 - 1 downto 0);
r_V_64_fu_928_p1 <= inst_V_reg_1423(9 - 1 downto 0);
r_V_66_cast_fu_1255_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),32));
r_V_68_cast_fu_1235_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),32));
r_V_70_cast_fu_1205_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),32));
r_V_71_cast_fu_935_p1 <= std_logic_vector(resize(unsigned(r_V_64_fu_928_p1),32));
r_V_78_tmp_s_fu_1247_p3 <=
reg_698 when (zero_flag(0) = '1') else
reg_720;
r_V_79_tmp_s_fu_1239_p3 <=
r_V_68_cast_fu_1235_p1 when (zero_flag(0) = '1') else
reg_720;
r_V_8_fu_910_p1 <= inst_V_reg_1423(18 - 1 downto 0);
-- registers_V_address0 assign process. --
registers_V_address0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, opcode_V_reg_1449, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st36_fsm_35, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st42_fsm_41, grp_agito_shift_fu_619_registers_V_address0, ap_sig_cseq_ST_st35_fsm_34, tmp_fu_784_p1, tmp_i9_44_fu_805_p1, tmp_i8_43_fu_810_p1, tmp_i7_42_fu_815_p1, tmp_i6_41_fu_820_p1, tmp_i5_40_fu_825_p1, tmp_i7_fu_839_p1, tmp_30_fu_844_p1, tmp_28_fu_849_p1, tmp_24_fu_854_p1, tmp_21_fu_859_p1, tmp_17_fu_864_p1, tmp_14_fu_869_p1, tmp_i6_fu_877_p1, tmp_i3_38_fu_882_p1, tmp_i2_37_fu_887_p1, tmp_i3_fu_892_p1, tmp_5_i_fu_900_p1, tmp_i1_fu_905_p1, tmp_1_i1_fu_1037_p1, tmp_7_i_fu_1114_p1, tmp_31_fu_1145_p1, tmp_29_fu_1153_p1, tmp_25_fu_1161_p1, tmp_22_fu_1169_p1, tmp_18_fu_1177_p1, tmp_15_fu_1185_p1, tmp_27_fu_1190_p1, tmp_20_fu_1195_p1, tmp_13_fu_1200_p1, tmp_39_i_fu_1326_p1, tmp_4_i_fu_1352_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) then
registers_V_address0 <= tmp_4_i_fu_1352_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35)) then
registers_V_address0 <= tmp_39_i_fu_1326_p1(4 - 1 downto 0);
elsif (((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25))) then
registers_V_address0 <= tmp_13_fu_1200_p1(4 - 1 downto 0);
elsif (((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25))) then
registers_V_address0 <= tmp_20_fu_1195_p1(4 - 1 downto 0);
elsif (((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25))) then
registers_V_address0 <= tmp_27_fu_1190_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_C))) then
registers_V_address0 <= tmp_15_fu_1185_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_D))) then
registers_V_address0 <= tmp_18_fu_1177_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_E))) then
registers_V_address0 <= tmp_22_fu_1169_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_F))) then
registers_V_address0 <= tmp_25_fu_1161_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_10))) then
registers_V_address0 <= tmp_29_fu_1153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_11))) then
registers_V_address0 <= tmp_31_fu_1145_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
registers_V_address0 <= tmp_7_i_fu_1114_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
registers_V_address0 <= tmp_1_i1_fu_1037_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_2))) then
registers_V_address0 <= tmp_i1_fu_905_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_3))) then
registers_V_address0 <= tmp_5_i_fu_900_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_4))) then
registers_V_address0 <= tmp_i3_fu_892_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_5))) then
registers_V_address0 <= tmp_i2_37_fu_887_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_6))) then
registers_V_address0 <= tmp_i3_38_fu_882_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_B))) then
registers_V_address0 <= tmp_i6_fu_877_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_C))) then
registers_V_address0 <= tmp_14_fu_869_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_D))) then
registers_V_address0 <= tmp_17_fu_864_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_E))) then
registers_V_address0 <= tmp_21_fu_859_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_F))) then
registers_V_address0 <= tmp_24_fu_854_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_10))) then
registers_V_address0 <= tmp_28_fu_849_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_11))) then
registers_V_address0 <= tmp_30_fu_844_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_12))) then
registers_V_address0 <= tmp_i7_fu_839_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_14))) then
registers_V_address0 <= tmp_i5_40_fu_825_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_15))) then
registers_V_address0 <= tmp_i6_41_fu_820_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_16))) then
registers_V_address0 <= tmp_i7_42_fu_815_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_17))) then
registers_V_address0 <= tmp_i8_43_fu_810_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_18))) then
registers_V_address0 <= tmp_i9_44_fu_805_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
registers_V_address0 <= tmp_fu_784_p1(4 - 1 downto 0);
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_address0 <= grp_agito_shift_fu_619_registers_V_address0;
else
registers_V_address0 <= "XXXX";
end if;
end process;
-- registers_V_address1 assign process. --
registers_V_address1_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st12_fsm_11, tmp_i12_reg_1554, tmp_i11_reg_1559, tmp_i10_reg_1600, grp_agito_shift_fu_619_registers_V_address1, ap_sig_cseq_ST_st35_fsm_34, tmp_i9_fu_1106_p1, ap_sig_cseq_ST_st16_fsm_15, tmp_i8_fu_1119_p1, ap_sig_cseq_ST_st20_fsm_19, tmp_i1_36_fu_1303_p1, ap_sig_cseq_ST_st29_fsm_28, tmp_i4_39_fu_1318_p1, ap_sig_cseq_ST_st34_fsm_33, tmp_i5_fu_1331_p1, ap_sig_cseq_ST_st40_fsm_39, tmp_i4_fu_1357_p1, ap_sig_cseq_ST_st44_fsm_43, tmp_i_fu_1394_p1, ap_sig_cseq_ST_st53_fsm_52)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) then
registers_V_address1 <= tmp_i_fu_1394_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) then
registers_V_address1 <= tmp_i4_fu_1357_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39)) then
registers_V_address1 <= tmp_i5_fu_1331_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) then
registers_V_address1 <= tmp_i4_39_fu_1318_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
registers_V_address1 <= tmp_i1_36_fu_1303_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then
registers_V_address1 <= tmp_i8_fu_1119_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
registers_V_address1 <= tmp_i9_fu_1106_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
registers_V_address1 <= tmp_i10_reg_1600(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
registers_V_address1 <= tmp_i11_reg_1559(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
registers_V_address1 <= tmp_i12_reg_1554(4 - 1 downto 0);
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_address1 <= grp_agito_shift_fu_619_registers_V_address1;
else
registers_V_address1 <= "XXXX";
end if;
end process;
-- registers_V_ce0 assign process. --
registers_V_ce0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, opcode_V_reg_1449, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st36_fsm_35, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st42_fsm_41, grp_agito_shift_fu_619_registers_V_ce0, ap_sig_cseq_ST_st35_fsm_34)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_11)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_10)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_F)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_E)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_D)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) and (opcode_V_reg_1449 = ap_const_lv5_C)) or (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_18)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_17)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_16)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_15)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_14)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_12)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_11)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_10)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_F)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_E)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_D)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_C)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_B)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_6)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_5)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_4)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_3)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (opcode_V_reg_1449 = ap_const_lv5_2)) or ((opcode_V_reg_1449 = ap_const_lv5_10) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_E) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or ((opcode_V_reg_1449 = ap_const_lv5_C) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41))) then
registers_V_ce0 <= ap_const_logic_1;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_ce0 <= grp_agito_shift_fu_619_registers_V_ce0;
else
registers_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- registers_V_ce1 assign process. --
registers_V_ce1_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st12_fsm_11, grp_agito_shift_fu_619_registers_V_ce1, ap_sig_cseq_ST_st35_fsm_34, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st34_fsm_33, ap_sig_cseq_ST_st40_fsm_39, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st53_fsm_52)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39) or (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43) or (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52))) then
registers_V_ce1 <= ap_const_logic_1;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_ce1 <= grp_agito_shift_fu_619_registers_V_ce1;
else
registers_V_ce1 <= ap_const_logic_0;
end if;
end process;
-- registers_V_d1 assign process. --
registers_V_d1_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st12_fsm_11, reg_715, reg_724, memory_V_load_1_reg_1763, memory_V_load_reg_1773, grp_agito_shift_fu_619_registers_V_d1, p_Val2_11_reg_538, p_Val2_9_reg_561, p_Val2_6_reg_584, ap_sig_cseq_ST_st35_fsm_34, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st34_fsm_33, ap_sig_cseq_ST_st40_fsm_39, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st53_fsm_52)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) then
registers_V_d1 <= memory_V_load_reg_1773;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39) or (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43))) then
registers_V_d1 <= reg_724;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
registers_V_d1 <= memory_V_load_1_reg_1763;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then
registers_V_d1 <= reg_715;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
registers_V_d1 <= p_Val2_6_reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
registers_V_d1 <= p_Val2_9_reg_561;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
registers_V_d1 <= p_Val2_11_reg_538;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_d1 <= grp_agito_shift_fu_619_registers_V_d1;
else
registers_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- registers_V_we1 assign process. --
registers_V_we1_assign_proc : process(opcode_V_reg_1449, ap_sig_cseq_ST_st6_fsm_5, exitcond_i_i2_fu_943_p2, ap_sig_cseq_ST_st8_fsm_7, exitcond_i_i1_fu_987_p2, ap_sig_cseq_ST_st12_fsm_11, exitcond_i_i_fu_1050_p2, grp_agito_shift_fu_619_registers_V_we1, ap_sig_cseq_ST_st35_fsm_34, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st34_fsm_33, ap_sig_cseq_ST_st40_fsm_39, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st53_fsm_52)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = exitcond_i_i2_fu_943_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = exitcond_i_i1_fu_987_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = exitcond_i_i_fu_1050_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or ((opcode_V_reg_1449 = ap_const_lv5_2) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) or (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39) or ((opcode_V_reg_1449 = ap_const_lv5_5) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) or (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52))) then
registers_V_we1 <= ap_const_logic_1;
elsif ((((opcode_V_reg_1449 = ap_const_lv5_A) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_9) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_8) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or ((opcode_V_reg_1449 = ap_const_lv5_7) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)))) then
registers_V_we1 <= grp_agito_shift_fu_619_registers_V_we1;
else
registers_V_we1 <= ap_const_logic_0;
end if;
end process;
sel_tmp3_fu_1209_p2 <= (zero_flag or tmp_150_reg_1673);
sel_tmp_fu_1222_p2 <= (zero_flag or tmp_148_reg_1678);
storemerge5_fu_1227_p3 <=
reg_720 when (sel_tmp_fu_1222_p2(0) = '1') else
reg_698;
storemerge_fu_1214_p3 <=
reg_720 when (sel_tmp3_fu_1209_p2(0) = '1') else
r_V_70_cast_fu_1205_p1;
tmp_13_fu_1200_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_14_fu_869_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_157_fu_1062_p3 <= reg_698(to_integer(unsigned(index_assign_cast9_fu_1046_p1)) downto to_integer(unsigned(index_assign_cast9_fu_1046_p1))) when (to_integer(unsigned(index_assign_cast9_fu_1046_p1))>= 0 and to_integer(unsigned(index_assign_cast9_fu_1046_p1))<=31) else "-";
tmp_158_fu_1070_p3 <= reg_709(to_integer(unsigned(index_assign_cast9_fu_1046_p1)) downto to_integer(unsigned(index_assign_cast9_fu_1046_p1))) when (to_integer(unsigned(index_assign_cast9_fu_1046_p1))>= 0 and to_integer(unsigned(index_assign_cast9_fu_1046_p1))<=31) else "-";
tmp_15_fu_1185_p1 <= std_logic_vector(resize(unsigned(r_V_28_fu_1182_p1),64));
tmp_160_fu_999_p3 <= reg_698(to_integer(unsigned(index_assign_1_cast7_fu_983_p1)) downto to_integer(unsigned(index_assign_1_cast7_fu_983_p1))) when (to_integer(unsigned(index_assign_1_cast7_fu_983_p1))>= 0 and to_integer(unsigned(index_assign_1_cast7_fu_983_p1))<=31) else "-";
tmp_161_fu_1007_p3 <= r_V_71_cast_reg_1564(to_integer(unsigned(index_assign_1_cast7_fu_983_p1)) downto to_integer(unsigned(index_assign_1_cast7_fu_983_p1))) when (to_integer(unsigned(index_assign_1_cast7_fu_983_p1))>= 0 and to_integer(unsigned(index_assign_1_cast7_fu_983_p1))<=31) else "-";
tmp_163_fu_955_p3 <= reg_698(to_integer(unsigned(index_assign_2_cast5_fu_939_p1)) downto to_integer(unsigned(index_assign_2_cast5_fu_939_p1))) when (to_integer(unsigned(index_assign_2_cast5_fu_939_p1))>= 0 and to_integer(unsigned(index_assign_2_cast5_fu_939_p1))<=31) else "-";
tmp_17_fu_864_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_18_fu_1177_p1 <= std_logic_vector(resize(unsigned(r_V_30_fu_1174_p1),64));
tmp_1_i1_fu_1037_p1 <= std_logic_vector(resize(unsigned(r_V_55_fu_1034_p1),64));
tmp_1_i_fu_1131_p2 <= std_logic_vector(unsigned(r_V_49_cast_fu_1127_p1) + unsigned(reg_698));
tmp_20_fu_1195_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_21_fu_859_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_22_fu_1169_p1 <= std_logic_vector(resize(unsigned(r_V_34_fu_1166_p1),64));
tmp_24_fu_854_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_25_fu_1161_p1 <= std_logic_vector(resize(unsigned(r_V_37_fu_1158_p1),64));
tmp_27_fu_1190_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_28_fu_849_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_29_fu_1153_p1 <= std_logic_vector(resize(unsigned(r_V_40_fu_1150_p1),64));
tmp_2_i_fu_1389_p1 <= std_logic_vector(resize(unsigned(reg_724),64));
tmp_30_fu_844_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_31_fu_1145_p1 <= std_logic_vector(resize(unsigned(r_V_43_fu_1142_p1),64));
tmp_39_i_fu_1326_p1 <= std_logic_vector(resize(unsigned(r_V_23_fu_1323_p1),64));
tmp_3_i_fu_1362_p1 <= std_logic_vector(resize(unsigned(reg_724),64));
tmp_45_r_V_s_fu_1266_p3 <=
reg_698 when (tmp_142_reg_1688(0) = '1') else
reg_720;
tmp_46_r_V_s_fu_1259_p3 <=
r_V_66_cast_fu_1255_p1 when (tmp_144_reg_1683(0) = '1') else
reg_720;
tmp_4_i_fu_1352_p1 <= std_logic_vector(resize(unsigned(r_V_17_fu_1344_p1),64));
tmp_5_i_fu_900_p1 <= std_logic_vector(resize(unsigned(r_V_12_fu_897_p1),64));
tmp_7_i_fu_1114_p1 <= std_logic_vector(resize(unsigned(r_V_49_fu_1111_p1),64));
tmp_fu_784_p1 <= std_logic_vector(resize(signed(output_loc),64));
tmp_i10_fu_1042_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i11_fu_931_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i12_fu_924_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i1_36_fu_1303_p1 <= std_logic_vector(resize(unsigned(r_V_13_reg_1758),64));
tmp_i1_fu_905_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i2_37_fu_887_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i2_fu_1376_p1 <= std_logic_vector(resize(unsigned(r_V_14_fu_1367_p4),64));
tmp_i3_38_fu_882_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i3_fu_892_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i4_39_fu_1318_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i4_fu_1357_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i5_40_fu_825_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i5_fu_1331_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i6_41_fu_820_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i6_fu_877_p1 <= std_logic_vector(resize(unsigned(r_V_24_fu_874_p1),64));
tmp_i7_42_fu_815_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i7_fu_839_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i8_43_fu_810_p1 <= std_logic_vector(resize(unsigned(grp_fu_642_p4),64));
tmp_i8_fu_1119_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i9_44_fu_805_p1 <= std_logic_vector(resize(unsigned(r_V_60_fu_802_p1),64));
tmp_i9_fu_1106_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i_35_fu_913_p1 <= std_logic_vector(resize(unsigned(r_V_8_fu_910_p1),64));
tmp_i_fu_1394_p1 <= std_logic_vector(resize(unsigned(grp_fu_651_p4),64));
tmp_i_i1_fu_1014_p2 <= (tmp_161_fu_1007_p3 or tmp_160_fu_999_p3);
tmp_i_i2_fu_963_p2 <= (tmp_163_fu_955_p3 xor ap_const_lv1_1);
tmp_i_i_fu_1078_p2 <= (tmp_158_fu_1070_p3 or tmp_157_fu_1062_p3);
tmp_s_fu_779_p1 <= std_logic_vector(resize(unsigned(pc_V),64));
val_assign_fu_1312_p2 <= (reg_698 xor ap_const_lv32_FFFFFFFF);
end behav;
|
--lee de la uart y combina LSB y MSB en un dato de 16bits con los datos de la UART.
--(Toma LSB y MSB de la uart)
--Version con maquinola de estados
-------------------------------------------------------------------------------
--UNIDAD ASINCRONICA
--Algo que podria generar problemas es inicializar la senial RxRdy_out en cero
--justo debajo del begin. Habria que revisar eso como prioridad en caso de que falle
--la recepcion de datos.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
entity data_loader is
generic (
in_data_bits : natural := 8; --cantidad de bits del dato que entra
out_data_bits: natural:=16; -- cant de bits del dato que sale
data_midpoint: natural:=8 -- bits/2 del dato que sale
);
port(
--clock: in std_logic;
reset: in std_logic;
data_in: in std_logic_vector(in_data_bits-1 downto 0);
data_out: out std_logic_vector(out_data_bits-1 downto 0);
RxRdy_in: in std_logic;
RxRdy_out: out std_logic
);
end entity data_loader;
architecture data_loader_arch of data_loader is
type state_t is (LSB, MSB);
signal state : state_t := LSB;
begin
FSM: process(RxRdy_in, reset, state, data_in)
begin
RxRdy_out <= '0';
-- RESET
if reset = '1' then
data_out <= (others => '0');
state <= LSB;
RxRdy_out <= '0';
else
case state is
-- LSByte
when LSB =>
if RxRdy_in = '1' then
data_out(data_midpoint-1 downto 0) <= data_in;
RxRdy_out <= '0';
state <= MSB;
end if;
-- MSByte
when MSB =>
if RxRdy_in = '1' then
data_out(out_data_bits-1 downto data_midpoint) <= data_in;
RxRdy_out <= '1';
state <= LSB;
end if;
end case;
end if;
end process;
end data_loader_arch;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= OutSelecttemp(0) or OutSelecttemp(1) or OutSelecttemp (2) or OutSelecttemp(3) or
OutSelecttemp(4) or OutSelecttemp(5) or OutSelecttemp (6) or OutSelecttemp(7);
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= '0' ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower; --Complete the right hand side of the expression
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or
(not (IssuequefullTemp_Upper) and not (IssuequefullTemp_Lower)) ;
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag(0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag(1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag(2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag(3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag(4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag(5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag(6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag(7)) - unsigned(Rob_TopPtr);
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= IssuequeInstrValReg(1); --Hint: Take into account the shift mechanism so is it i or i+1 or i - 1?
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= IssuequeInstrValReg(2);
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= IssuequeInstrValReg(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= IssuequeInstrValReg(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= IssuequeInstrValReg(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= IssuequeInstrValReg(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= IssuequeInstrValReg(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
|
-- ************************************
-- Automatically Generated FSM
-- interp
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity interp is
generic(
DATA_BITS : integer := 32;
REG_FILE_ADDR_BITS : integer := 8;
MEMORY_ADDR_BITS : integer := 32;
RESERVED_REG_START : integer := 128;
RESERVED_REG_STOP : integer := 255;
PC_REG_ADDR : integer := 195;
OPCODE_START : integer := 0;
OPCODE_TYPE_BITS : integer := 4;
OPCODE_BITS : integer := 8;
R_DEST_START : integer := 8;
R_DEST_BITS : integer := 8;
R_ARG_A_START : integer := 16;
R_ARG_A_BITS : integer := 8;
R_ARG_B_START : integer := 24;
R_ARG_B_BITS : integer := 8
);
port
(
prog_mem_addr0 : out std_logic_vector(0 to (MEMORY_ADDR_BITS - 1));
prog_mem_dIN0 : out std_logic_vector(0 to (DATA_BITS - 1));
prog_mem_dOUT0 : in std_logic_vector(0 to (DATA_BITS - 1));
prog_mem_rENA0 : out std_logic;
prog_mem_wENA0 : out std_logic;
state_mem_addr0 : out std_logic_vector(0 to (REG_FILE_ADDR_BITS - 1));
state_mem_dIN0 : out std_logic_vector(0 to (DATA_BITS - 1));
state_mem_dOUT0 : in std_logic_vector(0 to (DATA_BITS - 1));
state_mem_rENA0 : out std_logic;
state_mem_wENA0 : out std_logic;
go : in std_logic;
mode : in std_logic_vector(0 to 1);
done : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity interp;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of interp is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
begin_export_state,
export_state,
extra1,
extra2,
extra3,
extra4,
store_pc,
fetch,
begin_import_state,
import_state,
extra5,
extra6,
extra7,
extra8,
restore_pc,
extra9,
extra10,
extra11,
extra12,
decode,
extra13,
extra14,
do_arithmetic,
extra15,
extra16,
do_other,
writeback,
extra17,
extra18,
load_lo,
extra19,
extra20,
load_hi,
extra21,
extra22,
memory,
extra23,
extra24,
grab_multiply,
reset,
initRegFile
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal pc, pc_next : std_logic_vector(0 to MEMORY_ADDR_BITS - 1);
signal instr, instr_next : std_logic_vector(0 to DATA_BITS - 1);
signal a, a_next : std_logic_vector(0 to DATA_BITS - 1);
signal b, b_next : std_logic_vector(0 to DATA_BITS - 1);
signal c, c_next : std_logic_vector(0 to DATA_BITS - 1);
signal d, d_next : std_logic_vector(0 to DATA_BITS - 1);
signal offset, offset_next : std_logic_vector(0 to DATA_BITS - 1);
signal mult_res, mult_res_next : std_logic_vector(0 to DATA_BITS * 2 - 1);
signal reg_counter, reg_counter_next : std_logic_vector(0 to REG_FILE_ADDR_BITS - 1);
signal halt, halt_next : std_logic;
-- **************************
-- BRAM Signals for regfile
-- **************************
signal regfile_addr0 : std_logic_vector(0 to (REG_FILE_ADDR_BITS - 1));
signal regfile_dIN0 : std_logic_vector(0 to (DATA_BITS - 1));
signal regfile_dOUT0 : std_logic_vector(0 to (DATA_BITS - 1));
signal regfile_rENA0 : std_logic;
signal regfile_wENA0 : std_logic;
signal regfile_addr1 : std_logic_vector(0 to (REG_FILE_ADDR_BITS - 1));
signal regfile_dIN1 : std_logic_vector(0 to (DATA_BITS - 1));
signal regfile_dOUT1 : std_logic_vector(0 to (DATA_BITS - 1));
signal regfile_rENA1 : std_logic;
signal regfile_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant HALFPOINT : integer := DATA_BITS/2;
-- Command modes
-- **************************************************
constant CMD_HALT : std_logic_vector(0 to 1) := "00";
constant CMD_IMPORT_STATE : std_logic_vector(0 to 1) := "01";
constant CMD_EXPORT_STATE : std_logic_vector(0 to 1) := "10";
constant CMD_INTERPRET : std_logic_vector(0 to 1) := "11";
-- Instruction OPCODES TYPES
-- **************************************************
constant TYPE_ARITHMETIC : std_logic_vector(0 to OPCODE_TYPE_BITS-1) := conv_std_logic_vector(0, OPCODE_TYPE_BITS);
constant TYPE_OTHER : std_logic_vector(0 to OPCODE_TYPE_BITS-1) := conv_std_logic_vector(1, OPCODE_TYPE_BITS);
-- Instruction OPCODES
-- **************************************************
constant OPCODE_ADD : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(0, OPCODE_BITS);
constant OPCODE_SUB : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(1, OPCODE_BITS);
constant OPCODE_MULT : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(2, OPCODE_BITS);
constant OPCODE_AND : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(3, OPCODE_BITS);
constant OPCODE_OR : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(4, OPCODE_BITS);
constant OPCODE_XOR : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(5, OPCODE_BITS);
constant OPCODE_SHRA : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(6, OPCODE_BITS);
constant OPCODE_SHRL : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(7, OPCODE_BITS);
constant OPCODE_SHL : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(8, OPCODE_BITS);
constant OPCODE_LOAD_IMM : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(16, OPCODE_BITS);
constant OPCODE_JEZ : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(17, OPCODE_BITS);
constant OPCODE_LOAD : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(18, OPCODE_BITS);
constant OPCODE_STORE : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(19, OPCODE_BITS);
constant OPCODE_LOAD_LO : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(20, OPCODE_BITS);
constant OPCODE_LOAD_HI : std_logic_vector(0 to OPCODE_BITS-1) := conv_std_logic_vector(21, OPCODE_BITS);
-- Amount to increase PC on "normal" instructions
-- **************************************************
constant pcInc : std_logic_vector(0 to MEMORY_ADDR_BITS-1) := conv_std_logic_vector(4, MEMORY_ADDR_BITS);
constant PC_HALT : std_logic_vector(0 to MEMORY_ADDR_BITS-1) := (others => '1');
constant pcStore : std_logic_vector(0 to REG_FILE_ADDR_BITS-1) := conv_std_logic_vector(PC_REG_ADDR, REG_FILE_ADDR_BITS);
-- Aliases for instruction decode:
-- *************************************
-- Opcode-type of the current instruction
alias opcode_type is instr(OPCODE_START to (OPCODE_START+OPCODE_TYPE_BITS-1));
-- Opcode of the current instruction
alias opcode is instr(OPCODE_START to (OPCODE_START+OPCODE_BITS-1));
-- Register destination
alias r_dest is instr(R_DEST_START to (R_DEST_START+R_DEST_BITS-1));
-- Test register (for compares)
alias r_compare_test is instr(R_DEST_START to (R_DEST_START+R_DEST_BITS-1));
-- Register argument A
alias r_arg_a is instr(R_ARG_A_START to (R_ARG_A_START+R_ARG_A_BITS-1));
-- Register argument B
alias r_arg_b is instr(R_ARG_B_START to (R_ARG_B_START+R_ARG_B_BITS-1));
-- Immediate value
constant immediate_pad_length : integer := DATA_BITS-R_ARG_A_BITS-R_ARG_B_BITS;
constant immediate_zero_pad : std_logic_vector(0 to immediate_pad_length -1 ) := conv_std_logic_vector(0, immediate_pad_length);
alias immediate_value is instr(R_ARG_A_START to (R_ARG_A_START+R_ARG_A_BITS+R_ARG_B_BITS-1));
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
done <= halt;
-- ************************
-- BRAM implementations
-- ************************
regfile_BRAM : infer_bram
generic map (
ADDRESS_BITS => REG_FILE_ADDR_BITS,
DATA_BITS => DATA_BITS
)
port map (
CLKA => clock_sig,
ENA => regfile_rENA0,
WEA => regfile_wENA0,
ADDRA => regfile_addr0,
DIA => regfile_dIN0,
DOA => regfile_dOUT0,
CLKB => clock_sig,
ENB => regfile_rENA1,
WEB => regfile_wENA1,
ADDRB => regfile_addr1,
DIB => regfile_dIN1,
DOB => regfile_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
pc_next,
instr_next,
a_next,
b_next,
c_next,
d_next,
offset_next,
mult_res_next,
reg_counter_next,
halt_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
pc <= (others => '0');
instr <= (others => '0');
a <= (others => '0');
b <= (others => '0');
c <= (others => '0');
d <= (others => '0');
offset <= (others => '0');
mult_res <= (others => '0');
reg_counter <= (others => '0');
halt <= '0';
current_state <= reset;
else
-- Transition to next state
pc <= pc_next;
instr <= instr_next;
a <= a_next;
b <= b_next;
c <= c_next;
d <= d_next;
offset <= offset_next;
mult_res <= mult_res_next;
reg_counter <= reg_counter_next;
halt <= halt_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
regfile_dOUT0, regfile_dOUT1,
prog_mem_dOUT0,
state_mem_dOUT0,
go,
mode,
pc,
instr,
a,
b,
c,
d,
offset,
mult_res,
reg_counter,
halt,
current_state) is
begin
-- Default signal assignments
pc_next <= pc;
instr_next <= instr;
a_next <= a;
b_next <= b;
c_next <= c;
d_next <= d;
offset_next <= offset;
mult_res_next <= mult_res;
reg_counter_next <= reg_counter;
halt_next <= halt;
regfile_addr0 <= (others => '0');
regfile_dIN0 <= (others => '0');
regfile_rENA0 <= '0';
regfile_wENA0 <= '0';
regfile_addr1 <= (others => '0');
regfile_dIN1 <= (others => '0');
regfile_rENA1 <= '0';
regfile_wENA1 <= '0';
prog_mem_addr0 <= (others => '0');
prog_mem_dIN0 <= (others => '0');
prog_mem_rENA0 <= '0';
prog_mem_wENA0 <= '0';
state_mem_addr0 <= (others => '0');
state_mem_dIN0 <= (others => '0');
state_mem_rENA0 <= '0';
state_mem_wENA0 <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when begin_export_state =>
halt_next <= '0';
reg_counter_next <= conv_std_logic_vector(RESERVED_REG_STOP,REG_FILE_ADDR_BITS);
next_state <= export_state;
when begin_import_state =>
halt_next <= '0';
reg_counter_next <= conv_std_logic_vector(RESERVED_REG_STOP,REG_FILE_ADDR_BITS);
next_state <= import_state;
when decode =>
if ( opcode_type = TYPE_ARITHMETIC ) then
regfile_addr0 <= r_arg_b;
regfile_rENA0 <= '1';
regfile_addr1 <= r_arg_a;
regfile_rENA1 <= '1';
next_state <= extra13;
elsif ( opcode_type = TYPE_OTHER ) then
regfile_addr0 <= r_dest;
regfile_rENA0 <= '1';
regfile_addr1 <= r_arg_a;
regfile_rENA1 <= '1';
next_state <= extra15;
end if;
when do_arithmetic =>
if ( opcode = OPCODE_ADD ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a + b;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_SUB ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a - b;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_MULT ) then
mult_res_next <= a * b;
next_state <= grab_multiply;
elsif ( opcode = OPCODE_AND ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a and b;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_OR ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a or b;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_XOR ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a xor b;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_SHRA ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a(0) & a(0 to DATA_BITS - 2);
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_SHRL ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= '0' & a(0 to DATA_BITS - 2);
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_SHL ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= a(1 to DATA_BITS - 1) & '0';
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
end if;
when do_other =>
if ( opcode = OPCODE_LOAD_IMM ) then
regfile_addr0 <= r_dest;
regfile_dIN0 <= immediate_zero_pad & immediate_value;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
elsif ( opcode = OPCODE_LOAD_LO ) then
regfile_addr0 <= r_dest;
regfile_rENA0 <= '1';
next_state <= extra17;
elsif ( opcode = OPCODE_LOAD_HI ) then
regfile_addr0 <= r_dest;
regfile_rENA0 <= '1';
next_state <= extra19;
elsif ( opcode = OPCODE_JEZ and c /= 0 ) then
next_state <= writeback;
elsif ( opcode = OPCODE_JEZ and c = 0 ) then
pc_next <= a;
regfile_addr0 <= pcStore;
regfile_dIN0 <= a;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= fetch;
elsif ( opcode = OPCODE_LOAD ) or ( opcode = OPCODE_STORE ) then
regfile_addr0 <= r_arg_b;
regfile_rENA0 <= '1';
next_state <= extra21;
end if;
when export_state =>
if ( reg_counter > 0 ) then
regfile_addr0 <= reg_counter;
regfile_rENA0 <= '1';
next_state <= extra1;
elsif ( reg_counter = 0 ) then
regfile_addr0 <= reg_counter;
regfile_rENA0 <= '1';
next_state <= extra3;
end if;
when extra1 =>
next_state <= extra2;
when extra10 =>
regfile_addr0 <= pcStore;
regfile_dIN0 <= state_mem_dOUT0;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
pc_next <= state_mem_dOUT0;
next_state <= fetch;
when extra11 =>
next_state <= extra12;
when extra12 =>
instr_next <= prog_mem_dOUT0;
next_state <= decode;
when extra13 =>
next_state <= extra14;
when extra14 =>
b_next <= regfile_dOUT0;
a_next <= regfile_dOUT1;
halt_next <= '0';
next_state <= do_arithmetic;
when extra15 =>
next_state <= extra16;
when extra16 =>
c_next <= regfile_dOUT0;
a_next <= regfile_dOUT1;
next_state <= do_other;
when extra17 =>
next_state <= extra18;
when extra18 =>
d_next <= regfile_dOUT0;
next_state <= load_lo;
when extra19 =>
next_state <= extra20;
when extra2 =>
reg_counter_next <= reg_counter - 1;
state_mem_addr0 <= reg_counter;
state_mem_dIN0 <= regfile_dOUT0;
state_mem_wENA0 <= '1';
state_mem_rENA0 <= '1';
next_state <= export_state;
when extra20 =>
d_next <= regfile_dOUT0;
next_state <= load_hi;
when extra21 =>
next_state <= extra22;
when extra22 =>
offset_next <= regfile_dOUT0;
next_state <= memory;
when extra23 =>
next_state <= extra24;
when extra24 =>
regfile_addr0 <= r_dest;
regfile_dIN0 <= prog_mem_dOUT0;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
when extra3 =>
next_state <= extra4;
when extra4 =>
state_mem_addr0 <= reg_counter;
state_mem_dIN0 <= regfile_dOUT0;
state_mem_wENA0 <= '1';
state_mem_rENA0 <= '1';
next_state <= store_pc;
when extra5 =>
next_state <= extra6;
when extra6 =>
reg_counter_next <= reg_counter - 1;
regfile_addr0 <= reg_counter;
regfile_dIN0 <= state_mem_dOUT0;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= import_state;
when extra7 =>
next_state <= extra8;
when extra8 =>
regfile_addr0 <= reg_counter;
regfile_dIN0 <= state_mem_dOUT0;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= restore_pc;
when extra9 =>
next_state <= extra10;
when fetch =>
if ( go = '0' ) then
next_state <= fetch;
elsif ( go = '1' and mode = CMD_HALT ) then
next_state <= fetch;
elsif ( go = '1' and mode = CMD_EXPORT_STATE ) then
next_state <= begin_export_state;
elsif ( go = '1' and mode = CMD_IMPORT_STATE ) then
next_state <= begin_import_state;
elsif ( go = '1' and mode = CMD_INTERPRET and pc = PC_HALT ) then
halt_next <= '1';
next_state <= fetch;
elsif ( go = '1' and mode = CMD_INTERPRET ) then
prog_mem_addr0 <= pc;
prog_mem_rENA0 <= '1';
next_state <= extra11;
end if;
when grab_multiply =>
regfile_addr0 <= r_dest;
regfile_dIN0 <= mult_res(DATA_BITS to DATA_BITS * 2 - 1);
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
when import_state =>
if ( reg_counter > 0 ) then
state_mem_addr0 <= reg_counter;
state_mem_rENA0 <= '1';
next_state <= extra5;
elsif ( reg_counter = 0 ) then
state_mem_addr0 <= reg_counter;
state_mem_rENA0 <= '1';
next_state <= extra7;
end if;
when initRegFile =>
if ( reg_counter < RESERVED_REG_STOP ) then
regfile_addr0 <= reg_counter;
regfile_dIN0 <= c;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
reg_counter_next <= reg_counter + 1;
c_next <= c + 1;
next_state <= initRegFile;
elsif ( reg_counter = RESERVED_REG_STOP ) then
regfile_addr0 <= reg_counter;
regfile_dIN0 <= c;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
pc_next <= conv_std_logic_vector(0,MEMORY_ADDR_BITS);
regfile_addr0 <= pcStore;
regfile_dIN0 <= conv_std_logic_vector(0,MEMORY_ADDR_BITS);
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= fetch;
end if;
when load_hi =>
regfile_addr0 <= r_dest;
regfile_dIN0 <= immediate_value & d(HALFPOINT to DATA_BITS - 1);
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
when load_lo =>
regfile_addr0 <= r_dest;
regfile_dIN0 <= d(0 to HALFPOINT - 1) & immediate_value;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= writeback;
when memory =>
if ( opcode = OPCODE_LOAD ) then
prog_mem_addr0 <= a + offset;
prog_mem_rENA0 <= '1';
next_state <= extra23;
elsif ( opcode = OPCODE_STORE ) then
prog_mem_addr0 <= a + offset;
prog_mem_dIN0 <= c;
prog_mem_wENA0 <= '1';
prog_mem_rENA0 <= '1';
next_state <= writeback;
end if;
when reset =>
halt_next <= '0';
c_next <= conv_std_logic_vector(0,DATA_BITS);
reg_counter_next <= conv_std_logic_vector(0,REG_FILE_ADDR_BITS);
next_state <= initRegFile;
when restore_pc =>
state_mem_addr0 <= pcStore;
state_mem_rENA0 <= '1';
next_state <= extra9;
when store_pc =>
state_mem_addr0 <= pcStore;
state_mem_dIN0 <= pc;
state_mem_wENA0 <= '1';
state_mem_rENA0 <= '1';
next_state <= fetch;
when writeback =>
pc_next <= pc + pcInc;
regfile_addr0 <= pcStore;
regfile_dIN0 <= pc + pcInc;
regfile_wENA0 <= '1';
regfile_rENA0 <= '1';
next_state <= fetch;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
architecture rtl of fifo is
begin
process begin
report "hello"
severity FAILURE;
report "hello"
severity FAILURE;
end process;
end architecture rtl;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.1.1 use PLL for clkser_gentype
-- 2016-03-29 756 1.1 use serport_2clock2 -> define clkser
-- 2013-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
|
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- BPM definitions
use work.bpm_cores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC516 ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC,
-- programmable via Microwire Interface
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_o : out std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- DSP constants
constant c_dsp_ref_num_bits : natural := 24;
constant c_dsp_pos_num_bits : natural := 26;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_position_calc_core_sdb,
x"30008000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- FMC516 ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC516 Signals
signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc516_mmcm_lock_int : std_logic;
signal fmc516_lmk_lock_int : std_logic;
signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0);
signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
--signal fmc_debug : std_logic;
--signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fs_rst_sync_n : std_logic;
signal fs_rst_n : std_logic;
-- FMC516 Debug
signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- DSP signals
signal dsp_sysce : std_logic;
signal dsp_sysce_clr : std_logic;
signal dsp_sysclk : std_logic;
signal dsp_sysclk2x : std_logic;
signal dsp_rst_n : std_logic;
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_tbt_decim_q_ch01_incorrect : std_logic;
signal dsp_tbt_decim_q_ch23_incorrect : std_logic;
signal dsp_fofb_decim_q_01_missing : std_logic;
signal dsp_fofb_decim_q_23_missing : std_logic;
signal dsp_monit_cic_unexpected : std_logic;
signal dsp_monit_cfir_incorrect : std_logic;
signal dsp_monit_pfir_incorrect : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
signal CONTROL4 : std_logic_vector(35 downto 0);
signal CONTROL5 : std_logic_vector(35 downto 0);
signal CONTROL6 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 4 signals
signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 5 signals
signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 6 signals
signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_4_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_8_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0);
-- CONTROL4 : inout std_logic_vector(35 downto 0);
-- CONTROL5 : inout std_logic_vector(35 downto 0);
-- CONTROL6 : inout std_logic_vector(35 downto 0);
-- CONTROL7 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_7_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
component chipscope_ila_8192
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0);
TRIG4 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC516 is slave 8
cmp_xwb_fmc516 : xwb_fmc516
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (0.0, 0.0, 8.882, 8.882), --476.066*35/148 aprox 112.583 MHz
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from FMC516.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "0011",
g_use_data_chains => "1111",
g_map_clk_data_chains => (1,0,0,1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b => sys_i2c_scl_b,
sys_i2c_sda_b => sys_i2c_sda_b,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => adc_clk0_p_i,
adc_clk0_n_i => adc_clk0_n_i,
adc_clk1_p_i => adc_clk1_p_i,
adc_clk1_n_i => adc_clk1_n_i,
adc_clk2_p_i => adc_clk2_p_i,
adc_clk2_n_i => adc_clk2_n_i,
adc_clk3_p_i => adc_clk3_p_i,
adc_clk3_n_i => adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => adc_data_ch0_p_i,
adc_data_ch0_n_i => adc_data_ch0_n_i,
adc_data_ch1_p_i => adc_data_ch1_p_i,
adc_data_ch1_n_i => adc_data_ch1_n_i,
adc_data_ch2_p_i => adc_data_ch2_p_i,
adc_data_ch2_n_i => adc_data_ch2_n_i,
adc_data_ch3_p_i => adc_data_ch3_p_i,
adc_data_ch3_n_i => adc_data_ch3_n_i,
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => adc_clk_div_rst_n_o,
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o => fmc_leds_o,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_int,--sys_spi_clk_o,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_int,
--sys_spi_din_i => sys_spi_din_int,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
m2c_trig_n_i => m2c_trig_n_i,
c2m_trig_p_o => c2m_trig_p_o,
c2m_trig_n_o => c2m_trig_n_o,
-- LMK (National Semiconductor) is the clock and distribution IC.
-- uWire interface
lmk_lock_i => lmk_lock_int,--lmk_lock_i,
lmk_sync_o => lmk_sync_int,--lmk_sync_o,
lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o,
lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o,
lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o,
-- Programable VCXO via I2C
vcxo_i2c_sda_b => vcxo_i2c_sda_b,
vcxo_i2c_scl_o => vcxo_i2c_scl_o,
vcxo_pd_l_o => vcxo_pd_l_o,
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b => fmc_id_dq_b,
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b => fmc_key_dq_b,
-- General board pins
fmc_pwr_good_i => fmc_pwr_good_i,
-- Internal/External clock distribution selection
fmc_clk_sel_o => fmc_clk_sel_o,
-- Reset ADCs
fmc_reset_adcs_n_o => fmc_reset_adcs_n_o,--fmc_reset_adcs_n_int,
--FMC Present status
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-----------------------------
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => fmc516_fs_clk,
adc_clk2x_o => fmc516_fs_clk2x,
adc_rst_n_o => open,
adc_data_o => fmc516_adc_data,
adc_data_valid_o => fmc516_adc_valid,
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => clk_rffe_swap, -- from Position Calculation Core
-- General board status
fmc_mmcm_lock_o => fmc516_mmcm_lock_int,
fmc_lmk_lock_o => fmc516_lmk_lock_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
fifo_debug_empty_o => fmc516_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc516_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_o <= fmc516_mmcm_lock_int;
fmc_lmk_lock_o <= fmc516_lmk_lock_int;
sys_spi_clk_o <= sys_spi_clk_int;
sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int;
sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int;
sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int;
sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int;
lmk_lock_int <= lmk_lock_i;
lmk_sync_o <= lmk_sync_int;
lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int;
lmk_uwire_data_o <= lmk_uwire_data_int;
lmk_uwire_clock_o <= lmk_uwire_clock_int;
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => WORD
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- wishbone clock
fs_clk_i => dsp_sysclk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => fmc516_adc_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb),
adc_ch1_i => fmc516_adc_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb),
adc_ch2_i => fmc516_adc_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb),
adc_ch3_i => fmc516_adc_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb),
-----------------------------
-- DSP config parameter signals
-----------------------------
kx => dsp_kx,
ky => dsp_ky,
ksum => dsp_ksum,
del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_q_01_missing_o => dsp_fofb_decim_q_01_missing,
fofb_decim_q_23_missing_o => dsp_fofb_decim_q_23_missing,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch3_o => dsp_monit_amp_ch3,
x_tbt_o => dsp_x_tbt,
y_tbt_o => dsp_y_tbt,
q_tbt_o => dsp_q_tbt,
sum_tbt_o => dsp_sum_tbt,
x_fofb_o => dsp_x_fofb,
y_fofb_o => dsp_y_fofb,
q_fofb_o => dsp_q_fofb,
sum_fofb_o => dsp_sum_fofb,
x_monit_o => dsp_x_monit,
y_monit_o => dsp_y_monit,
q_monit_o => dsp_q_monit,
sum_monit_o => dsp_sum_monit,
monit_cic_unexpected_o => dsp_monit_cic_unexpected,
monit_cfir_incorrect_o => dsp_monit_cfir_incorrect,
monit_pfir_incorrect_o => dsp_monit_pfir_incorrect,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_rffe_swap,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70
);
--dsp_poly35_ch0 <= (others => '0');
--dsp_poly35_ch2 <= (others => '0');
--
--dsp_monit_amp_ch0 <= (others => '0');
--dsp_monit_amp_ch1 <= (others => '0');
--dsp_monit_amp_ch2 <= (others => '0');
--dsp_monit_amp_ch3 <= (others => '0');
-- Signals for the DSP chain
dsp_sysce <= '1';
dsp_sysce_clr <= '0';
--dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk);
dsp_sysclk2x <= fmc516_fs_clk2x(c_adc_ref_clk); -- oversampled DSP chain
dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk); -- oversampled DSP chain
--dsp_rst_n <= fmc516_fs_rst_n(c_adc_ref_clk);
dsp_del_sig_div_thres <= "00000000000000001000000000"; -- aprox 1.22e-4 FIX26_22
--dsp_kx <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_kx <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_kx <= "00100110001001011010000000"; -- 10000000 UFIX26_0
--dsp_ky <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_ky <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_ky <= "00100110001001011010000000"; -- 10000000 UFIX26_0
dsp_ksum <= "0111111111111111111111111"; -- 1.0 FIX25_24
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
--dsp_ksum <= "100000000000000000000000"; -- 1.0 FIX24_23
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
--cmp_chipscope_icon_0 : chipscope_icon_4_port
--port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2,
-- CONTROL3 => CONTROL3
--);
cmp_chipscope_icon_7_port : chipscope_icon_7_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3,
CONTROL4 => CONTROL4,
CONTROL5 => CONTROL5,
CONTROL6 => CONTROL6
);
cmp_chipscope_ila_0_fmc516_adc : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => fmc516_fs_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC516 WBS master output data
--TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_0 <= dsp_adc_ch1_data &
dsp_adc_ch0_data;
TRIG_ILA0_1 <= dsp_adc_ch3_data &
dsp_adc_ch2_data;
TRIG_ILA0_2 <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- FMC516 WBS master output data
--TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load &
-- adc_dly_reg_debug_int(1).data_load &
-- adc_dly_reg_debug_int(1).clk_dly_reg &
-- adc_dly_reg_debug_int(1).data_dly_reg;
--TRIG_ILA0_1(31 downto 12) <= (others => '0');
---- FMC516 WBS master output control signals
--TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
-- wbs_fmc516_out_array(1).stb &
-- wbs_fmc516_out_array(1).adr &
-- wbs_fmc516_out_array(1).sel &
-- wbs_fmc516_out_array(1).we &
-- wbs_fmc516_out_array(2).cyc &
-- wbs_fmc516_out_array(2).stb &
-- wbs_fmc516_out_array(2).adr &
-- wbs_fmc516_out_array(2).sel &
-- wbs_fmc516_out_array(2).we;
--TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid;
--TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int;
--TRIG_ILA0_2(24) <= fmc516_lmk_lock_int;
--TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1);
--TRIG_ILA0_2(26) <= fmc516_debug_full_int(1);
--TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1);
--TRIG_ILA0_2(31 downto 28) <= (others => '0');
--
--TRIG_ILA0_3 <= dsp_adc_ch3_data &
-- dsp_adc_ch2_data;
-- Mix and BPF data
cmp_chipscope_ila_8192_bpf_mix : chipscope_ila_8192
port map (
CONTROL => CONTROL1,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3,
TRIG4 => TRIG_ILA1_4
);
TRIG_ILA1_0(0) <= dsp_clk_ce_1;
TRIG_ILA1_0(1) <= dsp_clk_ce_35;
TRIG_ILA1_0(2) <= dsp_clk_ce_1112;
TRIG_ILA1_0(3) <= dsp_clk_ce_1390000; -- not used
TRIG_ILA1_0(4) <= dsp_clk_ce_2780000;
TRIG_ILA1_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA1_0(7 downto 6) <= (others => '0');
--TRIG_ILA1_1(dsp_bpf_ch0'range) <= dsp_bpf_ch0;
--TRIG_ILA1_2(dsp_bpf_ch2'range) <= dsp_bpf_ch2;
--TRIG_ILA1_1(dsp_poly35_ch0'range) <= dsp_poly35_ch0;
--TRIG_ILA1_2(dsp_poly35_ch2'range) <= dsp_poly35_ch2;
--TRIG_ILA1_3(dsp_cic_fofb_ch0'range) <= dsp_cic_fofb_ch0;
--TRIG_ILA1_4(dsp_cic_fofb_ch2'range) <= dsp_cic_fofb_ch2;
TRIG_ILA1_1(dsp_monit_amp_ch0'range) <= dsp_monit_amp_ch0;
TRIG_ILA1_2(dsp_monit_amp_ch1'range) <= dsp_monit_amp_ch1;
TRIG_ILA1_3(dsp_monit_amp_ch2'range) <= dsp_monit_amp_ch2;
TRIG_ILA1_4(dsp_monit_amp_ch3'range) <= dsp_monit_amp_ch3;
TRIG_ILA1_4(dsp_monit_amp_ch3'left+3 downto
dsp_monit_amp_ch3'left+1) <= dsp_monit_cic_unexpected &
dsp_monit_cfir_incorrect &
dsp_monit_pfir_incorrect;
-- TBT amplitudes data
cmp_chipscope_ila_8192_tbt_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL2,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3,
TRIG4 => TRIG_ILA2_4
);
TRIG_ILA2_0(0) <= dsp_clk_ce_1;
TRIG_ILA2_0(1) <= dsp_clk_ce_35;
TRIG_ILA2_0(2) <= dsp_clk_ce_1112;
TRIG_ILA2_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA2_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA2_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA2_0(7 downto 6) <= (others => '0');
TRIG_ILA2_1(dsp_tbt_amp_ch0'range) <= dsp_tbt_amp_ch0;
TRIG_ILA2_2(dsp_tbt_amp_ch1'range) <= dsp_tbt_amp_ch1;
TRIG_ILA2_3(dsp_tbt_amp_ch2'range) <= dsp_tbt_amp_ch2;
TRIG_ILA2_4(dsp_tbt_amp_ch3'range) <= dsp_tbt_amp_ch3;
TRIG_ILA2_4(dsp_tbt_amp_ch3'left+2 downto
dsp_tbt_amp_ch3'left+1) <= dsp_tbt_decim_q_ch01_incorrect &
dsp_tbt_decim_q_ch23_incorrect;
-- TBT position data
cmp_chipscope_ila_8192_tbt_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL3,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3,
TRIG4 => TRIG_ILA3_4
);
TRIG_ILA3_0(0) <= dsp_clk_ce_1;
TRIG_ILA3_0(1) <= dsp_clk_ce_35;
TRIG_ILA3_0(2) <= dsp_clk_ce_1112;
TRIG_ILA3_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA3_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA3_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA3_0(7 downto 6) <= (others => '0');
TRIG_ILA3_1(dsp_x_tbt'range) <= dsp_x_tbt;
TRIG_ILA3_2(dsp_y_tbt'range) <= dsp_y_tbt;
TRIG_ILA3_3(dsp_q_tbt'range) <= dsp_q_tbt;
TRIG_ILA3_4(dsp_sum_tbt'range) <= dsp_sum_tbt;
-- FOFB amplitudes data
cmp_chipscope_ila_8192_fofb_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL4,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA4_0,
TRIG1 => TRIG_ILA4_1,
TRIG2 => TRIG_ILA4_2,
TRIG3 => TRIG_ILA4_3,
TRIG4 => TRIG_ILA4_4
);
TRIG_ILA4_0(0) <= dsp_clk_ce_1;
TRIG_ILA4_0(1) <= dsp_clk_ce_35;
TRIG_ILA4_0(2) <= dsp_clk_ce_1112;
TRIG_ILA4_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA4_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA4_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA4_0(7 downto 6) <= (others => '0');
TRIG_ILA4_1(dsp_fofb_amp_ch0'range) <= dsp_fofb_amp_ch0;
TRIG_ILA4_2(dsp_fofb_amp_ch1'range) <= dsp_fofb_amp_ch1;
TRIG_ILA4_3(dsp_fofb_amp_ch2'range) <= dsp_fofb_amp_ch2;
TRIG_ILA4_4(dsp_fofb_amp_ch3'range) <= dsp_fofb_amp_ch3;
TRIG_ILA4_4(dsp_fofb_amp_ch3'left+2 downto
dsp_fofb_amp_ch3'left+1) <= dsp_fofb_decim_q_01_missing &
dsp_fofb_decim_q_23_missing;
-- FOFB position data
cmp_chipscope_ila_8192_fofb_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL5,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA5_0,
TRIG1 => TRIG_ILA5_1,
TRIG2 => TRIG_ILA5_2,
TRIG3 => TRIG_ILA5_3,
TRIG4 => TRIG_ILA5_4
);
TRIG_ILA5_0(0) <= dsp_clk_ce_1;
TRIG_ILA5_0(1) <= dsp_clk_ce_35;
TRIG_ILA5_0(2) <= dsp_clk_ce_1112;
TRIG_ILA5_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA5_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA5_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA5_0(7 downto 6) <= (others => '0');
TRIG_ILA5_1(dsp_x_fofb'range) <= dsp_x_fofb;
TRIG_ILA5_2(dsp_y_fofb'range) <= dsp_y_fofb;
TRIG_ILA5_3(dsp_q_fofb'range) <= dsp_q_fofb;
TRIG_ILA5_4(dsp_sum_fofb'range) <= dsp_sum_fofb;
-- Monitoring position data
cmp_chipscope_ila_8192_monit_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL6,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA6_0,
TRIG1 => TRIG_ILA6_1,
TRIG2 => TRIG_ILA6_2,
TRIG3 => TRIG_ILA6_3,
TRIG4 => TRIG_ILA6_4
);
TRIG_ILA6_0(0) <= dsp_clk_ce_1;
TRIG_ILA6_0(1) <= dsp_clk_ce_35;
TRIG_ILA6_0(2) <= dsp_clk_ce_1112;
TRIG_ILA6_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA6_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA6_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA6_0(7 downto 6) <= (others => '0');
TRIG_ILA6_1(dsp_x_monit'range) <= dsp_x_monit;
TRIG_ILA6_2(dsp_y_monit'range) <= dsp_y_monit;
TRIG_ILA6_3(dsp_q_monit'range) <= dsp_q_monit;
TRIG_ILA6_4(dsp_sum_monit'range) <= dsp_sum_monit;
end rtl;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : string(1 to 4) := "1234";
begin -- process
assert x'length = 4 report "TEST FAILED - x'length does not equal 4" severity failure;
assert x'length /= 4 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : string(1 to 4) := "1234";
begin -- process
assert x'length = 4 report "TEST FAILED - x'length does not equal 4" severity failure;
assert x'length /= 4 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : string(1 to 4) := "1234";
begin -- process
assert x'length = 4 report "TEST FAILED - x'length does not equal 4" severity failure;
assert x'length /= 4 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02935pkg is
procedure proc1 (i,l:integer; res: boolean);
end c02s02b00x00p07n03i02935pkg;
package body c02s02b00x00p07n03i02935pkg is
--ERROR : non-existent body for procedure proc1
end c02s02b00x00p07n03i02935pkg;
ENTITY c02s02b00x00p07n03i02935ent IS
END c02s02b00x00p07n03i02935ent;
ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02935arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02935pkg is
procedure proc1 (i,l:integer; res: boolean);
end c02s02b00x00p07n03i02935pkg;
package body c02s02b00x00p07n03i02935pkg is
--ERROR : non-existent body for procedure proc1
end c02s02b00x00p07n03i02935pkg;
ENTITY c02s02b00x00p07n03i02935ent IS
END c02s02b00x00p07n03i02935ent;
ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02935arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02935pkg is
procedure proc1 (i,l:integer; res: boolean);
end c02s02b00x00p07n03i02935pkg;
package body c02s02b00x00p07n03i02935pkg is
--ERROR : non-existent body for procedure proc1
end c02s02b00x00p07n03i02935pkg;
ENTITY c02s02b00x00p07n03i02935ent IS
END c02s02b00x00p07n03i02935ent;
ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02935arch;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
LED1 : out std_logic_vector(9 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
CLKFXDV_DIVIDE => 4,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
-- RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
LED1(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
LED1(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
LED1(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
LED1(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
LED1(4) <= C3_CALIB_DONE;
LED1(5) <= C3_RST0;
LED1(6) <= RESET0;
LED1(7) <= RESET;
LED1(8) <= '0';
LED1(9) <= '1';
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
LED1 : out std_logic_vector(9 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
CLKFXDV_DIVIDE => 4,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
-- RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
LED1(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
LED1(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
LED1(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
LED1(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
LED1(4) <= C3_CALIB_DONE;
LED1(5) <= C3_RST0;
LED1(6) <= RESET0;
LED1(7) <= RESET;
LED1(8) <= '0';
LED1(9) <= '1';
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
LED1 : out std_logic_vector(9 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
CLKFXDV_DIVIDE => 4,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
-- RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
LED1(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
LED1(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
LED1(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
LED1(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
LED1(4) <= C3_CALIB_DONE;
LED1(5) <= C3_RST0;
LED1(6) <= RESET0;
LED1(7) <= RESET;
LED1(8) <= '0';
LED1(9) <= '1';
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_asap_entity;
ARCHITECTURE ewf_asap_description OF ewf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register3 := register3 * 12;
output1 <= register6 + register4;
register2 := register2 * 15;
WHEN "00001001" =>
register3 := register1 + register3;
register2 := register2 + 17;
WHEN "00001010" =>
register1 := register1 + register3;
register4 := register5 + register3;
register5 := register6 + register2;
register6 := register2 + 19;
WHEN "00001011" =>
register1 := register1 * 21;
register4 := register4 + 23;
register5 := register5 + 25;
register6 := register6 * 27;
WHEN "00001100" =>
register1 := register1 + 29;
register7 := register4 * 31;
register8 := register5 * 33;
output2 <= register2 + register6;
WHEN "00001101" =>
output3 <= register3 + register1;
register1 := register7 + 37;
register2 := register8 + 39;
WHEN "00001110" =>
output4 <= register4 + register1;
output5 <= register5 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_asap_description; |
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.conversion.all;
entity dma_engine is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
start_dma : in std_logic; --enable receive DMA
--
--
--
address : out std_logic_vector(31 downto 0); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
--
--
--
mem_address : in std_logic_vector(31 downto 0); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic
);
end; --entity eth_dma
architecture logic of dma_engine is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal struc_ptr : std_logic_vector(31 downto 0);
SIGNAL dma_type : std_logic_vector( 7 DOWNTO 0);
SIGNAL ptr_src : std_logic_vector(31 downto 0);
SIGNAL ptr_src_2 : std_logic_vector(31 downto 0);
SIGNAL ptr_src_3 : std_logic_vector(31 downto 0);
SIGNAL ptr_dst : std_logic_vector(31 downto 0);
SIGNAL nWords : std_logic_vector(15 downto 0);
TYPE STATE_TYPE IS (waiting, nextS, addr_dma_type, read_dma_type, read_ptr_src, read_ptr_src_2, read_ptr_src_3, read_ptr_dst, read_nb_words, select_type, cpy_init_data, cpy_read_data, cpy_write_data, init_write_data, wait_one_cycle);
SIGNAL dma_state : STATE_TYPE;
CONSTANT INC_1_WORD : UNSIGNED(31 downto 0) := TO_UNSIGNED(4, 32);
begin --architecture
-- mem_address : in std_logic_vector(31 downto 2); --from CPU
-- mem_byte_we : in std_logic_vector(3 downto 0);
-- data_w : in std_logic_vector(31 downto 0);
-- pause_out : out std_logic
-- DMA CLEAR (0x00)
-- DMA COPY (0x01)
-- DMA XOR (0x02)
-- DMA F (0x03)
-- DMA G (0x04)
dma : process(reset, clk)
BEGIN
IF reset = '1' THEN
dma_state <= waiting;
dma_type <= ZERO( 7 downto 0);
ptr_src <= ZERO;
ptr_dst <= ZERO;
nWords <= ZERO(15 downto 0);
pause_out <= '0';
address <= ZERO;
byte_we <= "0000";
data_write <= ZERO;
ELSE
if CLK'event and CLK = '1' then
CASE dma_state IS
WHEN waiting =>
struc_ptr <= data_w(31 DOWNTO 0);
IF start_dma = '1' THEN
-- REPORT "STARTING DMA = " & to_hex_str( data_w );
dma_state <= nextS;
pause_out <= '1';
ELSE
dma_state <= waiting;
pause_out <= '0';
END IF;
address <= data_w(31 DOWNTO 0); -- ON POSITIONNE L'ADRESSE MEMOIRE
WHEN nextS =>
dma_state <= addr_dma_type;
pause_out <= '1';
WHEN addr_dma_type =>
-- REPORT "WRITING STRUCTURE ADDRESS";
pause_out <= '1';
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
byte_we <= "0000"; -- DE LA STRUCTURE CONTENANT LA
dma_state <= read_dma_type; -- REQUETE DMA
WHEN read_dma_type =>
-- REPORT "READING DMA TYPE = " & to_hex_str( data_read );
pause_out <= '1';
dma_type <= data_read( 7 DOWNTO 0); -- ON MEMORISE LE
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000000" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src; -- NEXT STATE
END IF;
WHEN read_ptr_src =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000001" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_2 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_2 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000010" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_3 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_3 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_ptr_dst; -- NEXT STATE
WHEN read_ptr_dst =>
-- REPORT "READING DST POINTER = " & to_hex_str( data_read );
ptr_dst <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_nb_words; -- NEXT STATE
WHEN read_nb_words =>
-- REPORT "READING NB WORDS = " & to_hex_str( data_read );
nWords <= data_read(15 DOWNTO 0); --
byte_we <= "0000"; --
dma_state <= select_type; -- NEXT STATE
WHEN select_type =>
-- REPORT "SELECTING DMA OPERATION";
IF dma_type = "00000000" THEN
dma_state <= init_write_data;
ELSE
dma_state <= cpy_init_data;
END IF;
-----------------------------------------------------------
-- on demande la donnee 0
WHEN cpy_init_data =>
REPORT "PROCESSING cpy_init_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
byte_we <= "0000"; -- TYPE DE LA REQUETE +
dma_state <= cpy_read_data;
-- on demande la donnee 1
WHEN cpy_read_data =>
REPORT "PROCESSING cpy_read_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) );
data_write <= data_read;
byte_we <= "0000";
dma_state <= cpy_write_data;
-- on ecrit la donnee 0
WHEN cpy_write_data =>
REPORT "PROCESSING cpy_write_data to " & to_hex_str( ptr_dst ) & " data_read = " & to_hex_str( data_read );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
-- data_write <= ZERO;
byte_we <= "1111"; -- TYPE DE LA REQUETE +
-- On decompte ...
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= cpy_read_data; -- NEXT STATE
END IF;
-----------------------------------------------------------
WHEN init_write_data =>
-- REPORT "PROCESSING init_write_data " & to_hex_str( ptr_dst ) & " - " & to_hex_str( nWords );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
byte_we <= "1111"; -- TYPE DE LA REQUETE +
pause_out <= '1';
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= init_write_data; -- NEXT STATE
END IF;
WHEN wait_one_cycle =>
-- REPORT "PROCESSING wait_one_cycle";
byte_we <= "0000"; -- TYPE DE LA REQUETE +
pause_out <= '0';
dma_state <= waiting; -- NEXT STATE
END CASE;
END IF;
END IF;
END process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.conversion.all;
entity dma_engine is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
start_dma : in std_logic; --enable receive DMA
--
--
--
address : out std_logic_vector(31 downto 0); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
--
--
--
mem_address : in std_logic_vector(31 downto 0); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic
);
end; --entity eth_dma
architecture logic of dma_engine is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal struc_ptr : std_logic_vector(31 downto 0);
SIGNAL dma_type : std_logic_vector( 7 DOWNTO 0);
SIGNAL ptr_src : std_logic_vector(31 downto 0);
SIGNAL ptr_src_2 : std_logic_vector(31 downto 0);
SIGNAL ptr_src_3 : std_logic_vector(31 downto 0);
SIGNAL ptr_dst : std_logic_vector(31 downto 0);
SIGNAL nWords : std_logic_vector(15 downto 0);
TYPE STATE_TYPE IS (waiting, nextS, addr_dma_type, read_dma_type, read_ptr_src, read_ptr_src_2, read_ptr_src_3, read_ptr_dst, read_nb_words, select_type, cpy_init_data, cpy_read_data, cpy_write_data, init_write_data, wait_one_cycle);
SIGNAL dma_state : STATE_TYPE;
CONSTANT INC_1_WORD : UNSIGNED(31 downto 0) := TO_UNSIGNED(4, 32);
begin --architecture
-- mem_address : in std_logic_vector(31 downto 2); --from CPU
-- mem_byte_we : in std_logic_vector(3 downto 0);
-- data_w : in std_logic_vector(31 downto 0);
-- pause_out : out std_logic
-- DMA CLEAR (0x00)
-- DMA COPY (0x01)
-- DMA XOR (0x02)
-- DMA F (0x03)
-- DMA G (0x04)
dma : process(reset, clk)
BEGIN
IF reset = '1' THEN
dma_state <= waiting;
dma_type <= ZERO( 7 downto 0);
ptr_src <= ZERO;
ptr_dst <= ZERO;
nWords <= ZERO(15 downto 0);
pause_out <= '0';
address <= ZERO;
byte_we <= "0000";
data_write <= ZERO;
ELSE
if CLK'event and CLK = '1' then
CASE dma_state IS
WHEN waiting =>
struc_ptr <= data_w(31 DOWNTO 0);
IF start_dma = '1' THEN
-- REPORT "STARTING DMA = " & to_hex_str( data_w );
dma_state <= nextS;
pause_out <= '1';
ELSE
dma_state <= waiting;
pause_out <= '0';
END IF;
address <= data_w(31 DOWNTO 0); -- ON POSITIONNE L'ADRESSE MEMOIRE
WHEN nextS =>
dma_state <= addr_dma_type;
pause_out <= '1';
WHEN addr_dma_type =>
-- REPORT "WRITING STRUCTURE ADDRESS";
pause_out <= '1';
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
byte_we <= "0000"; -- DE LA STRUCTURE CONTENANT LA
dma_state <= read_dma_type; -- REQUETE DMA
WHEN read_dma_type =>
-- REPORT "READING DMA TYPE = " & to_hex_str( data_read );
pause_out <= '1';
dma_type <= data_read( 7 DOWNTO 0); -- ON MEMORISE LE
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000000" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src; -- NEXT STATE
END IF;
WHEN read_ptr_src =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000001" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_2 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_2 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000010" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_3 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_3 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_ptr_dst; -- NEXT STATE
WHEN read_ptr_dst =>
-- REPORT "READING DST POINTER = " & to_hex_str( data_read );
ptr_dst <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_nb_words; -- NEXT STATE
WHEN read_nb_words =>
-- REPORT "READING NB WORDS = " & to_hex_str( data_read );
nWords <= data_read(15 DOWNTO 0); --
byte_we <= "0000"; --
dma_state <= select_type; -- NEXT STATE
WHEN select_type =>
-- REPORT "SELECTING DMA OPERATION";
IF dma_type = "00000000" THEN
dma_state <= init_write_data;
ELSE
dma_state <= cpy_init_data;
END IF;
-----------------------------------------------------------
-- on demande la donnee 0
WHEN cpy_init_data =>
REPORT "PROCESSING cpy_init_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
byte_we <= "0000"; -- TYPE DE LA REQUETE +
dma_state <= cpy_read_data;
-- on demande la donnee 1
WHEN cpy_read_data =>
REPORT "PROCESSING cpy_read_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) );
data_write <= data_read;
byte_we <= "0000";
dma_state <= cpy_write_data;
-- on ecrit la donnee 0
WHEN cpy_write_data =>
REPORT "PROCESSING cpy_write_data to " & to_hex_str( ptr_dst ) & " data_read = " & to_hex_str( data_read );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
-- data_write <= ZERO;
byte_we <= "1111"; -- TYPE DE LA REQUETE +
-- On decompte ...
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= cpy_read_data; -- NEXT STATE
END IF;
-----------------------------------------------------------
WHEN init_write_data =>
-- REPORT "PROCESSING init_write_data " & to_hex_str( ptr_dst ) & " - " & to_hex_str( nWords );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
byte_we <= "1111"; -- TYPE DE LA REQUETE +
pause_out <= '1';
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= init_write_data; -- NEXT STATE
END IF;
WHEN wait_one_cycle =>
-- REPORT "PROCESSING wait_one_cycle";
byte_we <= "0000"; -- TYPE DE LA REQUETE +
pause_out <= '0';
dma_state <= waiting; -- NEXT STATE
END CASE;
END IF;
END IF;
END process;
end; --architecture logic
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2017 12:34:40 AM
-- Design Name:
-- Module Name: AudioEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AudioEcho is
port (
led : out std_logic_vector(3 downto 0); -- Pretty light show for debugging stuff
clk_125 : in std_logic; -- 125 MHz Zybo clock
ac_sda : inout std_logic; -- I2C data
ac_scl : inout std_logic -- I2C clock
);
end AudioEcho;
architecture Driver of AudioEcho is
signal led_st : std_logic_vector(3 downto 0) := "0000"; -- output register for leds
subtype tCount is unsigned(31 downto 0); -- type alias: 32-bit unsigned integer
constant cZero : tCount := to_unsigned(0,tCount'length); -- zero constant
constant cMod : tCount := to_unsigned(2,tCount'length); -- 2/cMod is divider period in seconds
constant cMax : tCount := to_unsigned(125000000,tCount'length); -- input clock frequency constant
signal my_clk : std_logic := '0'; -- divider output
signal r_sda_i : std_logic := '1'; -- I2C sda input register
signal r_sda_o : std_logic := '1'; -- I2C sda output register
signal r_scl_i : std_logic := '1'; -- I2C scl input register
signal r_scl_o : std_logic := '1'; -- I2C scl output register
-- enumeration of audio configuration state machine states
type ac_states is (
acsInit,
acsStart,
acsA7pre,
acsA7set,
acsA7out,
acsA6pre,
acsA6set,
acsA6out,
acsA5pre,
acsA5set,
acsA5out,
acsA4pre,
acsA4set,
acsA4out,
acsA3pre,
acsA3set,
acsA3out,
acsA2pre,
acsA2set,
acsA2out,
acsA1pre,
acsA1set,
acsA1out,
acsWpre,
acsWset,
acsWout,
acsWACKpre,
acsWACKfloat,
acsWACKclk,
acsWACKtest,
acsStop,
acsForceStop,
acsForceStop2,
acsForceStop3,
acsSpin
);
signal ac_state : ac_states := acsInit;
signal ac_good : std_logic := '0';
begin
-- clock divider
divider: process(clk_125) is
variable dCur : tCount := cZero;
begin
if (rising_edge(clk_125)) then
dCur:=dCur+cMod;
if (dCur >= cMax) then
dCur := dCur - cMax;
my_clk <= not my_clk;
end if;
end if;
end process divider;
-- state machine for I2C
audioconf : process(my_clk) is
begin
-- NB: On the Zybo board only two slaves (EEPROM and SSM2603)
-- are present on the I2C bus thus we are the only master
-- in the system thus there is no need for arbitration logic.
if (rising_edge(my_clk)) then
case ac_state is
-- Initial state
when acsInit =>
-- Use a counter to pause the minimum initialization
-- duration before transitioning to starting condition.
ac_state <= acsStart;
-- Starting condition
when acsStart =>
if (r_scl_i='1' and r_sda_i='1') then
-- signal START on the bus
r_sda_o<='0';
ac_state <= acsA7pre;
else
-- still waiting for SCL=1 and SDA=1
ac_state <= acsStart;
end if;
-- each bit sent takes three states
-- since for I2C it is required to transition SDA
-- *after* the SCL low edge and not at the same
-- time (a device might register SDA before our
-- clock in that event and misinterpret a STOP
-- signal if SDA becomes 1 on this cycle when SDA
-- was 0 on the previous cycle since we'd have
-- set SCL to 1 to transmit that bit).
when acsA7pre => -- Call SSM2603 address for write (R=1, W=0):
r_scl_o<='0'; -- 0 0 1 1 0 1 0 W
ac_state<=acsA7set;
when acsA7set =>
r_sda_o<='0'; -- 0
ac_state<=acsA7out;
when acsA7out =>
r_scl_o<='1';
ac_state <= acsA6pre;
when acsA6pre =>
r_scl_o<='0';
ac_state<=acsA6set;
when acsA6set =>
r_sda_o<='0'; -- - 0
ac_state<=acsA6out;
when acsA6out =>
r_scl_o<='1';
ac_state <= acsA5pre;
when acsA5pre =>
r_scl_o<='0';
ac_state<=acsA5set;
when acsA5set =>
r_sda_o<='1'; -- - - 1
ac_state<=acsA5out;
when acsA5out =>
r_scl_o<='1';
ac_state <= acsA4pre;
when acsA4pre =>
r_scl_o<='0';
ac_state<=acsA4set;
when acsA4set =>
r_sda_o<='1'; -- - - - 1
ac_state<=acsA4out;
when acsA4out =>
r_scl_o<='1';
ac_state <= acsA3pre;
when acsA3pre =>
r_scl_o<='0';
ac_state<=acsA3set;
when acsA3set =>
r_sda_o<='0'; -- - - - - 0
ac_state<=acsA3out;
when acsA3out =>
r_scl_o<='1';
ac_state <= acsA2pre;
when acsA2pre =>
r_scl_o<='0';
ac_state<=acsA2set;
when acsA2set =>
r_sda_o<='1'; -- - - - - - 1
ac_state<=acsA2out;
when acsA2out =>
r_scl_o<='1';
ac_state <= acsA1pre;
when acsA1pre =>
r_scl_o<='0';
ac_state<=acsA1set;
when acsA1set =>
r_sda_o<='0'; -- - - - - - - 0
ac_state<=acsA1out;
when acsA1out =>
r_scl_o<='1';
ac_state <= acsWpre;
when acsWpre =>
r_scl_o<='0';
ac_state<=acsWset;
when acsWset =>
r_sda_o<='0'; -- - - - - - - - W
ac_state<=acsWout;
when acsWout =>
r_scl_o<='1';
ac_state <= acsWACKpre;
-- On the ackknowledge there's a similar pattern
-- first we'll lower the clock THEN float SDA
-- THEN raise the clock THEN test SDA for
-- ACK/NACK. THENs mean delay is necessary
-- thus requiring a different state for each
-- step so they span different clock cycles
when acsWACKpre =>
r_scl_o<='0'; -- lower clock
ac_state<=acsWACKfloat;
when acsWACKfloat =>
r_sda_o<='1'; -- SDA floats to 1
ac_state<=acsWACKclk;
when acsWACKclk =>
r_scl_o<='1'; -- raise clock
ac_state<=acsWACKtest;
when acsWACKtest =>
-- if all is right SDA should be low at this point
if (r_sda_i='0') then
ac_good<='1';
end if;
ac_state<=acsForceStop;
-- forcibly stop:
-- lower SCL
-- lower SDA
-- raise SCL
-- raise SDA
when acsForceStop =>
r_scl_o<='0';
ac_state <= acsForceStop2;
when acsForceStop2 =>
r_sda_o<='0';
ac_state <= acsForceStop3;
when acsForceStop3 =>
r_scl_o<='1';
ac_state <= acsStop;
when acsStop =>
r_sda_o<='1';
ac_state <= acsSpin;
-- Halted (infinite loop)
when acsSpin =>
ac_state <= acsSpin;
-- Catch-all: enter halted state
when others =>
ac_state <= acsSpin;
end case;
end if;
end process audioconf;
-- i2c output registers to i2c lines
with r_sda_o select
ac_sda <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
with r_scl_o select
ac_scl <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
-- i2c lines to i2c input registers
with ac_sda select
r_sda_i <= '0' when '0',
'1' when others;
with ac_scl select
r_scl_i <= '0' when '0',
'1' when others;
-- transfer led output register to led output lines
led_st(0) <= r_sda_i;
led_st(1) <= r_scl_i;
led_st(2) <= ac_good;
led_st(3) <= my_clk;
led <= led_st;
end Driver; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2100.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02100ent IS
END c07s02b04x00p20n01i02100ent;
ARCHITECTURE c07s02b04x00p20n01i02100arch OF c07s02b04x00p20n01i02100ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : record_4;
variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
variable r_operand : record_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***PASSED TEST: c07s02b04x00p20n01i02100"
severity NOTE;
assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***FAILED TEST: c07s02b04x00p20n01i02100 - Concatenation of null and RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2100.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02100ent IS
END c07s02b04x00p20n01i02100ent;
ARCHITECTURE c07s02b04x00p20n01i02100arch OF c07s02b04x00p20n01i02100ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : record_4;
variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
variable r_operand : record_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***PASSED TEST: c07s02b04x00p20n01i02100"
severity NOTE;
assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***FAILED TEST: c07s02b04x00p20n01i02100 - Concatenation of null and RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2100.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02100ent IS
END c07s02b04x00p20n01i02100ent;
ARCHITECTURE c07s02b04x00p20n01i02100arch OF c07s02b04x00p20n01i02100ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : record_4;
variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
variable r_operand : record_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***PASSED TEST: c07s02b04x00p20n01i02100"
severity NOTE;
assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
report "***FAILED TEST: c07s02b04x00p20n01i02100 - Concatenation of null and RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02100arch;
|
-- File name: aes_top.vhd
-- Created: 2009-04-04
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES top level
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aes_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte;
got_key : in std_logic;
got_pt : in std_logic;
send_ct : in std_logic;
aes_done : out std_logic;
tx_data : out byte
);
end entity aes_top;
architecture structural of aes_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal num_shifts : index;
signal filtered : slice;
signal round_num : round_type;
signal round_key : key_type;
signal sub_bytes_out : byte;
signal shift_rows_out : row;
signal mix_columns_out : col;
signal add_round_key_out : byte;
signal filtered_key : byte;
signal start_key : std_logic;
signal key_done : std_logic;
signal ks_sbox_lookup : byte;
signal key_load : std_logic;
signal ks_sbox_return : byte;
begin
state_b : entity work.state(dataflow) port map (
clk => clk, state_d => state_d, state_q => state_q
);
state_filter_in_b : entity work.state_filter_in(behavioral) port map (
s => state_q, subblock => subblock, i => i, d_out => filtered,
filtered_key => filtered_key, round_key => round_key
);
state_filter_out_b : entity work.state_filter_out(mux) port map (
current_state => state_q, sub_bytes_out => sub_bytes_out,
shift_rows_out => shift_rows_out, mix_columns_out => mix_columns_out,
add_round_key_out => add_round_key_out, load_out => rx_data,
subblock => subblock, i => i, next_state => state_d
);
sub_bytes_b : entity work.sbox(dataflow) port map (
clk => clk, a => filtered(0), b => sub_bytes_out
);
num_shifts <= i mod 4;
shift_rows_b : entity work.shift_rows(dataflow) port map (
data_in => filtered, num_shifts => num_shifts,
data_out => shift_rows_out
);
mix_columns_b : entity work.mix_columns(behavioral) port map (
d_in => filtered, d_out => mix_columns_out
);
add_round_key_b : entity work.add_round_key(dataflow) port map (
data_in => filtered(0), key_in => filtered_key,
data_out => add_round_key_out
);
aes_rcu_b : entity work.aes_rcu(behavioral) port map (
clk => clk, nrst => nrst, p => i, subblock => subblock,
current_round => round_num, start_key => start_key,
key_done => key_done, key_load => key_load,
got_key => got_key, got_pt => got_pt, aes_done => aes_done,
send_ct => send_ct
);
key_scheduler_b : entity work.key_scheduler(behavioral) port map (
clk => clk, nrst => nrst, round => round_num,
round_key => round_key, go => start_key, done => key_done,
key_data => rx_data, key_index => i, key_load => key_load
);
tx_data <= filtered(0);
end architecture structural;
architecture structural_p of aes_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal round_num : round_type;
signal round_key : key_type;
signal sub_bytes_out : state_type;
signal shift_rows_out : state_type;
signal mix_columns_out : state_type;
signal add_round_key_out : state_type;
signal start_key : std_logic;
signal key_done : std_logic;
signal ks_sbox_lookup : byte;
signal key_load : std_logic;
signal ks_sbox_return : byte;
begin
state_b : entity work.state(dataflow) port map (
clk => clk, state_d => state_d, state_q => state_q
);
state_filter_out_p_b : entity work.state_filter_out_p(mux) port map (
current_state => state_q, sub_bytes_out => sub_bytes_out,
shift_rows_out => shift_rows_out, mix_columns_out => mix_columns_out,
add_round_key_out => add_round_key_out, load_out => rx_data,
subblock => subblock, i => i, next_state => state_d
);
sub_bytes_p_b : entity work.sub_bytes_p(structural) port map (
d_in => state_q, d_out => sub_bytes_out
);
shift_rows_p_b : entity work.shift_rows_p(behavioral) port map (
d_in => state_q, d_out => shift_rows_out
);
mix_columns_p_b : entity work.mix_columns_p(behavioral) port map (
d_in => state_q, d_out => mix_columns_out
);
add_round_key_p_b : entity work.add_round_key_p(dataflow) port map (
data_in => state_q, key_in => round_key,
data_out => add_round_key_out
);
aes_rcu_b : entity work.aes_rcu(behavioral_p) port map (
clk => clk, nrst => nrst, p => i, subblock => subblock,
current_round => round_num, start_key => start_key,
key_done => key_done, key_load => key_load,
got_key => got_key, got_pt => got_pt, aes_done => aes_done,
send_ct => send_ct
);
key_scheduler_p_b : entity work.key_scheduler(behavioral_p) port map (
clk => clk, nrst => nrst, round => round_num,
round_key => round_key, go => start_key, done => key_done,
key_data => rx_data, key_index => i, key_load => key_load
);
tx_data <= state_q(i mod 4, i / 4);
end architecture structural_p;
|
library ieee;
use ieee.std_logic_1164.all;
entity repro4 is
generic (
num : natural := 1);
port (
clk : std_logic;
o : out std_logic);
end;
architecture behav of repro4 is
signal s : natural range 0 to num - 1 := 0;
begin
process (clk) is
begin
if rising_edge(clk) then
if s = 0 then
o <= '1';
else
o <= '0';
end if;
if s = num - 1 then
s <= 0;
else
s <= s + 1;
end if;
end if;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_4_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_4_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_4_e
--
architecture rtl of inst_shadow_4_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.