content stringlengths 1 1.04M ⌀ |
|---|
-- debouncer - switch debouncer logic written in vhdl
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity debouncer is
generic (
CLOCK_RATE_HZ : positive := 50000000;
SETTLING_TIME_MS : positive := 10
);
port (
clock : in std_logic;
input : in std_logic;
output : out std_logic := '0'
);
end debouncer;
architecture rtl of debouncer is
constant max : integer := (CLOCK_RATE_HZ * SETTLING_TIME_MS) / 1000;
signal cnt : integer range 0 to max := 0;
signal last : std_logic;
begin
process (clock)
begin
if rising_edge(clock) then
last <= input;
if input = last then
if cnt = max then
output <= input;
else
cnt <= cnt + 1;
end if;
else
cnt <= 0;
end if;
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_sig is
end entity cond_assign_sig ;
architecture doit of cond_assign_sig is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
begin
Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_sig is
end entity cond_assign_sig ;
architecture doit of cond_assign_sig is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
begin
Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
architecture RTl of FIFO is
component fifo is
port (
a : in std_logic
);
end component fifo;
-- Failures below
component fifo is
port (
a : in std_logic
);
end component fifo;
component fifo is
port (
a : in std_logic
);
end component fifo;
begin
end architecture RTL;
|
package TEST is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end TEST;
use WORK.TEST;
entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
constant init_event : TEST.EVENT_TYPE := TEST.EVENT_1; -- OK
begin
end MODEL;
-------------------------------------------------------------------------------
package p1 is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end package;
package p2 is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end package;
use work.p1.all;
use work.p2.all;
entity e is
end entity;
architecture a of e is
constant event1 : P1.EVENT_TYPE := P1.EVENT_1; -- OK
constant event2 : P2.EVENT_TYPE := P2.EVENT_1; -- OK
constant event3 : EVENT_TYPE := EVENT_1; -- Error
constant event4 : P1.EVENT_TYPE := P2.EVENT_1; -- Error
begin
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:33:18 07/09/2015
-- Design Name: zhuang
-- Module Name: F:/xilinx sie13.4/zhuangtaiji/fz.vhd
-- Project Name: zhuangtaiji
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: zhuang
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fz_vhd IS
END fz_vhd;
ARCHITECTURE behavior OF fz_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT zhuang
PORT(
read_wright : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
oe : OUT std_logic;
we : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL read_wright : std_logic := '0';
SIGNAL reset : std_logic := '1';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL oe : std_logic;
SIGNAL we : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: zhuang PORT MAP(
read_wright => read_wright,
reset => reset,
clk => clk,
oe => oe,
we => we
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 20 ns;
reset<='0';
for i in 1 to 100 loop
clk<=NOT clk;
wait for 20 ns;
clk<= NOT clk;
wait for 20 ns;
clk<= NOT clk;
wait for 10 ns;
read_wright<= NOT read_wright;
wait for 10 ns;
clk<= NOT clk;
wait for 20 ns;
clk<= NOT clk;
wait for 20 ns;
clk<= NOT clk;
read_wright<= NOT read_wright;
end loop;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
|
-- ======================================================================
-- CTR-AES
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity ctraes is
generic (
NONCE_WIDTH : natural range 64 to 96 := 96
);
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start ctr
nonce_i : in std_logic_vector(0 to NONCE_WIDTH-1); -- nonce
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity ctraes;
architecture rtl of ctraes is
signal s_aes_datain : std_logic_vector(data_i'range);
signal s_aes_dataout : std_logic_vector(data_o'range);
signal s_aes_key : std_logic_vector(key_i'range);
signal s_key : std_logic_vector(key_i'range);
signal s_nonce : std_logic_vector(nonce_i'range);
signal s_data_in : std_logic_vector(data_i'range);
signal s_counter : unsigned(0 to 127-NONCE_WIDTH);
begin
s_aes_key <= key_i when start_i = '1' else s_key;
s_aes_datain <= nonce_i & (s_counter'range => '0') when start_i = '1' else
s_nonce & std_logic_vector(s_counter);
data_o <= s_aes_dataout xor s_data_in;
inputreg : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_key <= (others => '0');
s_nonce <= (others => '0');
s_data_in <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_data_in <= data_i;
if (start_i = '1') then
s_key <= key_i;
s_nonce <= nonce_i;
end if;
end if;
end if;
end process inputreg;
counterreg : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_counter <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
if (start_i = '1') then
s_counter <= (others => '0');
s_counter(s_counter'high) <= '1';
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process counterreg;
i_aes_enc : entity work.aes_enc
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => s_aes_key,
data_i => s_aes_datain,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_aes_dataout,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
-- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
--constant CNT01 : std_logic_vector := x"1458"; --16 Bit
--constant CNT02 : std_logic_vector := x"2C98"; --usw.
--constant CNT03 : std_logic_vector := x"3D08";
--constant CNT04 : std_logic_vector := x"5160";
--constant CNT05 : std_logic_vector := x"65B8";
--constant CNT06 : std_logic_vector := x"7A10";
--constant CNT07 : std_logic_vector := x"8E68";
--constant CNT08 : std_logic_vector := x"A2C0";
--constant CNT09 : std_logic_vector := x"B718";
--constant CNT10 : std_logic_vector := x"CB70";
--Konstanten, lang 19200 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNT02 : std_logic_vector := x"1458"; --usw.
constant CNT03 : std_logic_vector := x"1E84";
constant CNT04 : std_logic_vector := x"28B0";
constant CNT05 : std_logic_vector := x"32DC";
constant CNT06 : std_logic_vector := x"3D09";
constant CNT07 : std_logic_vector := x"4735";
constant CNT08 : std_logic_vector := x"5161";
constant CNT09 : std_logic_vector := x"5B8D";
constant CNT10 : std_logic_vector := x"65B9";
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral; |
-- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
--constant CNT01 : std_logic_vector := x"1458"; --16 Bit
--constant CNT02 : std_logic_vector := x"2C98"; --usw.
--constant CNT03 : std_logic_vector := x"3D08";
--constant CNT04 : std_logic_vector := x"5160";
--constant CNT05 : std_logic_vector := x"65B8";
--constant CNT06 : std_logic_vector := x"7A10";
--constant CNT07 : std_logic_vector := x"8E68";
--constant CNT08 : std_logic_vector := x"A2C0";
--constant CNT09 : std_logic_vector := x"B718";
--constant CNT10 : std_logic_vector := x"CB70";
--Konstanten, lang 19200 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNT02 : std_logic_vector := x"1458"; --usw.
constant CNT03 : std_logic_vector := x"1E84";
constant CNT04 : std_logic_vector := x"28B0";
constant CNT05 : std_logic_vector := x"32DC";
constant CNT06 : std_logic_vector := x"3D09";
constant CNT07 : std_logic_vector := x"4735";
constant CNT08 : std_logic_vector := x"5161";
constant CNT09 : std_logic_vector := x"5B8D";
constant CNT10 : std_logic_vector := x"65B9";
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral; |
-- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
--constant CNT01 : std_logic_vector := x"1458"; --16 Bit
--constant CNT02 : std_logic_vector := x"2C98"; --usw.
--constant CNT03 : std_logic_vector := x"3D08";
--constant CNT04 : std_logic_vector := x"5160";
--constant CNT05 : std_logic_vector := x"65B8";
--constant CNT06 : std_logic_vector := x"7A10";
--constant CNT07 : std_logic_vector := x"8E68";
--constant CNT08 : std_logic_vector := x"A2C0";
--constant CNT09 : std_logic_vector := x"B718";
--constant CNT10 : std_logic_vector := x"CB70";
--Konstanten, lang 19200 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNT02 : std_logic_vector := x"1458"; --usw.
constant CNT03 : std_logic_vector := x"1E84";
constant CNT04 : std_logic_vector := x"28B0";
constant CNT05 : std_logic_vector := x"32DC";
constant CNT06 : std_logic_vector := x"3D09";
constant CNT07 : std_logic_vector := x"4735";
constant CNT08 : std_logic_vector := x"5161";
constant CNT09 : std_logic_vector := x"5B8D";
constant CNT10 : std_logic_vector := x"65B9";
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral; |
-- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
--constant CNT01 : std_logic_vector := x"1458"; --16 Bit
--constant CNT02 : std_logic_vector := x"2C98"; --usw.
--constant CNT03 : std_logic_vector := x"3D08";
--constant CNT04 : std_logic_vector := x"5160";
--constant CNT05 : std_logic_vector := x"65B8";
--constant CNT06 : std_logic_vector := x"7A10";
--constant CNT07 : std_logic_vector := x"8E68";
--constant CNT08 : std_logic_vector := x"A2C0";
--constant CNT09 : std_logic_vector := x"B718";
--constant CNT10 : std_logic_vector := x"CB70";
--Konstanten, lang 19200 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNT02 : std_logic_vector := x"1458"; --usw.
constant CNT03 : std_logic_vector := x"1E84";
constant CNT04 : std_logic_vector := x"28B0";
constant CNT05 : std_logic_vector := x"32DC";
constant CNT06 : std_logic_vector := x"3D09";
constant CNT07 : std_logic_vector := x"4735";
constant CNT08 : std_logic_vector := x"5161";
constant CNT09 : std_logic_vector := x"5B8D";
constant CNT10 : std_logic_vector := x"65B9";
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end entity wb_master_p_to_slave_np;
architecture behave of wb_master_p_to_slave_np is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
signal wo: wb_mosi_type;
begin
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
state <= idle;
mwbo.stall <= '0';
wo.cyc<='0';
else
case state is
when idle =>
if mwbi.cyc='1' and mwbi.stb='1' then
state <= wait_for_ack;
wo <= mwbi;
mwbo.stall <= '1';
end if;
when wait_for_ack =>
if swbi.ack='1' or swbi.err='1' then
wo.cyc <= '0';
wo.stb <= '0';
mwbo.stall <= '0';
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
swbo.stb <= wo.stb;-- when state=idle else '1';
swbo.dat <= wo.dat;
swbo.adr <= wo.adr;
swbo.sel <= wo.sel;
swbo.tag <= wo.tag;
swbo.we <= wo.we;
swbo.cyc <= wo.cyc;
mwbo.dat <= swbi.dat;
mwbo.ack <= swbi.ack;
mwbo.err <= swbi.err;
mwbo.tag <= swbi.tag;
end behave;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JoebDWcYlkOHjvU2HKmRi2IPq2IKfzMyADf7ipQmnq6p1pyLMzSFTP7/1XG7M77HOVM3SXm9S+gQ
RlzcwV6biA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
k8vUULxueW9U9HcziM2PT8ceHNns3t7dzMLrZ8seoaB3Df8Aw/Ovx02qwDodcfaAe1Fwvpwa0wUi
PE+Pg6GkAtDElsf3YNizR5k5kMtCKENPRgHVaTWrSPbY8oeTfJUZWltxgCPQj5zwlFBQcfStGWIf
yrtaXeAZ+NdzXeZZyAE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
L/xMMRcKKAGVNmFjHVcsXDvECPTC4SN8TfnHM+LUOFOpNppp6SVz/TvXBvZHk4BJTGOf8HCvpqWr
b1t/WIlalCDTK5H+8vScdsSearVTAxauZI7OjMpsvbXLIUWdigqfacEdnuYVXKx12D9mDQCGIfJF
93o/xsOPIPRRrpS7RWGCtg/knXGuNaCNGbmNy+t9j+Eo1nyonSdY/0FlZqqMY4ZkSm2jCdx0cjBs
FiPnGHBZEeXCAoOxLXtzrVDuQYE207wj9wnKUvLBVg9CTtzWxClhQdbFIHF+3vbqbD/eyzso81dU
rvicTcxBlmUIuDFcJExuV3OjUabyI68YSYY1/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sARaWuxHivXyPa47+10U3MJstnjV4iU5AQbQxAOgIjmz9IVz2qCQ5udA4GXsCGUpRpP/kUqwdma
HPjRLjXKbF8bgOvEtPo0rt1bIFXIVWV73qTIOZqHDhYEQLw1uY9FfhslrS3GMt1eYFoYen3r1m8O
UrF+deTl5nqkO7p1UhY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sMa8/fGtZNcS7csY6TeRUT184AxeAxezcclVhHDC0qumeCFV4BCmqmBCX0ebxotImfwNdBzo9bED
CUh9TE6a7MvzZ0uAR8//DDHYUPH2llx4fYYEqkZdNtVDgbCNU8RgeeIUbsobqcloOKkZJPG6/tVu
dgJrJnvGdMbU/Wz2+1hxmfbwVRYpm9hxtyfoR+BIWNfJV/WlaD5XlRBWKUzHsLrD5PmQbyPqCXmq
AA+qetLtxPXUjRZmQr2QQgHXgTC9PCkIRL69zCeiy4b3vqNzZ1P0b0wZkX3RGP0tzBrZq8ftLC8p
LeONVXizO7QRClOpt/hUJADi7wnOB07MzObKwA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37088)
`protect data_block
wXzPBGPafsSCrAw/gav6XYVMUUPeH44+T02ep7By5B84eE32MM/nLGYt2ZZ92bAUkMaY9I3dOtCw
IqiRxfuxq5giklBdocF0tl8c89iS5Ngf1ZuvHFJd9oqmOljqQlTnz0uU2BYHR/9sKPIw51pXUoVp
lgd7terQvYq4bmSD2a0toJAGhDoPW4r3BCGa9mt4ZDgav7WcqjynOE7C/8SDAMs2ss3O0BCdltdU
VImOA0uIhSBo9xrK62+czx+hsrrC6R+NHeGO/Gh7bDOA1tvyShRNeHN92AQpCIomN3QNMORl6LMC
WtKKb7CfYTTwzNcPTHmisZzxynoSGFyn7vRQEewKS5yGcUJVVFs8Clz8YpHixL1Y9MINIRorPCwG
zFTAfNxt5x/UilpUWrYnv3wR4/HKUoHnDxumot8N5MlonHhKCNkc2DNfE36YbQC+2oJwSzR3K/ZP
dHx6uf176re7y9uOu0SW5x1GQrXyhxNTkc8qb7WMWo8YTIKWOH/zyo5mz3+u3Cj8SiNWDtu4UwCR
wJy0ezTFbdLhshpxQl7ze/e5K+9q3B9gIVLa9vMWEx8pk64IC0c0GlRd5bbWHCuq5QYxrXczkH0C
l6ZFf+sD7h+HLrWdkzfeF91zKO0OcRwDxRGpWy/wLETKnsKhFjUvG7LOaCWPrGLozi0Oqx4+QgHr
vN9Y/mPi9fhDiOlhg3D8xQQxbKmmAmP4bo0gbamA1xgbSnFLPY/Ce9WF+rYejQMEGUMTnHt0a16h
XfNNQI6Gl0e1oUlsbc792ualM68bTED9i0lMd+uI+/9ethU93xfutMWhgMAGllZTWhXXRlc0QkjW
1modRc8Grz14/e+za67vJuI4QivWoDnnXslyqn79du47HY76Wd9gEqVWm9ZrzZwhqX7KcBJbcBB5
8po4NFsqMsOTMBPgghLdRWNRD+G8SlhvsbfdzlZCaDjvaKuycifqc7ve2WLJX0xd2+mbb/SUyiH8
VNYPVl3phWSej2gEQlk7ftN6w49Y4eSW3foLJEW6e5krXkZEyCfJXLUgaHPReb5uYkYK95ssnoi8
nTfkyC6gxZCjN9ojOIey5/xODMKz6YgWTCiq5VFDVfTTVJ4VJ9qaorHHZW3sIXRXx0NW5WVUCN6p
5HsmHbMgahfNEu9V35Zg7BSDXbJ5VP3VjBBbLYvS/GMO92LF6w+bwlnzYtp2kwQfQYzgmxvRNlSW
CKGxqvqn9mrXrZ8vpmrPz9gn4k+p2eJaT6mhAojC5yen5or1Bs6Qu7eiKfRPRGUFfM0Yae9ylTOt
7xLzb9VDD3TPp4Qp6rly0dKH9z6knLXJ4XUBqNtLMtqFqK0oe0/j7xSsrL2ZRW3/LQoYPM9V4Mgz
jyoQrwklahCe8ie44ZsHADVLD0vRu5YRarpo9yY9AE+dkbEIhA0EOQSmYlXYBGgMvIVoatz8iJ+N
hgFbXcM6tyo/t996j7p2ONLxCSU6hXwvwT2wXT6OIm3WI6etU7V4I02Z1WzQ+x7Kv7a0ACp206B6
ZQhHS19HLKP90yE9SX93zNNMlY8DnfODHk6hDNF8tYqQUP75IX8q4abVwrLlrGlzCrkau0dQ2+hB
dHGG0K9mDhWfRsUBp2ZryMkQey05nePAZ+xZ/+Ymao5LxoALWNEre1jZLEoZGaEqcjL3RACou4s4
0FVAFCoycmdXg5va9Ss/BgKoJFNyDw0qZfVHfaJBxKCfei8bk9BM8V0fzkPQqsk4gUIJhGyC+zDK
buuVoedQInsByXm1+r6pWcqVt8roC11rRK/lXYjBvqbVsMJdzLwrfFnZLMWV9uqAuLGz77mUJQnT
cKjxOlEFlXUgaTs30DCEuNDymLNuBeZxnLmwby6vLlV3t0MXzCA1B3ynxPbkq8F0CgLxeDDtp4WF
HbR5I+rcepcBNjtweT9/a7wnffUD1hB/TklwYI17YhXDJeQ8n+DBjWJyFDBq2zME4062Qoaxvrny
JqY22aNeFKr/JIIbYp0GqXKPdWJ7DLihFtiIksecpzwTbiCxQJi8kC6ZQfvAxIyceRmC1DROLE0p
foB8VyFmZQhKrYhjuSFc7P/3ElCG3ghWJMus8WxdNhl5+eqmrE0+cPxt/PyzslQfS7fJiZ20i/4w
Bz4Yyqekw6IxRZb+k/+gpQONLggmGZCbNvs/8Fow+wx5kP8WzF4nSl8/ChFcALTU1xRTvtUGrgsz
/lrs27HgnFY2XJyhoeJmVj9uVnG7kcGELLejc3JNFHK8GGmK+rHkjt0IyzicoU8fOzHtoGzNFsYT
Nt16kRg2YaFsKawWE9gJb5Eu33J2NP7P3Ff30jW2Drs1o6Y4pbOvpMvdxiKfDTy8nt+OeO5TW0GK
B5E8HE8Jh9GKaxdcOy9dpbvY2y06FB1CHG6rpW2H/TGSZrRjsS/SKs/80gVEgKHww2x97jRpF8Cn
7Eiv9fD9cHd4BXDQ6kRFPip60MB5PY3VQwpUdeO7LeHpAEQbJqurNpb4ZkLGfaFGQwvCwTbBTvX3
a4Mo7YN7UFx4T/FteMNe0iSq4UpK35dP6Ut1hMHJZ53zojiwGOyT3Deyl1D8H9gBYNkCfpys7PN7
XHLivSXfIvyQJ/ZmQ/KKKR4VsS8/fa5RPGHLkBS18KW+MoZ2HHdLmjDUumPIKCH3b9Vifn0yYDur
PKVQngsvXhCNVzP88gE/78AJ5D3Tg7sjg3d9mWC9/xql9jBmqQTx0+s0owXlM8PKekDGZTGs4Xwt
B+H9LoyB9iWUzO+H3koUmFqwENZt7puOwJ8vwX3NnMeMWHZfQSWtRh10hmPap7M1n8x6DmsCEqaW
r6bAv8iB6OolLnf916g6JJycocFZCM8PeLF5r66kdNGGPOmPnvUNEz5iVQjAerRHnk0wMrLqPBAm
+qwat6tIQxc99kUAaQynW1u6n/kqoW55y2cfm4Pqrkj230XX1rzx4mnB2rhITinDpiwPFzjra4cI
0vLS6vBPuydQfbNCuCQ7RP5HRV/reJuJ+ITVHKvi8EQ5uEewKSF+DgatCDhQ8ftlO0BXK0QZEYJz
IvyEKqAoiuKIyjR7b1k6IUz75weQbmlunRrMjD1Jf6MH/OczSFuxUu7X8mxyXz2V6PconJP+8tUU
ge9fjBvUrYhuBCxYubxfZVCVNCAKwCqbaH2TmPh1h/nqdM5tLPFHWGKZcaKpwWDbxLzkykrLSDXW
AZ9ohXteU+mX3TPweajRfRc5R1QOQ/tzD01zIIEhKCuGdoXbX2UaPnGbiaRrdL5seGjlobZE8J6k
eBY0BXITCkHVNVKn9ycuMgt+OZq5BypsNGIbTClzAUU5fscvPq6s0d3xalhNLJVqTUrVWJGYGFkx
hnVhD+9aIhWcZ+bAFDBCqD1UnoRJEaxJ5wY80h+kgocadeNsxxXfYnmBj10aFLLiJIF21QwVjsbh
CgVJTIOgT/+RYlSr4K7EZqIy67ESSMGlYC8Lxcd+QdWbuLrYCuvL7M/ppTszKZsKjHDQa2RuK+/e
6nnt0ylTWE3OnMugaZk2X+7icLkcx+X+EOloRJJPgwH/JKEisWagulUsbIg2mn9LhhBkDfDffv33
kYq7stqcV7AWjxUE9yCQ8YP/NKtBtz6f8JbZZ/Y7+drG/8ag0Qj0IcjMUe3k683yfmkjzHGOvbOg
cp27qN44BdxEh6O9waPERrzfBJR79pa92g3zogjd3gFVZp9SFwcl7WRkXyFnP99sP81BW4hlD2hd
wnsYUfS5Pp380CgTRcHBISsaywlPSFOnAna8C1HbUNXJI8e2T0gH1pnj+A360zbkQALVQ6gKuIR1
LhgqEXa0ZxjQ9TlY1cdRlrrOp8Z2Lu5PyuAqF+eBWyMGyt1YmXa3Bmm4/+VyHlVBv7kiqSoJgrGR
jvukUZo0asYRiGh6Ru0rFEMO1ACRQ0nymv/Pla6KkTa9npwHRQaQS++7T7wljIa46keYllCEs8+I
TaX4Au+SGt7LCEHJ3QFxlY9y7n/oaqfvC7nFBvBI3Qg8/7w3MS3vPaRauXGVL1U6Xo+p/8wOk6cN
9AIgN78P8i1XnKEvC7MNOvCA391XL7cXun7QR1clxqSlO+viTNpfu5n9Blx5dNd3306z/HXaVtS3
7jYwjFO8EuU//Db7sOC2lvWoLylV+fgT4Joqya5rMJiSHt8EH7eHNy0HcTFyqFi+LpYinV+jkQII
h33aifK82rveL/a+UeeMjnO/mbXleWYVAqLEq1fUz+3W0MGEV8AoxMR6veibHnFmn5O9I73q6dVV
56T+n56PokQMCy+KtbF82K/2a61VJpf+E7AoaFN0xK+YgBgoafg0fqIKPpL2R4UyuMBAqhN9iHUq
peM5YZ6jkYerB9OSMZd3Wwh15EaEJhEfWY3ZI0lqRLebHSkYcqlJgG/0j/8KC6+GWN2d9ZKQSz1L
dvb9iSZNCRr6u24QrTO5WeGk9YoG+G8dLSnfjXY/4AU0avCebhGT759MEw5m7E6C2NrpaAuvC120
7G5M0MNfr+3egftrpK5/viPBnjLFqrbB9H/9loWfMhnEFHgFt926oVeSf8UcAFcNfzmuqRywUqd7
aJDeQ0bMR6GUe1jjwNr+kJ0DzjMP5fcKKum2XGLVkN+M0uzoGL9a33nFzPjLphjH3rHjuWE8mfed
s4O+iaGUH8ySvrrmv6632JZvmeu9u83Jgr/Cs2dTR07+1hufGONyS3u5gSsBvw9wsyaKSeERTffj
Eh8Y9PoQ4jbbYXMXDHNd8dj6D2aQStFB40XozVpwMGpqQRbYyTQcbWJQapOrYF1suckg/vbvxAyx
py/EUZxa/MputlAduaeHNCYsSM+ZC1LvcJRmhAqzBCyYZ1iqeu+m7+N3TiPjSMvPsHwl164p1qi7
fo6h5710Wzv8gCcHVjHTL2Hq3KfFNqMTnPUu1pp6cydxJIgD94tCbsrOhKDWWoy15Xvra4l0o2rc
4Xjb4ctyxtIEHwW9qpc1ujLSp7NljkCJAgBf5a4+5iszzgfKx1AuOE6B5iVRYMsYxEchTbCUAzNo
I5CMXpkobvgbB55zbzEmF/SeEIowXjZWtdd4PC7/bSiG/N9aaC8Bg1w1rNnIpZQKVvtgtfMVrA+1
oJQvEn1pDGk1ulBMCAMUzQy6nyNpfcFkZmaQ2Z/P2F5LFGa+TIyhIzeZq0IDdJUhJwdglrSrFGF6
Z49547t06jpGLImY9adNysusf1zOsSQiIq3hCSZly1WlaF1UEHAp4PkcPVVdu+JikqkH2eOU5n0e
9WZ7CRXWlcFv+Q0b1BPE8dIvUQLHFN5+d83727W8+OpmsRs6tOWqw6dwm8RG5Fp/JN7AOs0tORcs
xKoyaUQ2DDJnCneIZomBREMnma/WREiuhqdoumvO3/W5ug9opIfvW5qk+Nxw1ODydwEmAQKAczUT
3rb5Y53+8DNqDKo8yKXfzk7NnTf7+d5IAxDeaase5dSnYjJE54LBC7heiLVtvEZ7OkfaxvN/tdhQ
VqF9+zVws/S6QK64LI+ozUgO2OTJKNZhq+zSabMpF5zf5UmrEchGD6/w3xt9q0x/ppprCgl0jGlo
8PQ5miLICiOolP9n6JgqF4gD3XkeXY72nX7UeLfnIGPLTw3bk95nOfucxX5yhpD8DvKWxUiA495A
+tBsmY4YlcjD8pLR4BvZ3TdvXSDO6vQFuxfgQa/1m1OcNYctjR/m8y+/BDTgPMdxIjBTUyhiAJfS
PnkAKErd1wdtWfLy1QmDe6vqxXBVavZBm5YqQwb64aosR3JBwUEUNQTRnR5X7FepdE2ZKDEJuTzw
tp1NCqWq2VF3RPxxAK5LuW/UUCWf7Hy/XykrfiIoRS60hVgZPprbuAlPVVgkm52NzXaoIHFvasrs
dg77uLmTpgdETZMgd1vLTnC1eENZWmN1g0Omeh3A0PCoSm18n2mtXHMpF87MWH32Dol0CJQ9Mth+
r7jjmisEw3CToNjJlJfM0jZesk51jnnnEm9nF3aU05EIk95HCXzn8skIHRDekoBvbbGRQLmjNIgW
qJnNp0pWL/A/K3jYreexX7dv1dR/6pXVU/Izh2n4w050hW8D9si5/s8bLBV1BYAmlk3SwN7ICn6O
3c2WQmKHaV6Lo7anAhr1Xhju6IQgE00vVqDfCXTesuV375k3aG+6ZyivIsrNUOfwmuJbNjR70SHr
W7KVUh8TLyzu7KYHp0ayL3VNl58ZiD+OxMhjxuYAdy06m3Cb5froUnN7pfecS0Siv2F6hURWCaPU
OrydoYNABmypVshNvpK4cS+9V8NOE57i/FLfaEycx628vTg34MHy8z43R5q2xuk6pyRtgzlZr/Qx
Wg700VGqMNktmG2kW06E8t77qcanmbzRf1XyrhWnso4wOi7fQuuCSw2/KcUO0FouRLUw7Kwod3jw
CF7dOOECzAihHt6mhCkklHN8kwJyV6D71qWgS7ZR2w+MfqEklxJBIpI/OqO8ITAjFalZhLqLsBYZ
CLoArxhzjIJbL9NzMAKPfg3Syt7RBHjrczyx4ETZcN9W+p1TZKnBDJBEGHlav3unCfJkJb/j+ipk
IDYVp4dSHZSanxBCspISyO8JLonUsG8vEASb6y97GtkK5A7bhbHcq3QzkPqyrRke687U9L08fv/A
QKLaSF/XJGg74qrZBvKK0GxY092RaM1IDIPOiv5u5faQvuk2PM9dq0YDkWRgCttC85NEfPfVO/Za
Q8QrMRdxl12h+7CUJ0SXY9g4V9G7CQg8PK5rWmdmQmyVoPaWU4dBn18KZQdemcBPZBMpdD4KL1dT
Lqeynr2l0qgcNbdW1KLm0HgBh/NuOt7jiTkO6Bbw8MWY7+gvEptxA/+Gs5hyDZyUkA2qSj628it7
Nv9IuLQGgQ3LMuJeDd1Kih03eWyWLawuCTVJLO+LbZPYsSZMfA2gCr6s6y1DoXhbqI2mLud6M2gS
797nErgqEnQ6qI8kY9Z4undWjKQdAbe5CLWaUrcc1JwjlkCfP97b8MZLeijcTZbC6KmBatQ1Galu
9KZuiKHap4o4vt9lVmaJTadG6n1HEL9Ks/IJ6jLk+F/YBvc5A8dg9IWMUPdipoBCGALJeMm/pe1L
CQfOxeStgPCiTjXdW8YRKc0WMSM9xKRBklWa34QxYMzXOfBhE7XsUZxWdh+IGq7yl7CYCVKQGLpK
YOClffHW8jNpHiZju68j6qHuOonQt+ryE9XEv2ESbKYLToPHA3Z5vX0X8bbRbLpqz98bukklgKrv
/daE/XieY0+UmJVOvUI0fRW/YI8Egb+gzF5xgCu17egLouOGCploI/LkS+OIIWTNYIrV9trfDZ6a
A9zSHs5OmgIjD5bRo7ylNg60hp7Ip3VrZQCP/ZdGEmlbUSSYpem8Zs5vkOeBhuUNjAV7PZ/89Uiw
a2XPXBxrkCYfr+iRt+NoWuFaRxhe9vGMph+mQxTAopqMWgt1Y3cZwYz+dANFTjnWhvwv8xolFsS3
1IKz3QMVhce0DkTpVK1P/lBVpyzejgqy4PFSdsOsrod/tFSvMh1Bz1VFIOFYA+bcZ3cRRNWeqPUf
933GgvJAEHEPutXWWrkRIO+bsuIg2fyBbDk51e60iGtWZQl8k9oRQGJGOPKDl5mPaj/rPQw+H0fk
qPeO+hQXjTW9TvbZZ7ALwis0e3KMZYp1YjUmmNun0WSjl+vdH3oiBeQbxbxoIMAMK++iSCG0QzE0
/dBDyr9xn4oK30EGlfSZfjaNrsSMuMmM/Bp8J4ILIHsStRsIVtN45oCCQyezo4CMJlwd1iTN/arR
HWUQ+3URZ2OxC/CgYjIQB3gC/bRBwletXAI6j2W69A8eDSRrexUuuddf5klEOYc1uXhNGb9LdKtI
4eYQoB1GxQVOGCI4do/yOIc4ZEzy8Fg0A1IYOKwUsGKNgXmFMqvgK0paLqd+wUQ2Raiu6m0U0PV7
c7w/5KSSueKCPtNVBp47PTAoDr4tm0Bd3CdaO/1Q8rdm3CuqTkAAVoiiY/u0iHcgQFaCQ1b+2Max
LDHvJO4kkN0ZUT7kTnHtX5K+wm2J2KvxkC90DM9oOmYfGfjpL14n98vdzx1s9s69F5ksI3giFYxT
Yf1srKn2o8uELB12X+OHztNNR9gLvuNsWYO463+RNLXibnfl79iF5zjwN6/QC5ZO2WW20+u9PxaT
IwohjLgivZyY8AGgXZJioS71YkHBWiC56pc0ScUoRkDiGylY2II2X1AcqH4t75nWdJX3phKl8JVO
RgMmF9xi78Il254xjJuVGnUOuGwzhXyJwi6HxKuTdF3Vf3U01/vhhBpRm+Sxl2sb8KaNJ3VGiREz
tWwoXY8h9rABvQcEot9RBtOWA7vD8Uj6kZZKXUmQJL+HLBFz74qYxxxwhhxNqcSLDD1YytRAqwb4
WzA7ic2jECEFakxImdNk69YkHA+vPFdCoRwnjvKFfZIBzvSqekBHOA4TA3JXiVjTcMXuUaZaJkK+
se8fGHEBsOD+mPdPO1fYyr6EQz4fAGDCcgnVZfJ27i8iZ/twIqLmXvlXRIqgJmhajl/4YN4anc7v
gx3T+lEweO4lPLT3NHjkewkG0LAIDLhMDpyttFkKB/ApiNq2BqLWgHswVd71hsM04E0NPdopvYoG
ZdrrYqTNxG5u5QZ/DhpU/gHUv5SwB+c32XTS8Ki0MoQKzxuZK8Qj2R0zC0PWqB4cZ20R4FQg/6qp
8V+zm5JdocC/++Q17ymwlg9rIbaH8sVxilbKvRGt1I5blAN1S+JhehNuKAKK59c6EazCIMkzdZHO
CscdRgrmUB8QGa6gDDGoqvDIWJwjEA42N2aeB9a0/ogfkqKbJ1S/wxplbh1KYlJ7EmT+vdq5Zl8i
BtDupcrUAmK57qMO+BNRvLMxl8kDdQFx8n7JUIHl6Uq0siB6lRICzpZvwb9Qq+cm3fIfBw8msDod
+dR9fif1q41Lw/3ofwt48h0olpGprShEDl0MzMkL3LMeY1ywWJDCiDPWgwLH9gJI0qkqPn2M37de
sMvTsSRzFGsAE15kS2zLAHeKC2How5HF3opd+zguFgJes3NNoCCVIO22j4Wg3wLWpdhdquYjL1yx
vAeLL/w1OIpeepeDgfmuf6Qtc67aekgNs7H2dRAC5mvs4gXbbdMytPlZ4ThvFVLEfTZtd8dle9Uj
SrvqB0v5RECqLlBodlhj5C5UqlQd69qRknYBzxW9hC/+7GJYkrUrFaHMWAeQZGp9RPe4SMQHGQ2u
7L11R3gpmYuoK1o+Wj03mD0DidCC43cwllUU9mPmmSAmGPbhaeHug9EhE5t1jQ/tzKXVAksm/7sV
JP7L+SZFpn1HRkRhz/MI88H3+e7y2oDWcGYQny7SWc5OiV6y97Hm48KAplddOIIXkrBkEmlFFyU/
l4ScukFLkr6quhi+70UbC9J1/UmZms37sJkxGNdtEvY1gWRMudIp1+OiQW3IzVskbxtmVoA9HNzX
jJC3BU9b5hDRbDO7DgPIufAf8/iN8iPcGCHO6H258+mheCS36YxjrebQ/IniJ80TvcQT2fXeY/1D
9tvWNsFvwNCH4XiwYOT1UNt7vAX3jimgpLo8BDOFZly2uIzzns5scxEpm/CQ8ER595STbI/I7sUZ
L2jXl7A63igL40v92ADDqqP/fcUyxyPAgDh3ADylsSkn1as90peagE9QWOH3nTncdtxBSkiIK0ZS
nspjDCxdpqunwRyC0J7WQDU3R6/TxzGjOFbMaWtHh9/NNwkh64DLfdBjurCf90bkc1mBaYaYALoh
F2utE2XdtJJz552sd6chSTn6bbjQ7Mwv9z6WdWZXxcAMhYP9RlAVt9ZzhhEWr5n7qUdJ5IgmjX1G
NsO1qspGeHWgR2om1xoazpMxOYep5kNdBeVJQ5E3WnnM4NgaY6tGbDoVizFmfCEtDdlqwZU/riFP
6OKx0ajz/TCmiej/KzzRiJ2PqYwGM86oBnYFcl/JguLokLlFyX8yfVzo/GCsV2PCHrD79XOA6V01
156pfZLZ3Lhy3FtLMRjmpepbvQYB+xR3t8x4G+AefgqNpdjhvNN20mx0NczoJO1Fol6bz/PnINy6
pagZtgfpIx0E7Xfse77ovEsQkHYDXVaZzugdYxrzQIA1OJtfljhQ5G8sHrI5tZkOlc+TDTLabzXi
pqyG34qAan3VfnOyFwpAKW2VU8ulaK1IS5+kYXZAwgBspnFOQ9Uy6ZT7J22EBy1AWAg0jnaKPE5x
/BxkYB2/8rbnfsajB/+3wsnx+mKmCNlzDBj20eFq71IbZ1lmgClfjDdiD1bHLyQYzX+ZBcw39Fpv
OpxyxsF5gfO1XIOg3dMXDfnA7kkgL1wTr55ALsDM0K7pGrpDVtp4boH+h1/VVV75/Sq4jlIsACdX
cS1FmA+MkgUx4hFAgLsfLigY6mNJ0hpSdHwywbFZC8+2+3/hQWj4e5hevomcVGxSVdCuHe/5c+f8
160PXVI2jZukjfOZIAzWG73rVYyagMmpxPs7Q5Eh3Jd2+TOoz1nrzTGzVc6iPAy0tltEf/atg0yz
ys7xdlwgx+GS9W0Sgk6pDEya4ukYrsJS6RaObpjFMSfb2ENNAIbaDId9nsepM1vCPesTp8X7M1s9
oxU9Fay1J2wnFPAYXFGuTGASVXlT7VLONEa9DK0v+Uro33qkl7Gc7LojVUR5U4LRAdFXl/iXxwVZ
/erd4NMQDiX5dPTtDTKa7weGa1wBc7oIAJwxdnGmtSXCzrskclSGlx+NbpRg3hPOSVkxtZcb9l80
PzPULNokIqx0QyoKUnwHrjmmA/g+m1I3c8hXBrBs0wMmvhdr/7SQY8g+7tTFTAu77ToJjingF4Nv
0MUl0yWE5QkyOJ7HcT4ZTIlsYUU88R9JutRmVMCNYhiyQ0CpqJTL+TnS0P9U9XDDkhOITBpCmPWX
xoKiT8zAgU1IkV1HRwvgHc2G4Z361v1P9+vQRFo099mvejrkHj5qKKiyndC4aBlfj2FS+ytSRB2V
0y6Y9ZLKM6iXDcFdUAEiK+8AMLLGxzVOIE/oInKUVDjr03/bOrEBrnrEb1OuJ4663CrMRiHq2Lo0
RTEoy0LBr9JXCp94qhLEz9pRcIcqCDxggt2YsSOApe2lmeHABXkjdRb/PCijYhtBmLHUET7k8JLY
i9YGAWNNC2DIuj48sE3SpJXGVrdCEVaHzpAatb49XPyHlgC6Kaohq5u0uJrl/V63r2mzF5VUX/wF
r0yXGHGUAVhNb8GqG9NZtiQ7jlFiaaNnaVF8ZOnmDh8nruc0ucYjJDXAwFXDa9fHNjGbpqahyI67
muCTJL8X43QV31mUAGWn9r9hLesXwoh1OB2nppxEcnAB4otFbbOFZ8uvLOVuXDsQ2Q00BjHbcqcU
PSEJYUFyclHE8nfDR4wMlLbRneI1c2SQ5UyAn0j1V6P29zFI5Zb5oa81TJOWCFDPBz5yISuQ+nfb
Ks/vsaVsxRZh1T4/ZP4wYYNuOQrHunapoXRY1p0nU5cGzmva+80tLaQNjsghHdBlBVhbYKHJV9Xd
zl7EyM8WdC79R8gqCB92r9RzATQlMj3X88wXLvz99zar6csyKaJAiVTv3XIjbl6WCiC0FAyC+isO
zwmnCYzCDoZtBxuSZlNU0qgXQD3ujdeosOxMur4nfIt1m11wzYwEhIf1Mnvwe5UUpHiu93JaFE8B
5DfkHOL9b63bWFBulxAH/Z9p907u8iH3h5jjMBkoizek4KAiKmu0Y0ktG80oSWdw4j39h+a+EYIg
sIZSuB7VQ2faS3YDo3ptqsa+/z8EvZBMUrTLmASbJfZQW/4iNpxNpECyS/o+htUthaeS2GxSlc2c
pyTQjdL3lUWzFYbe7N/91Pw34U8D22+DA4uWbtUJ/GAKH2pkIi6fSpkKnFEHcKO4azMPjH+zGfVD
jZV5jbmrZLTn+E1JnsscZuFsVJBYxdT0Rn1ATzjWYsb4Q6CXFegXoG0sutWfmPAllfmub9vDxWyg
7F7eY3zO+akjYpOpda7EOPXxE4DD9UtMonUkyYP6/T8q5/Pwe7GAL8jD3m6SNtXJ0I4iOVdjHFbx
s0iVjlak6teALt3S22DUhe0rkbJZk9Pr/hfb4cX6hVLJ1qiLPnFz24mDSJEA2JotFd3SrZ910c4x
74ZUYbm9Kr3qX7ECJZapzIglXA53wNVhRsfSiWRYnrwQ0qoOhXz8dnzQSDmqzmjhBcWHpnMLFYE3
cEvNJ5G3fCM2uVdY9C7SI9XF0MnVS0JJI8xme+w13SopfaqGwAXe6WenPKMmbUx3t1uxpdU20iyQ
KoLak6kWBPXhddZ0gLtnN6yIAoWK7c9jFJ4QwurltFI8tUgHQVB421UWtw8b0cURoSXfzLQHup3R
BvBFF8yYRIn3Dohc6e9hGce+Z+idhQwVFXNviEsPgSbJP5mtAKhu13FnYOUvpuuydyVmiXQONcaY
T0wNdHEYlR1PtZMrTcFJzgBa+yxH9cOdQuIculRufFzITUSsFlYTElwv3a/qbX1851ZYkcAzyMO9
T5LqaAlRZU/ac26ND2JyPQcabSllQVklzg+5qDbxqyNUnnBwTwwEL3jRFribjqRa5BnCCqU1K8wi
ur/m8AWx7yytV3EANC5j0VCOZdk530PLfBHA7nrZa3XPVZAm8IR8h4VBHLZRwRtr0CrEl25xi/3m
AwJhVmlUFtnuo/8xRRGTV+4VRXb32j+xArRTX1SyAqSZBTP43YmW+oQiYisAQ9JzkAVKFTXwSHew
AwVWZBXyUqvMvGbhbiEi8Jy441hPOweNJwsyJI+U/EOiU+YKd0UvXahgjlsMNr/8t3fboIlRGJRk
RhOipDDEzxQhR0l3XRnaKihoOP58uQd8JoEmQXlwW8soLfWxV1q5OEtl78AJNkoX/ZdhxbPLCkQp
3KwJE0cAdYgH9zmvW5N9hcDFOYJyNXcMHFajvd6bafmel4CmE9jG4umFzooiAU+oZ6OrArVaFMYB
9HOnsF+LCramkyVIeBrJ0ENijVWvkZvB/XSUPd/STYYbtcTPNgrgmwknKt65uiHIPhIJqjQzW7yE
nyhDIsLJvVNgCOtu6njdHhbG5qPamNZ/5CCujnmL1GdXqOgt3lQoRxJ0J85sOPWBh6OIBJaB0EHZ
L/SG30dJqaduW7K2SmRsrQ0Ni9pQ2GRdivGFqKaXSKespGnmakm9bCKKQtix4JZKnhlV1LJYWywA
bn9FbgH6QOod1UWDnOkpS0Q7WnkJ63lq6pPCxeGrOGxss91mSu0Ip1nt8M4HEdiW3k+EcviFrnhA
iL6wile4aYR/ZYbYaGPz5uD+hQcQjg2Blp6HO+Jj09N/YZdW3ia44EPrQj94xxoLDBSXLfVIOdNw
Rb/x3zvuMZ/JujJ1R5X+gdY3VpLxPuvrzVPG9fQPnDqDT38hsdvjjDXp8W9ntEwTbyQUrkJKNrC5
ckvmSL2U8kGiS8l5OT65xwP6HK6n85ZI9SdtGBUhGuOysOvjEXvPaU03dgwL+6nMv9tUshuycrI6
Kiv842UbnjW91bKzG7qKPdIamd5omtmC9cO0TavQoOiHdMI0QmNnP7fYa8yf4mgqq5kkfEAFd5zC
Qzu5oPkuWvxKAjXAe2J0zYd1vxFkF0/KJ+K3CtwaZnmoH6Wb+TjEjPVXFyLb2zNIJ+OpdCwtCE7L
wHxZipktDnkZsLl+Ae1dLT57GAWLExAAA2JTGTHb3UjZ5ONCByhKuJojyaPb/a2zYOmLbSPBbEYW
WcH9pjIh0N8T0BwagrWclZFc3ISkuT+F5t1/FTF7mLNhSMihrY4fvh+H9lNraPNVlHoOUjeCl4G5
vArsvcM4CjaFNGxwwm2yatKOioP/RkkD8hSbmIF+Uo1StHUQPH9RXMPHFyzPiKEuJZdbzrmy6Hnb
aP5J97zgwNbm8LQoTwRWHYhWqJRKSnvdhlIPinUNgsAAJ94gsCGKELz9iFPCEPjv9SLHeeLP9x6M
QDRhIKIu6A0HqV7Z0EQ7DeJU1WbRcDHCeWizqXqVIL12zNUblqzYw5EDWUTQ3P43GIyHHJfZ8Z/Y
VxIpN4sO6ze2yyTrfUiD+CKh4uYC6OjCb+NBCkr0vDOM3zzvotuB+b1zq0dfnz6/rEQp5gKBA6O9
VBDCrFBv/6w82M2okj06jpB5zlyifgYXw7FzauYWjDKPNGRUtw2YfA86eF5IwZI413LlUb6Asz41
DMpdL3zYzZ4VIa/Bk+9hGvRn+5JV2OkXy73iyFzKFv4vc61ujBTdpImyOrH5sNTP9+c+aP1xvUj5
fq9TGEPgTfXPJNpWRfntmQTA47u1x1bqZIQK7WYUj8zPCr1Nto/dTk3cdvgpiv9P5k1cgwyjfBY+
rqyGXZXs+Yg02nuZEGihPslFrAd9ViWq+Zl2VjgVx1g+bHtbn1A+H+Qtwfkc7NwF7Nrbv/9lheQ7
zkkNVTaFvpn0lnnSnxUMWeExvb/6wNMaz7Z/SU0JHs5pt2uK4QUJm0c0RLEBbPfVrS3VnuoOSUDb
7MNjVHBIqd1+Ug6yZ8H0et+fwY1rju8VHkUDI8R8SK0Qy3sbmg5x5c/Tjr/YMldf7re0aWl+Itbm
/Ik/hatWMmHkek5Gv64yXyHn84EwhTdR5/rUIcwCxLcPLpWPMWnR1rg5A3Q8iV483/hejVJJfoUs
sDt3D5LiPIOgW1QaHcjE/IjlpZpyytQhKDc/ffpz9bj1jXfHnsia6/m6Lq0d5UNkxslL2qH6ojF+
aqydq5xRCLubh3SlWpEvQH51UtBjU3IRwxelmIr3erMhwqMx8ud0d63a20NYeWFpxjEewgy4yIQ2
CMaiwUoTAlgcfHlYGQjyUc6F4CWWLBKDLFEzyoVksXpuLNHw38bqSDrs4tCxNdce04qoASM4cwxA
aJFMa0ceIglPf3NMftB22im5fROnbj2fHLqvZMoKkzkP6a1cygXTdAopu1XSuZLpHHjE+G7nwW98
/27fJfk1g6OEqw5cTVnWqFt3uHFCo8WFJ8LBC2RxscfQ+YfB0VJm3KiLJI8Pt8LqNSD3mv/yd7pi
O32/c10q9IBVj4dL9icHnZLmFoqKpA9gEOixIH50W1blXv8kwnOVUyTMPJXfsNVAfeK1o87KEljk
1RmlEsM9I/jzrc+ivtmaFeGAxnlKkwE4KUqguN/11HBWBs4BhP2rSThoYNk6/OQzbw5wfGdrR/NT
dtKvGnb0KWHgbaQ/MqEAiBBLW032zbyG/Z/xsrn33YZWd65mEMvragGNhEKmU81kJMilFV3KsmsT
7Yr2sngI+m60zYcvjN4gAaQSanHiDwV7Dwz7bOmwjIBDssAKZuRo2Lo3ybM/RGc1PiYHQ6U7bZZ1
f7wWzwMsQSHVcFw/Ol2LD/hoRVwYavwbPXEyfnZuKmmYEjBb24dBNp3SOPkJbxj84pPCzIwDihk/
oLOiDEt+lzpoqCEsZ9nIVOnDA7lHmUPUQfaKqZSCaGq6wDn+AFuScy+YzAw2Je7ZgbNF8uxA7qln
4WoVfNDVXHnp73hc6XYWnuvCOnZwZsJx2ChqX26SYH1GN/lgw73MS0K8az1FlqRPK82jdou6rxNs
KUsIe1JwsAdpM+mHv85uFUkStJ9vARmAUE8lT9ud4Zgfdqjlpk1j07KX1tSyo3Pq/6vysZbmZf7W
C8yH/1t0Y2TmHCJf5fdxhOBXmjDcKbB/othmIRnTmLnULv12cWlUxKZy+NkGOrwudqAx52lpA0CT
gT5KuZf+LhLmylo9qM9g/kTJ9J4jBNucKsBT0z3b3/J4AYSbxwXZj6BBMnq/DQVkJKS064/gbCH+
nQdImUEr3kVW4RhtPBmEptNWTkLdJWnvMz4isLQ5L72cGlKGFGTucys4FqOtVlQeutZr9x/LejFq
Jn/Y39GZuHyteX2Pm6zrSXId1wpd671/DyhUHMHCMSL9IDsWB6q12C+zFtg3TyCutPV1gyvybNIu
oy7FRLZXUt5BPsoSr0rvPccZXVOLkvSf/ZPyCBa0CFLuvI3fqKXH0DTrY+03B6tSv6UtYAH8HzGM
uvYE2OU5k12MdZffQcd+5xNjzQ6QWHg7XuKkm3VpIJFm+g2YEJenDHjPwiq69COAcTLCwOFOEP1k
BW+5nzLxRXK878NwaW38yN73t8OvORcOYP29Fpatz4HnCaVaKSBwT07EzRhNjLvgzYxPY0sBKhsy
6eu1w8PIad1Fm/dQtX1JHTjag4lMa8kUnWFuIz3kxnb9LgiNweqs/cBCtzVgl6vW1nkSdNfuuCam
InT+m5zYm29bhuJokTOZW39wJ/X9QVoxef6/T+ziTJUqv55q4DaNzFrZxL4sZLau440/HlL83aNR
q3EqJ+X8GxvTfJdSbFqpWl4HQ9GjVRqInDcu9mHHvnt8NbUcLB7gubbdlQzjpZYMB4fJ5UK4zXep
+0S4izJ9V8iVvskI/y2hG8zEQwkVpvvoR+4hfCDn3cJ9CsZy0lOBV1ACBA1k9SB/PO1puy30A8F+
LHkwdIezVyb7kBg/UIypmIxvi+8WoT+u0O0METpdW/F+XDXtGEpBphbnOQYXsFbt3lpnJLMCOeUv
L8nTzVGhtMm+D4Zo867lvNNW0qRidyOX7PDcxFZUfg/C+zIMAhsOuOP6S/kOtfjfQyYq3FxaK9Xn
IUbb7tsT9Tcp5GrE7Sxhe4r+e36AKue9R+DZR3BOSHMxyFsYWpScw5VbUd/+25XV1EB71xvHCXXA
VTdSIrnPZN8zVspjxAwsz6duHRBybhSbjIm2qP0QAdigvF0fMKLUHaC9QNysRvqjJsu+KEDL25si
BA/ZQVaH/dQxJDj2qqJrW0oqnRSW4B3rhRvc7yccSIzOq7L2GWWdE/Eq0oQH7o2U6vCebuOzv7eJ
xk7GRRh7zWgFcXjurnTlZppXSx+r6k4MWEDWR1db3AiIHER80tQ4+WqxQwxsYTfrHN+WzXdryd3n
xPWbASiHfZLI1w+6rHhp7L8VTQke7FYYc1YSwrRfrpKnPZxlg6nzptZRP39I+raiGdpmUtKUhkkE
dbMnsmEtWVCS/4qxQDQBNCoEN+OCWJIrpjRLfV51Go7OvNaPTxo3Er9nqDOghOg/V/wiQcnDRZ9l
IpJ9P2fALMSg3XDf2WZ4t9De6CM3846vXCtZ6ouYGY7gah1n1aZPJnq4QVEE0W+YkImnR6HYNBfO
Uqaw2XBumEjUvQI4hG+ViaLFbNjMSYKlJELDMDWdp7Ci04LjOQLaNBA659Uk66AIvJ6nPGtkGe+7
27bAkQnhqZBa4chDCimz40P4YqNvGoDxk8QyacvEMunWnscYiU6GZCmu4WuZIBVXS2Q1wr7ItlDS
WD4FxhUv6uc/tFRa3MO6W7bwagS/o3DKPFb8V5bot6sR9YmVgZbnk1O76xdmRoEL0DYJWMCZojE/
4UMi0JEdIURimE0YtU35ca8IjpcxVCZwm1J35xAxYRtuaZ5gnzf8T8G6mQvQXQ7gKMEwWZarMBS1
z+79C9fI2YMgpWhY61LOCWU+HOpQS8jfRKsREvq+UxfjqVsAZ6raWfGFWG36AWEcYfWLLPu8kCCX
FH19yoNIqA/CQ8EJsHapfQmgGmSsMZtyTlxJPntwAA+S6AwXNNOcdWkljUtquS97cfK8vBcowW5M
aesi5jbUpdv8d+bWZTyFRU4DXo5o0bLO+UgHwVLdep9FhbET5LlDsiUKWgh8O2Z+g8vQ4LwWDxeX
cpZYKJuNjp5c0Py/yQkSfK57BWZjS3m84BmPmR/m0lgBWTIyW7bNhWFctnLmr3eWGDcJnw0mB1k6
NHwGbxnnw+6fdYbVtjEltbGHwxeDRlDWrUwaBol+ZXuFL8HsahzCXOAtmByHat05SgZHRhaoRb8t
xRMYxm3/zlRBLFuGDg5s/Cm2B5fzKBU9cL95xWLaRmrMVsjF2ptUVHecAndcx09hxpfpFsL3SFzp
20OVaxg9nVZPGFApSCLvufpfaZIDfa6bqoylWML/lQZq5qyP6HmAj0xpyU9hxPfzJWIqRaioxmtS
60ebTSMxiI6W13SKuV0R+R+7bsiuMPEqJ7BLa8cNqcZ1m73DQY7fFpIYDzn8U91EKwoWE3RzlOAy
RccBwF8oiSK8i7gIjvF/aI4RbRlJDDHoP6CsqBgQXFQNAZlc2zIfQIc5H2kdrYbGPrO3KcpbUlG+
RjbAVLEczrhh7E7GtfQVyky0DyPH4IgstvCpxi8dGxvBMMZAVZ2f1esngRiJilERZ5yB6ZLs6xUg
WInIrzwIivQVoTGympBL7E1szR5NqCL0iExfxeqVwmnHr0JYl33dFDzHtGwpiiIyijwOlKOSoBjq
6BAHJAZCBgGydCWhZKzRtppv5SFIEMpcllgzKHr8a6hAafwh6ARVjh997aAoyAacFC+Kpz+fNV0z
HUyKUTdRX0ED+hUyDsKkjiaUOFPAO/pxg83JJ/M2ruHND6uooxfhG90d47x97bsxhNS5CnmrZlj+
ogeOjxfi7jqKUJN8mPU4MWKEBYqlp4/CYbYcN9SAD2XPXR4uiouevtLcv8SZze1jv0NJEWhjANyp
BB/op6L6Kx1cVNqulTq3N9zfAAcljGgqNOJZ9kJAdhjUxh09Uyldat2pM5WBuVA0Xs5ZOn2o5SRL
ru4I23IqTGKAEFWuYmL4fo3RVLopWVf9da15t6uS6aLj0Drd/2xJrUv9efEkLETX6BDdF8uuZrhM
2HGUWR07EL/3bZPoPTBYYLrHSCO3XVgVrwRuMzrvi+mHA/vcxv4FGSBZt34rwogeRCe53W8qlr50
kRda6zEnd8a8O3MwtaGcw8bF9az7SjtL4fGGa+/un7fv0mxd2zuSJw0ihBx0XEsDOXgX9+RjnThx
mVSyL42XHuADTiqC/lOfCi/QecZHkf5VdMBX/uqqrIC8bfqkz0d5N7OcwQRP5LmesQEFMsgy/ekp
E+z7Pa4EDgDHn6iTC9JyBevDFErJvf7o0loGGaa0NRzSjYcMrRe3RzvircNiLMmKG5NS/kxgVinj
zrmxo/ugwdK2GyD/4zoRaU5CXHjdvmnWEpYyzBQEVkT+eGN9PWjbX2RGfpdg1+1sgrlwrkPodBH7
UFCk7fMM2408CJM3AsUUd9D5sz2sGifaTnKXBjM2cc0R42EbrztyZIU7lCQIrDcYsoXI0ydoDnXE
eKSOLeHZmQmxmzA6HsA8xlGimiN/M8UDRUvp5NX90CAdbJHq5vR6qhCSR//SDuyUFXcq/3tRJxk4
9Vzs2q7VExrzs97FFyhltroOlty9oLqexOtSjPYhquVvB6liQqRHmZ3IxaDVdybxM0cbmiPzqfoP
heCgc+IBRIx/g6u5RqNol6kpE+AEqSuFWUYbEYF9C58hLUmlHSSljhwVziotAOI0Xjdsj52T1JD9
RlsP9cSUGxYSbvMbEUjmy64GN3P3zeC4mXGDJW7G1QjLX7T2B8ZsASs/9jC7Qorwv8/FopKuulz6
EZKSXysCHQ53c8qYtKyMSRV/mJy/pbTh2JuUvZxIUu7QJ5sZSgPDTWwZCyKAoDs0omoT9WgffPiv
Wtywm19aXh2LlAECCWwgP7VRtdmWGdCFKk8ASsUoXkqdn6/0HkkVSRLvNKPlDuDAZPk1tx2e9QWA
Tyj+d0at/n/64LO5alcun5J68k2L1yNa3RSJeL8YC+cPrFeqXnDknjJok9TvBl5Hee1CbXK68BC2
8Rh4sh1Sk2LVkaPiwqnjotKuGxNfA7cedaJo2YyyTt4IqlvBmhzz5JLKWGdwKI8/D9oZ8Si6yyNa
hNg7fDtRPJ47EHdmBv4udtl/By8k+aG3fbP8W3RN00Mgki3SL06H1t3ws6vQUWyHyeRa0lXWfel/
Xx29gXaGxPTJLpnqWhuxqDerv0TLsYgTnKN//B+ww71MlIIreaUsDYbVujRR900ytuv75TxVvf/C
eYrM5rbIDo9tBsWUk3AE2DpcaCzUF/c6n+iSU4a57RbJybNF+mWOsUti0vXBOfdVqzetB007+9re
aOGe2ENHWLypIS9xlFzuKRpBpsNvUtXey6FBPajZ6ecAgakroJbKkBXmO06Tg4DWLhE80v5ZSeRR
l7W0g4PKMWht1R3ff5Hv2N3VgztFpOCcCLudvNkZ1H6fFGdg+9hohh1+wrPnErApHM1mhqrXoDBd
2S7xJBWSoqnf0uR+1ngd/jOIh2Ei4kh0C9s3zzUM3uoQx0I1eUq+YKFlSzKhpMbM+Qm/WBNzqolS
/pkRt5nU1elF/V2Q3leR1qZRO/FpDUyVtAqmmc7yER7ON417a8S7JkG4UthiJ43KKoLqAqtUwGqm
cFoOGXE52gwPFqIecWQGkb7f3rvJC4X75/eEaaFkEFq6dSaKT6fFdth07d2I9DquGJi8uh1ZRe4M
oTvcm3d05X7I4gmJ/SCSLlltf7IZK3ATJjqJakdJwblQewkp7wBivhEC1OHXjiihRs6YLuOah/i4
6bMgQNpDGirjrvwLtHBQDjJ5WqK1rSa9hFXFNk2rhWmfGzOgoQDKzdvAB83kgaQqmAB46LqJOr0J
9IM/Ve0EkdsDaA54XlfaPwy7sllwv2vPKr+nkPUNF/UMsVzoCK6b/8fSlK5C238Q0qsgaeC0gjzR
6IB+d1p5HT2AvYuwoKTDpZabaYxzbAGmLCOqxoVdH/7WKE6L8Dwm091451XtIgMpZQ4p59yBnVwp
Mox886cTif907tRFnyQes5jtReYZSkDqqyv/96ghU1R7Nmunoo2onps80Y9EHtEmQ4HOX6p1fdIX
8Zq9agUtdRoq0VMXaak86ZVowPF9qJ2G4pAltHcz7mDBAvNJuXPjvjvQMFhLbDPEdYh3xNykkdDC
+H8QSq1QmX9i9WIIoI0J6xq+RVuJPYI7+itz0Rh5lfLD/q57MmRnui8rqpMzVAxw6idKUaBTy6d4
eOZ/6S8YJdHRdd1YzKVn1y9W3wzK2lWheyQhGWp79bX4uc0QDfqvGYOWbQjXqX+bY7qS1Uxpx7jD
kLmG4dKOwQ51QOrCAcLpmwwQZxzycU7TYFY0sEdx1nBt71OyEbYl+qv3lIMDHeYQOEMI+HKFKXDy
7IrGr8F0LC6QTlhmB5D3w4Qdaa2+QX3ZkjlnLkv3ERggFzTWg7wZsYlCkX3KuOgnj6JhcITtHfnX
5ej08llRiyQ8E8LLp7Rys4izHmkXnyyse2MpIjV9HmTq2rXZBbWnVHIlK3q4UtJeK/IoB93r5T3s
USbNYDP46kAa98QRLO4s+dfzPe3/AZs4hXbJwI7c5HtNrO2EK6xFWAU7PP2RDoMJ3CxI8kfC4vWR
AthqTXs0fCreT/mRWDN5kdq7ZEkpm2dNzqkeq1BN8tk/EgSqcCngH2mkDjbp3QYU0p2kKRl4NlEb
QMlCVkV63EbuAC5wyodkXMIsE4SLOXwJ9edDGdpF4STiN7UH5sKDQ+SbS6GNPFIagfxyz0ufOhf8
Xf5PasN699kyVpiignZTKMgGokRsSwRse+mkeLkreP+4JiZtJZCqhazvF3mvtdLh5MylfSx/4KZt
bbB/jp5q4zcGRF5M19mSAUaAOnn47P77MJbF09IBjAyPyAT3sSz+MbJ711YgheUtml67gcZ1L3ua
NQ1tAneQf+TVjRX3wcJukYJy6NhLBC/jkbzbxdlLkEYS4GWa3Q0bryBOMzws+N57R+PWNwSvkROX
gkHU28IyxvmAO0HBuvnYcEcA7ToAhbwXHWwddzxMMShyEHxHheDAbqBiu2RJX55r8DUG0G+UNYtJ
dGtNZeUQUGr/usnPAJo/gdL5FTounqPY6Y4qdmsMqCqChlgAPQSled+FpSUFMoeR7L77/WWLnPoH
RJqaSj11ocJG4qlwoZJwMA6IH7XBBB+MrzttNIqhrKqiPVHRO6mK8I47myHkd/p5w5AoZEx6rSFi
E6NL3Bkiy3WbUweh8KZqkI74AU3Y8XiTXVh4GucdHUmbzZk5/4x3OZtsAg1v3eXb4yV7keoeN1MQ
ao5JQJRV4rQcFIbH0Unhgf75G4seerI27VT3AG7nnt78sYZdefjbsNLDL6sJRWkn85q4/dIDAddw
ko+PnZOsbXtoofq6sbyqAalTntRfcMpS0w8mNoHyliMkGWo5HAv7ty0ADga5E8EARfqRSu/uV3Va
iy0sLKEkRF+uU+2Y5TRBie7R88K63tYF4AMSpquqWP7zf8zmWLEXVfI+gKB24PC0u12NwUcVXbUI
ZzB6+KNyHrvLRWA2SrWA640kD8u5Enaa4xA50fdOiprRkQHgZtZ5o2nfIdHMOZ7EB4e1srXi8Zhs
mZ7Z3AbZZVsP5LNhDq1Be4PN4bEpeFxIj52XVqMHzbQfXJLGn+pRZcn+IyjWLz1hBNZUOfX3jld9
Xq+sr0odRG3Uxr2vwf47KlfErm5ejsjGCWMEUtgVd6Q/fPLFUb7Vdl9unOZ+IY+J5VirsK4DlTy1
ljWEvCdcftnoEfeb/meS0ELG3OiWAE6gBqLo3DkIHatGyxY1GpwPOwHi3hmYk+t1xkZbQZVRJuCO
Dr2w08BD7Rl4sOpg1UsLn9TNZx4/cQxDbrRG7Hwia5hC+P/xUDsBavsBQV8VMa7znhXLtkA9QFDT
CgXxE2Hr1qvFoaTFCr1WbQwuCMjm3zA9aMnEW8YpLO4xgiGwbyrwinQLv7G5ziZ07mr2zavlYD0p
Lx8n+NZ8gDAdRQS46vmiYyMMiLhbpeX9ziq6k19ksBzVD/i7hJxfV3cE0kbht3hC0jr50hwDXIei
76CqSY96RzpmZg/ng3PcPghBZgZ5weB0SZDiQN3SH8UIzCRs3eisjDtZf1hMA3KaibyDfArlTUba
9o6wgloTZLaNilwbP8zaInLBIwodVemBTbMM63Zc5yZGwdbBxkqF7JY5B6mRDNvj3Pnri6xeAWst
TjXfsouU+x6iv2eXREzBk5TdQYe08x3sifHApRoEPta/4D1d4WHv1exUAtarnGRHf3CgK4MdpCkE
p+4i2hffJlvQxP+vJ6yI1rmWi6ceDen0amvbOCl75799W+QjaE2Pn51EVqoVPO8tcaDt+X4sgJom
3/FeJUvbTc3gOqBeqXb4tOqUtmc/rKWfXgtCa8pvFuqEal1uckOyFK03bJTZxMkV3GvYB/Cl9Suh
yuNzsDe/phVrUFw3eBtvlLinuFI9qlIE+Qc7aJqBRXNIUASDFJ0jHb0yF2qE5aIatV7Fp7qEIYYp
lpMdwayUI51fspXkBkGhh0a4bQUETCHe2JY881eW6rOntato9f5D1t2H7dQf6H3/irnkuw8w6UNy
5R/3W6yfe48g+Y/ObRKoDzc0WBbC3WSMbIJ9TR+RvNlEeolRC39bi25/qH3dYRy7njUMaQYEjYGw
/1evk+P2d45JgKPqmgGXFQ8RMten1USCTDIEQskyc/MIpoD3X579EmHNWybKt0YzcoXLVjmKuzWx
34YXc5NAihXBRH4eOJFFoq8BCaBRzn+hMeBTiyCZcvJCHKEgbTyS1kANxzTMvJvXb6IT2EtGWzK1
d3HO6dZxe/2lC3OTQFPFJkYHGakJYEVOKRTbf2V/lxk52N4Lhl2RsYx1ZrBkcuJYQnioMy++lHnM
pt6TadAC5u7g/nvxO0w5J4ihkObS0tnmS1gHg4OPm1TQs2gJkAweY0KQgPqhJIbHjz4o9giRN4xm
lLhl/Kew+leyhEFOAT4sWEwHOnRDxFYf+x95jCGO6wtaKNsG/6sLtl/lE9/l1exj/rRec87qkC51
qwyk4rpyRKXdGMnWElJU4/hUtorzTy59f5gSWtN6sgbgm3pBTj3LRdlHGUcsm4L9VLQ2kY9s25Nn
Ocbk3dHgNlcbNrAhtwg5MFtmWqZQsPtRxuoGKrqPgqBbBai+9IMzoFwBngjOvNCuP4eBk8gGn4bJ
YzryKcbz3/BbChbvAyqaUeB+TmzvLH+9xcKbTA3jpztiEYAx2shCbCHMhpep8IyFmRU7GdcIcmDI
UxWB5mzFC5xif8kq83/7Od1AMlliLopL82tvQe9/5ji3xfC95ba+IswNCxtV+TFRmVYKbWBJc7JP
7kvQzo9lvsXdsrMkZked9BdaZO7AzW4SxCj7qN5t1nzc/gpMCOkTmrdWF97M2qH7CklPRQ7o/Skk
dQ3XnudS+gpbB2h6S6uvAQj5SVkb5qCpBROvGahYgNLR0oLVPNwmUvT2ejZMGYnyXcXxB5PtGzPX
rvL/g+eEUCGczs8HNmpcqEugszlMb+bmGPC/8m52jBGfMqTLEafzmpN6zq+4cJ50S7gE4rC1wQcO
YDKrklwc94JQMVMizuf/3FFdQ64qDwoBmLcJk+/ao1UNobqx6Lk+BZ2gUbAO6XPf56raHH+I6eSy
5RP9LUhusdaj69vqpGwtPndxZOBYGo3fjF9WWhl8JErNNeFNkwQTXqx3Zn/PGTarrWUxI+Jf9h6T
AQVooeCalDZOAJiY12idwIG587DqcInbos/wqOC2KGH8N2Jrm4zZgQHytDnNN/l6EaioFjlCnR/O
av8M6+ZNzGFWbHX5mFC6Tg2QvuRarsdk+Al9DUFrezw7wTmcdcKG/8YnuLCvb9A36VzwkqS35BP3
bvvX33gbfXy6124rQSSxCfUYvV4hqKEYPLtW9dCx5o9hv4N37sXQ5QA32RJr3+Z5Xbfugj0S3xTQ
M/MiD7SQZcjNk0TO+cnj8CzaKys450fAkRSb/XAHl93RWFvvypKjTop7cJSLJb/gYo1DTj3nmCKs
aiyKFqmnjODZGVvX3wn7pxEKQf67Vwzma+JtFuwFLdEN9w8v/ex71bAmYaKpKJwjyYo5t6Knqdgq
lD1mSi66vzwKi7Y1Bi9TSrOFQ9LM2z7L70pUOTpzz+H9nluejMlAekCaG8QyIzInVwb+1oiZGNbj
Q6ImkVdwUdyDMVPulOsBWHbF1mjwlh8kcrZeYNLj3K7iYHD29y0b5CjX5/Cb0a+BDQSlxDjvls0z
yOt3MWJEuwZNhdfevLKI244GuEkUFFJzZkstvTu+/u7U8c+UfrbKtafrLeWdUMaGC1BL3OjEjbmv
yujEc1OtSMDWSFC3GvhxM2VoEE/hAoB61KvHRUxXIKY3DA53A+45vMC1MTeVpjaK4iFjoHIQBUbW
Kk5na9ynFQwDRvXcj+UUsb/bC5UXrOXjl7RjQikXm+wGJ9HPMb3nQrpzvYJH1J5UB1VGtQRML6PC
fRtgbx7seJU1J/9D++sPBkUKrA63plgmJu7I++tN57IOPydzBuLKKnZaWHpmViy4js217NlcLaku
M0RUBhd8v4zMJ0y7V9f6SItAM1AN/RDlA65h5/n2iu8/I1wXnU4Ya6xqCsQUsaiRxHMt5PrkUt2X
4FYZhbvmVIV0M6yt9JyaKTp16bkr0Wi1/mylwjMXX4ChmFxQK8YBGWti1xWJLfp9VMZ9axo2NwNN
ngAX3Oq8MI142OSfKKqDgxXVZwL1ArLsV/1ktYuzht2P2bhu5aumvVjs0m0x2vzfRI/ZRA2wNSgN
W279S5Cbc45WhA76kZ0E0Fv/uEKXFCdS4XhJwCcxjOSRbCZBjOsfuJS5JY8MMtSs2QxBOHzjAIhq
nZkGIRi+QU6YF7yk/kStQ3YX3F1p5SE5Em4XHz0BdUG1gIJ4gO9aCME+EvEMiRdk7JEP5y49RUWO
/2cZNpyxifQv07hdilFR3IBfA0SQMJZ4nyuW6chj6RddXjJLvrvvbHs3aIYSccdfSom8bLSVKjPw
4ey/fpD1DHRXWjSqadkJxnH2+ywAa4YvBi/e7ITk9iye8epi2amouVTihRqtP+Hh5mW5r70p0XVu
1QvcWq3h8VhKTicWEMy79hiQOsP1opFTA5UKfG7zY7dtiGgDarPv8f3VgsrFTVXJd2i+wMgKVkV4
aWIydNTMc7h63N5dqAYmMqY2q6L9khZfurWk5FOIhBBKMFamOXEsZpYx6UI5e062+j1YqeEP+fVM
g0BhTnatG7QrB9iUTsYEgZVAc2BLtKxtozwnOvx4Lv6OBmgYy0d/MbN2gOePQO/rIdwA7PggqRmh
c4lDyR+fyjEQbmYUQr/QTb7+CRqSPQhqNT3b8LdiDbkYvpr+/RkkMMDApzPOvkBn0d+ozw95A8O9
b95y+RW+snCxLHJbOAtYpfke2ZGV3W0ntB2egdo1XLbCYkQjQuGJ4IhFm4zTS7OrsAhLxRq55Wwa
1BqaV0po/iihwguIwCYP5vwxicIR5dpSi82AZ/fdDnGcHXUBYRCayIrD11mCniq01mii9zJhQKXN
nSfQCcNc4nsW6MFdIaH+pbs+u4pG7VsZaa3GxDdQB7wpjLOXBdg8+l4LbuS1KoHcz5eGRE2s8uUW
D8ZobJtILtSmrR2AOLEniibKB1UbywXAKWy28qwGdeJ2HMh8e/V+sGFJF2kvopAn7LegNNwRJOFd
Pwvc91TPTjjrD25t+RCglehG6VonQd7f3amGyfoxmDjwpFAARlpnECialAp+Ul+WO85jTjgn57Rk
6diFSs9AIjxS/9QhUhrLGO2Dd09Gz/fQFALutZNQJvaXrMbMzELnEXJf3NgkqZ5nkNqfVVeh/ioG
3eWAz1Tto08OGjJK9YQEK9HkYLigPSQKGvUIPSObmlcYahTDNV0+EkejMYwKGdzTECudSpVkCEwL
zn/qw6OGUvE07U46VpFPMoLNGLR6anEG8TjXfxi3Zp+CxrDzj8YBvI49ZjA5uluBPEoaD3pqypBf
EeJhbGM++7zg6ZlIUskrjQsHPMN3MSdAWCWraUWsgQtDyMu7JYPmuU+kw769nbg1UgluuFBsXvKG
dLRwbkIykMdMVRw8DPG+i4q9/PxxkmkGcpBdeVnar/cogaXnriZWIupSX0EZuG7OUMXAR7IAikN0
lf9zCuRk5Ee2IMIFkLet7y0omiNVsVkfJSnSolLyEUxt6NOgorTm875jDHkEWN5E9IF8YJBux4Vy
TJBHcwKV3FTL5el8GTg9JoCwycjXcvB/5lrJRfpNx+O+F92qbt0fmJRJR8KnJ5F+vUSW8GTi1p6s
0SMq/I7iyVqLLP3NbGX/Nqi6/3cpdl5GGknYUQwZig/q5wo3jlWiaHM5Y+1TE7QzIueEDAb5A/x1
X7RD7+uztEnPq17EXIgowOjPksfsE8mpaHGFiaTNWQ+EIAanz45Exz0JzJokM+1fb+kkiOD1yP+Y
3kwC01X41wvj6+QxP6D8+JnypiMA+YRop9fB6Nc+XpFwqglJYqfdnBGYzMBqnH+mzoWlX+efg/TS
MhmagEkantHhHRLGlqjAYS01YT4/8NHM0viogvjeJhKc/yXRqad3XZah0osAVvaq9CczO438K6De
wyaDWz4axAtbARyX4YmhmfKV8EL0nrM8SXch0JRy2o6E3p1UJvnyoTEoHuIEi+ymyyOZ1aRqBW74
AFAq9dPWVQiQifhrRUVz8Ov/4g8WoLgYkRYf+JV2vRiVzOSE8EAOvKzLuyPCz9OUkQF4tquRqlk1
sho34aBi8a6vJcB3jrXXD8uv/zfODB5VwCwPfv80CkdYLxauJ8tHPWHiIz/0X6kQUpgfXh1jsCil
HHkW9NQeQ5UPr/BB5G9njF1y8IZEs6wB21kj0hPDu1wUGBkjnFCMmyAbPv2mL8O2TcUiWnvc2hEw
6n835SqYyJlkMnkUms8i8MjoZMwoI8Cenpv9G/laF49YdndglwwR/bVXZkwfu2t+kKI1xkzaizZn
V6ZGYPEicjRn/TEYXdouMQxNcSNvKHwcxePO1knjxDCqVTykfhVUSDz0EyBFLdLD0p70G/yqRCJY
EDvDW1Iq935hLxQS7sVU9OmD4lj3U6KKKUNf7xGKs7Oi3w5DoUa2SGoZ+Sn5471lWu28OfJvwJpH
o098Fd6hMhL1KOYK1MSnYtZdxodnyVDPBdkgx9vyJUuUx5QeI1P6ccP1G4/9upKPTIZvIU3rCJyO
KndJwHSb2+f/6707ezqnYrpuwfQFMM66oUp4aruGSfjZ28GpGvlVqdNn6QlhXRNZDCmrfBoTMLXc
UZgrlVZwplLy271c1kkpUxPD9m7n4U2iT3dVv6078yGo/jqA0W5rNtMhCkphthXLkMZUjatt3CBw
fQngAAaWd18LHjl1DDLEeMPdjUzFFFsFra65VtFvHpM2k0DgqgQzL11VpkBhxgP+3BBdxMANR/sq
qOQYpbzfCLOTIZbaljCEV5okXvgR3sv5h037WvLOh15M9wXJ+gUi863DOPnhhu/fAJhOk8Qs/taN
ZGK2t+a9By3Kuz23V1k6ISBZyuoww1oDvreYdAjZ68M9NvuYRyZoG/WTfCxSwaa/i5SL8qmjEZT7
4K0mBSjawNu1OfdIc65SLgi3XKpEAk+DGFUP0OeF+0/CwAP2hZL5FXEG9LEk9PolFWXH40ImE4K+
3dayCAmIgLYs4jBAGkB7LLN+L9u6kh9eemdBm4XeDg37LcVGzDZTat2bmxXKC+vZ8YDtMaJ1FP0j
WWy4QclbxaL1q1aQZhJvRiGMxSKcDoHjCRklW0Nd8aeGNIfsD/Rn+0KKUAdILsPhsa2wnnZW7j4Y
hjNO9ZMFuBfOUrU0lPC6ZgLjulvpeUr7w3arPuglZytCnh4GQ2oENMnbDdWtsdWbVrggqAn/1duc
plYtuX49kk64NUeDnFL6uKPgCQKmrui6kQghzF7ax5dwr9wJjDaPDITc1Mukzrz9eZVmMtOac+bg
YSq4sBMqFdXAyGuec2Xd91s1ZDJdaaKfd564Gb8Pg9YJLxRicPIW2rAX6kKKAPtttpWntJ3Ds+ut
RJOYm/IQtCO7MLA1nVoUkcX1GYwWIb91XrSs1ZAO9iWXwyVng27l+olVWEJVvbQ6QDGu9fzfJPtb
5Q39uq6QnLjXGrmSpO3DIyzrfe9H8v0LNDWX9NXYCj2Y2Dt68bjGx6wZISnVYKfXI33YFUmHuofB
DgkFyTDvD6R4JGj/yjdJZRl9+wb+OgP1yadgCljzEsdB90WKC0uBkYYh39+BnRLQ8Ah/TG9Xcg/s
r3a/axJzxXURtSA34ghDj0SRvDtAvaZXQJEjIyKGIG8VcJ+2w0Fx6nXDPRUi6howiSvoe5XAMaL4
IYMqSgW+2m7zdgsY7rAciaCrdYVTV81Z9PhHoEXJyeIFWzJbNCWeFUclPUEdilE5+1eK+qsO5aQi
n/b+vAXY20RuON4d4/1abNQlUvjhxwrUzZ32qIDRXxA0TmRZVE4FY2ZFZpnK77rLFr9iKZZNxNub
nDp+2eQ7oLbX4wTWDiKe4anYahrtQZLvuCIBEzD7Z4TDq7152/vo3dt1pELlpU/Jvm1hDf2f4hIR
ehPWs/8ex32VsdiSptQCXsbhzlJxLERGj+z1QwYzZzr7K/y/PvM2b3R6UyeWJ5Qx5scRMr7WwIF8
j6LSQQlx4jZty53BqmWCuYJdfrR55KxoHmhV8oqUnLotAm515CAg90qRn+WEocqKYtqaVqAsMqli
YvtST0oiasAGSs6NHElGfajcNGW67oDckfah04RnCWpYaVzsbwPdI/k8MTqpKq/oADnF9KArNt9D
A9gtI3I/B9yWshcNosao3yUwBeCS5MfwqL33yxfXE5JzyfCV3F+8oo92yNrI2g2mb6ZK94TUCRJD
DgZPeTP3DHeuxqWkmOZQ20izowFvifkw3wbKdluHavK4S9W+KnKSL2HFkVRslrs4Huv2hMiW3jL+
AAU67buB+R9iYuQpWkLChCojM40Y9v4aLfkAWHchfZKMX8VwtymE5m2mkucNd2KE46VaBVKahbK8
eOfifQD54K+O+MC1/ZhH2aFQQ9T9bTR39G9sr9PREIrroaF0Cd8JxjXcMfiAXd8srzvLZR8Rrs3x
eOCu882+cxbJUu/tNTTMUcseXLjtnnaCNXb2I35xth0r//dBe7EChyKIGigcUIc3pRXx47lKqz0d
hPx+PZvakUwVhCuMLNQtQwBrocRmzn6sIIEjs+v2Yxy2awqTfHo2fJIE9YA+QYmzjNfU2k4kMElr
DrocpRHczcrdzaSWNKkP89kthiVK4/sURFf7rOCcspJCjgBzz2gkWrY/0tSVEM5nDIOm+92KifXC
oJNJX8bYrg9APx6DAJM16vXvekpy2H2kKJjzCLCDAUJW8VO2CgHZ+QbijgpWtx2TSi8dXZvnYRqI
X97iENLuV9+jtmduKGiCHJ7guiCTarHXtocK/nzny5NXXVf0QzLTfxF88Peq01W9kOl+GEtgMC8X
pF5QtgDBjkXexy0P0IO+9Yk/MlLk/Mn1ClSw+1ntisepCrfA1gAz0PCbMlz9INtHTzdPErmy167O
Z6EtoeuGKjNc9y7eMoKtojALJltYXdq+rKD/Mv64HaTJ3olKK8EN2WP0YuRl1/GdkN2NGiq94Hov
2BG+7966k5ydIwip1kPm7rGkSdC0603RtZXmZbKFWSF93C9vQi2aaRtvVVnwlfhkyWXPhiUGtAM3
N3z5lLUexHIHEI0n2/6CnuGYZoqNTY7/YKHtKrFFoSUVP4t/x9SUwDq/BePx95lEHtjbHFlN+YHl
P9hBRw9n1lu8bqXZ2VGFMj7vOMYLt2Wcp4RZJoLvF5reCu3dWf7Ir18iMNh/2woQ3AhbryE2s4DD
sAEChUDA84FxTHkxCY48H+SdqJ+lliL8/F92GtFZ9jOl8dpdY+hwzI/SUxIZ9m70IUZhqM7nmv8X
oIb+my/bLTE4w+NXBYakDjTbVeMtT0mQkQrPvl5rTxq2zuzvrSb1L+75wTkm/HVs3Z1UeF9Gw6Ha
xDxAgjwOc073GWBY/OxqbzlrQ/iC0/3mwyFdr0CJXBpoYmIOxVlcXmgba1trkNS1vDJlvS0N1JxK
IA3ApP+7mYI7fw+Z91CVXsjKoIi4QTLgd6pWaMqz89VPtwoCxhh7zeTlFu+GrcVq2lAbnVd+6AGj
4dow5KxBBxran8E9PYiJtql6uiCiDP9nYchdPDN9J6cYL73UIybhzAZIj41MpbX1g2lgCsOrC00r
1u4wdn9ZrErduOyqGAkNnD7PyhDTkaSMlQjpUC/f7XlNSegUYOyCOGcC8/JBurGmGTPqwTFGVRMn
L6mxDCmH2DfstgC+XqjUo3ka/j3DD3f/9OnHJZqeNfoQEN0B73nLnnT0XI3g0WoB8Fo9Js7op9v4
TsgAVoB5Ms1mYzQntAUj5WqYCiMYIQEGZ9Y/kI7Em4Vz82/hFUBUvtv2Tex6p0reT89ubSpxwvZi
AmCUg23zwqZSy2H88hsFh3Q+FnNqUAwGLHuPU/Jw/acFA5D3J7zuvKcuVXxo/FUEcFK3Bj05tv+J
sLU76FugBTI+e2FPQzoalkzCkosbW1MRiZyotgSn+NW2TyQ4PsPbpntQIXyr5i2rRo/DgI7X9Vfu
DBdLtLK2yQUBxUIhZ09yNg+lTOBPSk28EX7pF7rNYn2Y1Fw628rs+m1rWT8OauMDYtVuhLjomtXn
M8+Roenw1FqaalD0IUgxc7R8/wuaAPZbSKDmg5M7bMlYZIB2l9VNkatqx6LgUKu97lS2EHyevrz+
fsExbpWSsuwq5XeYw5XUNJqa7BJf2uwK4F6lV3tOq7oxAVCd+5gJjqBzoi3nUx+k/pk7YmcRV9Rf
NeoLfa6M0Nx4xfDx21XApPu0LSrg9hIsK4UJeTWeRD4+j7dCGZmBdFDS7AZiGHbegOwbYNLQBYFv
yzUXK2Xh20UehgoiC+asshn92aYOOEAkdWChzDXMneOp8xeHmQkjt3hLEBOEttEZbiuEnZF6xRXt
p3Enshc31c6VLxNdwQGbPsdvq9mqOyt18oFlexcEWHlVve1mOOLwVQ0Ttzp9ILk7H8HCrg9h8ok+
7FhGits9orpGqEwPBJq9vLY1/osR+cpPz330s6gmcqF+yRTzEBQ9W4V49uAVpfAp9wcxGl72m+8U
vzMUXF5roULxsaqlZDE0s3ZvJ3ilcuKpSftMmVY3RU6YD4hhuE0GrTf6wgbP//Jw/qKTA7lsF9jk
w6mdcLhlwETxs7Xa4/vl1GvfSti0TWRITupOCvE2Nr/wCmBVtIEJMVXSyFfaqKdcjvZMzhSfJ73t
Jvu3yFuOvzHmUyGHGO7MJMVGLnEnBkgCI87rDScXOr3kMLzFzvj0/eYxbpY2h7daBYMqizZ9AjjU
ha/oOosq4MocC21sViWjceHgg7mjfhwohOMFmpZ48IgERUpQQystpGibA/BH/snrK89gyaXQOr+a
sjDfdny2ZhMODW9pVd8PQezUNa63KgpN+nFu62GIPc7KnQUCa2Br8eTIukPRAtZEtcBpnwQElmQ+
+12y8HDbYcjVyucjshdLrllyK2RWupQ1+dxOR70FkeB+1MV/z1BizUJKaeSRTfhXVYnvNjrv7BWS
DqJE7arFdeFhFZhnrXSHeuFqh6Jie7fvUf7eiVFCuBxbb9fPuXUlwcim+8ehFW0AZtwkLrxvDWmK
QkUDi0wBCLt9kFw/GKnrze1iVPIw6/vn/ud1klBtGPrpIK+GsP8u7W4NfDUCJ8KamTzGLsPZGfyc
UTG3w9UBOmVcazJV9YK6ViMeYgOgLg0s82LFHUS5w+NcTjj6hWcq6FTo7wj+U0MQdXPJ83RQXHUs
vG3L7s4yymBLrAV4FnLu9Mo4M4V32LJfdV02ybEfbnRXd/4zGDajpYuDfHZs1Nt/S/7WTytqKC1r
APyoQ+Dou29oZmzRmPaF3B4HO1/+larqndulpnyL8Q4vV5hiY+mB19H/wEOjLMPvTwb2SjRjYrB5
9CvYAVCY0d42uz62CvQJuJSC2rw03K3RQwVjX2nrwHtPixH7iua+DiSaenoQDwnJd4HikyFsTv6Y
bTIv1h6ouqpvN2YVPza8SnEEsNDwU3U5LSCRftjNhF9rS8AwXcsLkWWccpZ/HaCzubeZB8NJmgDI
nXOLrTje+xycRT9JznKWcoxnzLTXKbdlMyC5yuvxmpZhl3W24KWVtPZwXg/nSCZGuDx5KTbnxct9
U643H2Q8nBoi0Ml6Rw7Riu7iN3mdDJIG3KuQWSivZdK8GZ+8yzKyTrBtU1uRyEe/lkoI1OMNcpQo
jRbedFdXp/tiDg163ClJUMksdI8etDieJzwhRxpf5gh8/aH0BbYNOIwStl2JTfw5HPvIS+eZDTuR
iwAuWDaxfDaBwEWjb5s1bq29on/7R3/rt1c4C5JcMoKgi1Q+GyD2Ah7AdZ3nMLynEHbzp1a4RCqM
te9H54V3NHM68/Gkni5vgiaXIeFsYgLcWxXeaVm6L0wF9DN++y9yDH7RuCwHAbMLP8IfXL4Yk4f/
+MwoVICbraHSbpMSZ+FPSsGBKdwr2rarG3+up1s1yZQ3843YLCqisssm2V54FJJSZYWOkoO8Qyzm
QlBq7Cm9h9TUqsAb7mYyYK9JvXSUB4z6OGXE2tbWYGTtf4Bisn3wgkqRo7eodRqmetfCwTPRhTSt
nbzPEcTBQzNaDFjd77VGyMctIHX7+gc0PojtZvmNldHUktIYQOzPg/3QcGTNn5X97+tRPSQUGIMN
7R9alqpEO5axbXzG6rSZHyJKdMunMdRvE8E71/L6LVCE+Hgpj83mRQUF0KrijMBgprpKsZeQ19Uf
iqtbbo0Jdrf0fN85UG4dzweW4k3b3otOzeq91bbf7Eodg4i6QY+Uzl7oV8UfhWNti10BT6reSVR/
pj5z2h9hXmVvhALShnm1gqG10g+tqzzSlpB6/Op5vJL0Se833+wlPxEf+RNTQkJCXwwKd+WpDCXc
6KIPss2rA90Hh6AiFvSM3airU6q51GhQJ53wTQHn73CCTDcY2R9TEIk6MzXebVdME+QQ+Oad5XOc
oT+BAj3/lQIg026uzjMPT3Tm5L5N6AJ6aqLQbKtGptJdAfOhw8Pl1TKh2xstx82HeiXs/lVOsCpC
xHpLxkxv7OAK2CPpMy7Qo5lJafverf0XxZge69oZ306gSTCbOCNJ21eWpmOmlZARfilJ8G0dE+NX
gERuMP34CaKm6+goIAqDZvBWQBIoaEpJ667H3SPwta5nQzVoLviLlhnGMlpqR7lxR0jVOxTetR+7
yaoZ+4I7Z3Ahw1O4wjs+n0iGajNMsPjP7lXWxN0yATWj8go6oRHAV44PHuMoaOS9rQBriIeOobss
36g+FIstmriob7H3DiBsxgWcg/XSTQKQsDr3NfwTzguUartQ4EfxvT2/zahbU3awrwoSlHzO6JRZ
55bpzAb10jjXEZrJ+7jqIO0LG6qO14AAdNgyZqPhT0t/qbcLCaQE0/Ets0u39/BU+3y6vu8YCK3w
jzTU8ZjdHWhCu/vxhR/JL/OsPTc4C6mUV7zM+ZMJXHOa4VB6eXST3OIyEj+De6oIo1khZ95WRWz2
oGwGFMcQ9YfYpxK++ThCEfNFq+a2/DIVFjj3ArZtpgwW2GYbJdOSer9MEj8Kn5XU7OLw4mmrw6bM
UgPzwZqXiXTzEzVbpjNiS70v3DphLJsaU4XIXkpDD/vWENRrpSAL2+EHAca9PeRabcOTPN1U7txH
SuFKj06SvWFz6ZgtClTHd/9TVmh9qEBnUjqf6PBzN+gkZMGBm0QqUkFUISY5IDpssAf55ggmIGE6
rPL/yA+I+M54wbkQAU7LGqcSDAwCr5veWRiEKsgwKsvCe7bfTdwn++h60sxdX5BB8coOzVVBfa6u
6+ZmKISfjVeEuKwKxQEvn/zYZCJstt6W5RocSnJm11JhdBqlkpt3qQUSWaNRylB6yqYA9UNrB6Y0
m3tFr0dGWxWtO8qPjOFhaeyCJM/QWdVTFm1UXWTcgopPkorigU9KjsFMucElcBaJd1vz8j/65VJ4
o0Wgje9ICsKIMcpa7rAWX3smiNJ3uzzwax6kYowtMVtYJgbXMKOj57GLXtiU9vnkAUsK6KMshgsC
WFPenacop1hUSQVBzwjaEwtrQ1OybO/M9befCDYSl9lkTFmYA7Za/tXQulVJrLOET5BFT3T3+90B
w0d7shZjZrn9xWSVVRIup/vMxboiNNaEADKd8ObvK5pXM+IFiJ70IY8xZNzLEaXGj0SAeuAErHhx
SYtVNubyiqtV5jBT0tgBjFo67OPu1A0enwRltD83/V0cnNBAKYmOBt0EoK76sGx1j4GbpSWJANYH
GIGAo3PDMK0FuN5EOS7U7yrhG0fSGeloyfOjrBtz7Vrp6NXauAHtbSXkLHPjS2ZJG/8sgYGfW8pq
hLODiyEQQ7AWKyb7fP1hz4tWxrC388GIwJBj1QrfTja6NIC8K+TCuRDav4cUGIMMDwU/kU2lb3uZ
94UhpYrj4dqfe6Jh38ZHwGczaWhMHL5IwzXDNUX6wcMs3qEnEt1ieo9vtDQRfk9FzCEiyklqaWQ/
vj4wQWMJmSk7s+6m3RANHjWV7IDrKsNs1zWhtcaneSFToWzjnyipPlLmlAXbb99tZJxlueEKDkj1
gZHgLyRmMKeYkzHPT4CquuOIXSeFEIbzbMcAxR4QgKPZIlKq+3Z9xclPIMa9+1Ep0lomtXTmWGz7
7MuBQ8iNGFr4s+Oy8Yd48zSv8N7wEM8tBkRnXWkLOd7QaBtod5fGxpEgOp4wO1biaVMet+aTAIB5
1+cyv18wea6Wi9MrPhkc8puro/3kbb1LUDvgKiOgPR/gm7rEATA3fmF43twrZCVImdHhWTgiorjV
yyTuVc91J021EUzFDMb6jeVc8U8XIIeEolgMW/vwCibr9Q+4oGCX9JDXDrKnEaN+T1j4C8hQBEoR
Cs4yBD2ZiQQOgRQr0n8zeCqAL41avtIsOpOxR07USQQ8UxIqWH3IizRu+bNV+o7VNh3nw2OSscQX
/rO2Dkwiwoh5PezlBV5EiKaOtuWcknTG3DIWkCokgPbea0lMjQyUsjVy2GjrNrpc4k/6qj8RrPRP
ofLFilVJzew/QiQgWeHh5+trTY/A20//n94y628SXvb+WrOKHe7mkGSl3MvyTNnItWU9feQoO/Pb
nDBgvFXZYnGjZDESZifaOvh8A8fe3ypyCALItWWNCTp6bUFCke3bkbP7mNl72g3ASjx7CD5x9N58
QDLPsY7CBj+SeNZePZyaiVzjFSRk1wxCVmBRBt3RX/FMG+v/920MNheZOarDbcdJWHRE4jaLKrT8
i4ak3BuQtzZYdGRpHp1eYTORxdRbTj+njQKehPJ0+qRYBlbBa/0RtWXIKrRrfbNAp9Cjv4LR3L77
ReUUnAvbCjx+zxXlzaAdasSQkO1j7MNnm+LDhsjO0M7rOCvihGrg3cczn0fI1m/mFuhwDRvXsguK
LDNVROAxpNs2DMGC2WTFYZeOoZmVYWiMgQTb/CZCtNVTGgf/uaSIa4lsfKJPRANjwZGVSZB9TcnJ
YQhG4qIiCr/lKs9ZtI1s06M9Tb3wMAAC/chYZ8d1c8a/vS4lroM+/kX5Gta/Ykd84yLt9+Nghly2
qs0g6xQQ9b5bhKEYeWSUHDM2nlADDRdQPXO9x5RV4XK5MAchLSdAvtUo+0gWHdzLzhZV8utf7unh
sQlS+LhdGPb6TBiUyRg4dKEE9YJ45n4AAAUlI+ah+vXcmoxOEsRXDuLvBm+VBxABXxWDI5olJSi1
heDw1MuX62HIt83wcWAWojLcNUyW5ydfM0AgAH3uNcdTt497yLJ90b5xTvJN8aQ9c1I3doH8tz4O
f4oQ/I6exaPywsScU3a3KaqD0yQtUItyMo7MQ+czT73fwWjF/9p7ofY9T5NM7odCImueverFoEB0
G8u/JxcdPqUNBFis157I/LkTS+98i2QoXiA6SUSwgTLvLHvHB2QpbRG1DF1WoJdG82/WgKcCfI6x
ELNOFz/UvBMiqj5A8XZD77ob2WCBXxiW6EHBs7F8wfYgsjBGsq5qVXxpKDHP5sDDJhPhPH5eni86
r5pXB6iLqQwcVFF5mkNU8f3huZ7RHVeJ5G79YELfJqgCOxf0ZsoMnNL2wwMKJazRoMLj4ED4sov5
9gf0KZpBe7SzSKr5UCzSX4AzzezXHoFEenoZ1S7HoTKvGv2zrxCQP0N8rjZsYN/+uBfcFyttCp9+
W6x5ozCDW/gMsWzNXMo1pcfVxs+7sOsEF8YWZQ/boZcm3lJMZ7cMn3njsd9PpekplJOtWH3rzJjY
ceBg4INFmzqChHjogbCoJPkgASTSrVKY/q0BoUU9s2vVG/X64bM/TJQ7qefexmYVRgWrJmiKtnHb
Rhsh9uROc0kQAerTiaZ65GxsHKhgAtG1pzOgjIBgoWMfbNPwt1zk4q5B47FVkNu8Qi90pbnvz1lF
53pNWOf6b3qdMVrch9OlQ6dEx0B4y+dN82DZTxrvnxjoHhAooETLMZC/SHOM81ooMpBvmOUulMsY
cn249+00BCcPeJN/SG0hqRIGxWcQbVXKTpdme1QM0OhC/hTW7SRkIiPr/NYVxcC9yGhEnh3lkJOA
mveH6ZfOmsxkpNLL3L3lNlKptCz/KpIvUma8z9ZCPXjhei1zIeLhgfTI/ypAMJ3vLuwDlGhS/TjB
WYpTlFvK4VvbX0r6bWohDxV9gIa7UA0pbI/BaSZTwyqTxNrSOP03Q9Pt1t5kRH8KM5JkysO7F2Zc
RiRpoP9LOvBedlKHNI7QvrsyCjCyz+pArW4jIoZWxH7shaxbuB+KphJl5qpcuK+a1lCXa91Em3e+
DRmwfyYwtuL86nOIKhWmg+WL63eoOK9l6uqXfmMeGbd2Z/Gsms7TfQgeSlWK+wlUxG7t4IdJYIVT
DKioa5fIaO4FFX3ZAbMIKgS0FuK87vS2hzEV0d+vNgJUcX9KwOvJx6baGigdO5U7sXa+V74zJ6rv
T0sJf7Ybh7bspwtOT4o61Wk/cmTaJWzoVsQvUj5ZvRwwA9cZdAURlMFzl/Zsl7pXo2TfU7Sq1dfY
R/SssBVRAz20FzDt3wpEqgF3lL/ZZnJU86Auq6yWqdjyAbhJetfiIw+RQXma5NYc355icj3Khe3M
QIkg2654HZNybBnzS879PRAjefewRC2u11smnQD/VTvBUhG+sM0g4TSQS/k0eUVwiloml0s8jply
fSPGzt+edsFnTVwWn1M/i866IVoJI0lxtGThqE/Tdml5ggGhwpb/hFWxToDFqtYWWm8cGdWt/QEA
TXJBUpkfJGneBnmBGecER50S+HqEPAsz+dWi6g7BlTP+lie7q9DEufCSx0JhASFHPBQSWr6fllkz
Uw+th9+D1oWZA6F35Fe0GVFzlTKp6p2IRvNJay8jXD8xGXVf7GMEhaYuT1x3gYgKh1lelzwDVAgk
QzEGpd6g8p/Sa4txI6RnDuBei65iUDaJuzB8ql/qCPXpJx/cCZHY6E/QRKHmyI1/LYsIEtUD+57W
61W8WOUZR4/n8eBWpqgE0xBtQjmnfylM53SmNEzWh7mClpM8P0BT+Hsym8fFC6Fx+PiAu/thhS1M
cVnP1r+LRZJenacW1cvdfj9kay84JQXcdWQDa9cl46hd0/mN3aSMKgQwGvtFCIQTZq57QdNdzctb
noQKW5sX4pnw92KUMcoHBXfNBOdGcBhF8A8Ak/tuum9oy7JrlAfE/DbOwkLO9iHyuU+GiFN6Cnhp
15oc1+U3aQMUGFRkXEVYKzAN1co9d68Yd/2+f/drKgDq9GgewzhwVq54DZ/NiZMXXVW6WsoaP2nB
bdGusBZZO81TxUCDYbFxwQ7SByZuz+ootyu980MwYMxdl4e3m53+SI4S3Hy2C5wPPTBJMjg7IYdd
BSHgqFli8CtlzyW/dQS/rbsjX2U8uZ3DjrwVzBIU2LqCHvDBFc/q2TW34DZkUrfzFhLLUezU6f8A
Jfs6ym5MQceuZclpM7WJtGwqRPPYRYx8mCsd7PfnvnnY9K9y/Z2KLeEy5Wx0RZvhnb78c8woYD2D
f14zEKtvDlQIBPLFHOPlBP7dwFL6BCx9hBXNyrjlD57GZwYWxlFI2HwWU/C04PT2QUvSpQWFZLNC
fOOLPZcr7ImIg1RvaPXpw5NmYv0HMfaWGpIeiQmQZWNwlhTISEQc8Bm3o4snpEsjdWL/DUo9p8Wg
7TLdq0KCDV+6Pep7HRaWx3/Ojin/MdGsD4EpnWZvGMOhOa67lBKj8RgjPKl3M7MlUQJ7Q0xT869s
O5BqWtawB378CdwWLuSNM4iEf0wsD9tq0/PQoA5zCzXtpzzLhbrcAXs6/KOMW8E/vlBqglX5DFPW
Kal/HFRL3nSVgCKy93VGvev3m2cjxW5QV4p7a7AdUXk9vEOUHUnrk19zXkBBVhvRPVr1QvVSDjIH
AczCoStIPaPHuqlNjbRbg8bBb+IqTe33JaeGSVJ6DFvXIuO3I7reepz4ujl23y4a+ah1tJe+R0Y/
3DfVOQyFpTBg1Gwf9O93L2Ez8YKlAATRDmOq6iw4A4bE3PqG55MxOszI1HQNkSuUOBtrzfMpsPJI
GD35QBNHEuBgu8WZMw9TEh5x9v0cDG0D1hG+AgIs1Nn99MeTehl51UGTg2gznYS4ZgLSFpZvK8zi
dqiE6dp6p1usnuO2piXf2ZPPcJIoY2BwcH6vIyiVbgSWiwQhkhNRYuceKBJLvY8EGT1ABVLgq2Vc
pBZjhkyc4g8gFLv6E+hQhEUVLHVbmvb2hKc5X89/raJvQM1G2WNdI0k39c+QowRYfPQMDn5BscIS
ULL7RzlXKh7aUbBczYBYnBUKO53KtsUGmnH6vysNDr5Ha7AuZsRezn4mCKqU9BS43odFUmQ4NSWk
jdwBI1QQOXDasbVO+X6lDSlW3C4U8aAAV5gY1uBJyVtM/azDhqG4d9tYY0sOvNu3XF5bhdPCGqpF
VXKr/S56Erk0mxJyfUbpa6W08K9g7Hl3ZAIIyydthgYr+uGY9HouzrgPH0BRzFMNvO5Ym2hQRvta
Vnac5Lg+AVG0wEliMsoJ8ozTocTWGQoZIRiHmpE54po0mTUY4M5SNfWsvIwedCzyewZGBJyuisjG
pRjdZpN9XR1F07BYxu/3YGdWyE6/CuTl6YR5B01+2yGsfXNhfwmN0X5tRMlTSdsnejU8j70hHRvN
gumDqYagtNaImorqhemRCJ5CkpODBA3ZOLENM/mJXcvo8uLFUSZhtujwMigCrtQStM1KBso3TuiJ
pGzniPi9fhUBtcKx/eD4OLl6ZR78IcV/6zVERjVJnF3/Kxd4UcvR4dWmal/Lzjjr2DxNZIqa+24W
x3ieQSHNfr/3icuG4IX1jUnmOigcYzAMhBf9sV13xnmia87QXryfwRBKQoWg2UtYtp+yMIiE2/xl
629+3g3/uOXv0H2O/tJf88gKBSmEW83JrJbBU/F0neWJUQjx3rDO7eXehLhg8Wy/M1uSqcyyidWl
/dw8LrVtSLcE5UHDSyNBg38iglGTFBpj8g7qoBGiefqy8UaugBsjX/yiv5OPgnr9ePxeNSPFgK8y
rlUG8hmPSAZEcFQVNCn3cT7tBwH1Clwm3lehKCKUfoiA5IrUAnF5nOVbhrEPyqKWVEIS4juxKIhw
ozMlrLOUZBUXsPwp3OFLy2InYk24Zy2H51A9QWJiif3yRlg3P0No2i4bmvtiaYlj9R/AMA81iLcr
Udp/TEkPvIQIKI0mg6LNxJhZzpN/eChunA+QMA1O73dQa2OBnG+2tcvwnuXIyjCk8w6bRh7AgvK9
1bbsaIzhDyn+a99A3IHGbV1PIg4q0PdV2oJp+MRsa3Uzbwg+e4K2sWEdDDTvfQ5cCqrgUSCJebNA
oe/isfP7/MTdnYPf1RfBSWMF0lZb2DJeq3Pvoa3Qy1j5wlJEaNiqhrgMgIF9UG1kOUTeDpOp3IWy
nVWwcH6QTuOIxcdns7F7a0KHeavYxYxt9EHr63gmtnPaIAFUk9PdtymmcDCjhmjEoAhpXFji3euf
pi9Tzin1/zhlZTbFlHw1ONdhTbaH3S9gnD6v58ma6+1uWaV/TbyKXlDVAweYM8WI7zpJ0kikpAWl
1VJiFavZ4EyOTiamaKeFuOv92uCEl+A8Kx6WRrJUCC5lvc6Q/pxA3qXCoMgr104bYLasErW4FfKi
w3A7/7S159rNkzMTDvqZNMwxoxuINPfdSNJn65CENHb8k8BEcs0kN6Q1KbX/GU//TijmOPRumBtu
sd7tPsF+G94P7YloTWHJfWKn1Tl03wg5c9HAofZ0L1q2ZD9Vn84zZqJBjLRdNEzmWzIGqH6PnKby
ybuZJ7VpiU/j0Md7ReyLZD26xHgyYT5f+TF6A1QTquv3prulUlxkZWPJD/Cq9k5j7RxwlRlyPo1v
LoPLQQo/DvlYq25W3N8KosFQhSTXz/zGKxgqi5oQFPxw1213qKFL2DpF2qJ+T1HgZRKkvjtrsnsI
7G+rbeBsIEdp0ZDV0EA5CCzauBBGte3Q17kj4OjS12tytSXhye/NhiKdL5UVVt5oH3kMJ0SMivyT
8cnZ4WFHLvtUorLl4Q31RGJRVd4j6pAwzISKB+Rj9y1nVkEzW73jx1iN91MEC2vbeT3kfEsCNsWG
95mK+uXJpeyYT0yC6rfJqHg8LPDIeaZ9eLdED+gaCqBiofnogr2+LmEGPy5rKq4XLI5UjULHvz4N
iY2dsgvRWGZUdBu1GXQZZ/zaSOMeta2VNOZpyMqPZRO4I8plmdpVAUca8hTOgzIrSr1f4369CX4P
D5h9Oh5lJkeTpCGrgkmSk7CRWNU7rd5+AkcKnE0tf3gBZGyH289krBp9gvZT4NT4Nl+3Ap9IRAB4
A7k0XzzUQ2lCIDjggdjAok7bvPz+27qTOsXgnUUWa6Xyz/HZwgT+3iL5bgSLplft3viboo0DJeyy
NTFDccZY+OohtEKjuiw6ObpWlkc1LcUAJ9Ianj2nrQsxYdRc6jzAXeeUK6SrUfHezPmBcEZJ5cET
LeLkUvjVz4fsby3z2nEZr2RXVN3Hbgf7Gl3sQasIX9OW+ig1HSg4qMnPLaK0L5uDm3Zoi6k26VWo
NZz90eDpg2x4lpS9Tf88wDapEla0YOh9QrAEBHWRjddy8RdtZaGVz31iNnappectYntLFWTxKzJ1
9XECGXae2p4Ubb4yvihGfiRJUGKDPCrWdViuu59iaDdHWmexTeGjzqTdAnlmN9V3oWqmoIq+Vqhv
/xQD8EM+1jxcTpFVKR7pFi7TdHfhCKnjwV/48UguzcS4lJviUXbtGsw+VUxlpBGeoHMUrtvjVmSx
egAt2fcULIr4ObSU7t2hk0tWhHfaIhqqlplMZUT+2opQRfGWJ3G6IpqBD9/T5eXle6eIgo8bWNW0
lwFf5LCh5hRoxZ5uquwZ5Y/NoleKHpMAY/YQfBHsnHHqHxcq68JXdgzsDu1mklMHoJqZqTHC/KbJ
+83BNh0tVARWqkqVKL4hLFNcR/+RMwc2Lpx6+9HdASXq7WgkKddMYTfd7LS/+uv9mTHhit9LILii
gXjGn8pkOT9rqoyr4BnliEQ5rrguv0i94o+p4E9t9tZp6VXAu5PVDY9JsrtkkZT+i/eOXxoL9I/L
QnCItK4gXko6T/DAmE2Rsb4yjqNg3yxrcFlYDWh4bXaV8r6R4ZhDwOauR7dIMOyLSdXk33Vr6Zgh
4QRfHDpgwg2OWDdP59rmL4P+IAn8mF8AFG33fbA2+Q+5732Yl4vJk8y/l1eGx5W0q7e+oTs4zf2k
NwbCx0HG4pG6/TuB169wamd+xkIjFigmkS8bTASUymNlqrd21qRPhsiOzwjMjVVayr1HxrCq8h3H
XvBFg0/yIGWjakzk56iZkh/ACh6Z2akinjEAkh4uJj96+lgPxRSn+o0teJ4HM7ZJzZYy0XCpUEpt
beY7tREDIBEyZDJ4mbGDWbItzXw9UCpPoz9U9w+Qpc/uDYVu7VZOQtu1bnrihyd3PNoRnNzKrfK3
kihESzx57R/5u4aIj/9CbC9UG7nZZSeVvOT3Pwt1C5d56FFXGDtpStw0MARjc4PD03qfCVkeCneD
rrebWXDQtfDZYcOo995atoYiRDY7CuAcefM076nY776G+NeIMkZrBHN88Ex/sOmG9VGx0w6OSn3l
AlkO+/FaYeJ2XvsjrgLJ//qRLjaCDbThEZs8pLcBBOBMMKFML63MGPMquOrDRRzNDZifZJpcdKSs
u8CnMcAI+zJf5LQOhbar/iYczUpfVMVGthd3EpVbbP6sDRBNN2l+vR9LmeHKkGwPkNNnhLgDwG+j
0T6zsQyS2PzjClqVC4jdwfKkiqnhrrJHvANgJTt5dFGJQlsrEFHPnSnMzYpG5mIQq6OwzgukIlzA
YQChSawlHd3ztkmccyvZERuEiNqFPKkTDmAVSNnWLVQDrej8ZW0krjsKu9yi1bTJ36iEqbxda3dj
JFqY3QGK4z//sPkIbORT8O9w3IRsNvwcBvc/yh+uTufu7ef8GnzMmjr0ROWcIiuzPtIGXedegFg4
7Aj5ovL4dRGz23lte2GHY1NE2K8/Y9Q2Mf00hUT61GLOKfx+TSekyHxlERNpZ3xKpFuy/Z20nO3W
NhVafII9vjwQFk47+YBz0BXuGMSV+9A3tcffYwumy+Z73005z2qV9yB4zQQ1EgKuWKFmbOaQERBf
adot7mkmT302jmVlsOODv+TTcyYO0jAvXOCdzgNl+0ZvvyZQFH7/DBH7SEZGGrSCPPXEQAiBixXI
hKG1eiwtpzFKu4KKlPBOGo/tiQbNF/4ig5Q3yd3TNzYmoeI9el6575P0NTyusXFJS//CRJ4O/+x7
PxkeL4NEC3SYvDJHv0aJ3Ac0R1iZGV+2+1juGSK6FO6+eEkeE1XlLTomNlhPqqgAwYbukk3ww4Vd
OAU115vIyxTPHgOJ5oBUR9Ph19QEhzp/wfcVPPAcSamAOOuCdXydF/AI8WiiTVFaVlw3t/nn3yI8
5aG1xCAoZm4Pl8JFlLSv+bDgU9dFqQRuv5kMDzC9vxgxzVMHAVPduhFTv/Y5osDaazVTyEUzg9u2
RZ1BPVzg0qPBWNghhOmx7Vx/XijLgIxqJn3D5NsF4dnr8UpbvbPF0CJbm3/ZvEkWVchf59cJw1I2
9wzRJute3AAmtekhcDYVQCuELPmay8p5qfWUoKX/3a3pXI+zLTwNFJBP9BE46sdPyoV5xkL7KVM2
nGsuIMuEl7pihFU2f/XDQw6yCehEGQoIuX/DOMjawTFeBgslUAl4sNN4aVqwekPtcY7kdNEEuGjI
ywFF8hLLLjkoQA3woUhwKNc7hXXi8qG4efHpC+wXyOSSuBCXdqhgFGD0pzhlmYoSaKZIpzbNiRVB
3TA5HxMp4SkOx4+iYPJCSAyzNp7pqhgo7sTbmqmnO0Kek7Ifpx/Clc5cDbNZVa6taEpRoRtXz0WC
Q9JJF0MRWcvxAWfNi0xu20qCwXh02NjT1MCo2aPP7EPomCzo39oAtT73+PEyOEWer+7b7OF5Oh76
LSiok8XPRqyIsKoCxt9qLXYlEtQRMOS/qRvO6GzA55K/OWsSPhah6iYUvB357MoEVbVE4Ty7P2PG
NuytH7/rTNfswmjJrfBpPCDAu96NQ/DLHykodQTRRQXuRiIrd0e5DLr68iTdJVz2tBWI8qvhRzl1
oTTcC5Ue8uUzgFR6gfVU4DPsHrU7t0JPPwp4jNBrfWniU37750SKK0ljcgZ0qsmzCzWBYK2/cI8b
tARPhIqeehWOFeOk+pRsIlsensxy8Dgd+N2nVmeMqIlC6SZ6yN8fJgShdILv1kr7egxWftp5JXDk
oRWl3U8eVYUMcmJKo+YE0VPWkecSGU3eaBnzEzpy27jyFZQ9p0FKXY8O34ZUvpLYY7sNJVQ3+2KH
nC6rkFugiopI8oGlLK5YugjyRPGTd9nslsOlbbCZysTY3QQmpNMqovCEX6uGdgWu8c3zmU9e7voN
Tyrpsze7QeOSiyQc5Qr5+UJpe8QsrbK2yDE+5oT44okTxa8bd5Cw3FCyVo5tjMZ3va6yBFsx6Iom
E4+0aWizHhdCwTpuHnVosxKrLxA928s7FkLrw05LhGW8Y1g1RvpFYh67KmKViSChi51JqwLV8UhX
rc1tNxBUppm/Sw7gH5MOzzx8ijc6zIMu6BXiGU4S8fsWA25tRaVXTVwxwr1Ai5MVRvExplWZIg1Q
jXGGvnCqMfHJgBSIKPBMRsMREx1eV3uTZFNqj5rCtS0w2HlJnjV/3hnQXc8w3JE/SQYiu0D4G1Rh
CilJn9IkUMwU0w9/iWecxdhNiae26MYHMw3wWXsE2ajPPMQDAfhLCguuZnjTDgE8gcV9Zb8g0kKt
PXgSUyAd4NiJXhfhSADhpFwIOrJ097W2ZxFghb1vZpTqDPr3hYnEH0Eg99FxjLEy5kDe28srazp0
Z0rXgBacLYGztxTzrAzFr+t5H5wm6YOtI7qRuFls3w8S7Qjiw7u1BsvA831G2y/+5VPqoC5n7ak4
DJx19bGtZhBNxWfMS6I3UAuYFvjV9I37SsU2jKleYRrsTkjG0dWJ4OADB61N3V+rDan92/bQWEn8
Vzo66QRBNUhYrjVJLzIyTA08OTawdoR7FktdefJiuYkWekAwsPptXUq7MyrMK/MyBYBFLgE/6Dxr
9wsdKXWKyYljXcCahzcPHsoC2IrR7QOCW4apNNBKN8DsvRKEAALA0cfPgHsNooLalEO/zc3dNeMt
7Pe6UIVStMvOaXkhG+rQWbCzeewmGn1abLwHf5jdmG++3DgbYB50Sijwu/8jXBcQ/9m82rbVmb/h
nB6HNpUV3x4Xbeqaf7/HjkBLuRetYHGwTuukra22uKUYd8/WczW68Ybp0k/S3wca7ORHpkrPXsjm
gEBjKClHUj8jZMEYBAykHNdZHIGhgmrAFIZE6MqKo1fOVybluG3KotqYR/ui5NV4juWrHEiDJ8JH
4tGCh0dGXuf0bMT4fbq5bV6nhFCU7WD0I+HtlcMgMkS6PBp5G59U/eQj0bBRIR+e5pc9WJ7K80t+
x0yd05j9PkM2cPxkwaCtd2kj2YT5OabQmTaSPJuG2d2f5mSbMMZJGf0yFdhGZYLMRs/R3652mgie
Tj613abWVud1ff6iA/gUgSWUtbFeDdPYtTj50hfJxrkxMhVakb20lRrsGdQfqiNWbQOpLtnL9fkL
a6oxOq2BORVcXEYR+TSKTsVzJJX4km+VJXIg9CsxWG/q4iL/BgFl27fKoQF89EQ0JDb8qxhdvM5V
81rG0HjJsyirm66OAxBizg/S6m9VVStVs10+hK25lcjeZHROrfAjWBPflG6af78WFMHoBb4410Y+
qCzbyc8ydxn92riwEtSrncY9YjYVsmKJRCQwvPHTj3Rr2WMxj3tuuhfvC1k/RZ9jTnfxck1B83d2
b7dleJ6Chc6Cf6gBcIQyRBmIVkZgUIDIxLXWQb9bY//6mXTM4nJSyHFMEHj6FWuqhDIow6ccteNH
tHpJ9XS9Zwq0tBa6OK91FpgEpWqqPuOgK0xEQLkd8i+VJTA59EWk5rLJjhJm4f8JNOjfSXO3lZ59
f0bynFR5rzvBif759801akFY03cdgjnrWu2jnD2q8l0HdIvhFkdt4O6uTrhnkS0gEOx34dPBVVle
yirr9v42P9vZU1WvypMuPu2decW62bnUpuc166zU/LsTCUEBqxLVTTQqRC9hUFyeLmuweYQUXDZ3
XFfL1NVRGVzz07OeRc2UQk1YEa2JUqK8pP4c9LSsUm8CcNqd93D6HKHFCsQZXgAaYrQ5T76lmL1V
O+8cDWOlq0GxRmDQQjmS/NuTbU36vNoBZ1ZgHkRbuc2mTtgX4lDFDi8q2yLOO7U8Tg4dgHnJqRvj
WFzovZvFQGePwUkgk1hEo7NAC0PxaOa463pcUFkraTOJp5pOgGbIYNOtDIZsgf4uBu+kprolPckZ
e9lxoXqUTaK+ODeQ5AgHk33JdeOSSuNd6lwXLYiDPYFZwOtap1ROf5imz0xepMT3LEGaeV5iQ/Hl
9CR1DrqWuja7T9brLWWVtqVtjaut32sLzUmmRuvS/PL4NaxMZd/+pixk19qm5KHce7fkYmPqp391
yqdK1Icn9uOzqNiZ4TnRD2Zw23KiFriQIAKTQH7MUhHUG6IuXpGJTi6mcli39+Klf+9l7Lqo0dA6
7yTYuKAWMoZsigLKFqCVjLMovZkHsVrX1PQKWCVga8aJDpuli+29CtzyfVkbGzqTFUik+hG3Ubxr
FApmAD6nPsp14m9m3MoFqIE1G+BUvt6/N6A4kZo0dzBhQakulvChEo+OIjJhsrgGYHpLCFq4froC
s5PLEtg0nO8iRgsA4K62N6Y1rQ3vkO9X4npRaLsbnIK5/AF6JL8wZILBAmr2oXq6P0hNwoHmNQDQ
PGp9xaT3+R8aoIKXflYdSr9bgboCFToLRjh/POCoKLYuIJ7wgGMgwA5a8D52hNatC3Rh0+x6a/Z3
bH2GTIRujjQ0ifoZ+86n9vN2T/5QO9iKfCfZHiRA7/UOKyLEyl7b+6wLTM6VSVggEZ4wSxBK+wey
mPcyIYIvVtKPY7Eex6x+2rEFNEtqyf59j2ZE1Q+LIY6DX9DlxYwYShaIUNLNE/VxwO5TFgLTMmJJ
z5TwT2102FA0AUasufrHagArFajfLoVQ2Q4JFw7ZHd9k32MxAHa1K9gV0TVvwc4bvEXoBLHAneMZ
wZtkIqGfgW8TgmROb1ijmu0aAUqvJbKtIZ7ADNDEktUZPWpvJBYK4MFRXqUvLClxR3AbVfjMfl2H
Qh7DcIo7Kve9rfsUjaCYEYMqu4BCU93bSWa/+v7icosYZBTaOm8VGzea+be2xIK3dcANOvIkR+yr
fEMKtjT3SzOEz2F9cvHSFazaua3TfxkMMFvKfcB7csur5JoIz5uARi3DrEF7vnUNFTKxfcd1yXOm
aZ/vYLxUdkCfa55iTYG8rW72lKEQnl0jsZy7d7ipTuy1YVviG3Ub3qo4Z7bULjYQI3n0QOa7+vNu
iB5FqhEd1wjzMG/CUdYyKfygcMDd/0k7+SckoCmzY4XBN0gOLhSyOAburVoKSUTwrRPcGTW9IjCc
Bc+D48UoblgomkVq2kHY+vCQr6d7MAvq9+Idh71VLT3yNkY+XmOmVwMuTC6oTxyNiGb3uOc4aPy7
K8yuE74Ah6eY/E99DH8xb1VhsmTYmXgl55HaJXVSWRjoLXdo73iOhEYYPcRnoRZ0jE8sJdXFja6L
MWmtCRIXOwylGo82+V+6xOs70SBgul7KOBYlESLNjLerKhflWNZyIGuM+Zz/wEcxeeG1kk9zYVAx
ZYO3ZP/Koqd+KxSZcjx6I7qci7vzUcIguUZ4W1QqQHAd+8o4Sij/FQg6lin+o/NNYeACSkC9b64E
FO7xLi7lk5A+FbYKiX7Wx51bc+aixFnyxUtqQwM1tur2r1u5RMAgpEzF7n0h2SCLiLP3IsYV9Zt/
mMB6KqsLJEE9qHSipRdLWjJJ/Q8MShMsEA6d156l8s+FkB4CQ/eXphudmaqXaqct1JaRNv0eoFUm
IlLgc0L9PKzxPWbIXYESH3c5EeOsATRp21XDJMnbJgaW3HRdrO13vGhBVvrNTwQavX90+GbkmGV3
quA6sWLhs/OneP/oo60EV+rqdvitOJidkCWZhzA7A3IfS49HLkb4905dk1+6gWoOO9YIYFMOCNXt
pLq97LGMRyTxA0CBC2tkg+VqKUsYKdTKrnI411aoGL0ZsBlgUAcq9klzQ5KLkVmTVUVZaItOSZ04
Zr4J39cSPrQHlUpnA6tcsshsPbG7S+i5LTcU02c4dWDn17bEfcB6Aflxe00e+cl2m97IZGMIyMwY
eqV5q7S8ke4wA63x1/urOtlmYusHucu0CF19GDyyiHD8fgR6OtIrdsku7jm0IGVuYm7khlPEOPnv
SnFXW4tDdDAaqVXKbVwAIo9cE5zyqjKWsfjisfzmaiTNvn5aE2CLomQlrpQsh6kWYnI+4A9JtKc+
o/2qeDmE2fYR4MNGU8xjw6GCyqX+ZJ5YAGQzQgkEeNEmv9RUjdoEzwhZdXd27sI3TRl4NX5v+73D
ixw5yHxoJQ3r2egNjAm9a2SiMeItYDr/fRFMKgDqXaJkSAgwWUqO2OuKCGNzXlIg8QpOHqq1s64P
A2HQtV7uaWT0MUA0+VE46Bky+RAb0B4kgiX759yopuY3jt2b0I7/y3z67hBVEUJ6KowQBRe0T9zt
uENeSdnt7195NVZmID0LT8SaODhNX63y3ns9N+xyV7I43mzyG+PSzXbmBCDC9L+tyLr6i430OnG4
tFX5VrYwa2tlo1e/hb8UGL+mpl8DPT3Jvi3MqvRWYymP9NZPDA4w4kt34E4HJQ7X2eWlXZhXUJl+
P2m/6vP+T7nksU3Sz/sXzOxW07Uf/F7y263WST9hv7M2FMN0s7i+/gmKpjtNmVGKUIttT5EiIh7J
ReeR0Chi84D4dzh80b9CLu9Id4MxojGrhB0NTWlzb5g2FLVcZ+zWtiAD9lV7/WhaqA2cKQvoKH50
5bN4Tt486OntQVHWzq5yo+GQOtyioz/j+omMSmarZR8uSzvDwxUsGnO70EmzJWdZVGw+iehfCXEz
aoUn+fDLLUteNjAeJ98MwVCOiR49VEGydcl7l3Wv56b0oFgUsAkSW6oB2WgCL5nhSaVCW+jXkf9H
ZgieDo90yAd7N2CsoaW0TbxFpajMU1F0ofbjbu5WHoaBepN9r49vEK3rlsTLIVZf7XI/sC6AF8bJ
7Uc/yRgGYicE32iOIcA/ZHOHOpzLSpChk0F3ku15jjcEwdDBHTY=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JoebDWcYlkOHjvU2HKmRi2IPq2IKfzMyADf7ipQmnq6p1pyLMzSFTP7/1XG7M77HOVM3SXm9S+gQ
RlzcwV6biA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
k8vUULxueW9U9HcziM2PT8ceHNns3t7dzMLrZ8seoaB3Df8Aw/Ovx02qwDodcfaAe1Fwvpwa0wUi
PE+Pg6GkAtDElsf3YNizR5k5kMtCKENPRgHVaTWrSPbY8oeTfJUZWltxgCPQj5zwlFBQcfStGWIf
yrtaXeAZ+NdzXeZZyAE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
L/xMMRcKKAGVNmFjHVcsXDvECPTC4SN8TfnHM+LUOFOpNppp6SVz/TvXBvZHk4BJTGOf8HCvpqWr
b1t/WIlalCDTK5H+8vScdsSearVTAxauZI7OjMpsvbXLIUWdigqfacEdnuYVXKx12D9mDQCGIfJF
93o/xsOPIPRRrpS7RWGCtg/knXGuNaCNGbmNy+t9j+Eo1nyonSdY/0FlZqqMY4ZkSm2jCdx0cjBs
FiPnGHBZEeXCAoOxLXtzrVDuQYE207wj9wnKUvLBVg9CTtzWxClhQdbFIHF+3vbqbD/eyzso81dU
rvicTcxBlmUIuDFcJExuV3OjUabyI68YSYY1/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sARaWuxHivXyPa47+10U3MJstnjV4iU5AQbQxAOgIjmz9IVz2qCQ5udA4GXsCGUpRpP/kUqwdma
HPjRLjXKbF8bgOvEtPo0rt1bIFXIVWV73qTIOZqHDhYEQLw1uY9FfhslrS3GMt1eYFoYen3r1m8O
UrF+deTl5nqkO7p1UhY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sMa8/fGtZNcS7csY6TeRUT184AxeAxezcclVhHDC0qumeCFV4BCmqmBCX0ebxotImfwNdBzo9bED
CUh9TE6a7MvzZ0uAR8//DDHYUPH2llx4fYYEqkZdNtVDgbCNU8RgeeIUbsobqcloOKkZJPG6/tVu
dgJrJnvGdMbU/Wz2+1hxmfbwVRYpm9hxtyfoR+BIWNfJV/WlaD5XlRBWKUzHsLrD5PmQbyPqCXmq
AA+qetLtxPXUjRZmQr2QQgHXgTC9PCkIRL69zCeiy4b3vqNzZ1P0b0wZkX3RGP0tzBrZq8ftLC8p
LeONVXizO7QRClOpt/hUJADi7wnOB07MzObKwA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37088)
`protect data_block
wXzPBGPafsSCrAw/gav6XYVMUUPeH44+T02ep7By5B84eE32MM/nLGYt2ZZ92bAUkMaY9I3dOtCw
IqiRxfuxq5giklBdocF0tl8c89iS5Ngf1ZuvHFJd9oqmOljqQlTnz0uU2BYHR/9sKPIw51pXUoVp
lgd7terQvYq4bmSD2a0toJAGhDoPW4r3BCGa9mt4ZDgav7WcqjynOE7C/8SDAMs2ss3O0BCdltdU
VImOA0uIhSBo9xrK62+czx+hsrrC6R+NHeGO/Gh7bDOA1tvyShRNeHN92AQpCIomN3QNMORl6LMC
WtKKb7CfYTTwzNcPTHmisZzxynoSGFyn7vRQEewKS5yGcUJVVFs8Clz8YpHixL1Y9MINIRorPCwG
zFTAfNxt5x/UilpUWrYnv3wR4/HKUoHnDxumot8N5MlonHhKCNkc2DNfE36YbQC+2oJwSzR3K/ZP
dHx6uf176re7y9uOu0SW5x1GQrXyhxNTkc8qb7WMWo8YTIKWOH/zyo5mz3+u3Cj8SiNWDtu4UwCR
wJy0ezTFbdLhshpxQl7ze/e5K+9q3B9gIVLa9vMWEx8pk64IC0c0GlRd5bbWHCuq5QYxrXczkH0C
l6ZFf+sD7h+HLrWdkzfeF91zKO0OcRwDxRGpWy/wLETKnsKhFjUvG7LOaCWPrGLozi0Oqx4+QgHr
vN9Y/mPi9fhDiOlhg3D8xQQxbKmmAmP4bo0gbamA1xgbSnFLPY/Ce9WF+rYejQMEGUMTnHt0a16h
XfNNQI6Gl0e1oUlsbc792ualM68bTED9i0lMd+uI+/9ethU93xfutMWhgMAGllZTWhXXRlc0QkjW
1modRc8Grz14/e+za67vJuI4QivWoDnnXslyqn79du47HY76Wd9gEqVWm9ZrzZwhqX7KcBJbcBB5
8po4NFsqMsOTMBPgghLdRWNRD+G8SlhvsbfdzlZCaDjvaKuycifqc7ve2WLJX0xd2+mbb/SUyiH8
VNYPVl3phWSej2gEQlk7ftN6w49Y4eSW3foLJEW6e5krXkZEyCfJXLUgaHPReb5uYkYK95ssnoi8
nTfkyC6gxZCjN9ojOIey5/xODMKz6YgWTCiq5VFDVfTTVJ4VJ9qaorHHZW3sIXRXx0NW5WVUCN6p
5HsmHbMgahfNEu9V35Zg7BSDXbJ5VP3VjBBbLYvS/GMO92LF6w+bwlnzYtp2kwQfQYzgmxvRNlSW
CKGxqvqn9mrXrZ8vpmrPz9gn4k+p2eJaT6mhAojC5yen5or1Bs6Qu7eiKfRPRGUFfM0Yae9ylTOt
7xLzb9VDD3TPp4Qp6rly0dKH9z6knLXJ4XUBqNtLMtqFqK0oe0/j7xSsrL2ZRW3/LQoYPM9V4Mgz
jyoQrwklahCe8ie44ZsHADVLD0vRu5YRarpo9yY9AE+dkbEIhA0EOQSmYlXYBGgMvIVoatz8iJ+N
hgFbXcM6tyo/t996j7p2ONLxCSU6hXwvwT2wXT6OIm3WI6etU7V4I02Z1WzQ+x7Kv7a0ACp206B6
ZQhHS19HLKP90yE9SX93zNNMlY8DnfODHk6hDNF8tYqQUP75IX8q4abVwrLlrGlzCrkau0dQ2+hB
dHGG0K9mDhWfRsUBp2ZryMkQey05nePAZ+xZ/+Ymao5LxoALWNEre1jZLEoZGaEqcjL3RACou4s4
0FVAFCoycmdXg5va9Ss/BgKoJFNyDw0qZfVHfaJBxKCfei8bk9BM8V0fzkPQqsk4gUIJhGyC+zDK
buuVoedQInsByXm1+r6pWcqVt8roC11rRK/lXYjBvqbVsMJdzLwrfFnZLMWV9uqAuLGz77mUJQnT
cKjxOlEFlXUgaTs30DCEuNDymLNuBeZxnLmwby6vLlV3t0MXzCA1B3ynxPbkq8F0CgLxeDDtp4WF
HbR5I+rcepcBNjtweT9/a7wnffUD1hB/TklwYI17YhXDJeQ8n+DBjWJyFDBq2zME4062Qoaxvrny
JqY22aNeFKr/JIIbYp0GqXKPdWJ7DLihFtiIksecpzwTbiCxQJi8kC6ZQfvAxIyceRmC1DROLE0p
foB8VyFmZQhKrYhjuSFc7P/3ElCG3ghWJMus8WxdNhl5+eqmrE0+cPxt/PyzslQfS7fJiZ20i/4w
Bz4Yyqekw6IxRZb+k/+gpQONLggmGZCbNvs/8Fow+wx5kP8WzF4nSl8/ChFcALTU1xRTvtUGrgsz
/lrs27HgnFY2XJyhoeJmVj9uVnG7kcGELLejc3JNFHK8GGmK+rHkjt0IyzicoU8fOzHtoGzNFsYT
Nt16kRg2YaFsKawWE9gJb5Eu33J2NP7P3Ff30jW2Drs1o6Y4pbOvpMvdxiKfDTy8nt+OeO5TW0GK
B5E8HE8Jh9GKaxdcOy9dpbvY2y06FB1CHG6rpW2H/TGSZrRjsS/SKs/80gVEgKHww2x97jRpF8Cn
7Eiv9fD9cHd4BXDQ6kRFPip60MB5PY3VQwpUdeO7LeHpAEQbJqurNpb4ZkLGfaFGQwvCwTbBTvX3
a4Mo7YN7UFx4T/FteMNe0iSq4UpK35dP6Ut1hMHJZ53zojiwGOyT3Deyl1D8H9gBYNkCfpys7PN7
XHLivSXfIvyQJ/ZmQ/KKKR4VsS8/fa5RPGHLkBS18KW+MoZ2HHdLmjDUumPIKCH3b9Vifn0yYDur
PKVQngsvXhCNVzP88gE/78AJ5D3Tg7sjg3d9mWC9/xql9jBmqQTx0+s0owXlM8PKekDGZTGs4Xwt
B+H9LoyB9iWUzO+H3koUmFqwENZt7puOwJ8vwX3NnMeMWHZfQSWtRh10hmPap7M1n8x6DmsCEqaW
r6bAv8iB6OolLnf916g6JJycocFZCM8PeLF5r66kdNGGPOmPnvUNEz5iVQjAerRHnk0wMrLqPBAm
+qwat6tIQxc99kUAaQynW1u6n/kqoW55y2cfm4Pqrkj230XX1rzx4mnB2rhITinDpiwPFzjra4cI
0vLS6vBPuydQfbNCuCQ7RP5HRV/reJuJ+ITVHKvi8EQ5uEewKSF+DgatCDhQ8ftlO0BXK0QZEYJz
IvyEKqAoiuKIyjR7b1k6IUz75weQbmlunRrMjD1Jf6MH/OczSFuxUu7X8mxyXz2V6PconJP+8tUU
ge9fjBvUrYhuBCxYubxfZVCVNCAKwCqbaH2TmPh1h/nqdM5tLPFHWGKZcaKpwWDbxLzkykrLSDXW
AZ9ohXteU+mX3TPweajRfRc5R1QOQ/tzD01zIIEhKCuGdoXbX2UaPnGbiaRrdL5seGjlobZE8J6k
eBY0BXITCkHVNVKn9ycuMgt+OZq5BypsNGIbTClzAUU5fscvPq6s0d3xalhNLJVqTUrVWJGYGFkx
hnVhD+9aIhWcZ+bAFDBCqD1UnoRJEaxJ5wY80h+kgocadeNsxxXfYnmBj10aFLLiJIF21QwVjsbh
CgVJTIOgT/+RYlSr4K7EZqIy67ESSMGlYC8Lxcd+QdWbuLrYCuvL7M/ppTszKZsKjHDQa2RuK+/e
6nnt0ylTWE3OnMugaZk2X+7icLkcx+X+EOloRJJPgwH/JKEisWagulUsbIg2mn9LhhBkDfDffv33
kYq7stqcV7AWjxUE9yCQ8YP/NKtBtz6f8JbZZ/Y7+drG/8ag0Qj0IcjMUe3k683yfmkjzHGOvbOg
cp27qN44BdxEh6O9waPERrzfBJR79pa92g3zogjd3gFVZp9SFwcl7WRkXyFnP99sP81BW4hlD2hd
wnsYUfS5Pp380CgTRcHBISsaywlPSFOnAna8C1HbUNXJI8e2T0gH1pnj+A360zbkQALVQ6gKuIR1
LhgqEXa0ZxjQ9TlY1cdRlrrOp8Z2Lu5PyuAqF+eBWyMGyt1YmXa3Bmm4/+VyHlVBv7kiqSoJgrGR
jvukUZo0asYRiGh6Ru0rFEMO1ACRQ0nymv/Pla6KkTa9npwHRQaQS++7T7wljIa46keYllCEs8+I
TaX4Au+SGt7LCEHJ3QFxlY9y7n/oaqfvC7nFBvBI3Qg8/7w3MS3vPaRauXGVL1U6Xo+p/8wOk6cN
9AIgN78P8i1XnKEvC7MNOvCA391XL7cXun7QR1clxqSlO+viTNpfu5n9Blx5dNd3306z/HXaVtS3
7jYwjFO8EuU//Db7sOC2lvWoLylV+fgT4Joqya5rMJiSHt8EH7eHNy0HcTFyqFi+LpYinV+jkQII
h33aifK82rveL/a+UeeMjnO/mbXleWYVAqLEq1fUz+3W0MGEV8AoxMR6veibHnFmn5O9I73q6dVV
56T+n56PokQMCy+KtbF82K/2a61VJpf+E7AoaFN0xK+YgBgoafg0fqIKPpL2R4UyuMBAqhN9iHUq
peM5YZ6jkYerB9OSMZd3Wwh15EaEJhEfWY3ZI0lqRLebHSkYcqlJgG/0j/8KC6+GWN2d9ZKQSz1L
dvb9iSZNCRr6u24QrTO5WeGk9YoG+G8dLSnfjXY/4AU0avCebhGT759MEw5m7E6C2NrpaAuvC120
7G5M0MNfr+3egftrpK5/viPBnjLFqrbB9H/9loWfMhnEFHgFt926oVeSf8UcAFcNfzmuqRywUqd7
aJDeQ0bMR6GUe1jjwNr+kJ0DzjMP5fcKKum2XGLVkN+M0uzoGL9a33nFzPjLphjH3rHjuWE8mfed
s4O+iaGUH8ySvrrmv6632JZvmeu9u83Jgr/Cs2dTR07+1hufGONyS3u5gSsBvw9wsyaKSeERTffj
Eh8Y9PoQ4jbbYXMXDHNd8dj6D2aQStFB40XozVpwMGpqQRbYyTQcbWJQapOrYF1suckg/vbvxAyx
py/EUZxa/MputlAduaeHNCYsSM+ZC1LvcJRmhAqzBCyYZ1iqeu+m7+N3TiPjSMvPsHwl164p1qi7
fo6h5710Wzv8gCcHVjHTL2Hq3KfFNqMTnPUu1pp6cydxJIgD94tCbsrOhKDWWoy15Xvra4l0o2rc
4Xjb4ctyxtIEHwW9qpc1ujLSp7NljkCJAgBf5a4+5iszzgfKx1AuOE6B5iVRYMsYxEchTbCUAzNo
I5CMXpkobvgbB55zbzEmF/SeEIowXjZWtdd4PC7/bSiG/N9aaC8Bg1w1rNnIpZQKVvtgtfMVrA+1
oJQvEn1pDGk1ulBMCAMUzQy6nyNpfcFkZmaQ2Z/P2F5LFGa+TIyhIzeZq0IDdJUhJwdglrSrFGF6
Z49547t06jpGLImY9adNysusf1zOsSQiIq3hCSZly1WlaF1UEHAp4PkcPVVdu+JikqkH2eOU5n0e
9WZ7CRXWlcFv+Q0b1BPE8dIvUQLHFN5+d83727W8+OpmsRs6tOWqw6dwm8RG5Fp/JN7AOs0tORcs
xKoyaUQ2DDJnCneIZomBREMnma/WREiuhqdoumvO3/W5ug9opIfvW5qk+Nxw1ODydwEmAQKAczUT
3rb5Y53+8DNqDKo8yKXfzk7NnTf7+d5IAxDeaase5dSnYjJE54LBC7heiLVtvEZ7OkfaxvN/tdhQ
VqF9+zVws/S6QK64LI+ozUgO2OTJKNZhq+zSabMpF5zf5UmrEchGD6/w3xt9q0x/ppprCgl0jGlo
8PQ5miLICiOolP9n6JgqF4gD3XkeXY72nX7UeLfnIGPLTw3bk95nOfucxX5yhpD8DvKWxUiA495A
+tBsmY4YlcjD8pLR4BvZ3TdvXSDO6vQFuxfgQa/1m1OcNYctjR/m8y+/BDTgPMdxIjBTUyhiAJfS
PnkAKErd1wdtWfLy1QmDe6vqxXBVavZBm5YqQwb64aosR3JBwUEUNQTRnR5X7FepdE2ZKDEJuTzw
tp1NCqWq2VF3RPxxAK5LuW/UUCWf7Hy/XykrfiIoRS60hVgZPprbuAlPVVgkm52NzXaoIHFvasrs
dg77uLmTpgdETZMgd1vLTnC1eENZWmN1g0Omeh3A0PCoSm18n2mtXHMpF87MWH32Dol0CJQ9Mth+
r7jjmisEw3CToNjJlJfM0jZesk51jnnnEm9nF3aU05EIk95HCXzn8skIHRDekoBvbbGRQLmjNIgW
qJnNp0pWL/A/K3jYreexX7dv1dR/6pXVU/Izh2n4w050hW8D9si5/s8bLBV1BYAmlk3SwN7ICn6O
3c2WQmKHaV6Lo7anAhr1Xhju6IQgE00vVqDfCXTesuV375k3aG+6ZyivIsrNUOfwmuJbNjR70SHr
W7KVUh8TLyzu7KYHp0ayL3VNl58ZiD+OxMhjxuYAdy06m3Cb5froUnN7pfecS0Siv2F6hURWCaPU
OrydoYNABmypVshNvpK4cS+9V8NOE57i/FLfaEycx628vTg34MHy8z43R5q2xuk6pyRtgzlZr/Qx
Wg700VGqMNktmG2kW06E8t77qcanmbzRf1XyrhWnso4wOi7fQuuCSw2/KcUO0FouRLUw7Kwod3jw
CF7dOOECzAihHt6mhCkklHN8kwJyV6D71qWgS7ZR2w+MfqEklxJBIpI/OqO8ITAjFalZhLqLsBYZ
CLoArxhzjIJbL9NzMAKPfg3Syt7RBHjrczyx4ETZcN9W+p1TZKnBDJBEGHlav3unCfJkJb/j+ipk
IDYVp4dSHZSanxBCspISyO8JLonUsG8vEASb6y97GtkK5A7bhbHcq3QzkPqyrRke687U9L08fv/A
QKLaSF/XJGg74qrZBvKK0GxY092RaM1IDIPOiv5u5faQvuk2PM9dq0YDkWRgCttC85NEfPfVO/Za
Q8QrMRdxl12h+7CUJ0SXY9g4V9G7CQg8PK5rWmdmQmyVoPaWU4dBn18KZQdemcBPZBMpdD4KL1dT
Lqeynr2l0qgcNbdW1KLm0HgBh/NuOt7jiTkO6Bbw8MWY7+gvEptxA/+Gs5hyDZyUkA2qSj628it7
Nv9IuLQGgQ3LMuJeDd1Kih03eWyWLawuCTVJLO+LbZPYsSZMfA2gCr6s6y1DoXhbqI2mLud6M2gS
797nErgqEnQ6qI8kY9Z4undWjKQdAbe5CLWaUrcc1JwjlkCfP97b8MZLeijcTZbC6KmBatQ1Galu
9KZuiKHap4o4vt9lVmaJTadG6n1HEL9Ks/IJ6jLk+F/YBvc5A8dg9IWMUPdipoBCGALJeMm/pe1L
CQfOxeStgPCiTjXdW8YRKc0WMSM9xKRBklWa34QxYMzXOfBhE7XsUZxWdh+IGq7yl7CYCVKQGLpK
YOClffHW8jNpHiZju68j6qHuOonQt+ryE9XEv2ESbKYLToPHA3Z5vX0X8bbRbLpqz98bukklgKrv
/daE/XieY0+UmJVOvUI0fRW/YI8Egb+gzF5xgCu17egLouOGCploI/LkS+OIIWTNYIrV9trfDZ6a
A9zSHs5OmgIjD5bRo7ylNg60hp7Ip3VrZQCP/ZdGEmlbUSSYpem8Zs5vkOeBhuUNjAV7PZ/89Uiw
a2XPXBxrkCYfr+iRt+NoWuFaRxhe9vGMph+mQxTAopqMWgt1Y3cZwYz+dANFTjnWhvwv8xolFsS3
1IKz3QMVhce0DkTpVK1P/lBVpyzejgqy4PFSdsOsrod/tFSvMh1Bz1VFIOFYA+bcZ3cRRNWeqPUf
933GgvJAEHEPutXWWrkRIO+bsuIg2fyBbDk51e60iGtWZQl8k9oRQGJGOPKDl5mPaj/rPQw+H0fk
qPeO+hQXjTW9TvbZZ7ALwis0e3KMZYp1YjUmmNun0WSjl+vdH3oiBeQbxbxoIMAMK++iSCG0QzE0
/dBDyr9xn4oK30EGlfSZfjaNrsSMuMmM/Bp8J4ILIHsStRsIVtN45oCCQyezo4CMJlwd1iTN/arR
HWUQ+3URZ2OxC/CgYjIQB3gC/bRBwletXAI6j2W69A8eDSRrexUuuddf5klEOYc1uXhNGb9LdKtI
4eYQoB1GxQVOGCI4do/yOIc4ZEzy8Fg0A1IYOKwUsGKNgXmFMqvgK0paLqd+wUQ2Raiu6m0U0PV7
c7w/5KSSueKCPtNVBp47PTAoDr4tm0Bd3CdaO/1Q8rdm3CuqTkAAVoiiY/u0iHcgQFaCQ1b+2Max
LDHvJO4kkN0ZUT7kTnHtX5K+wm2J2KvxkC90DM9oOmYfGfjpL14n98vdzx1s9s69F5ksI3giFYxT
Yf1srKn2o8uELB12X+OHztNNR9gLvuNsWYO463+RNLXibnfl79iF5zjwN6/QC5ZO2WW20+u9PxaT
IwohjLgivZyY8AGgXZJioS71YkHBWiC56pc0ScUoRkDiGylY2II2X1AcqH4t75nWdJX3phKl8JVO
RgMmF9xi78Il254xjJuVGnUOuGwzhXyJwi6HxKuTdF3Vf3U01/vhhBpRm+Sxl2sb8KaNJ3VGiREz
tWwoXY8h9rABvQcEot9RBtOWA7vD8Uj6kZZKXUmQJL+HLBFz74qYxxxwhhxNqcSLDD1YytRAqwb4
WzA7ic2jECEFakxImdNk69YkHA+vPFdCoRwnjvKFfZIBzvSqekBHOA4TA3JXiVjTcMXuUaZaJkK+
se8fGHEBsOD+mPdPO1fYyr6EQz4fAGDCcgnVZfJ27i8iZ/twIqLmXvlXRIqgJmhajl/4YN4anc7v
gx3T+lEweO4lPLT3NHjkewkG0LAIDLhMDpyttFkKB/ApiNq2BqLWgHswVd71hsM04E0NPdopvYoG
ZdrrYqTNxG5u5QZ/DhpU/gHUv5SwB+c32XTS8Ki0MoQKzxuZK8Qj2R0zC0PWqB4cZ20R4FQg/6qp
8V+zm5JdocC/++Q17ymwlg9rIbaH8sVxilbKvRGt1I5blAN1S+JhehNuKAKK59c6EazCIMkzdZHO
CscdRgrmUB8QGa6gDDGoqvDIWJwjEA42N2aeB9a0/ogfkqKbJ1S/wxplbh1KYlJ7EmT+vdq5Zl8i
BtDupcrUAmK57qMO+BNRvLMxl8kDdQFx8n7JUIHl6Uq0siB6lRICzpZvwb9Qq+cm3fIfBw8msDod
+dR9fif1q41Lw/3ofwt48h0olpGprShEDl0MzMkL3LMeY1ywWJDCiDPWgwLH9gJI0qkqPn2M37de
sMvTsSRzFGsAE15kS2zLAHeKC2How5HF3opd+zguFgJes3NNoCCVIO22j4Wg3wLWpdhdquYjL1yx
vAeLL/w1OIpeepeDgfmuf6Qtc67aekgNs7H2dRAC5mvs4gXbbdMytPlZ4ThvFVLEfTZtd8dle9Uj
SrvqB0v5RECqLlBodlhj5C5UqlQd69qRknYBzxW9hC/+7GJYkrUrFaHMWAeQZGp9RPe4SMQHGQ2u
7L11R3gpmYuoK1o+Wj03mD0DidCC43cwllUU9mPmmSAmGPbhaeHug9EhE5t1jQ/tzKXVAksm/7sV
JP7L+SZFpn1HRkRhz/MI88H3+e7y2oDWcGYQny7SWc5OiV6y97Hm48KAplddOIIXkrBkEmlFFyU/
l4ScukFLkr6quhi+70UbC9J1/UmZms37sJkxGNdtEvY1gWRMudIp1+OiQW3IzVskbxtmVoA9HNzX
jJC3BU9b5hDRbDO7DgPIufAf8/iN8iPcGCHO6H258+mheCS36YxjrebQ/IniJ80TvcQT2fXeY/1D
9tvWNsFvwNCH4XiwYOT1UNt7vAX3jimgpLo8BDOFZly2uIzzns5scxEpm/CQ8ER595STbI/I7sUZ
L2jXl7A63igL40v92ADDqqP/fcUyxyPAgDh3ADylsSkn1as90peagE9QWOH3nTncdtxBSkiIK0ZS
nspjDCxdpqunwRyC0J7WQDU3R6/TxzGjOFbMaWtHh9/NNwkh64DLfdBjurCf90bkc1mBaYaYALoh
F2utE2XdtJJz552sd6chSTn6bbjQ7Mwv9z6WdWZXxcAMhYP9RlAVt9ZzhhEWr5n7qUdJ5IgmjX1G
NsO1qspGeHWgR2om1xoazpMxOYep5kNdBeVJQ5E3WnnM4NgaY6tGbDoVizFmfCEtDdlqwZU/riFP
6OKx0ajz/TCmiej/KzzRiJ2PqYwGM86oBnYFcl/JguLokLlFyX8yfVzo/GCsV2PCHrD79XOA6V01
156pfZLZ3Lhy3FtLMRjmpepbvQYB+xR3t8x4G+AefgqNpdjhvNN20mx0NczoJO1Fol6bz/PnINy6
pagZtgfpIx0E7Xfse77ovEsQkHYDXVaZzugdYxrzQIA1OJtfljhQ5G8sHrI5tZkOlc+TDTLabzXi
pqyG34qAan3VfnOyFwpAKW2VU8ulaK1IS5+kYXZAwgBspnFOQ9Uy6ZT7J22EBy1AWAg0jnaKPE5x
/BxkYB2/8rbnfsajB/+3wsnx+mKmCNlzDBj20eFq71IbZ1lmgClfjDdiD1bHLyQYzX+ZBcw39Fpv
OpxyxsF5gfO1XIOg3dMXDfnA7kkgL1wTr55ALsDM0K7pGrpDVtp4boH+h1/VVV75/Sq4jlIsACdX
cS1FmA+MkgUx4hFAgLsfLigY6mNJ0hpSdHwywbFZC8+2+3/hQWj4e5hevomcVGxSVdCuHe/5c+f8
160PXVI2jZukjfOZIAzWG73rVYyagMmpxPs7Q5Eh3Jd2+TOoz1nrzTGzVc6iPAy0tltEf/atg0yz
ys7xdlwgx+GS9W0Sgk6pDEya4ukYrsJS6RaObpjFMSfb2ENNAIbaDId9nsepM1vCPesTp8X7M1s9
oxU9Fay1J2wnFPAYXFGuTGASVXlT7VLONEa9DK0v+Uro33qkl7Gc7LojVUR5U4LRAdFXl/iXxwVZ
/erd4NMQDiX5dPTtDTKa7weGa1wBc7oIAJwxdnGmtSXCzrskclSGlx+NbpRg3hPOSVkxtZcb9l80
PzPULNokIqx0QyoKUnwHrjmmA/g+m1I3c8hXBrBs0wMmvhdr/7SQY8g+7tTFTAu77ToJjingF4Nv
0MUl0yWE5QkyOJ7HcT4ZTIlsYUU88R9JutRmVMCNYhiyQ0CpqJTL+TnS0P9U9XDDkhOITBpCmPWX
xoKiT8zAgU1IkV1HRwvgHc2G4Z361v1P9+vQRFo099mvejrkHj5qKKiyndC4aBlfj2FS+ytSRB2V
0y6Y9ZLKM6iXDcFdUAEiK+8AMLLGxzVOIE/oInKUVDjr03/bOrEBrnrEb1OuJ4663CrMRiHq2Lo0
RTEoy0LBr9JXCp94qhLEz9pRcIcqCDxggt2YsSOApe2lmeHABXkjdRb/PCijYhtBmLHUET7k8JLY
i9YGAWNNC2DIuj48sE3SpJXGVrdCEVaHzpAatb49XPyHlgC6Kaohq5u0uJrl/V63r2mzF5VUX/wF
r0yXGHGUAVhNb8GqG9NZtiQ7jlFiaaNnaVF8ZOnmDh8nruc0ucYjJDXAwFXDa9fHNjGbpqahyI67
muCTJL8X43QV31mUAGWn9r9hLesXwoh1OB2nppxEcnAB4otFbbOFZ8uvLOVuXDsQ2Q00BjHbcqcU
PSEJYUFyclHE8nfDR4wMlLbRneI1c2SQ5UyAn0j1V6P29zFI5Zb5oa81TJOWCFDPBz5yISuQ+nfb
Ks/vsaVsxRZh1T4/ZP4wYYNuOQrHunapoXRY1p0nU5cGzmva+80tLaQNjsghHdBlBVhbYKHJV9Xd
zl7EyM8WdC79R8gqCB92r9RzATQlMj3X88wXLvz99zar6csyKaJAiVTv3XIjbl6WCiC0FAyC+isO
zwmnCYzCDoZtBxuSZlNU0qgXQD3ujdeosOxMur4nfIt1m11wzYwEhIf1Mnvwe5UUpHiu93JaFE8B
5DfkHOL9b63bWFBulxAH/Z9p907u8iH3h5jjMBkoizek4KAiKmu0Y0ktG80oSWdw4j39h+a+EYIg
sIZSuB7VQ2faS3YDo3ptqsa+/z8EvZBMUrTLmASbJfZQW/4iNpxNpECyS/o+htUthaeS2GxSlc2c
pyTQjdL3lUWzFYbe7N/91Pw34U8D22+DA4uWbtUJ/GAKH2pkIi6fSpkKnFEHcKO4azMPjH+zGfVD
jZV5jbmrZLTn+E1JnsscZuFsVJBYxdT0Rn1ATzjWYsb4Q6CXFegXoG0sutWfmPAllfmub9vDxWyg
7F7eY3zO+akjYpOpda7EOPXxE4DD9UtMonUkyYP6/T8q5/Pwe7GAL8jD3m6SNtXJ0I4iOVdjHFbx
s0iVjlak6teALt3S22DUhe0rkbJZk9Pr/hfb4cX6hVLJ1qiLPnFz24mDSJEA2JotFd3SrZ910c4x
74ZUYbm9Kr3qX7ECJZapzIglXA53wNVhRsfSiWRYnrwQ0qoOhXz8dnzQSDmqzmjhBcWHpnMLFYE3
cEvNJ5G3fCM2uVdY9C7SI9XF0MnVS0JJI8xme+w13SopfaqGwAXe6WenPKMmbUx3t1uxpdU20iyQ
KoLak6kWBPXhddZ0gLtnN6yIAoWK7c9jFJ4QwurltFI8tUgHQVB421UWtw8b0cURoSXfzLQHup3R
BvBFF8yYRIn3Dohc6e9hGce+Z+idhQwVFXNviEsPgSbJP5mtAKhu13FnYOUvpuuydyVmiXQONcaY
T0wNdHEYlR1PtZMrTcFJzgBa+yxH9cOdQuIculRufFzITUSsFlYTElwv3a/qbX1851ZYkcAzyMO9
T5LqaAlRZU/ac26ND2JyPQcabSllQVklzg+5qDbxqyNUnnBwTwwEL3jRFribjqRa5BnCCqU1K8wi
ur/m8AWx7yytV3EANC5j0VCOZdk530PLfBHA7nrZa3XPVZAm8IR8h4VBHLZRwRtr0CrEl25xi/3m
AwJhVmlUFtnuo/8xRRGTV+4VRXb32j+xArRTX1SyAqSZBTP43YmW+oQiYisAQ9JzkAVKFTXwSHew
AwVWZBXyUqvMvGbhbiEi8Jy441hPOweNJwsyJI+U/EOiU+YKd0UvXahgjlsMNr/8t3fboIlRGJRk
RhOipDDEzxQhR0l3XRnaKihoOP58uQd8JoEmQXlwW8soLfWxV1q5OEtl78AJNkoX/ZdhxbPLCkQp
3KwJE0cAdYgH9zmvW5N9hcDFOYJyNXcMHFajvd6bafmel4CmE9jG4umFzooiAU+oZ6OrArVaFMYB
9HOnsF+LCramkyVIeBrJ0ENijVWvkZvB/XSUPd/STYYbtcTPNgrgmwknKt65uiHIPhIJqjQzW7yE
nyhDIsLJvVNgCOtu6njdHhbG5qPamNZ/5CCujnmL1GdXqOgt3lQoRxJ0J85sOPWBh6OIBJaB0EHZ
L/SG30dJqaduW7K2SmRsrQ0Ni9pQ2GRdivGFqKaXSKespGnmakm9bCKKQtix4JZKnhlV1LJYWywA
bn9FbgH6QOod1UWDnOkpS0Q7WnkJ63lq6pPCxeGrOGxss91mSu0Ip1nt8M4HEdiW3k+EcviFrnhA
iL6wile4aYR/ZYbYaGPz5uD+hQcQjg2Blp6HO+Jj09N/YZdW3ia44EPrQj94xxoLDBSXLfVIOdNw
Rb/x3zvuMZ/JujJ1R5X+gdY3VpLxPuvrzVPG9fQPnDqDT38hsdvjjDXp8W9ntEwTbyQUrkJKNrC5
ckvmSL2U8kGiS8l5OT65xwP6HK6n85ZI9SdtGBUhGuOysOvjEXvPaU03dgwL+6nMv9tUshuycrI6
Kiv842UbnjW91bKzG7qKPdIamd5omtmC9cO0TavQoOiHdMI0QmNnP7fYa8yf4mgqq5kkfEAFd5zC
Qzu5oPkuWvxKAjXAe2J0zYd1vxFkF0/KJ+K3CtwaZnmoH6Wb+TjEjPVXFyLb2zNIJ+OpdCwtCE7L
wHxZipktDnkZsLl+Ae1dLT57GAWLExAAA2JTGTHb3UjZ5ONCByhKuJojyaPb/a2zYOmLbSPBbEYW
WcH9pjIh0N8T0BwagrWclZFc3ISkuT+F5t1/FTF7mLNhSMihrY4fvh+H9lNraPNVlHoOUjeCl4G5
vArsvcM4CjaFNGxwwm2yatKOioP/RkkD8hSbmIF+Uo1StHUQPH9RXMPHFyzPiKEuJZdbzrmy6Hnb
aP5J97zgwNbm8LQoTwRWHYhWqJRKSnvdhlIPinUNgsAAJ94gsCGKELz9iFPCEPjv9SLHeeLP9x6M
QDRhIKIu6A0HqV7Z0EQ7DeJU1WbRcDHCeWizqXqVIL12zNUblqzYw5EDWUTQ3P43GIyHHJfZ8Z/Y
VxIpN4sO6ze2yyTrfUiD+CKh4uYC6OjCb+NBCkr0vDOM3zzvotuB+b1zq0dfnz6/rEQp5gKBA6O9
VBDCrFBv/6w82M2okj06jpB5zlyifgYXw7FzauYWjDKPNGRUtw2YfA86eF5IwZI413LlUb6Asz41
DMpdL3zYzZ4VIa/Bk+9hGvRn+5JV2OkXy73iyFzKFv4vc61ujBTdpImyOrH5sNTP9+c+aP1xvUj5
fq9TGEPgTfXPJNpWRfntmQTA47u1x1bqZIQK7WYUj8zPCr1Nto/dTk3cdvgpiv9P5k1cgwyjfBY+
rqyGXZXs+Yg02nuZEGihPslFrAd9ViWq+Zl2VjgVx1g+bHtbn1A+H+Qtwfkc7NwF7Nrbv/9lheQ7
zkkNVTaFvpn0lnnSnxUMWeExvb/6wNMaz7Z/SU0JHs5pt2uK4QUJm0c0RLEBbPfVrS3VnuoOSUDb
7MNjVHBIqd1+Ug6yZ8H0et+fwY1rju8VHkUDI8R8SK0Qy3sbmg5x5c/Tjr/YMldf7re0aWl+Itbm
/Ik/hatWMmHkek5Gv64yXyHn84EwhTdR5/rUIcwCxLcPLpWPMWnR1rg5A3Q8iV483/hejVJJfoUs
sDt3D5LiPIOgW1QaHcjE/IjlpZpyytQhKDc/ffpz9bj1jXfHnsia6/m6Lq0d5UNkxslL2qH6ojF+
aqydq5xRCLubh3SlWpEvQH51UtBjU3IRwxelmIr3erMhwqMx8ud0d63a20NYeWFpxjEewgy4yIQ2
CMaiwUoTAlgcfHlYGQjyUc6F4CWWLBKDLFEzyoVksXpuLNHw38bqSDrs4tCxNdce04qoASM4cwxA
aJFMa0ceIglPf3NMftB22im5fROnbj2fHLqvZMoKkzkP6a1cygXTdAopu1XSuZLpHHjE+G7nwW98
/27fJfk1g6OEqw5cTVnWqFt3uHFCo8WFJ8LBC2RxscfQ+YfB0VJm3KiLJI8Pt8LqNSD3mv/yd7pi
O32/c10q9IBVj4dL9icHnZLmFoqKpA9gEOixIH50W1blXv8kwnOVUyTMPJXfsNVAfeK1o87KEljk
1RmlEsM9I/jzrc+ivtmaFeGAxnlKkwE4KUqguN/11HBWBs4BhP2rSThoYNk6/OQzbw5wfGdrR/NT
dtKvGnb0KWHgbaQ/MqEAiBBLW032zbyG/Z/xsrn33YZWd65mEMvragGNhEKmU81kJMilFV3KsmsT
7Yr2sngI+m60zYcvjN4gAaQSanHiDwV7Dwz7bOmwjIBDssAKZuRo2Lo3ybM/RGc1PiYHQ6U7bZZ1
f7wWzwMsQSHVcFw/Ol2LD/hoRVwYavwbPXEyfnZuKmmYEjBb24dBNp3SOPkJbxj84pPCzIwDihk/
oLOiDEt+lzpoqCEsZ9nIVOnDA7lHmUPUQfaKqZSCaGq6wDn+AFuScy+YzAw2Je7ZgbNF8uxA7qln
4WoVfNDVXHnp73hc6XYWnuvCOnZwZsJx2ChqX26SYH1GN/lgw73MS0K8az1FlqRPK82jdou6rxNs
KUsIe1JwsAdpM+mHv85uFUkStJ9vARmAUE8lT9ud4Zgfdqjlpk1j07KX1tSyo3Pq/6vysZbmZf7W
C8yH/1t0Y2TmHCJf5fdxhOBXmjDcKbB/othmIRnTmLnULv12cWlUxKZy+NkGOrwudqAx52lpA0CT
gT5KuZf+LhLmylo9qM9g/kTJ9J4jBNucKsBT0z3b3/J4AYSbxwXZj6BBMnq/DQVkJKS064/gbCH+
nQdImUEr3kVW4RhtPBmEptNWTkLdJWnvMz4isLQ5L72cGlKGFGTucys4FqOtVlQeutZr9x/LejFq
Jn/Y39GZuHyteX2Pm6zrSXId1wpd671/DyhUHMHCMSL9IDsWB6q12C+zFtg3TyCutPV1gyvybNIu
oy7FRLZXUt5BPsoSr0rvPccZXVOLkvSf/ZPyCBa0CFLuvI3fqKXH0DTrY+03B6tSv6UtYAH8HzGM
uvYE2OU5k12MdZffQcd+5xNjzQ6QWHg7XuKkm3VpIJFm+g2YEJenDHjPwiq69COAcTLCwOFOEP1k
BW+5nzLxRXK878NwaW38yN73t8OvORcOYP29Fpatz4HnCaVaKSBwT07EzRhNjLvgzYxPY0sBKhsy
6eu1w8PIad1Fm/dQtX1JHTjag4lMa8kUnWFuIz3kxnb9LgiNweqs/cBCtzVgl6vW1nkSdNfuuCam
InT+m5zYm29bhuJokTOZW39wJ/X9QVoxef6/T+ziTJUqv55q4DaNzFrZxL4sZLau440/HlL83aNR
q3EqJ+X8GxvTfJdSbFqpWl4HQ9GjVRqInDcu9mHHvnt8NbUcLB7gubbdlQzjpZYMB4fJ5UK4zXep
+0S4izJ9V8iVvskI/y2hG8zEQwkVpvvoR+4hfCDn3cJ9CsZy0lOBV1ACBA1k9SB/PO1puy30A8F+
LHkwdIezVyb7kBg/UIypmIxvi+8WoT+u0O0METpdW/F+XDXtGEpBphbnOQYXsFbt3lpnJLMCOeUv
L8nTzVGhtMm+D4Zo867lvNNW0qRidyOX7PDcxFZUfg/C+zIMAhsOuOP6S/kOtfjfQyYq3FxaK9Xn
IUbb7tsT9Tcp5GrE7Sxhe4r+e36AKue9R+DZR3BOSHMxyFsYWpScw5VbUd/+25XV1EB71xvHCXXA
VTdSIrnPZN8zVspjxAwsz6duHRBybhSbjIm2qP0QAdigvF0fMKLUHaC9QNysRvqjJsu+KEDL25si
BA/ZQVaH/dQxJDj2qqJrW0oqnRSW4B3rhRvc7yccSIzOq7L2GWWdE/Eq0oQH7o2U6vCebuOzv7eJ
xk7GRRh7zWgFcXjurnTlZppXSx+r6k4MWEDWR1db3AiIHER80tQ4+WqxQwxsYTfrHN+WzXdryd3n
xPWbASiHfZLI1w+6rHhp7L8VTQke7FYYc1YSwrRfrpKnPZxlg6nzptZRP39I+raiGdpmUtKUhkkE
dbMnsmEtWVCS/4qxQDQBNCoEN+OCWJIrpjRLfV51Go7OvNaPTxo3Er9nqDOghOg/V/wiQcnDRZ9l
IpJ9P2fALMSg3XDf2WZ4t9De6CM3846vXCtZ6ouYGY7gah1n1aZPJnq4QVEE0W+YkImnR6HYNBfO
Uqaw2XBumEjUvQI4hG+ViaLFbNjMSYKlJELDMDWdp7Ci04LjOQLaNBA659Uk66AIvJ6nPGtkGe+7
27bAkQnhqZBa4chDCimz40P4YqNvGoDxk8QyacvEMunWnscYiU6GZCmu4WuZIBVXS2Q1wr7ItlDS
WD4FxhUv6uc/tFRa3MO6W7bwagS/o3DKPFb8V5bot6sR9YmVgZbnk1O76xdmRoEL0DYJWMCZojE/
4UMi0JEdIURimE0YtU35ca8IjpcxVCZwm1J35xAxYRtuaZ5gnzf8T8G6mQvQXQ7gKMEwWZarMBS1
z+79C9fI2YMgpWhY61LOCWU+HOpQS8jfRKsREvq+UxfjqVsAZ6raWfGFWG36AWEcYfWLLPu8kCCX
FH19yoNIqA/CQ8EJsHapfQmgGmSsMZtyTlxJPntwAA+S6AwXNNOcdWkljUtquS97cfK8vBcowW5M
aesi5jbUpdv8d+bWZTyFRU4DXo5o0bLO+UgHwVLdep9FhbET5LlDsiUKWgh8O2Z+g8vQ4LwWDxeX
cpZYKJuNjp5c0Py/yQkSfK57BWZjS3m84BmPmR/m0lgBWTIyW7bNhWFctnLmr3eWGDcJnw0mB1k6
NHwGbxnnw+6fdYbVtjEltbGHwxeDRlDWrUwaBol+ZXuFL8HsahzCXOAtmByHat05SgZHRhaoRb8t
xRMYxm3/zlRBLFuGDg5s/Cm2B5fzKBU9cL95xWLaRmrMVsjF2ptUVHecAndcx09hxpfpFsL3SFzp
20OVaxg9nVZPGFApSCLvufpfaZIDfa6bqoylWML/lQZq5qyP6HmAj0xpyU9hxPfzJWIqRaioxmtS
60ebTSMxiI6W13SKuV0R+R+7bsiuMPEqJ7BLa8cNqcZ1m73DQY7fFpIYDzn8U91EKwoWE3RzlOAy
RccBwF8oiSK8i7gIjvF/aI4RbRlJDDHoP6CsqBgQXFQNAZlc2zIfQIc5H2kdrYbGPrO3KcpbUlG+
RjbAVLEczrhh7E7GtfQVyky0DyPH4IgstvCpxi8dGxvBMMZAVZ2f1esngRiJilERZ5yB6ZLs6xUg
WInIrzwIivQVoTGympBL7E1szR5NqCL0iExfxeqVwmnHr0JYl33dFDzHtGwpiiIyijwOlKOSoBjq
6BAHJAZCBgGydCWhZKzRtppv5SFIEMpcllgzKHr8a6hAafwh6ARVjh997aAoyAacFC+Kpz+fNV0z
HUyKUTdRX0ED+hUyDsKkjiaUOFPAO/pxg83JJ/M2ruHND6uooxfhG90d47x97bsxhNS5CnmrZlj+
ogeOjxfi7jqKUJN8mPU4MWKEBYqlp4/CYbYcN9SAD2XPXR4uiouevtLcv8SZze1jv0NJEWhjANyp
BB/op6L6Kx1cVNqulTq3N9zfAAcljGgqNOJZ9kJAdhjUxh09Uyldat2pM5WBuVA0Xs5ZOn2o5SRL
ru4I23IqTGKAEFWuYmL4fo3RVLopWVf9da15t6uS6aLj0Drd/2xJrUv9efEkLETX6BDdF8uuZrhM
2HGUWR07EL/3bZPoPTBYYLrHSCO3XVgVrwRuMzrvi+mHA/vcxv4FGSBZt34rwogeRCe53W8qlr50
kRda6zEnd8a8O3MwtaGcw8bF9az7SjtL4fGGa+/un7fv0mxd2zuSJw0ihBx0XEsDOXgX9+RjnThx
mVSyL42XHuADTiqC/lOfCi/QecZHkf5VdMBX/uqqrIC8bfqkz0d5N7OcwQRP5LmesQEFMsgy/ekp
E+z7Pa4EDgDHn6iTC9JyBevDFErJvf7o0loGGaa0NRzSjYcMrRe3RzvircNiLMmKG5NS/kxgVinj
zrmxo/ugwdK2GyD/4zoRaU5CXHjdvmnWEpYyzBQEVkT+eGN9PWjbX2RGfpdg1+1sgrlwrkPodBH7
UFCk7fMM2408CJM3AsUUd9D5sz2sGifaTnKXBjM2cc0R42EbrztyZIU7lCQIrDcYsoXI0ydoDnXE
eKSOLeHZmQmxmzA6HsA8xlGimiN/M8UDRUvp5NX90CAdbJHq5vR6qhCSR//SDuyUFXcq/3tRJxk4
9Vzs2q7VExrzs97FFyhltroOlty9oLqexOtSjPYhquVvB6liQqRHmZ3IxaDVdybxM0cbmiPzqfoP
heCgc+IBRIx/g6u5RqNol6kpE+AEqSuFWUYbEYF9C58hLUmlHSSljhwVziotAOI0Xjdsj52T1JD9
RlsP9cSUGxYSbvMbEUjmy64GN3P3zeC4mXGDJW7G1QjLX7T2B8ZsASs/9jC7Qorwv8/FopKuulz6
EZKSXysCHQ53c8qYtKyMSRV/mJy/pbTh2JuUvZxIUu7QJ5sZSgPDTWwZCyKAoDs0omoT9WgffPiv
Wtywm19aXh2LlAECCWwgP7VRtdmWGdCFKk8ASsUoXkqdn6/0HkkVSRLvNKPlDuDAZPk1tx2e9QWA
Tyj+d0at/n/64LO5alcun5J68k2L1yNa3RSJeL8YC+cPrFeqXnDknjJok9TvBl5Hee1CbXK68BC2
8Rh4sh1Sk2LVkaPiwqnjotKuGxNfA7cedaJo2YyyTt4IqlvBmhzz5JLKWGdwKI8/D9oZ8Si6yyNa
hNg7fDtRPJ47EHdmBv4udtl/By8k+aG3fbP8W3RN00Mgki3SL06H1t3ws6vQUWyHyeRa0lXWfel/
Xx29gXaGxPTJLpnqWhuxqDerv0TLsYgTnKN//B+ww71MlIIreaUsDYbVujRR900ytuv75TxVvf/C
eYrM5rbIDo9tBsWUk3AE2DpcaCzUF/c6n+iSU4a57RbJybNF+mWOsUti0vXBOfdVqzetB007+9re
aOGe2ENHWLypIS9xlFzuKRpBpsNvUtXey6FBPajZ6ecAgakroJbKkBXmO06Tg4DWLhE80v5ZSeRR
l7W0g4PKMWht1R3ff5Hv2N3VgztFpOCcCLudvNkZ1H6fFGdg+9hohh1+wrPnErApHM1mhqrXoDBd
2S7xJBWSoqnf0uR+1ngd/jOIh2Ei4kh0C9s3zzUM3uoQx0I1eUq+YKFlSzKhpMbM+Qm/WBNzqolS
/pkRt5nU1elF/V2Q3leR1qZRO/FpDUyVtAqmmc7yER7ON417a8S7JkG4UthiJ43KKoLqAqtUwGqm
cFoOGXE52gwPFqIecWQGkb7f3rvJC4X75/eEaaFkEFq6dSaKT6fFdth07d2I9DquGJi8uh1ZRe4M
oTvcm3d05X7I4gmJ/SCSLlltf7IZK3ATJjqJakdJwblQewkp7wBivhEC1OHXjiihRs6YLuOah/i4
6bMgQNpDGirjrvwLtHBQDjJ5WqK1rSa9hFXFNk2rhWmfGzOgoQDKzdvAB83kgaQqmAB46LqJOr0J
9IM/Ve0EkdsDaA54XlfaPwy7sllwv2vPKr+nkPUNF/UMsVzoCK6b/8fSlK5C238Q0qsgaeC0gjzR
6IB+d1p5HT2AvYuwoKTDpZabaYxzbAGmLCOqxoVdH/7WKE6L8Dwm091451XtIgMpZQ4p59yBnVwp
Mox886cTif907tRFnyQes5jtReYZSkDqqyv/96ghU1R7Nmunoo2onps80Y9EHtEmQ4HOX6p1fdIX
8Zq9agUtdRoq0VMXaak86ZVowPF9qJ2G4pAltHcz7mDBAvNJuXPjvjvQMFhLbDPEdYh3xNykkdDC
+H8QSq1QmX9i9WIIoI0J6xq+RVuJPYI7+itz0Rh5lfLD/q57MmRnui8rqpMzVAxw6idKUaBTy6d4
eOZ/6S8YJdHRdd1YzKVn1y9W3wzK2lWheyQhGWp79bX4uc0QDfqvGYOWbQjXqX+bY7qS1Uxpx7jD
kLmG4dKOwQ51QOrCAcLpmwwQZxzycU7TYFY0sEdx1nBt71OyEbYl+qv3lIMDHeYQOEMI+HKFKXDy
7IrGr8F0LC6QTlhmB5D3w4Qdaa2+QX3ZkjlnLkv3ERggFzTWg7wZsYlCkX3KuOgnj6JhcITtHfnX
5ej08llRiyQ8E8LLp7Rys4izHmkXnyyse2MpIjV9HmTq2rXZBbWnVHIlK3q4UtJeK/IoB93r5T3s
USbNYDP46kAa98QRLO4s+dfzPe3/AZs4hXbJwI7c5HtNrO2EK6xFWAU7PP2RDoMJ3CxI8kfC4vWR
AthqTXs0fCreT/mRWDN5kdq7ZEkpm2dNzqkeq1BN8tk/EgSqcCngH2mkDjbp3QYU0p2kKRl4NlEb
QMlCVkV63EbuAC5wyodkXMIsE4SLOXwJ9edDGdpF4STiN7UH5sKDQ+SbS6GNPFIagfxyz0ufOhf8
Xf5PasN699kyVpiignZTKMgGokRsSwRse+mkeLkreP+4JiZtJZCqhazvF3mvtdLh5MylfSx/4KZt
bbB/jp5q4zcGRF5M19mSAUaAOnn47P77MJbF09IBjAyPyAT3sSz+MbJ711YgheUtml67gcZ1L3ua
NQ1tAneQf+TVjRX3wcJukYJy6NhLBC/jkbzbxdlLkEYS4GWa3Q0bryBOMzws+N57R+PWNwSvkROX
gkHU28IyxvmAO0HBuvnYcEcA7ToAhbwXHWwddzxMMShyEHxHheDAbqBiu2RJX55r8DUG0G+UNYtJ
dGtNZeUQUGr/usnPAJo/gdL5FTounqPY6Y4qdmsMqCqChlgAPQSled+FpSUFMoeR7L77/WWLnPoH
RJqaSj11ocJG4qlwoZJwMA6IH7XBBB+MrzttNIqhrKqiPVHRO6mK8I47myHkd/p5w5AoZEx6rSFi
E6NL3Bkiy3WbUweh8KZqkI74AU3Y8XiTXVh4GucdHUmbzZk5/4x3OZtsAg1v3eXb4yV7keoeN1MQ
ao5JQJRV4rQcFIbH0Unhgf75G4seerI27VT3AG7nnt78sYZdefjbsNLDL6sJRWkn85q4/dIDAddw
ko+PnZOsbXtoofq6sbyqAalTntRfcMpS0w8mNoHyliMkGWo5HAv7ty0ADga5E8EARfqRSu/uV3Va
iy0sLKEkRF+uU+2Y5TRBie7R88K63tYF4AMSpquqWP7zf8zmWLEXVfI+gKB24PC0u12NwUcVXbUI
ZzB6+KNyHrvLRWA2SrWA640kD8u5Enaa4xA50fdOiprRkQHgZtZ5o2nfIdHMOZ7EB4e1srXi8Zhs
mZ7Z3AbZZVsP5LNhDq1Be4PN4bEpeFxIj52XVqMHzbQfXJLGn+pRZcn+IyjWLz1hBNZUOfX3jld9
Xq+sr0odRG3Uxr2vwf47KlfErm5ejsjGCWMEUtgVd6Q/fPLFUb7Vdl9unOZ+IY+J5VirsK4DlTy1
ljWEvCdcftnoEfeb/meS0ELG3OiWAE6gBqLo3DkIHatGyxY1GpwPOwHi3hmYk+t1xkZbQZVRJuCO
Dr2w08BD7Rl4sOpg1UsLn9TNZx4/cQxDbrRG7Hwia5hC+P/xUDsBavsBQV8VMa7znhXLtkA9QFDT
CgXxE2Hr1qvFoaTFCr1WbQwuCMjm3zA9aMnEW8YpLO4xgiGwbyrwinQLv7G5ziZ07mr2zavlYD0p
Lx8n+NZ8gDAdRQS46vmiYyMMiLhbpeX9ziq6k19ksBzVD/i7hJxfV3cE0kbht3hC0jr50hwDXIei
76CqSY96RzpmZg/ng3PcPghBZgZ5weB0SZDiQN3SH8UIzCRs3eisjDtZf1hMA3KaibyDfArlTUba
9o6wgloTZLaNilwbP8zaInLBIwodVemBTbMM63Zc5yZGwdbBxkqF7JY5B6mRDNvj3Pnri6xeAWst
TjXfsouU+x6iv2eXREzBk5TdQYe08x3sifHApRoEPta/4D1d4WHv1exUAtarnGRHf3CgK4MdpCkE
p+4i2hffJlvQxP+vJ6yI1rmWi6ceDen0amvbOCl75799W+QjaE2Pn51EVqoVPO8tcaDt+X4sgJom
3/FeJUvbTc3gOqBeqXb4tOqUtmc/rKWfXgtCa8pvFuqEal1uckOyFK03bJTZxMkV3GvYB/Cl9Suh
yuNzsDe/phVrUFw3eBtvlLinuFI9qlIE+Qc7aJqBRXNIUASDFJ0jHb0yF2qE5aIatV7Fp7qEIYYp
lpMdwayUI51fspXkBkGhh0a4bQUETCHe2JY881eW6rOntato9f5D1t2H7dQf6H3/irnkuw8w6UNy
5R/3W6yfe48g+Y/ObRKoDzc0WBbC3WSMbIJ9TR+RvNlEeolRC39bi25/qH3dYRy7njUMaQYEjYGw
/1evk+P2d45JgKPqmgGXFQ8RMten1USCTDIEQskyc/MIpoD3X579EmHNWybKt0YzcoXLVjmKuzWx
34YXc5NAihXBRH4eOJFFoq8BCaBRzn+hMeBTiyCZcvJCHKEgbTyS1kANxzTMvJvXb6IT2EtGWzK1
d3HO6dZxe/2lC3OTQFPFJkYHGakJYEVOKRTbf2V/lxk52N4Lhl2RsYx1ZrBkcuJYQnioMy++lHnM
pt6TadAC5u7g/nvxO0w5J4ihkObS0tnmS1gHg4OPm1TQs2gJkAweY0KQgPqhJIbHjz4o9giRN4xm
lLhl/Kew+leyhEFOAT4sWEwHOnRDxFYf+x95jCGO6wtaKNsG/6sLtl/lE9/l1exj/rRec87qkC51
qwyk4rpyRKXdGMnWElJU4/hUtorzTy59f5gSWtN6sgbgm3pBTj3LRdlHGUcsm4L9VLQ2kY9s25Nn
Ocbk3dHgNlcbNrAhtwg5MFtmWqZQsPtRxuoGKrqPgqBbBai+9IMzoFwBngjOvNCuP4eBk8gGn4bJ
YzryKcbz3/BbChbvAyqaUeB+TmzvLH+9xcKbTA3jpztiEYAx2shCbCHMhpep8IyFmRU7GdcIcmDI
UxWB5mzFC5xif8kq83/7Od1AMlliLopL82tvQe9/5ji3xfC95ba+IswNCxtV+TFRmVYKbWBJc7JP
7kvQzo9lvsXdsrMkZked9BdaZO7AzW4SxCj7qN5t1nzc/gpMCOkTmrdWF97M2qH7CklPRQ7o/Skk
dQ3XnudS+gpbB2h6S6uvAQj5SVkb5qCpBROvGahYgNLR0oLVPNwmUvT2ejZMGYnyXcXxB5PtGzPX
rvL/g+eEUCGczs8HNmpcqEugszlMb+bmGPC/8m52jBGfMqTLEafzmpN6zq+4cJ50S7gE4rC1wQcO
YDKrklwc94JQMVMizuf/3FFdQ64qDwoBmLcJk+/ao1UNobqx6Lk+BZ2gUbAO6XPf56raHH+I6eSy
5RP9LUhusdaj69vqpGwtPndxZOBYGo3fjF9WWhl8JErNNeFNkwQTXqx3Zn/PGTarrWUxI+Jf9h6T
AQVooeCalDZOAJiY12idwIG587DqcInbos/wqOC2KGH8N2Jrm4zZgQHytDnNN/l6EaioFjlCnR/O
av8M6+ZNzGFWbHX5mFC6Tg2QvuRarsdk+Al9DUFrezw7wTmcdcKG/8YnuLCvb9A36VzwkqS35BP3
bvvX33gbfXy6124rQSSxCfUYvV4hqKEYPLtW9dCx5o9hv4N37sXQ5QA32RJr3+Z5Xbfugj0S3xTQ
M/MiD7SQZcjNk0TO+cnj8CzaKys450fAkRSb/XAHl93RWFvvypKjTop7cJSLJb/gYo1DTj3nmCKs
aiyKFqmnjODZGVvX3wn7pxEKQf67Vwzma+JtFuwFLdEN9w8v/ex71bAmYaKpKJwjyYo5t6Knqdgq
lD1mSi66vzwKi7Y1Bi9TSrOFQ9LM2z7L70pUOTpzz+H9nluejMlAekCaG8QyIzInVwb+1oiZGNbj
Q6ImkVdwUdyDMVPulOsBWHbF1mjwlh8kcrZeYNLj3K7iYHD29y0b5CjX5/Cb0a+BDQSlxDjvls0z
yOt3MWJEuwZNhdfevLKI244GuEkUFFJzZkstvTu+/u7U8c+UfrbKtafrLeWdUMaGC1BL3OjEjbmv
yujEc1OtSMDWSFC3GvhxM2VoEE/hAoB61KvHRUxXIKY3DA53A+45vMC1MTeVpjaK4iFjoHIQBUbW
Kk5na9ynFQwDRvXcj+UUsb/bC5UXrOXjl7RjQikXm+wGJ9HPMb3nQrpzvYJH1J5UB1VGtQRML6PC
fRtgbx7seJU1J/9D++sPBkUKrA63plgmJu7I++tN57IOPydzBuLKKnZaWHpmViy4js217NlcLaku
M0RUBhd8v4zMJ0y7V9f6SItAM1AN/RDlA65h5/n2iu8/I1wXnU4Ya6xqCsQUsaiRxHMt5PrkUt2X
4FYZhbvmVIV0M6yt9JyaKTp16bkr0Wi1/mylwjMXX4ChmFxQK8YBGWti1xWJLfp9VMZ9axo2NwNN
ngAX3Oq8MI142OSfKKqDgxXVZwL1ArLsV/1ktYuzht2P2bhu5aumvVjs0m0x2vzfRI/ZRA2wNSgN
W279S5Cbc45WhA76kZ0E0Fv/uEKXFCdS4XhJwCcxjOSRbCZBjOsfuJS5JY8MMtSs2QxBOHzjAIhq
nZkGIRi+QU6YF7yk/kStQ3YX3F1p5SE5Em4XHz0BdUG1gIJ4gO9aCME+EvEMiRdk7JEP5y49RUWO
/2cZNpyxifQv07hdilFR3IBfA0SQMJZ4nyuW6chj6RddXjJLvrvvbHs3aIYSccdfSom8bLSVKjPw
4ey/fpD1DHRXWjSqadkJxnH2+ywAa4YvBi/e7ITk9iye8epi2amouVTihRqtP+Hh5mW5r70p0XVu
1QvcWq3h8VhKTicWEMy79hiQOsP1opFTA5UKfG7zY7dtiGgDarPv8f3VgsrFTVXJd2i+wMgKVkV4
aWIydNTMc7h63N5dqAYmMqY2q6L9khZfurWk5FOIhBBKMFamOXEsZpYx6UI5e062+j1YqeEP+fVM
g0BhTnatG7QrB9iUTsYEgZVAc2BLtKxtozwnOvx4Lv6OBmgYy0d/MbN2gOePQO/rIdwA7PggqRmh
c4lDyR+fyjEQbmYUQr/QTb7+CRqSPQhqNT3b8LdiDbkYvpr+/RkkMMDApzPOvkBn0d+ozw95A8O9
b95y+RW+snCxLHJbOAtYpfke2ZGV3W0ntB2egdo1XLbCYkQjQuGJ4IhFm4zTS7OrsAhLxRq55Wwa
1BqaV0po/iihwguIwCYP5vwxicIR5dpSi82AZ/fdDnGcHXUBYRCayIrD11mCniq01mii9zJhQKXN
nSfQCcNc4nsW6MFdIaH+pbs+u4pG7VsZaa3GxDdQB7wpjLOXBdg8+l4LbuS1KoHcz5eGRE2s8uUW
D8ZobJtILtSmrR2AOLEniibKB1UbywXAKWy28qwGdeJ2HMh8e/V+sGFJF2kvopAn7LegNNwRJOFd
Pwvc91TPTjjrD25t+RCglehG6VonQd7f3amGyfoxmDjwpFAARlpnECialAp+Ul+WO85jTjgn57Rk
6diFSs9AIjxS/9QhUhrLGO2Dd09Gz/fQFALutZNQJvaXrMbMzELnEXJf3NgkqZ5nkNqfVVeh/ioG
3eWAz1Tto08OGjJK9YQEK9HkYLigPSQKGvUIPSObmlcYahTDNV0+EkejMYwKGdzTECudSpVkCEwL
zn/qw6OGUvE07U46VpFPMoLNGLR6anEG8TjXfxi3Zp+CxrDzj8YBvI49ZjA5uluBPEoaD3pqypBf
EeJhbGM++7zg6ZlIUskrjQsHPMN3MSdAWCWraUWsgQtDyMu7JYPmuU+kw769nbg1UgluuFBsXvKG
dLRwbkIykMdMVRw8DPG+i4q9/PxxkmkGcpBdeVnar/cogaXnriZWIupSX0EZuG7OUMXAR7IAikN0
lf9zCuRk5Ee2IMIFkLet7y0omiNVsVkfJSnSolLyEUxt6NOgorTm875jDHkEWN5E9IF8YJBux4Vy
TJBHcwKV3FTL5el8GTg9JoCwycjXcvB/5lrJRfpNx+O+F92qbt0fmJRJR8KnJ5F+vUSW8GTi1p6s
0SMq/I7iyVqLLP3NbGX/Nqi6/3cpdl5GGknYUQwZig/q5wo3jlWiaHM5Y+1TE7QzIueEDAb5A/x1
X7RD7+uztEnPq17EXIgowOjPksfsE8mpaHGFiaTNWQ+EIAanz45Exz0JzJokM+1fb+kkiOD1yP+Y
3kwC01X41wvj6+QxP6D8+JnypiMA+YRop9fB6Nc+XpFwqglJYqfdnBGYzMBqnH+mzoWlX+efg/TS
MhmagEkantHhHRLGlqjAYS01YT4/8NHM0viogvjeJhKc/yXRqad3XZah0osAVvaq9CczO438K6De
wyaDWz4axAtbARyX4YmhmfKV8EL0nrM8SXch0JRy2o6E3p1UJvnyoTEoHuIEi+ymyyOZ1aRqBW74
AFAq9dPWVQiQifhrRUVz8Ov/4g8WoLgYkRYf+JV2vRiVzOSE8EAOvKzLuyPCz9OUkQF4tquRqlk1
sho34aBi8a6vJcB3jrXXD8uv/zfODB5VwCwPfv80CkdYLxauJ8tHPWHiIz/0X6kQUpgfXh1jsCil
HHkW9NQeQ5UPr/BB5G9njF1y8IZEs6wB21kj0hPDu1wUGBkjnFCMmyAbPv2mL8O2TcUiWnvc2hEw
6n835SqYyJlkMnkUms8i8MjoZMwoI8Cenpv9G/laF49YdndglwwR/bVXZkwfu2t+kKI1xkzaizZn
V6ZGYPEicjRn/TEYXdouMQxNcSNvKHwcxePO1knjxDCqVTykfhVUSDz0EyBFLdLD0p70G/yqRCJY
EDvDW1Iq935hLxQS7sVU9OmD4lj3U6KKKUNf7xGKs7Oi3w5DoUa2SGoZ+Sn5471lWu28OfJvwJpH
o098Fd6hMhL1KOYK1MSnYtZdxodnyVDPBdkgx9vyJUuUx5QeI1P6ccP1G4/9upKPTIZvIU3rCJyO
KndJwHSb2+f/6707ezqnYrpuwfQFMM66oUp4aruGSfjZ28GpGvlVqdNn6QlhXRNZDCmrfBoTMLXc
UZgrlVZwplLy271c1kkpUxPD9m7n4U2iT3dVv6078yGo/jqA0W5rNtMhCkphthXLkMZUjatt3CBw
fQngAAaWd18LHjl1DDLEeMPdjUzFFFsFra65VtFvHpM2k0DgqgQzL11VpkBhxgP+3BBdxMANR/sq
qOQYpbzfCLOTIZbaljCEV5okXvgR3sv5h037WvLOh15M9wXJ+gUi863DOPnhhu/fAJhOk8Qs/taN
ZGK2t+a9By3Kuz23V1k6ISBZyuoww1oDvreYdAjZ68M9NvuYRyZoG/WTfCxSwaa/i5SL8qmjEZT7
4K0mBSjawNu1OfdIc65SLgi3XKpEAk+DGFUP0OeF+0/CwAP2hZL5FXEG9LEk9PolFWXH40ImE4K+
3dayCAmIgLYs4jBAGkB7LLN+L9u6kh9eemdBm4XeDg37LcVGzDZTat2bmxXKC+vZ8YDtMaJ1FP0j
WWy4QclbxaL1q1aQZhJvRiGMxSKcDoHjCRklW0Nd8aeGNIfsD/Rn+0KKUAdILsPhsa2wnnZW7j4Y
hjNO9ZMFuBfOUrU0lPC6ZgLjulvpeUr7w3arPuglZytCnh4GQ2oENMnbDdWtsdWbVrggqAn/1duc
plYtuX49kk64NUeDnFL6uKPgCQKmrui6kQghzF7ax5dwr9wJjDaPDITc1Mukzrz9eZVmMtOac+bg
YSq4sBMqFdXAyGuec2Xd91s1ZDJdaaKfd564Gb8Pg9YJLxRicPIW2rAX6kKKAPtttpWntJ3Ds+ut
RJOYm/IQtCO7MLA1nVoUkcX1GYwWIb91XrSs1ZAO9iWXwyVng27l+olVWEJVvbQ6QDGu9fzfJPtb
5Q39uq6QnLjXGrmSpO3DIyzrfe9H8v0LNDWX9NXYCj2Y2Dt68bjGx6wZISnVYKfXI33YFUmHuofB
DgkFyTDvD6R4JGj/yjdJZRl9+wb+OgP1yadgCljzEsdB90WKC0uBkYYh39+BnRLQ8Ah/TG9Xcg/s
r3a/axJzxXURtSA34ghDj0SRvDtAvaZXQJEjIyKGIG8VcJ+2w0Fx6nXDPRUi6howiSvoe5XAMaL4
IYMqSgW+2m7zdgsY7rAciaCrdYVTV81Z9PhHoEXJyeIFWzJbNCWeFUclPUEdilE5+1eK+qsO5aQi
n/b+vAXY20RuON4d4/1abNQlUvjhxwrUzZ32qIDRXxA0TmRZVE4FY2ZFZpnK77rLFr9iKZZNxNub
nDp+2eQ7oLbX4wTWDiKe4anYahrtQZLvuCIBEzD7Z4TDq7152/vo3dt1pELlpU/Jvm1hDf2f4hIR
ehPWs/8ex32VsdiSptQCXsbhzlJxLERGj+z1QwYzZzr7K/y/PvM2b3R6UyeWJ5Qx5scRMr7WwIF8
j6LSQQlx4jZty53BqmWCuYJdfrR55KxoHmhV8oqUnLotAm515CAg90qRn+WEocqKYtqaVqAsMqli
YvtST0oiasAGSs6NHElGfajcNGW67oDckfah04RnCWpYaVzsbwPdI/k8MTqpKq/oADnF9KArNt9D
A9gtI3I/B9yWshcNosao3yUwBeCS5MfwqL33yxfXE5JzyfCV3F+8oo92yNrI2g2mb6ZK94TUCRJD
DgZPeTP3DHeuxqWkmOZQ20izowFvifkw3wbKdluHavK4S9W+KnKSL2HFkVRslrs4Huv2hMiW3jL+
AAU67buB+R9iYuQpWkLChCojM40Y9v4aLfkAWHchfZKMX8VwtymE5m2mkucNd2KE46VaBVKahbK8
eOfifQD54K+O+MC1/ZhH2aFQQ9T9bTR39G9sr9PREIrroaF0Cd8JxjXcMfiAXd8srzvLZR8Rrs3x
eOCu882+cxbJUu/tNTTMUcseXLjtnnaCNXb2I35xth0r//dBe7EChyKIGigcUIc3pRXx47lKqz0d
hPx+PZvakUwVhCuMLNQtQwBrocRmzn6sIIEjs+v2Yxy2awqTfHo2fJIE9YA+QYmzjNfU2k4kMElr
DrocpRHczcrdzaSWNKkP89kthiVK4/sURFf7rOCcspJCjgBzz2gkWrY/0tSVEM5nDIOm+92KifXC
oJNJX8bYrg9APx6DAJM16vXvekpy2H2kKJjzCLCDAUJW8VO2CgHZ+QbijgpWtx2TSi8dXZvnYRqI
X97iENLuV9+jtmduKGiCHJ7guiCTarHXtocK/nzny5NXXVf0QzLTfxF88Peq01W9kOl+GEtgMC8X
pF5QtgDBjkXexy0P0IO+9Yk/MlLk/Mn1ClSw+1ntisepCrfA1gAz0PCbMlz9INtHTzdPErmy167O
Z6EtoeuGKjNc9y7eMoKtojALJltYXdq+rKD/Mv64HaTJ3olKK8EN2WP0YuRl1/GdkN2NGiq94Hov
2BG+7966k5ydIwip1kPm7rGkSdC0603RtZXmZbKFWSF93C9vQi2aaRtvVVnwlfhkyWXPhiUGtAM3
N3z5lLUexHIHEI0n2/6CnuGYZoqNTY7/YKHtKrFFoSUVP4t/x9SUwDq/BePx95lEHtjbHFlN+YHl
P9hBRw9n1lu8bqXZ2VGFMj7vOMYLt2Wcp4RZJoLvF5reCu3dWf7Ir18iMNh/2woQ3AhbryE2s4DD
sAEChUDA84FxTHkxCY48H+SdqJ+lliL8/F92GtFZ9jOl8dpdY+hwzI/SUxIZ9m70IUZhqM7nmv8X
oIb+my/bLTE4w+NXBYakDjTbVeMtT0mQkQrPvl5rTxq2zuzvrSb1L+75wTkm/HVs3Z1UeF9Gw6Ha
xDxAgjwOc073GWBY/OxqbzlrQ/iC0/3mwyFdr0CJXBpoYmIOxVlcXmgba1trkNS1vDJlvS0N1JxK
IA3ApP+7mYI7fw+Z91CVXsjKoIi4QTLgd6pWaMqz89VPtwoCxhh7zeTlFu+GrcVq2lAbnVd+6AGj
4dow5KxBBxran8E9PYiJtql6uiCiDP9nYchdPDN9J6cYL73UIybhzAZIj41MpbX1g2lgCsOrC00r
1u4wdn9ZrErduOyqGAkNnD7PyhDTkaSMlQjpUC/f7XlNSegUYOyCOGcC8/JBurGmGTPqwTFGVRMn
L6mxDCmH2DfstgC+XqjUo3ka/j3DD3f/9OnHJZqeNfoQEN0B73nLnnT0XI3g0WoB8Fo9Js7op9v4
TsgAVoB5Ms1mYzQntAUj5WqYCiMYIQEGZ9Y/kI7Em4Vz82/hFUBUvtv2Tex6p0reT89ubSpxwvZi
AmCUg23zwqZSy2H88hsFh3Q+FnNqUAwGLHuPU/Jw/acFA5D3J7zuvKcuVXxo/FUEcFK3Bj05tv+J
sLU76FugBTI+e2FPQzoalkzCkosbW1MRiZyotgSn+NW2TyQ4PsPbpntQIXyr5i2rRo/DgI7X9Vfu
DBdLtLK2yQUBxUIhZ09yNg+lTOBPSk28EX7pF7rNYn2Y1Fw628rs+m1rWT8OauMDYtVuhLjomtXn
M8+Roenw1FqaalD0IUgxc7R8/wuaAPZbSKDmg5M7bMlYZIB2l9VNkatqx6LgUKu97lS2EHyevrz+
fsExbpWSsuwq5XeYw5XUNJqa7BJf2uwK4F6lV3tOq7oxAVCd+5gJjqBzoi3nUx+k/pk7YmcRV9Rf
NeoLfa6M0Nx4xfDx21XApPu0LSrg9hIsK4UJeTWeRD4+j7dCGZmBdFDS7AZiGHbegOwbYNLQBYFv
yzUXK2Xh20UehgoiC+asshn92aYOOEAkdWChzDXMneOp8xeHmQkjt3hLEBOEttEZbiuEnZF6xRXt
p3Enshc31c6VLxNdwQGbPsdvq9mqOyt18oFlexcEWHlVve1mOOLwVQ0Ttzp9ILk7H8HCrg9h8ok+
7FhGits9orpGqEwPBJq9vLY1/osR+cpPz330s6gmcqF+yRTzEBQ9W4V49uAVpfAp9wcxGl72m+8U
vzMUXF5roULxsaqlZDE0s3ZvJ3ilcuKpSftMmVY3RU6YD4hhuE0GrTf6wgbP//Jw/qKTA7lsF9jk
w6mdcLhlwETxs7Xa4/vl1GvfSti0TWRITupOCvE2Nr/wCmBVtIEJMVXSyFfaqKdcjvZMzhSfJ73t
Jvu3yFuOvzHmUyGHGO7MJMVGLnEnBkgCI87rDScXOr3kMLzFzvj0/eYxbpY2h7daBYMqizZ9AjjU
ha/oOosq4MocC21sViWjceHgg7mjfhwohOMFmpZ48IgERUpQQystpGibA/BH/snrK89gyaXQOr+a
sjDfdny2ZhMODW9pVd8PQezUNa63KgpN+nFu62GIPc7KnQUCa2Br8eTIukPRAtZEtcBpnwQElmQ+
+12y8HDbYcjVyucjshdLrllyK2RWupQ1+dxOR70FkeB+1MV/z1BizUJKaeSRTfhXVYnvNjrv7BWS
DqJE7arFdeFhFZhnrXSHeuFqh6Jie7fvUf7eiVFCuBxbb9fPuXUlwcim+8ehFW0AZtwkLrxvDWmK
QkUDi0wBCLt9kFw/GKnrze1iVPIw6/vn/ud1klBtGPrpIK+GsP8u7W4NfDUCJ8KamTzGLsPZGfyc
UTG3w9UBOmVcazJV9YK6ViMeYgOgLg0s82LFHUS5w+NcTjj6hWcq6FTo7wj+U0MQdXPJ83RQXHUs
vG3L7s4yymBLrAV4FnLu9Mo4M4V32LJfdV02ybEfbnRXd/4zGDajpYuDfHZs1Nt/S/7WTytqKC1r
APyoQ+Dou29oZmzRmPaF3B4HO1/+larqndulpnyL8Q4vV5hiY+mB19H/wEOjLMPvTwb2SjRjYrB5
9CvYAVCY0d42uz62CvQJuJSC2rw03K3RQwVjX2nrwHtPixH7iua+DiSaenoQDwnJd4HikyFsTv6Y
bTIv1h6ouqpvN2YVPza8SnEEsNDwU3U5LSCRftjNhF9rS8AwXcsLkWWccpZ/HaCzubeZB8NJmgDI
nXOLrTje+xycRT9JznKWcoxnzLTXKbdlMyC5yuvxmpZhl3W24KWVtPZwXg/nSCZGuDx5KTbnxct9
U643H2Q8nBoi0Ml6Rw7Riu7iN3mdDJIG3KuQWSivZdK8GZ+8yzKyTrBtU1uRyEe/lkoI1OMNcpQo
jRbedFdXp/tiDg163ClJUMksdI8etDieJzwhRxpf5gh8/aH0BbYNOIwStl2JTfw5HPvIS+eZDTuR
iwAuWDaxfDaBwEWjb5s1bq29on/7R3/rt1c4C5JcMoKgi1Q+GyD2Ah7AdZ3nMLynEHbzp1a4RCqM
te9H54V3NHM68/Gkni5vgiaXIeFsYgLcWxXeaVm6L0wF9DN++y9yDH7RuCwHAbMLP8IfXL4Yk4f/
+MwoVICbraHSbpMSZ+FPSsGBKdwr2rarG3+up1s1yZQ3843YLCqisssm2V54FJJSZYWOkoO8Qyzm
QlBq7Cm9h9TUqsAb7mYyYK9JvXSUB4z6OGXE2tbWYGTtf4Bisn3wgkqRo7eodRqmetfCwTPRhTSt
nbzPEcTBQzNaDFjd77VGyMctIHX7+gc0PojtZvmNldHUktIYQOzPg/3QcGTNn5X97+tRPSQUGIMN
7R9alqpEO5axbXzG6rSZHyJKdMunMdRvE8E71/L6LVCE+Hgpj83mRQUF0KrijMBgprpKsZeQ19Uf
iqtbbo0Jdrf0fN85UG4dzweW4k3b3otOzeq91bbf7Eodg4i6QY+Uzl7oV8UfhWNti10BT6reSVR/
pj5z2h9hXmVvhALShnm1gqG10g+tqzzSlpB6/Op5vJL0Se833+wlPxEf+RNTQkJCXwwKd+WpDCXc
6KIPss2rA90Hh6AiFvSM3airU6q51GhQJ53wTQHn73CCTDcY2R9TEIk6MzXebVdME+QQ+Oad5XOc
oT+BAj3/lQIg026uzjMPT3Tm5L5N6AJ6aqLQbKtGptJdAfOhw8Pl1TKh2xstx82HeiXs/lVOsCpC
xHpLxkxv7OAK2CPpMy7Qo5lJafverf0XxZge69oZ306gSTCbOCNJ21eWpmOmlZARfilJ8G0dE+NX
gERuMP34CaKm6+goIAqDZvBWQBIoaEpJ667H3SPwta5nQzVoLviLlhnGMlpqR7lxR0jVOxTetR+7
yaoZ+4I7Z3Ahw1O4wjs+n0iGajNMsPjP7lXWxN0yATWj8go6oRHAV44PHuMoaOS9rQBriIeOobss
36g+FIstmriob7H3DiBsxgWcg/XSTQKQsDr3NfwTzguUartQ4EfxvT2/zahbU3awrwoSlHzO6JRZ
55bpzAb10jjXEZrJ+7jqIO0LG6qO14AAdNgyZqPhT0t/qbcLCaQE0/Ets0u39/BU+3y6vu8YCK3w
jzTU8ZjdHWhCu/vxhR/JL/OsPTc4C6mUV7zM+ZMJXHOa4VB6eXST3OIyEj+De6oIo1khZ95WRWz2
oGwGFMcQ9YfYpxK++ThCEfNFq+a2/DIVFjj3ArZtpgwW2GYbJdOSer9MEj8Kn5XU7OLw4mmrw6bM
UgPzwZqXiXTzEzVbpjNiS70v3DphLJsaU4XIXkpDD/vWENRrpSAL2+EHAca9PeRabcOTPN1U7txH
SuFKj06SvWFz6ZgtClTHd/9TVmh9qEBnUjqf6PBzN+gkZMGBm0QqUkFUISY5IDpssAf55ggmIGE6
rPL/yA+I+M54wbkQAU7LGqcSDAwCr5veWRiEKsgwKsvCe7bfTdwn++h60sxdX5BB8coOzVVBfa6u
6+ZmKISfjVeEuKwKxQEvn/zYZCJstt6W5RocSnJm11JhdBqlkpt3qQUSWaNRylB6yqYA9UNrB6Y0
m3tFr0dGWxWtO8qPjOFhaeyCJM/QWdVTFm1UXWTcgopPkorigU9KjsFMucElcBaJd1vz8j/65VJ4
o0Wgje9ICsKIMcpa7rAWX3smiNJ3uzzwax6kYowtMVtYJgbXMKOj57GLXtiU9vnkAUsK6KMshgsC
WFPenacop1hUSQVBzwjaEwtrQ1OybO/M9befCDYSl9lkTFmYA7Za/tXQulVJrLOET5BFT3T3+90B
w0d7shZjZrn9xWSVVRIup/vMxboiNNaEADKd8ObvK5pXM+IFiJ70IY8xZNzLEaXGj0SAeuAErHhx
SYtVNubyiqtV5jBT0tgBjFo67OPu1A0enwRltD83/V0cnNBAKYmOBt0EoK76sGx1j4GbpSWJANYH
GIGAo3PDMK0FuN5EOS7U7yrhG0fSGeloyfOjrBtz7Vrp6NXauAHtbSXkLHPjS2ZJG/8sgYGfW8pq
hLODiyEQQ7AWKyb7fP1hz4tWxrC388GIwJBj1QrfTja6NIC8K+TCuRDav4cUGIMMDwU/kU2lb3uZ
94UhpYrj4dqfe6Jh38ZHwGczaWhMHL5IwzXDNUX6wcMs3qEnEt1ieo9vtDQRfk9FzCEiyklqaWQ/
vj4wQWMJmSk7s+6m3RANHjWV7IDrKsNs1zWhtcaneSFToWzjnyipPlLmlAXbb99tZJxlueEKDkj1
gZHgLyRmMKeYkzHPT4CquuOIXSeFEIbzbMcAxR4QgKPZIlKq+3Z9xclPIMa9+1Ep0lomtXTmWGz7
7MuBQ8iNGFr4s+Oy8Yd48zSv8N7wEM8tBkRnXWkLOd7QaBtod5fGxpEgOp4wO1biaVMet+aTAIB5
1+cyv18wea6Wi9MrPhkc8puro/3kbb1LUDvgKiOgPR/gm7rEATA3fmF43twrZCVImdHhWTgiorjV
yyTuVc91J021EUzFDMb6jeVc8U8XIIeEolgMW/vwCibr9Q+4oGCX9JDXDrKnEaN+T1j4C8hQBEoR
Cs4yBD2ZiQQOgRQr0n8zeCqAL41avtIsOpOxR07USQQ8UxIqWH3IizRu+bNV+o7VNh3nw2OSscQX
/rO2Dkwiwoh5PezlBV5EiKaOtuWcknTG3DIWkCokgPbea0lMjQyUsjVy2GjrNrpc4k/6qj8RrPRP
ofLFilVJzew/QiQgWeHh5+trTY/A20//n94y628SXvb+WrOKHe7mkGSl3MvyTNnItWU9feQoO/Pb
nDBgvFXZYnGjZDESZifaOvh8A8fe3ypyCALItWWNCTp6bUFCke3bkbP7mNl72g3ASjx7CD5x9N58
QDLPsY7CBj+SeNZePZyaiVzjFSRk1wxCVmBRBt3RX/FMG+v/920MNheZOarDbcdJWHRE4jaLKrT8
i4ak3BuQtzZYdGRpHp1eYTORxdRbTj+njQKehPJ0+qRYBlbBa/0RtWXIKrRrfbNAp9Cjv4LR3L77
ReUUnAvbCjx+zxXlzaAdasSQkO1j7MNnm+LDhsjO0M7rOCvihGrg3cczn0fI1m/mFuhwDRvXsguK
LDNVROAxpNs2DMGC2WTFYZeOoZmVYWiMgQTb/CZCtNVTGgf/uaSIa4lsfKJPRANjwZGVSZB9TcnJ
YQhG4qIiCr/lKs9ZtI1s06M9Tb3wMAAC/chYZ8d1c8a/vS4lroM+/kX5Gta/Ykd84yLt9+Nghly2
qs0g6xQQ9b5bhKEYeWSUHDM2nlADDRdQPXO9x5RV4XK5MAchLSdAvtUo+0gWHdzLzhZV8utf7unh
sQlS+LhdGPb6TBiUyRg4dKEE9YJ45n4AAAUlI+ah+vXcmoxOEsRXDuLvBm+VBxABXxWDI5olJSi1
heDw1MuX62HIt83wcWAWojLcNUyW5ydfM0AgAH3uNcdTt497yLJ90b5xTvJN8aQ9c1I3doH8tz4O
f4oQ/I6exaPywsScU3a3KaqD0yQtUItyMo7MQ+czT73fwWjF/9p7ofY9T5NM7odCImueverFoEB0
G8u/JxcdPqUNBFis157I/LkTS+98i2QoXiA6SUSwgTLvLHvHB2QpbRG1DF1WoJdG82/WgKcCfI6x
ELNOFz/UvBMiqj5A8XZD77ob2WCBXxiW6EHBs7F8wfYgsjBGsq5qVXxpKDHP5sDDJhPhPH5eni86
r5pXB6iLqQwcVFF5mkNU8f3huZ7RHVeJ5G79YELfJqgCOxf0ZsoMnNL2wwMKJazRoMLj4ED4sov5
9gf0KZpBe7SzSKr5UCzSX4AzzezXHoFEenoZ1S7HoTKvGv2zrxCQP0N8rjZsYN/+uBfcFyttCp9+
W6x5ozCDW/gMsWzNXMo1pcfVxs+7sOsEF8YWZQ/boZcm3lJMZ7cMn3njsd9PpekplJOtWH3rzJjY
ceBg4INFmzqChHjogbCoJPkgASTSrVKY/q0BoUU9s2vVG/X64bM/TJQ7qefexmYVRgWrJmiKtnHb
Rhsh9uROc0kQAerTiaZ65GxsHKhgAtG1pzOgjIBgoWMfbNPwt1zk4q5B47FVkNu8Qi90pbnvz1lF
53pNWOf6b3qdMVrch9OlQ6dEx0B4y+dN82DZTxrvnxjoHhAooETLMZC/SHOM81ooMpBvmOUulMsY
cn249+00BCcPeJN/SG0hqRIGxWcQbVXKTpdme1QM0OhC/hTW7SRkIiPr/NYVxcC9yGhEnh3lkJOA
mveH6ZfOmsxkpNLL3L3lNlKptCz/KpIvUma8z9ZCPXjhei1zIeLhgfTI/ypAMJ3vLuwDlGhS/TjB
WYpTlFvK4VvbX0r6bWohDxV9gIa7UA0pbI/BaSZTwyqTxNrSOP03Q9Pt1t5kRH8KM5JkysO7F2Zc
RiRpoP9LOvBedlKHNI7QvrsyCjCyz+pArW4jIoZWxH7shaxbuB+KphJl5qpcuK+a1lCXa91Em3e+
DRmwfyYwtuL86nOIKhWmg+WL63eoOK9l6uqXfmMeGbd2Z/Gsms7TfQgeSlWK+wlUxG7t4IdJYIVT
DKioa5fIaO4FFX3ZAbMIKgS0FuK87vS2hzEV0d+vNgJUcX9KwOvJx6baGigdO5U7sXa+V74zJ6rv
T0sJf7Ybh7bspwtOT4o61Wk/cmTaJWzoVsQvUj5ZvRwwA9cZdAURlMFzl/Zsl7pXo2TfU7Sq1dfY
R/SssBVRAz20FzDt3wpEqgF3lL/ZZnJU86Auq6yWqdjyAbhJetfiIw+RQXma5NYc355icj3Khe3M
QIkg2654HZNybBnzS879PRAjefewRC2u11smnQD/VTvBUhG+sM0g4TSQS/k0eUVwiloml0s8jply
fSPGzt+edsFnTVwWn1M/i866IVoJI0lxtGThqE/Tdml5ggGhwpb/hFWxToDFqtYWWm8cGdWt/QEA
TXJBUpkfJGneBnmBGecER50S+HqEPAsz+dWi6g7BlTP+lie7q9DEufCSx0JhASFHPBQSWr6fllkz
Uw+th9+D1oWZA6F35Fe0GVFzlTKp6p2IRvNJay8jXD8xGXVf7GMEhaYuT1x3gYgKh1lelzwDVAgk
QzEGpd6g8p/Sa4txI6RnDuBei65iUDaJuzB8ql/qCPXpJx/cCZHY6E/QRKHmyI1/LYsIEtUD+57W
61W8WOUZR4/n8eBWpqgE0xBtQjmnfylM53SmNEzWh7mClpM8P0BT+Hsym8fFC6Fx+PiAu/thhS1M
cVnP1r+LRZJenacW1cvdfj9kay84JQXcdWQDa9cl46hd0/mN3aSMKgQwGvtFCIQTZq57QdNdzctb
noQKW5sX4pnw92KUMcoHBXfNBOdGcBhF8A8Ak/tuum9oy7JrlAfE/DbOwkLO9iHyuU+GiFN6Cnhp
15oc1+U3aQMUGFRkXEVYKzAN1co9d68Yd/2+f/drKgDq9GgewzhwVq54DZ/NiZMXXVW6WsoaP2nB
bdGusBZZO81TxUCDYbFxwQ7SByZuz+ootyu980MwYMxdl4e3m53+SI4S3Hy2C5wPPTBJMjg7IYdd
BSHgqFli8CtlzyW/dQS/rbsjX2U8uZ3DjrwVzBIU2LqCHvDBFc/q2TW34DZkUrfzFhLLUezU6f8A
Jfs6ym5MQceuZclpM7WJtGwqRPPYRYx8mCsd7PfnvnnY9K9y/Z2KLeEy5Wx0RZvhnb78c8woYD2D
f14zEKtvDlQIBPLFHOPlBP7dwFL6BCx9hBXNyrjlD57GZwYWxlFI2HwWU/C04PT2QUvSpQWFZLNC
fOOLPZcr7ImIg1RvaPXpw5NmYv0HMfaWGpIeiQmQZWNwlhTISEQc8Bm3o4snpEsjdWL/DUo9p8Wg
7TLdq0KCDV+6Pep7HRaWx3/Ojin/MdGsD4EpnWZvGMOhOa67lBKj8RgjPKl3M7MlUQJ7Q0xT869s
O5BqWtawB378CdwWLuSNM4iEf0wsD9tq0/PQoA5zCzXtpzzLhbrcAXs6/KOMW8E/vlBqglX5DFPW
Kal/HFRL3nSVgCKy93VGvev3m2cjxW5QV4p7a7AdUXk9vEOUHUnrk19zXkBBVhvRPVr1QvVSDjIH
AczCoStIPaPHuqlNjbRbg8bBb+IqTe33JaeGSVJ6DFvXIuO3I7reepz4ujl23y4a+ah1tJe+R0Y/
3DfVOQyFpTBg1Gwf9O93L2Ez8YKlAATRDmOq6iw4A4bE3PqG55MxOszI1HQNkSuUOBtrzfMpsPJI
GD35QBNHEuBgu8WZMw9TEh5x9v0cDG0D1hG+AgIs1Nn99MeTehl51UGTg2gznYS4ZgLSFpZvK8zi
dqiE6dp6p1usnuO2piXf2ZPPcJIoY2BwcH6vIyiVbgSWiwQhkhNRYuceKBJLvY8EGT1ABVLgq2Vc
pBZjhkyc4g8gFLv6E+hQhEUVLHVbmvb2hKc5X89/raJvQM1G2WNdI0k39c+QowRYfPQMDn5BscIS
ULL7RzlXKh7aUbBczYBYnBUKO53KtsUGmnH6vysNDr5Ha7AuZsRezn4mCKqU9BS43odFUmQ4NSWk
jdwBI1QQOXDasbVO+X6lDSlW3C4U8aAAV5gY1uBJyVtM/azDhqG4d9tYY0sOvNu3XF5bhdPCGqpF
VXKr/S56Erk0mxJyfUbpa6W08K9g7Hl3ZAIIyydthgYr+uGY9HouzrgPH0BRzFMNvO5Ym2hQRvta
Vnac5Lg+AVG0wEliMsoJ8ozTocTWGQoZIRiHmpE54po0mTUY4M5SNfWsvIwedCzyewZGBJyuisjG
pRjdZpN9XR1F07BYxu/3YGdWyE6/CuTl6YR5B01+2yGsfXNhfwmN0X5tRMlTSdsnejU8j70hHRvN
gumDqYagtNaImorqhemRCJ5CkpODBA3ZOLENM/mJXcvo8uLFUSZhtujwMigCrtQStM1KBso3TuiJ
pGzniPi9fhUBtcKx/eD4OLl6ZR78IcV/6zVERjVJnF3/Kxd4UcvR4dWmal/Lzjjr2DxNZIqa+24W
x3ieQSHNfr/3icuG4IX1jUnmOigcYzAMhBf9sV13xnmia87QXryfwRBKQoWg2UtYtp+yMIiE2/xl
629+3g3/uOXv0H2O/tJf88gKBSmEW83JrJbBU/F0neWJUQjx3rDO7eXehLhg8Wy/M1uSqcyyidWl
/dw8LrVtSLcE5UHDSyNBg38iglGTFBpj8g7qoBGiefqy8UaugBsjX/yiv5OPgnr9ePxeNSPFgK8y
rlUG8hmPSAZEcFQVNCn3cT7tBwH1Clwm3lehKCKUfoiA5IrUAnF5nOVbhrEPyqKWVEIS4juxKIhw
ozMlrLOUZBUXsPwp3OFLy2InYk24Zy2H51A9QWJiif3yRlg3P0No2i4bmvtiaYlj9R/AMA81iLcr
Udp/TEkPvIQIKI0mg6LNxJhZzpN/eChunA+QMA1O73dQa2OBnG+2tcvwnuXIyjCk8w6bRh7AgvK9
1bbsaIzhDyn+a99A3IHGbV1PIg4q0PdV2oJp+MRsa3Uzbwg+e4K2sWEdDDTvfQ5cCqrgUSCJebNA
oe/isfP7/MTdnYPf1RfBSWMF0lZb2DJeq3Pvoa3Qy1j5wlJEaNiqhrgMgIF9UG1kOUTeDpOp3IWy
nVWwcH6QTuOIxcdns7F7a0KHeavYxYxt9EHr63gmtnPaIAFUk9PdtymmcDCjhmjEoAhpXFji3euf
pi9Tzin1/zhlZTbFlHw1ONdhTbaH3S9gnD6v58ma6+1uWaV/TbyKXlDVAweYM8WI7zpJ0kikpAWl
1VJiFavZ4EyOTiamaKeFuOv92uCEl+A8Kx6WRrJUCC5lvc6Q/pxA3qXCoMgr104bYLasErW4FfKi
w3A7/7S159rNkzMTDvqZNMwxoxuINPfdSNJn65CENHb8k8BEcs0kN6Q1KbX/GU//TijmOPRumBtu
sd7tPsF+G94P7YloTWHJfWKn1Tl03wg5c9HAofZ0L1q2ZD9Vn84zZqJBjLRdNEzmWzIGqH6PnKby
ybuZJ7VpiU/j0Md7ReyLZD26xHgyYT5f+TF6A1QTquv3prulUlxkZWPJD/Cq9k5j7RxwlRlyPo1v
LoPLQQo/DvlYq25W3N8KosFQhSTXz/zGKxgqi5oQFPxw1213qKFL2DpF2qJ+T1HgZRKkvjtrsnsI
7G+rbeBsIEdp0ZDV0EA5CCzauBBGte3Q17kj4OjS12tytSXhye/NhiKdL5UVVt5oH3kMJ0SMivyT
8cnZ4WFHLvtUorLl4Q31RGJRVd4j6pAwzISKB+Rj9y1nVkEzW73jx1iN91MEC2vbeT3kfEsCNsWG
95mK+uXJpeyYT0yC6rfJqHg8LPDIeaZ9eLdED+gaCqBiofnogr2+LmEGPy5rKq4XLI5UjULHvz4N
iY2dsgvRWGZUdBu1GXQZZ/zaSOMeta2VNOZpyMqPZRO4I8plmdpVAUca8hTOgzIrSr1f4369CX4P
D5h9Oh5lJkeTpCGrgkmSk7CRWNU7rd5+AkcKnE0tf3gBZGyH289krBp9gvZT4NT4Nl+3Ap9IRAB4
A7k0XzzUQ2lCIDjggdjAok7bvPz+27qTOsXgnUUWa6Xyz/HZwgT+3iL5bgSLplft3viboo0DJeyy
NTFDccZY+OohtEKjuiw6ObpWlkc1LcUAJ9Ianj2nrQsxYdRc6jzAXeeUK6SrUfHezPmBcEZJ5cET
LeLkUvjVz4fsby3z2nEZr2RXVN3Hbgf7Gl3sQasIX9OW+ig1HSg4qMnPLaK0L5uDm3Zoi6k26VWo
NZz90eDpg2x4lpS9Tf88wDapEla0YOh9QrAEBHWRjddy8RdtZaGVz31iNnappectYntLFWTxKzJ1
9XECGXae2p4Ubb4yvihGfiRJUGKDPCrWdViuu59iaDdHWmexTeGjzqTdAnlmN9V3oWqmoIq+Vqhv
/xQD8EM+1jxcTpFVKR7pFi7TdHfhCKnjwV/48UguzcS4lJviUXbtGsw+VUxlpBGeoHMUrtvjVmSx
egAt2fcULIr4ObSU7t2hk0tWhHfaIhqqlplMZUT+2opQRfGWJ3G6IpqBD9/T5eXle6eIgo8bWNW0
lwFf5LCh5hRoxZ5uquwZ5Y/NoleKHpMAY/YQfBHsnHHqHxcq68JXdgzsDu1mklMHoJqZqTHC/KbJ
+83BNh0tVARWqkqVKL4hLFNcR/+RMwc2Lpx6+9HdASXq7WgkKddMYTfd7LS/+uv9mTHhit9LILii
gXjGn8pkOT9rqoyr4BnliEQ5rrguv0i94o+p4E9t9tZp6VXAu5PVDY9JsrtkkZT+i/eOXxoL9I/L
QnCItK4gXko6T/DAmE2Rsb4yjqNg3yxrcFlYDWh4bXaV8r6R4ZhDwOauR7dIMOyLSdXk33Vr6Zgh
4QRfHDpgwg2OWDdP59rmL4P+IAn8mF8AFG33fbA2+Q+5732Yl4vJk8y/l1eGx5W0q7e+oTs4zf2k
NwbCx0HG4pG6/TuB169wamd+xkIjFigmkS8bTASUymNlqrd21qRPhsiOzwjMjVVayr1HxrCq8h3H
XvBFg0/yIGWjakzk56iZkh/ACh6Z2akinjEAkh4uJj96+lgPxRSn+o0teJ4HM7ZJzZYy0XCpUEpt
beY7tREDIBEyZDJ4mbGDWbItzXw9UCpPoz9U9w+Qpc/uDYVu7VZOQtu1bnrihyd3PNoRnNzKrfK3
kihESzx57R/5u4aIj/9CbC9UG7nZZSeVvOT3Pwt1C5d56FFXGDtpStw0MARjc4PD03qfCVkeCneD
rrebWXDQtfDZYcOo995atoYiRDY7CuAcefM076nY776G+NeIMkZrBHN88Ex/sOmG9VGx0w6OSn3l
AlkO+/FaYeJ2XvsjrgLJ//qRLjaCDbThEZs8pLcBBOBMMKFML63MGPMquOrDRRzNDZifZJpcdKSs
u8CnMcAI+zJf5LQOhbar/iYczUpfVMVGthd3EpVbbP6sDRBNN2l+vR9LmeHKkGwPkNNnhLgDwG+j
0T6zsQyS2PzjClqVC4jdwfKkiqnhrrJHvANgJTt5dFGJQlsrEFHPnSnMzYpG5mIQq6OwzgukIlzA
YQChSawlHd3ztkmccyvZERuEiNqFPKkTDmAVSNnWLVQDrej8ZW0krjsKu9yi1bTJ36iEqbxda3dj
JFqY3QGK4z//sPkIbORT8O9w3IRsNvwcBvc/yh+uTufu7ef8GnzMmjr0ROWcIiuzPtIGXedegFg4
7Aj5ovL4dRGz23lte2GHY1NE2K8/Y9Q2Mf00hUT61GLOKfx+TSekyHxlERNpZ3xKpFuy/Z20nO3W
NhVafII9vjwQFk47+YBz0BXuGMSV+9A3tcffYwumy+Z73005z2qV9yB4zQQ1EgKuWKFmbOaQERBf
adot7mkmT302jmVlsOODv+TTcyYO0jAvXOCdzgNl+0ZvvyZQFH7/DBH7SEZGGrSCPPXEQAiBixXI
hKG1eiwtpzFKu4KKlPBOGo/tiQbNF/4ig5Q3yd3TNzYmoeI9el6575P0NTyusXFJS//CRJ4O/+x7
PxkeL4NEC3SYvDJHv0aJ3Ac0R1iZGV+2+1juGSK6FO6+eEkeE1XlLTomNlhPqqgAwYbukk3ww4Vd
OAU115vIyxTPHgOJ5oBUR9Ph19QEhzp/wfcVPPAcSamAOOuCdXydF/AI8WiiTVFaVlw3t/nn3yI8
5aG1xCAoZm4Pl8JFlLSv+bDgU9dFqQRuv5kMDzC9vxgxzVMHAVPduhFTv/Y5osDaazVTyEUzg9u2
RZ1BPVzg0qPBWNghhOmx7Vx/XijLgIxqJn3D5NsF4dnr8UpbvbPF0CJbm3/ZvEkWVchf59cJw1I2
9wzRJute3AAmtekhcDYVQCuELPmay8p5qfWUoKX/3a3pXI+zLTwNFJBP9BE46sdPyoV5xkL7KVM2
nGsuIMuEl7pihFU2f/XDQw6yCehEGQoIuX/DOMjawTFeBgslUAl4sNN4aVqwekPtcY7kdNEEuGjI
ywFF8hLLLjkoQA3woUhwKNc7hXXi8qG4efHpC+wXyOSSuBCXdqhgFGD0pzhlmYoSaKZIpzbNiRVB
3TA5HxMp4SkOx4+iYPJCSAyzNp7pqhgo7sTbmqmnO0Kek7Ifpx/Clc5cDbNZVa6taEpRoRtXz0WC
Q9JJF0MRWcvxAWfNi0xu20qCwXh02NjT1MCo2aPP7EPomCzo39oAtT73+PEyOEWer+7b7OF5Oh76
LSiok8XPRqyIsKoCxt9qLXYlEtQRMOS/qRvO6GzA55K/OWsSPhah6iYUvB357MoEVbVE4Ty7P2PG
NuytH7/rTNfswmjJrfBpPCDAu96NQ/DLHykodQTRRQXuRiIrd0e5DLr68iTdJVz2tBWI8qvhRzl1
oTTcC5Ue8uUzgFR6gfVU4DPsHrU7t0JPPwp4jNBrfWniU37750SKK0ljcgZ0qsmzCzWBYK2/cI8b
tARPhIqeehWOFeOk+pRsIlsensxy8Dgd+N2nVmeMqIlC6SZ6yN8fJgShdILv1kr7egxWftp5JXDk
oRWl3U8eVYUMcmJKo+YE0VPWkecSGU3eaBnzEzpy27jyFZQ9p0FKXY8O34ZUvpLYY7sNJVQ3+2KH
nC6rkFugiopI8oGlLK5YugjyRPGTd9nslsOlbbCZysTY3QQmpNMqovCEX6uGdgWu8c3zmU9e7voN
Tyrpsze7QeOSiyQc5Qr5+UJpe8QsrbK2yDE+5oT44okTxa8bd5Cw3FCyVo5tjMZ3va6yBFsx6Iom
E4+0aWizHhdCwTpuHnVosxKrLxA928s7FkLrw05LhGW8Y1g1RvpFYh67KmKViSChi51JqwLV8UhX
rc1tNxBUppm/Sw7gH5MOzzx8ijc6zIMu6BXiGU4S8fsWA25tRaVXTVwxwr1Ai5MVRvExplWZIg1Q
jXGGvnCqMfHJgBSIKPBMRsMREx1eV3uTZFNqj5rCtS0w2HlJnjV/3hnQXc8w3JE/SQYiu0D4G1Rh
CilJn9IkUMwU0w9/iWecxdhNiae26MYHMw3wWXsE2ajPPMQDAfhLCguuZnjTDgE8gcV9Zb8g0kKt
PXgSUyAd4NiJXhfhSADhpFwIOrJ097W2ZxFghb1vZpTqDPr3hYnEH0Eg99FxjLEy5kDe28srazp0
Z0rXgBacLYGztxTzrAzFr+t5H5wm6YOtI7qRuFls3w8S7Qjiw7u1BsvA831G2y/+5VPqoC5n7ak4
DJx19bGtZhBNxWfMS6I3UAuYFvjV9I37SsU2jKleYRrsTkjG0dWJ4OADB61N3V+rDan92/bQWEn8
Vzo66QRBNUhYrjVJLzIyTA08OTawdoR7FktdefJiuYkWekAwsPptXUq7MyrMK/MyBYBFLgE/6Dxr
9wsdKXWKyYljXcCahzcPHsoC2IrR7QOCW4apNNBKN8DsvRKEAALA0cfPgHsNooLalEO/zc3dNeMt
7Pe6UIVStMvOaXkhG+rQWbCzeewmGn1abLwHf5jdmG++3DgbYB50Sijwu/8jXBcQ/9m82rbVmb/h
nB6HNpUV3x4Xbeqaf7/HjkBLuRetYHGwTuukra22uKUYd8/WczW68Ybp0k/S3wca7ORHpkrPXsjm
gEBjKClHUj8jZMEYBAykHNdZHIGhgmrAFIZE6MqKo1fOVybluG3KotqYR/ui5NV4juWrHEiDJ8JH
4tGCh0dGXuf0bMT4fbq5bV6nhFCU7WD0I+HtlcMgMkS6PBp5G59U/eQj0bBRIR+e5pc9WJ7K80t+
x0yd05j9PkM2cPxkwaCtd2kj2YT5OabQmTaSPJuG2d2f5mSbMMZJGf0yFdhGZYLMRs/R3652mgie
Tj613abWVud1ff6iA/gUgSWUtbFeDdPYtTj50hfJxrkxMhVakb20lRrsGdQfqiNWbQOpLtnL9fkL
a6oxOq2BORVcXEYR+TSKTsVzJJX4km+VJXIg9CsxWG/q4iL/BgFl27fKoQF89EQ0JDb8qxhdvM5V
81rG0HjJsyirm66OAxBizg/S6m9VVStVs10+hK25lcjeZHROrfAjWBPflG6af78WFMHoBb4410Y+
qCzbyc8ydxn92riwEtSrncY9YjYVsmKJRCQwvPHTj3Rr2WMxj3tuuhfvC1k/RZ9jTnfxck1B83d2
b7dleJ6Chc6Cf6gBcIQyRBmIVkZgUIDIxLXWQb9bY//6mXTM4nJSyHFMEHj6FWuqhDIow6ccteNH
tHpJ9XS9Zwq0tBa6OK91FpgEpWqqPuOgK0xEQLkd8i+VJTA59EWk5rLJjhJm4f8JNOjfSXO3lZ59
f0bynFR5rzvBif759801akFY03cdgjnrWu2jnD2q8l0HdIvhFkdt4O6uTrhnkS0gEOx34dPBVVle
yirr9v42P9vZU1WvypMuPu2decW62bnUpuc166zU/LsTCUEBqxLVTTQqRC9hUFyeLmuweYQUXDZ3
XFfL1NVRGVzz07OeRc2UQk1YEa2JUqK8pP4c9LSsUm8CcNqd93D6HKHFCsQZXgAaYrQ5T76lmL1V
O+8cDWOlq0GxRmDQQjmS/NuTbU36vNoBZ1ZgHkRbuc2mTtgX4lDFDi8q2yLOO7U8Tg4dgHnJqRvj
WFzovZvFQGePwUkgk1hEo7NAC0PxaOa463pcUFkraTOJp5pOgGbIYNOtDIZsgf4uBu+kprolPckZ
e9lxoXqUTaK+ODeQ5AgHk33JdeOSSuNd6lwXLYiDPYFZwOtap1ROf5imz0xepMT3LEGaeV5iQ/Hl
9CR1DrqWuja7T9brLWWVtqVtjaut32sLzUmmRuvS/PL4NaxMZd/+pixk19qm5KHce7fkYmPqp391
yqdK1Icn9uOzqNiZ4TnRD2Zw23KiFriQIAKTQH7MUhHUG6IuXpGJTi6mcli39+Klf+9l7Lqo0dA6
7yTYuKAWMoZsigLKFqCVjLMovZkHsVrX1PQKWCVga8aJDpuli+29CtzyfVkbGzqTFUik+hG3Ubxr
FApmAD6nPsp14m9m3MoFqIE1G+BUvt6/N6A4kZo0dzBhQakulvChEo+OIjJhsrgGYHpLCFq4froC
s5PLEtg0nO8iRgsA4K62N6Y1rQ3vkO9X4npRaLsbnIK5/AF6JL8wZILBAmr2oXq6P0hNwoHmNQDQ
PGp9xaT3+R8aoIKXflYdSr9bgboCFToLRjh/POCoKLYuIJ7wgGMgwA5a8D52hNatC3Rh0+x6a/Z3
bH2GTIRujjQ0ifoZ+86n9vN2T/5QO9iKfCfZHiRA7/UOKyLEyl7b+6wLTM6VSVggEZ4wSxBK+wey
mPcyIYIvVtKPY7Eex6x+2rEFNEtqyf59j2ZE1Q+LIY6DX9DlxYwYShaIUNLNE/VxwO5TFgLTMmJJ
z5TwT2102FA0AUasufrHagArFajfLoVQ2Q4JFw7ZHd9k32MxAHa1K9gV0TVvwc4bvEXoBLHAneMZ
wZtkIqGfgW8TgmROb1ijmu0aAUqvJbKtIZ7ADNDEktUZPWpvJBYK4MFRXqUvLClxR3AbVfjMfl2H
Qh7DcIo7Kve9rfsUjaCYEYMqu4BCU93bSWa/+v7icosYZBTaOm8VGzea+be2xIK3dcANOvIkR+yr
fEMKtjT3SzOEz2F9cvHSFazaua3TfxkMMFvKfcB7csur5JoIz5uARi3DrEF7vnUNFTKxfcd1yXOm
aZ/vYLxUdkCfa55iTYG8rW72lKEQnl0jsZy7d7ipTuy1YVviG3Ub3qo4Z7bULjYQI3n0QOa7+vNu
iB5FqhEd1wjzMG/CUdYyKfygcMDd/0k7+SckoCmzY4XBN0gOLhSyOAburVoKSUTwrRPcGTW9IjCc
Bc+D48UoblgomkVq2kHY+vCQr6d7MAvq9+Idh71VLT3yNkY+XmOmVwMuTC6oTxyNiGb3uOc4aPy7
K8yuE74Ah6eY/E99DH8xb1VhsmTYmXgl55HaJXVSWRjoLXdo73iOhEYYPcRnoRZ0jE8sJdXFja6L
MWmtCRIXOwylGo82+V+6xOs70SBgul7KOBYlESLNjLerKhflWNZyIGuM+Zz/wEcxeeG1kk9zYVAx
ZYO3ZP/Koqd+KxSZcjx6I7qci7vzUcIguUZ4W1QqQHAd+8o4Sij/FQg6lin+o/NNYeACSkC9b64E
FO7xLi7lk5A+FbYKiX7Wx51bc+aixFnyxUtqQwM1tur2r1u5RMAgpEzF7n0h2SCLiLP3IsYV9Zt/
mMB6KqsLJEE9qHSipRdLWjJJ/Q8MShMsEA6d156l8s+FkB4CQ/eXphudmaqXaqct1JaRNv0eoFUm
IlLgc0L9PKzxPWbIXYESH3c5EeOsATRp21XDJMnbJgaW3HRdrO13vGhBVvrNTwQavX90+GbkmGV3
quA6sWLhs/OneP/oo60EV+rqdvitOJidkCWZhzA7A3IfS49HLkb4905dk1+6gWoOO9YIYFMOCNXt
pLq97LGMRyTxA0CBC2tkg+VqKUsYKdTKrnI411aoGL0ZsBlgUAcq9klzQ5KLkVmTVUVZaItOSZ04
Zr4J39cSPrQHlUpnA6tcsshsPbG7S+i5LTcU02c4dWDn17bEfcB6Aflxe00e+cl2m97IZGMIyMwY
eqV5q7S8ke4wA63x1/urOtlmYusHucu0CF19GDyyiHD8fgR6OtIrdsku7jm0IGVuYm7khlPEOPnv
SnFXW4tDdDAaqVXKbVwAIo9cE5zyqjKWsfjisfzmaiTNvn5aE2CLomQlrpQsh6kWYnI+4A9JtKc+
o/2qeDmE2fYR4MNGU8xjw6GCyqX+ZJ5YAGQzQgkEeNEmv9RUjdoEzwhZdXd27sI3TRl4NX5v+73D
ixw5yHxoJQ3r2egNjAm9a2SiMeItYDr/fRFMKgDqXaJkSAgwWUqO2OuKCGNzXlIg8QpOHqq1s64P
A2HQtV7uaWT0MUA0+VE46Bky+RAb0B4kgiX759yopuY3jt2b0I7/y3z67hBVEUJ6KowQBRe0T9zt
uENeSdnt7195NVZmID0LT8SaODhNX63y3ns9N+xyV7I43mzyG+PSzXbmBCDC9L+tyLr6i430OnG4
tFX5VrYwa2tlo1e/hb8UGL+mpl8DPT3Jvi3MqvRWYymP9NZPDA4w4kt34E4HJQ7X2eWlXZhXUJl+
P2m/6vP+T7nksU3Sz/sXzOxW07Uf/F7y263WST9hv7M2FMN0s7i+/gmKpjtNmVGKUIttT5EiIh7J
ReeR0Chi84D4dzh80b9CLu9Id4MxojGrhB0NTWlzb5g2FLVcZ+zWtiAD9lV7/WhaqA2cKQvoKH50
5bN4Tt486OntQVHWzq5yo+GQOtyioz/j+omMSmarZR8uSzvDwxUsGnO70EmzJWdZVGw+iehfCXEz
aoUn+fDLLUteNjAeJ98MwVCOiR49VEGydcl7l3Wv56b0oFgUsAkSW6oB2WgCL5nhSaVCW+jXkf9H
ZgieDo90yAd7N2CsoaW0TbxFpajMU1F0ofbjbu5WHoaBepN9r49vEK3rlsTLIVZf7XI/sC6AF8bJ
7Uc/yRgGYicE32iOIcA/ZHOHOpzLSpChk0F3ku15jjcEwdDBHTY=
`protect end_protected
|
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/10/16 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Simple testebench for manual signal inspection of the Wishbone interfaces
--* and the DMA unit of CompressorTop.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity CompressorTop_tb is
end CompressorTop_tb;
architecture TB of CompressorTop_tb is
component CompressorTop
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
SlCycxSI : in std_logic;
SlStbxSI : in std_logic;
SlWexSI : in std_logic;
SlSelxDI : in std_logic_vector(3 downto 0);
SlAdrxDI : in std_logic_vector(4 downto 2);
SlDatxDI : in std_logic_vector(31 downto 0);
SlDatxDO : out std_logic_vector(31 downto 0);
SlAckxSO : out std_logic;
SlErrxSO : out std_logic;
IntxSO : out std_logic;
MaCycxSO : out std_logic;
MaStbxSO : out std_logic;
MaWexSO : out std_logic;
MaSelxDO : out std_logic_vector(3 downto 0);
MaAdrxDO : out std_logic_vector(31 downto 0);
MaDatxDO : out std_logic_vector(31 downto 0);
MaDatxDI : in std_logic_vector(31 downto 0);
MaAckxSI : in std_logic;
MaErrxSI : in std_logic);
end component;
constant PERIOD : time := 25 ns;
signal ClkxCI : std_logic := '0';
signal RstxRI : std_logic := '1';
signal SlCycxSI : std_logic := '0';
signal SlStbxSI : std_logic := '0';
signal SlWexSI : std_logic := '0';
signal SlSelxDI : std_logic_vector(3 downto 0) := "0000";
signal SlAdrxDI : std_logic_vector(4 downto 2) := (others => '0');
signal SlDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal SlDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal SlAckxSO : std_logic;
signal SlErrxSO : std_logic;
signal IntxSO : std_logic;
signal MaCycxSO : std_logic;
signal MaStbxSO : std_logic;
signal MaWexSO : std_logic;
signal MaSelxDO : std_logic_vector(3 downto 0) := (others => '0');
signal MaAdrxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal MaAckxSI : std_logic := '0';
signal MaErrxSI : std_logic := '0';
begin
ClkxCI <= not ClkxCI after PERIOD/2;
process
begin
RstxRI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RstxRI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
-- reset core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlSelxDI <= "1111";
SlDatxDI <= x"00000001";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- set inc dest addr flag and IE for in fifo full and for core done
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '1';
SlDatxDI <= x"00020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
-- setup dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '1';
SlDatxDI <= x"12345670";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup dma length
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "101";
SlWexSI <= '1';
SlDatxDI <= x"00000030";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup in fifo thresholds
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "010";
SlWexSI <= '1';
SlDatxDI <= x"000f0004";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"03020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"07060504";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0908";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0f0e0d0c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"05030201";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0706";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"1413120c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"08070605";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
--wait for PERIOD*2*20;
-- enable done interrupt
-- wait until ClkxCI'event and ClkxCI = '1';
-- SlCycxSI <= '1';
-- SlStbxSI <= '1';
-- SlAdrxDI <= "001";
-- SlWexSI <= '1';
-- SlDatxDI <= x"00200102";
-- wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
-- SlCycxSI <= '0';
-- SlStbxSI <= '0';
-- SlAdrxDI <= "000";
-- SlWexSI <= '0';
-- SlDatxDI <= x"00000000";
-- flush core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlDatxDI <= x"00000002";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait for PERIOD*200;
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
wait;
end process;
MaAckxSI <= MaCycxSO and MaStbxSO;
--MaErrxSI <= MaCycxSO and MaStbxSO;
DUT : CompressorTop
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
SlCycxSI => SlCycxSI,
SlStbxSI => SlStbxSI,
SlWexSI => SlWexSI,
SlSelxDI => SlSelxDI,
SlAdrxDI => SlAdrxDI,
SlDatxDI => SlDatxDI,
SlDatxDO => SlDatxDO,
SlAckxSO => SlAckxSO,
SlErrxSO => SlErrxSO,
IntxSO => IntxSO,
MaCycxSO => MaCycxSO,
MaStbxSO => MaStbxSO,
MaWexSO => MaWexSO,
MaSelxDO => MaSelxDO,
MaAdrxDO => MaAdrxDO,
MaDatxDO => MaDatxDO,
MaDatxDI => MaDatxDI,
MaAckxSI => MaAckxSI,
MaErrxSI => MaErrxSI);
end TB;
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
--Date : Thu May 12 11:41:56 2016
--Host : fx6 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target week1.bd
--Design : week1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_QJRQ3J is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_QJRQ3J;
architecture STRUCTURE of m00_couplers_imp_QJRQ3J is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(3 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(3 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1RWPDFB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_1RWPDFB;
architecture STRUCTURE of m01_couplers_imp_1RWPDFB is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(3 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(3 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1WKUKB2 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1WKUKB2;
architecture STRUCTURE of m02_couplers_imp_1WKUKB2 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_LVBNAE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_LVBNAE;
architecture STRUCTURE of m03_couplers_imp_LVBNAE is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(6 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(6 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(6 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(6 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(6 downto 0) <= S_AXI_araddr(6 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(6 downto 0) <= S_AXI_awaddr(6 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_1NBU6D8 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_1NBU6D8;
architecture STRUCTURE of m04_couplers_imp_1NBU6D8 is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m04_couplers_to_m04_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m04_couplers_to_m04_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m04_couplers_to_m04_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m04_couplers_to_m04_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_U0DM50 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_U0DM50;
architecture STRUCTURE of m05_couplers_imp_U0DM50 is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(6 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(6 downto 0);
M_AXI_arprot(2 downto 0) <= m05_couplers_to_m05_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(6 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(6 downto 0);
M_AXI_awprot(2 downto 0) <= m05_couplers_to_m05_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(6 downto 0) <= S_AXI_araddr(6 downto 0);
m05_couplers_to_m05_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(6 downto 0) <= S_AXI_awaddr(6 downto 0);
m05_couplers_to_m05_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_YRXD0T is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_YRXD0T;
architecture STRUCTURE of m06_couplers_imp_YRXD0T is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m06_couplers_to_m06_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m06_couplers_to_m06_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m06_couplers_to_m06_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m06_couplers_to_m06_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_2QEUYC is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_2QEUYC;
architecture STRUCTURE of s00_couplers_imp_2QEUYC is
component week1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component week1_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component week1_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity week1_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M05_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M05_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end week1_processing_system7_0_axi_periph_0;
architecture STRUCTURE of week1_processing_system7_0_axi_periph_0 is
component week1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component week1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(6 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(6 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1(0) <= M04_ARESETN(0);
M04_AXI_araddr(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M04_AXI_arprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID;
M04_AXI_awaddr(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M04_AXI_awprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1(0) <= M05_ARESETN(0);
M05_AXI_araddr(6 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0);
M05_AXI_arprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M05_AXI_arvalid <= m05_couplers_to_processing_system7_0_axi_periph_ARVALID;
M05_AXI_awaddr(6 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0);
M05_AXI_awprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M05_AXI_awvalid <= m05_couplers_to_processing_system7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_processing_system7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_processing_system7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_processing_system7_0_axi_periph_WVALID;
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1(0) <= M06_ARESETN(0);
M06_AXI_araddr(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M06_AXI_arprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M06_AXI_arvalid <= m06_couplers_to_processing_system7_0_axi_periph_ARVALID;
M06_AXI_awaddr(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M06_AXI_awprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M06_AXI_awvalid <= m06_couplers_to_processing_system7_0_axi_periph_AWVALID;
M06_AXI_bready <= m06_couplers_to_processing_system7_0_axi_periph_BREADY;
M06_AXI_rready <= m06_couplers_to_processing_system7_0_axi_periph_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_processing_system7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_processing_system7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_processing_system7_0_axi_periph_WREADY <= M05_AXI_wready;
m06_couplers_to_processing_system7_0_axi_periph_ARREADY <= M06_AXI_arready;
m06_couplers_to_processing_system7_0_axi_periph_AWREADY <= M06_AXI_awready;
m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_BVALID <= M06_AXI_bvalid;
m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RVALID <= M06_AXI_rvalid;
m06_couplers_to_processing_system7_0_axi_periph_WREADY <= M06_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_QJRQ3J
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m00_couplers_ARADDR(3 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(3 downto 0) => xbar_to_m00_couplers_AWADDR(3 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1RWPDFB
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m01_couplers_ARADDR(35 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(3 downto 0) => xbar_to_m01_couplers_AWADDR(35 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1WKUKB2
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m02_couplers_ARADDR(67 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(3 downto 0) => xbar_to_m02_couplers_AWADDR(67 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_LVBNAE
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(6 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(6 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(6 downto 0) => xbar_to_m03_couplers_ARADDR(102 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(6 downto 0) => xbar_to_m03_couplers_AWADDR(102 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_1NBU6D8
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN(0) => M04_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m04_couplers_ARADDR(131 downto 128),
S_AXI_arprot(2 downto 0) => xbar_to_m04_couplers_ARPROT(14 downto 12),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(3 downto 0) => xbar_to_m04_couplers_AWADDR(131 downto 128),
S_AXI_awprot(2 downto 0) => xbar_to_m04_couplers_AWPROT(14 downto 12),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_U0DM50
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN(0) => M05_ARESETN_1(0),
M_AXI_araddr(6 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0),
M_AXI_arprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m05_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(6 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0),
M_AXI_awprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m05_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(6 downto 0) => xbar_to_m05_couplers_ARADDR(166 downto 160),
S_AXI_arprot(2 downto 0) => xbar_to_m05_couplers_ARPROT(17 downto 15),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(6 downto 0) => xbar_to_m05_couplers_AWADDR(166 downto 160),
S_AXI_awprot(2 downto 0) => xbar_to_m05_couplers_AWPROT(17 downto 15),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_YRXD0T
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN(0) => M06_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m06_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m06_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m06_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m06_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m06_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m06_couplers_ARADDR(195 downto 192),
S_AXI_arprot(2 downto 0) => xbar_to_m06_couplers_ARPROT(20 downto 18),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(3 downto 0) => xbar_to_m06_couplers_AWADDR(195 downto 192),
S_AXI_awprot(2 downto 0) => xbar_to_m06_couplers_AWPROT(20 downto 18),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_2QEUYC
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component week1_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 18) => xbar_to_m06_couplers_ARPROT(20 downto 18),
m_axi_arprot(17 downto 15) => xbar_to_m05_couplers_ARPROT(17 downto 15),
m_axi_arprot(14 downto 12) => xbar_to_m04_couplers_ARPROT(14 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 18) => xbar_to_m06_couplers_AWPROT(20 downto 18),
m_axi_awprot(17 downto 15) => xbar_to_m05_couplers_AWPROT(17 downto 15),
m_axi_awprot(14 downto 12) => xbar_to_m04_couplers_AWPROT(14 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity week1 is
port (
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of week1 : entity is "week1,IP_Integrator,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=week1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=23,numReposBlks=14,numNonXlnxBlks=9,numHierBlks=9,maxHierDepth=0,da_axi4_cnt=7,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of week1 : entity is "week1.hwdef";
end week1;
architecture STRUCTURE of week1 is
component week1_zed_audio_0_0 is
port (
clk_100 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
hphone_l : in STD_LOGIC_VECTOR ( 23 downto 0 );
hphone_l_valid : in STD_LOGIC;
hphone_r : in STD_LOGIC_VECTOR ( 23 downto 0 );
hphone_r_valid_dummy : in STD_LOGIC;
line_in_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
line_in_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
new_sample : out STD_LOGIC;
sample_clk_48k : out STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC
);
end component week1_zed_audio_0_0;
component week1_audio_to_AXI_0_1 is
port (
audio_in_l : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_in_r : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_in_valid : in STD_LOGIC;
audio_out_valid_irq : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_audio_to_AXI_0_1;
component week1_AXI_to_audio_0_0 is
port (
audio_out_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_valid : out STD_LOGIC;
audio_in_valid_irq : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_AXI_to_audio_0_0;
component week1_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component week1_processing_system7_0_0;
component week1_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component week1_rst_processing_system7_0_100M_0;
component week1_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component week1_xlconstant_0_1;
component week1_AXI_to_audio_0_1 is
port (
audio_out_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_valid : out STD_LOGIC;
audio_in_valid_irq : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_AXI_to_audio_0_1;
component week1_audio_mixer_0_0 is
port (
audio_mixed_a_b_left_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_mixed_a_b_right_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_a_left_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_a_right_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_b_left_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_b_right_in : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component week1_audio_mixer_0_0;
component week1_FILTER_IIR_0_0 is
port (
AUDIO_OUT_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_OUT_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
FILTER_DONE : out STD_LOGIC;
SAMPLE_TRIG : in STD_LOGIC;
AUDIO_IN_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_IN_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_FILTER_IIR_0_0;
component week1_Volume_Pregain_0_0 is
port (
OUT_VOLCTRL_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_VOLCTRL_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
IN_SIG_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_Volume_Pregain_0_0;
component week1_FILTER_IIR_0_1 is
port (
AUDIO_OUT_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_OUT_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
FILTER_DONE : out STD_LOGIC;
SAMPLE_TRIG : in STD_LOGIC;
AUDIO_IN_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_IN_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_FILTER_IIR_0_1;
component week1_Volume_Pregain_0_1 is
port (
OUT_VOLCTRL_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_VOLCTRL_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
IN_SIG_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_Volume_Pregain_0_1;
signal AC_GPIO1_1 : STD_LOGIC;
signal AC_GPIO2_1 : STD_LOGIC;
signal AC_GPIO3_1 : STD_LOGIC;
signal AXI_to_audio_0_audio_out_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_0_audio_out_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_0_audio_out_valid : STD_LOGIC;
signal AXI_to_audio_1_audio_out_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_1_audio_out_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_0_AUDIO_OUT_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_0_AUDIO_OUT_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_1_AUDIO_OUT_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_1_AUDIO_OUT_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal GND_1 : STD_LOGIC;
signal Net : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal Volume_Pregain_0_OUT_RDY : STD_LOGIC;
signal Volume_Pregain_0_OUT_VOLCTRL_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_0_OUT_VOLCTRL_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_1_OUT_RDY : STD_LOGIC;
signal Volume_Pregain_1_OUT_VOLCTRL_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_1_OUT_VOLCTRL_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_mixer_0_audio_mixed_a_b_left_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_mixer_0_audio_mixed_a_b_right_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_to_AXI_0_audio_out_valid_irq : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal zed_audio_0_AC_ADR0 : STD_LOGIC;
signal zed_audio_0_AC_ADR1 : STD_LOGIC;
signal zed_audio_0_AC_GPIO0 : STD_LOGIC;
signal zed_audio_0_AC_MCLK : STD_LOGIC;
signal zed_audio_0_AC_SCK : STD_LOGIC;
signal zed_audio_0_line_in_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_audio_0_line_in_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_audio_0_new_sample : STD_LOGIC;
signal NLW_AXI_to_audio_1_audio_out_valid_UNCONNECTED : STD_LOGIC;
signal NLW_FILTER_IIR_0_FILTER_DONE_UNCONNECTED : STD_LOGIC;
signal NLW_FILTER_IIR_1_FILTER_DONE_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_zed_audio_0_sample_clk_48k_UNCONNECTED : STD_LOGIC;
begin
AC_ADR0 <= zed_audio_0_AC_ADR0;
AC_ADR1 <= zed_audio_0_AC_ADR1;
AC_GPIO0 <= zed_audio_0_AC_GPIO0;
AC_GPIO1_1 <= AC_GPIO1;
AC_GPIO2_1 <= AC_GPIO2;
AC_GPIO3_1 <= AC_GPIO3;
AC_MCLK <= zed_audio_0_AC_MCLK;
AC_SCK <= zed_audio_0_AC_SCK;
AXI_to_audio_0: component week1_AXI_to_audio_0_0
port map (
audio_in_valid_irq => xlconstant_0_dout(0),
audio_out_l(23 downto 0) => AXI_to_audio_0_audio_out_l(23 downto 0),
audio_out_r(23 downto 0) => AXI_to_audio_0_audio_out_r(23 downto 0),
audio_out_valid => AXI_to_audio_0_audio_out_valid,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
AXI_to_audio_1: component week1_AXI_to_audio_0_1
port map (
audio_in_valid_irq => xlconstant_0_dout(0),
audio_out_l(23 downto 0) => AXI_to_audio_1_audio_out_l(23 downto 0),
audio_out_r(23 downto 0) => AXI_to_audio_1_audio_out_r(23 downto 0),
audio_out_valid => NLW_AXI_to_audio_1_audio_out_valid_UNCONNECTED,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID
);
FILTER_IIR_0: component week1_FILTER_IIR_0_0
port map (
AUDIO_IN_L(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_L(23 downto 0),
AUDIO_IN_R(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_R(23 downto 0),
AUDIO_OUT_L(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_L(23 downto 0),
AUDIO_OUT_R(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_R(23 downto 0),
FILTER_DONE => NLW_FILTER_IIR_0_FILTER_DONE_UNCONNECTED,
SAMPLE_TRIG => Volume_Pregain_0_OUT_RDY,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(6 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s00_axi_awaddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(6 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID
);
FILTER_IIR_1: component week1_FILTER_IIR_0_1
port map (
AUDIO_IN_L(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_L(23 downto 0),
AUDIO_IN_R(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_R(23 downto 0),
AUDIO_OUT_L(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_L(23 downto 0),
AUDIO_OUT_R(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_R(23 downto 0),
FILTER_DONE => NLW_FILTER_IIR_1_FILTER_DONE_UNCONNECTED,
SAMPLE_TRIG => Volume_Pregain_1_OUT_RDY,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
s00_axi_awaddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID
);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
Volume_Pregain_0: component week1_Volume_Pregain_0_0
port map (
IN_SIG_L(23 downto 0) => AXI_to_audio_0_audio_out_l(23 downto 0),
IN_SIG_R(23 downto 0) => AXI_to_audio_0_audio_out_r(23 downto 0),
OUT_RDY => Volume_Pregain_0_OUT_RDY,
OUT_VOLCTRL_L(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_L(23 downto 0),
OUT_VOLCTRL_R(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_R(23 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID
);
Volume_Pregain_1: component week1_Volume_Pregain_0_1
port map (
IN_SIG_L(23 downto 0) => AXI_to_audio_1_audio_out_l(23 downto 0),
IN_SIG_R(23 downto 0) => AXI_to_audio_1_audio_out_r(23 downto 0),
OUT_RDY => Volume_Pregain_1_OUT_RDY,
OUT_VOLCTRL_L(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_L(23 downto 0),
OUT_VOLCTRL_R(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_R(23 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID
);
audio_mixer_0: component week1_audio_mixer_0_0
port map (
audio_channel_a_left_in(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_L(23 downto 0),
audio_channel_a_right_in(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_R(23 downto 0),
audio_channel_b_left_in(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_L(23 downto 0),
audio_channel_b_right_in(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_R(23 downto 0),
audio_mixed_a_b_left_out(23 downto 0) => audio_mixer_0_audio_mixed_a_b_left_out(23 downto 0),
audio_mixed_a_b_right_out(23 downto 0) => audio_mixer_0_audio_mixed_a_b_right_out(23 downto 0)
);
audio_to_AXI_0: component week1_audio_to_AXI_0_1
port map (
audio_in_l(23 downto 0) => zed_audio_0_line_in_l(23 downto 0),
audio_in_r(23 downto 0) => zed_audio_0_line_in_r(23 downto 0),
audio_in_valid => zed_audio_0_new_sample,
audio_out_valid_irq => audio_to_AXI_0_audio_out_valid_irq,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
processing_system7_0: component week1_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => audio_to_AXI_0_audio_out_valid_irq,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.week1_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
M00_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
M00_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
M01_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
M01_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
M02_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
M02_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(6 downto 0),
M03_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(6 downto 0),
M03_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(3 downto 0),
M04_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(3 downto 0),
M04_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
M05_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
M05_AXI_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
M05_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
M05_AXI_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
M06_ACLK => processing_system7_0_FCLK_CLK0,
M06_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M06_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(3 downto 0),
M06_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
M06_AXI_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
M06_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(3 downto 0),
M06_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
M06_AXI_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
M06_AXI_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component week1_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconstant_0: component week1_xlconstant_0_1
port map (
dout(0) => xlconstant_0_dout(0)
);
zed_audio_0: component week1_zed_audio_0_0
port map (
AC_ADR0 => zed_audio_0_AC_ADR0,
AC_ADR1 => zed_audio_0_AC_ADR1,
AC_GPIO0 => zed_audio_0_AC_GPIO0,
AC_GPIO1 => AC_GPIO1_1,
AC_GPIO2 => AC_GPIO2_1,
AC_GPIO3 => AC_GPIO3_1,
AC_MCLK => zed_audio_0_AC_MCLK,
AC_SCK => zed_audio_0_AC_SCK,
AC_SDA => AC_SDA,
clk_100 => processing_system7_0_FCLK_CLK0,
hphone_l(23 downto 0) => audio_mixer_0_audio_mixed_a_b_left_out(23 downto 0),
hphone_l_valid => AXI_to_audio_0_audio_out_valid,
hphone_r(23 downto 0) => audio_mixer_0_audio_mixed_a_b_right_out(23 downto 0),
hphone_r_valid_dummy => AXI_to_audio_0_audio_out_valid,
line_in_l(23 downto 0) => zed_audio_0_line_in_l(23 downto 0),
line_in_r(23 downto 0) => zed_audio_0_line_in_r(23 downto 0),
new_sample => zed_audio_0_new_sample,
sample_clk_48k => NLW_zed_audio_0_sample_clk_48k_UNCONNECTED
);
end STRUCTURE;
|
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port (
-- 16MHz pixel clock from BBC Micro
sysClk_in : in std_logic;
-- Input 15.625kHz RGB signals
rgbi_in : in std_logic_vector(3 downto 0);
hSync_in : in std_logic;
vSync_in : in std_logic;
-- Output 31.250kHz VGA signals
rgbi_out : out std_logic_vector(3 downto 0);
hSync_out : out std_logic;
vSync_out : out std_logic
);
end entity;
architecture rtl of top_level is
-- Config parameters
constant SAMPLE_OFFSET : integer := 248;
constant SAMPLE_WIDTH : integer := 656;
constant HORIZ_RT : integer := 96;
constant HORIZ_BP : integer := 30;
constant HORIZ_DISP : integer := 656;
constant HORIZ_FP : integer := 18;
-- VSYNC state-machine
type VType is (
S_WAIT_VSYNC,
S_EXTRA1,
S_EXTRA2,
S_NOEXTRA,
S_ASSERT_VSYNC
);
-- Clocks
signal clk16 : std_logic;
signal clk25 : std_logic;
-- Registers in the 16MHz clock domain:
signal state : VType := S_WAIT_VSYNC;
signal state_next : VType;
signal hSync_s16 : std_logic;
signal vSync_s16 : std_logic;
signal hSyncStart : std_logic;
signal vSyncStart : std_logic;
signal hCount16 : unsigned(9 downto 0) := (others => '0');
signal hCount16_next : unsigned(9 downto 0);
signal lineToggle : std_logic := '1';
signal lineToggle_next : std_logic;
-- Registers in the 25MHz clock domain:
signal hSync_s25a : std_logic;
signal hSync_s25b : std_logic;
signal hCount25 : unsigned(9 downto 0) := to_unsigned(HORIZ_DISP + HORIZ_FP, 10);
signal hCount25_next : unsigned(9 downto 0);
-- Signals on the write side of the RAMs:
signal writeEn0 : std_logic;
signal writeEn1 : std_logic;
-- Signals on the read side of the RAMs:
signal ram0Data : std_logic_vector(3 downto 0);
signal ram1Data : std_logic_vector(3 downto 0);
begin
-- Generate 16MHz and 25MHz clocks
clk_gen: entity work.clk_gen
port map(
inclk0 => sysClk_in,
c0 => clk16,
c1 => clk25
);
-- Two RAM blocks, each straddling the 16MHz and 25MHz clock domains, for storing pixel lines;
-- whilst we're reading from one at 25MHz, we're writing to the other at 16MHz. Their roles
-- swap every incoming 64us scanline.
--
ram0: entity work.dpram
port map(
-- Write port
wrclock => clk16,
wraddress => std_logic_vector(hCount16),
wren => writeEn0,
data => rgbi_in,
-- Read port
rdclock => clk25,
rdaddress => std_logic_vector(hCount25),
q => ram0data
);
ram1: entity work.dpram
port map(
-- Write port
wrclock => clk16,
wraddress => std_logic_vector(hCount16),
wren => writeEn1,
data => rgbi_in,
-- Read port
rdclock => clk25,
rdaddress => std_logic_vector(hCount25),
q => ram1data
);
-- 16MHz clock domain ---------------------------------------------------------------------------
process(clk16)
begin
if ( rising_edge(clk16) ) then
hSync_s16 <= hSync_in;
vSync_s16 <= vSync_in;
hCount16 <= hCount16_next;
lineToggle <= lineToggle_next;
state <= state_next;
end if;
end process;
-- Pulses representing the start of incoming HSYNC & VSYNC
hSyncStart <=
'1' when hSync_s16 = '0' and hSync_in = '1'
else '0';
vSyncStart <=
'1' when vSync_s16 = '0' and vSync_in = '1'
else '0';
-- Create horizontal count, aligned to incoming HSYNC
hCount16_next <=
to_unsigned(2**10 - SAMPLE_OFFSET + 1, 10) when hSyncStart = '1'
else hCount16 + 1;
-- Toggle every incoming HSYNC
lineToggle_next <=
not(lineToggle) when hSyncStart = '1'
else lineToggle;
-- Generate interleaved write signals for dual-port RAMs
writeEn0 <=
'1' when hCount16 < SAMPLE_WIDTH and lineToggle = '0'
else '0';
writeEn1 <=
'1' when hCount16 < SAMPLE_WIDTH and lineToggle = '1'
else '0';
-- Interleave output of dual-port RAMs
rgbi_out <=
ram0Data when lineToggle = '1'
else ram1Data;
-- State machine to generate VGA VSYNC
process(state, vSyncStart, hSyncStart, hCount16(9))
begin
state_next <= state;
case state is
-- Wait for VSYNC start
when S_WAIT_VSYNC =>
vSync_out <= '1';
if ( vSyncStart = '1' ) then
if ( hCount16(9) = '0' ) then
state_next <= S_EXTRA1;
else
state_next <= S_NOEXTRA;
end if;
end if;
-- Insert an extra 64us scanline
when S_EXTRA1 =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_EXTRA2; -- 0.5 lines after VSYNC
end if;
when S_EXTRA2 =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_ASSERT_VSYNC; -- 1.5 lines after VSYNC
end if;
-- Don't insert an extra 64us scanline
when S_NOEXTRA =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_ASSERT_VSYNC; -- 0.5 lines after VSYNC
end if;
-- Assert VGA VSYNC for 64us
when S_ASSERT_VSYNC =>
vSync_out <= '0';
if ( hSyncStart = '1' ) then
state_next <= S_WAIT_VSYNC;
end if;
end case;
end process;
-- 25MHz clock domain ---------------------------------------------------------------------------
process(clk25)
begin
if ( rising_edge(clk25) ) then
hCount25 <= hCount25_next;
hSync_s25a <= hSync_in;
hSync_s25b <= hSync_s25a;
end if;
end process;
-- Generate 25MHz hCount
hCount25_next <=
to_unsigned(2**10 - HORIZ_RT - HORIZ_BP, 10) when
(hSync_s25a = '1' and hSync_s25b = '0') or
(hCount25 = HORIZ_DISP + HORIZ_FP - 1)
else hCount25 + 1;
-- Generate VGA HSYNC
hSync_out <=
'0' when hCount25 >= to_unsigned(2**10 - HORIZ_RT - HORIZ_BP, 10) and hCount25 < to_unsigned(2**10 - HORIZ_BP, 10)
else '1';
end architecture;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver channel status capture module ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, gedra@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/19 16:58:37 gedra
-- Fixed bug.
--
-- Revision 1.3 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.2 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.1 2004/06/05 17:16:46 gedra
-- Channel status/user data capture register
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rx_package.all;
entity rx_cap_reg is
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
--cap_ctrl_wr: in std_logic; -- control register write
--cap_ctrl_rd: in std_logic; -- control register read
--cap_data_rd: in std_logic; -- data register read
cap_reg: in std_logic_vector(31 downto 0);
cap_din: in std_logic_vector(31 downto 0); -- write data
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
ud_a_en: in std_logic; -- user data ch. A enable
ud_b_en: in std_logic; -- user data ch. B enable
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
cap_dout: out std_logic_vector(31 downto 0); -- read data
cap_evt: out std_logic); -- capture event (interrupt)
end rx_cap_reg;
architecture rtl of rx_cap_reg is
signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0);
signal cap_reg_1, cap_new : std_logic_vector(31 downto 0);
signal bitlen, cap_len : integer range 0 to 63;
signal bitpos, cur_pos : integer range 0 to 255;
signal chid, cdata, compared : std_logic;
signal d_enable : std_logic_vector(3 downto 0);
begin
-- Data bus or'ing
cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout;
chid <= cap_reg(6);
cdata <= cap_reg(7);
-- capture data register
CDAT: process (clk, rst)
begin
if rst = '1' then
cap_reg_1 <= (others => '0'); --
cap_new <= (others => '0');
cur_pos <= 0;
cap_len <= 0;
cap_evt <= '0';
compared <= '0';
bitpos <= 0;
bitlen <= 0;
else
if rising_edge(clk) then
bitlen <= to_integer(unsigned(cap_reg(5 downto 0)));
bitpos <= to_integer(unsigned(cap_reg(15 downto 8)));
if bitlen > 0 then -- bitlen = 0 disables the capture function
-- bit counter, 0 to 191
if rx_block_start = '1' then
cur_pos <= 0;
cap_len <= 0;
cap_new <= (others => '0');
compared <= '0';
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
cur_pos <= cur_pos + 1;
end if;
-- capture bits
if cur_pos >= bitpos and cap_len < bitlen then
case d_enable is
when "0001" => -- user data channel A
if cdata = '0' and chid = '0' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0010" => -- user data channel B
if cdata = '0' and chid = '1' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0100" => -- channel status ch. A
if cdata = '1' and chid = '0' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "1000" => -- channel status ch. B
if cdata = '1' and chid = '1' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when others => null;
end case;
end if;
-- if all bits captured, check with previous data
if cap_len = bitlen and compared = '0' then
compared <= '1';
-- event generated if captured bits differ
if cap_reg_1 /= cap_new then
cap_evt <= '1';
end if;
cap_reg_1 <= cap_new;
else
cap_evt <= '0';
end if;
end if;
end if;
end if;
end process CDAT;
d_enable(0) <= ud_a_en;
d_enable(1) <= ud_b_en;
d_enable(2) <= cs_a_en;
d_enable(3) <= cs_b_en;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_axi_lite
-- Source Path: lms_pcore/lms_pcore_axi_lite
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_axi_lite IS
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END lms_pcore_axi_lite;
ARCHITECTURE rtl OF lms_pcore_axi_lite IS
-- Component Declarations
COMPONENT lms_pcore_addr_decoder
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
data_write : IN std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : IN std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : IN std_logic; -- ufix1
rd_enb : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
data_read : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite_module
PORT( clk : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
data_read : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
data_write : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : OUT std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : OUT std_logic; -- ufix1
rd_enb : OUT std_logic; -- ufix1
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_addr_decoder
USE ENTITY work.lms_pcore_addr_decoder(rtl);
FOR ALL : lms_pcore_axi_lite_module
USE ENTITY work.lms_pcore_axi_lite_module(rtl);
-- Signals
SIGNAL top_data_write : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL top_addr_sel : std_logic_vector(13 DOWNTO 0); -- ufix14
SIGNAL top_wr_enb : std_logic; -- ufix1
SIGNAL top_rd_enb : std_logic; -- ufix1
SIGNAL top_data_read : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL write_x_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL top_reset_internal : std_logic; -- ufix1
BEGIN
u_lms_pcore_addr_decoder_inst : lms_pcore_addr_decoder
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
reset => reset,
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
read_cop_out_ready => read_cop_out_ready, -- ufix1
cop_reg_strobe => cop_reg_strobe, -- ufix1
read_e_k => read_e_k, -- sfix16_En14
data_read => top_data_read, -- ufix32
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k_tmp, -- sfix16_En14
write_d_k => write_d_k_tmp -- sfix16_En14
);
u_lms_pcore_axi_lite_module_inst : lms_pcore_axi_lite_module
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
data_read => top_data_read, -- ufix32
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
reset_internal => top_reset_internal -- ufix1
);
reset_internal <= top_reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
write_x_k <= write_x_k_tmp;
write_d_k <= write_d_k_tmp;
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_axi_lite
-- Source Path: lms_pcore/lms_pcore_axi_lite
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_axi_lite IS
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END lms_pcore_axi_lite;
ARCHITECTURE rtl OF lms_pcore_axi_lite IS
-- Component Declarations
COMPONENT lms_pcore_addr_decoder
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
data_write : IN std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : IN std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : IN std_logic; -- ufix1
rd_enb : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
data_read : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite_module
PORT( clk : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
data_read : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
data_write : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : OUT std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : OUT std_logic; -- ufix1
rd_enb : OUT std_logic; -- ufix1
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_addr_decoder
USE ENTITY work.lms_pcore_addr_decoder(rtl);
FOR ALL : lms_pcore_axi_lite_module
USE ENTITY work.lms_pcore_axi_lite_module(rtl);
-- Signals
SIGNAL top_data_write : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL top_addr_sel : std_logic_vector(13 DOWNTO 0); -- ufix14
SIGNAL top_wr_enb : std_logic; -- ufix1
SIGNAL top_rd_enb : std_logic; -- ufix1
SIGNAL top_data_read : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL write_x_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL top_reset_internal : std_logic; -- ufix1
BEGIN
u_lms_pcore_addr_decoder_inst : lms_pcore_addr_decoder
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
reset => reset,
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
read_cop_out_ready => read_cop_out_ready, -- ufix1
cop_reg_strobe => cop_reg_strobe, -- ufix1
read_e_k => read_e_k, -- sfix16_En14
data_read => top_data_read, -- ufix32
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k_tmp, -- sfix16_En14
write_d_k => write_d_k_tmp -- sfix16_En14
);
u_lms_pcore_axi_lite_module_inst : lms_pcore_axi_lite_module
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
data_read => top_data_read, -- ufix32
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
reset_internal => top_reset_internal -- ufix1
);
reset_internal <= top_reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
write_x_k <= write_x_k_tmp;
write_d_k <= write_d_k_tmp;
END rtl;
|
library verilog;
use verilog.vl_types.all;
entity arm_if_stage is
port(
pc : in vl_logic_vector(31 downto 0);
IFID_Write : in vl_logic;
inst : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
next_pc : out vl_logic_vector(31 downto 0);
IFID_inst : out vl_logic_vector(31 downto 0)
);
end arm_if_stage;
|
architecture rtl of fifo is
begin
process begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end process;
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RECV_REQ_QUEUE_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);
begin
end architecture rtl;
|
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; --V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector; --V93
FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;--V93
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-V93
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-V93
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-V93
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2360.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p10n01i02360ent IS
END c07s02b07x00p10n01i02360ent;
ARCHITECTURE c07s02b07x00p10n01i02360arch OF c07s02b07x00p10n01i02360ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
BEGIN
k := 2.5**4;
wait for 5 ns;
assert NOT(k=39.0625)
report "***PASSED TEST: c07s02b07x00p10n01i02360"
severity NOTE;
assert (k=39.0625)
report "***FAILED TEST: c07s02b07x00p10n01i02360 - Exponentiation with an integer exponent is equivalent to repeated multiplication of the left operand by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p10n01i02360arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2360.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p10n01i02360ent IS
END c07s02b07x00p10n01i02360ent;
ARCHITECTURE c07s02b07x00p10n01i02360arch OF c07s02b07x00p10n01i02360ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
BEGIN
k := 2.5**4;
wait for 5 ns;
assert NOT(k=39.0625)
report "***PASSED TEST: c07s02b07x00p10n01i02360"
severity NOTE;
assert (k=39.0625)
report "***FAILED TEST: c07s02b07x00p10n01i02360 - Exponentiation with an integer exponent is equivalent to repeated multiplication of the left operand by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p10n01i02360arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2360.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p10n01i02360ent IS
END c07s02b07x00p10n01i02360ent;
ARCHITECTURE c07s02b07x00p10n01i02360arch OF c07s02b07x00p10n01i02360ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
BEGIN
k := 2.5**4;
wait for 5 ns;
assert NOT(k=39.0625)
report "***PASSED TEST: c07s02b07x00p10n01i02360"
severity NOTE;
assert (k=39.0625)
report "***FAILED TEST: c07s02b07x00p10n01i02360 - Exponentiation with an integer exponent is equivalent to repeated multiplication of the left operand by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p10n01i02360arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P32LS16_tb is
end ADT7310P32LS16_tb;
architecture behavior of ADT7310P32LS16_tb is
component ADT7310P32LS16
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
ADT7310CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
SPICounterPreset_i : in std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic
);
end component;
-- component generics
constant DataWidth : integer := 8;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal ADT7310CS_n_o : std_logic;
signal SPI_Data_i : std_logic_vector(7 downto 0);
signal SPI_Write_o : std_logic;
signal SPI_ReadNext_o : std_logic;
signal SPI_Data_o : std_logic_vector(7 downto 0);
signal SPI_FIFOFull_i : std_logic;
signal SPI_FIFOEmpty_i : std_logic;
signal SPI_Transmission_i : std_logic;
signal SPICounterPreset_i : std_logic_vector(15 downto 0);
signal Threshold_i : std_logic_vector(15 downto 0);
signal PeriodCounterPresetH_i : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
signal SensorValue_real : real;
signal SPI_CPOL_o : std_logic;
signal SPI_CPHA_o : std_logic;
signal SPI_LSBFE_o : std_logic;
signal SPI_SPPR_SPR_o : std_logic_vector(7 downto 0);
-- look into the ADT7310P32LS16 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_i : std_logic; -- directly from inside SPI_FSM
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal SPIFSM_Done_a : std_logic; -- SPIFSM_Done_i and SPIFSM_Done_d
-- ADT7310 component ports
signal SCLK_s : std_logic := '1';
signal DOUT_s : std_logic;
signal DIN_s : std_logic := '0';
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
-- SPI Master generics
constant SPPRWidth : integer := 4;
constant SPRWidth : integer := 4;
constant SPIFIFOReadWidth : integer := 4;
constant SPIFIFOWriteWidth : integer := 4;
-- SPI Master component ports
signal SPI_ScanEnable_s : std_logic := '0';
signal SPI_ScanClk_s : std_logic := '0';
signal SPI_ScanDataIn_s : std_logic := '0';
signal SPI_ScanDataOut_s : std_logic := '0';
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: ADT7310P32LS16
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
ADT7310CS_n_o => ADT7310CS_n_o,
SPI_Data_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Data_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
SPICounterPreset_i => SPICounterPreset_i,
Threshold_i => Threshold_i,
PeriodCounterPresetH_i => PeriodCounterPresetH_i,
PeriodCounterPresetL_i => PeriodCounterPresetL_i,
SensorValue_o => SensorValue_o,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o
);
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_i
);
SPIFSM_Done_d <= SPIFSM_Done_i after 1.0 ns;
SPIFSM_Done_a <= SPIFSM_Done_i and SPIFSM_Done_d;
spi_master_1: spi_master
generic map (
DataWidth => DataWidth,
SPPRWidth => SPPRWidth,
SPRWidth => SPRWidth,
FIFOReadWidth => SPIFIFOReadWidth,
FIFOWriteWidth => SPIFIFOWriteWidth
)
port map (
Reset_n => Reset_n_i,
Clk => Clk_i,
-- IO
SCK_o => SCLK_s,
MOSI_o => DIN_s,
MISO_i => DOUT_s,
-- control signals
CPOL_i => SPI_CPOL_o,
CPHA_i => SPI_CPHA_o,
LSBFE_i => SPI_LSBFE_o,
SPPR_i => SPI_SPPR_SPR_o(7 downto 4),
SPR_i => SPI_SPPR_SPR_o(3 downto 0),
Transmission_o => SPI_Transmission_i,
Write_i => SPI_Write_o,
ReadNext_i => SPI_ReadNext_o,
Data_i => SPI_Data_o,
Data_o => SPI_Data_i,
FIFOFull_o => SPI_FIFOFull_i,
FIFOEmpty_o => SPI_FIFOEmpty_i,
ScanEnable_i => SPI_ScanEnable_s,
ScanClk_i => SPI_ScanClk_s,
ScanDataIn_i => SPI_ScanDataIn_s,
ScanDataOut_o => SPI_ScanDataOut_s
);
adt7310_1: adt7310_model
port map (
SCLK_i => SCLK_s,
DOUT_o => DOUT_s,
DIN_i => DIN_s,
CS_n_i => ADT7310CS_n_o,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
-- constant value for reconfig signal
SPI_SPPR_SPR_o <= "00000000";
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
SPICounterPreset_i <= "0101110111000000";
Threshold_i <= "0000000000011110";
PeriodCounterPresetH_i <= "0000000000000000";
PeriodCounterPresetL_i <= "0000000000001010";
wait for 2.3*ClkPeriode;
assert SPI_CPOL_o = '1'
report "Dynamic signal SPI_CPOL_o should have constant value '1'" severity failure;
assert SPI_CPHA_o = '1'
report "Dynamic signal SPI_CPHA_o should have constant value '1'" severity failure;
assert SPI_LSBFE_o = '0'
report "Dynamic signal SPI_LSBFE_o should have constant value '0'" severity failure;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:15:07 09/02/2015
-- Design Name:
-- Module Name: DM74LS151 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DM74LS151 is
Port ( C : in STD_LOGIC;
B : in STD_LOGIC;
A : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (7 downto 0);
Strobe : in STD_LOGIC;
Y : out STD_LOGIC;
W : out STD_LOGIC);
end DM74LS151;
architecture Behavioral of DM74LS151 is
-- Declaracion de senales embebidas
signal Sel : STD_LOGIC_VECTOR (2 downto 0);
signal Temp: STD_LOGIC;
begin
-- Agrupar C, B y A en una sola senal embebida
-- para facilidad de manejo
Sel <= C & B & A;
-- Compartamiento Concurrente utilizando When/Else
Temp <= '0' when Strobe = '1' else
D(0) when Sel = "000" else
D(1) when Sel = "001" else
D(2) when Sel = "010" else
D(3) when Sel = "011" else
D(4) when Sel = "100" else
D(5) when Sel = "101" else
D(6) when Sel = "110" else
D(7);
Y <= Temp;
W <= not Temp;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity HazardUnit is
Port (
ID_EX_MemRead : in std_logic;
ID_EX_RegRt : in std_logic_vector(4 downto 0);
IF_ID_RegRs : in std_logic_vector(4 downto 0);
IF_ID_RegRt : in std_logic_vector(4 downto 0);
Jump : in std_logic;
STALL : out std_logic
);
end HazardUnit;
architecture Behavioral of HazardUnit is
begin
-- Load-use Hazard
STALL <= '1' when (ID_EX_MemRead = '1' and
((ID_EX_RegRt = IF_ID_RegRs) or (ID_EX_RegRt = IF_ID_RegRt)))
else '0';
end Behavioral; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
architecture RTL of FIFO is
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
PROC_1 : process
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
a <= 2;
b := 1;
a <= 2;
b := 3;
a <= 3;
b := 10;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro is
port (r : out std_logic);
end repro;
architecture beh of repro is
begin
r <= '1';
assert (unsigned'(b"1001_0001") srl 1) = b"0100_1000";
assert (unsigned'(b"1001_0001") sll 1) = b"0010_0010";
assert (signed'(b"1001_0001") srl 1) = b"0100_1000";
assert (signed'(b"1001_0001") sll 1) = b"0010_0010";
-- assert false report to_bstring(signed'(b"1001_0001") srl 1);
end architecture beh;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2;
USE axi_quad_spi_v3_2.axi_quad_spi;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
di : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=1,C_FAMILY=zynq,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000"
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:24:12 07/09/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC;
Card : in STD_LOGIC_VECTOR (4 downto 0);
F : out STD_LOGIC_VECTOR (7 downto 0);
Cout : out STD_LOGIC);
end ALU;
architecture Behavioral of ALU is
signal A1,B1,P : STD_LOGIC_VECTOR (8 downto 0) := (others => '0');
begin
A1(7 downto 0) <= A;
B1(7 downto 0) <= B;
WITH Card SELECT
P <=
A1+B1 WHEN "00000", ---A+B
A1+B1+Cin WHEN "00001", ---A+B+Cin
A1-B1 WHEN "00010", ---A-B
A1-B1-Cin WHEN "00011", ---A-B-Cin
B1-A1 WHEN "00100", ---B-A
B1-A1-Cin WHEN "00101", ---B-A-Cin
A1 WHEN "00110", ---A
B1 WHEN "00111", ---B
NOT A1 WHEN "01000", ---/A
NOT B1 WHEN "01001", ---/B
A1 or B1 WHEN "01010", ---A+B
A1 and B1 WHEN "01011", ---A*B
A1 XNOR B1 WHEN "01100", ---A xnor B
A1 XOR B1 WHEN "01101", ---A xor B
NOT(A1 and B1) WHEN "01110", ---not (A * B)
"000000000" WHEN "01111", ---0
"ZZZZZZZZZ" WHEN OTHERS; ---others
F <= P(7 downto 0);
Cout <= P(8);
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests23 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END vests23;
ARCHITECTURE c01s01b01x01p05n02i00749arch OF vests23 IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a :record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record := (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) ;
signal V2 : severity_level_vector(zero to fifteen);
signal V3 : integer_vector(zero to fifteen) ;
signal V4 : real_vector(zero to fifteen) ;
signal V5 : time_vector (zero to fifteen);
signal V6 : natural_vector(zero to fifteen);
signal V7 : positive_vector(zero to fifteen);
signal V8 : boolean_cons_vector;
signal V9 : severity_level_cons_vector ;
signal V10 : integer_cons_vector;
signal V11 : real_cons_vector;
signal V12 : time_cons_vector ;
signal V13 : natural_cons_vector ;
signal V14 : positive_cons_vector ;
signal V15 : boolean_cons_vectorofvector ;
signal V16 : severity_level_cons_vectorofvector;
signal V17 : integer_cons_vectorofvector;
signal V18 : real_cons_vectorofvector;
signal V19 : time_cons_vectorofvector;
signal V20 : natural_cons_vectorofvector;
signal V21 : positive_cons_vectorofvector;
signal V22 : record_std_package;
signal V23 : record_cons_array ;
signal V24 : record_cons_arrayofarray ;
signal V25 : boolean_vector_st ;
signal V26 : severity_level_vector_st ;
signal V27 : integer_vector_st ;
signal V28 : real_vector_st ;
signal V29 : time_vector_st ;
signal V30 : natural_vector_st ;
signal V31 : positive_vector_st ;
signal V32 : record_array_st ;
signal V33 : record_array_st ;
signal V34 : record_array_new ;
signal V35 : record_of_records ;
signal V36 : byte ;
signal V37 : word ;
signal V41 : boolean_vector_range ;
signal V42 : severity_level_vector_range ;
signal V43 : integer_vector_range ;
signal V44 : real_vector_range ;
signal V45 : time_vector_range ;
signal V46 : natural_vector_range ;
signal V47 : positive_vector_range ;
signal V48 : array_rec_std(zero to seven) ;
signal V49 : array_rec_cons(zero to seven) ;
signal V50 : array_rec_rec(zero to seven) ;
signal V51 : record_of_arr_of_record ;
BEGIN
V1 <= (zero to fifteen => C1);
V2 <= (zero to fifteen => C4);
V3 <= (zero to fifteen => C5);
V4 <= (zero to fifteen => C6);
V5 <= (zero to fifteen => C7);
V6 <= (zero to fifteen => C8);
V7 <= (zero to fifteen => C9);
V8 <= C19;
V9 <= C20;
V10 <= C21;
V11 <= C22;
V12 <= C23;
V13 <= C24;
V14 <= C25;
V15 <= C26;
V16 <= C27;
V17 <= C28;
V18 <= C29;
V19 <= C30;
V20 <= C31;
V21 <= C32;
V22 <= C50;
V23 <= C51;
V24 <= C53;
V25 <= C70;
V26 <= C71;
V27 <= C72;
V28 <= C73;
V29 <= C74;
V30 <= C75;
V31 <= C76;
V32 <= C54a;
V33 <= C54a;
V34 <= C54b;
V35 <= C55;
V36 <= C60;
V37 <= C61;
V41 <= C78;
V42 <= C79;
V43 <= C80;
V44 <= C81;
V45 <= C82;
V46 <= C83;
V47 <= C84;
V48 <= C85;
V49 <= C86;
V50 <= C88;
V51 <= C102;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00749"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00749arch;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_dma.vhd
-- |- axi_dma_pkg.vhd
-- |- axi_dma_rst_module.vhd
-- |- axi_dma_reg_module.vhd
-- | |- axi_dma_lite_if.vhd
-- | |- axi_dma_register.vhd (mm2s)
-- | |- axi_dma_register.vhd (s2mm)
-- |- axi_dma_mm2s_mngr.vhd
-- | |- axi_dma_mm2s_sg_if.vhd
-- | |- axi_dma_mm2s_sm.vhd
-- | |- axi_dma_mm2s_cmdsts_if.vhd
-- | |- axi_dma_mm2s_cntrl_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- | |- axi_dma_strm_rst.vhd
-- |- axi_dma_s2mm_mngr.vhd
-- | |- axi_dma_s2mm_sg_if.vhd
-- | |- axi_dma_s2mm_sm.vhd
-- | |- axi_dma_s2mm_cmdsts_if.vhd
-- | |- axi_dma_s2mm_sts_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- |- axi_datamover_v3_00_a.axi_data_mover.vhd (FULL)
-- |- axi_dma_strm_rst.vhd
-- |- axi_dma_skid_buf.vhd
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
max_value := "11100";
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_SignExtender IS
END tb_SignExtender;
ARCHITECTURE behavior OF tb_SignExtender IS
--Inputs
SIGNAL tb_se_in : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_se_out : std_logic_vector(31 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (U1_Test)
U1_Test : ENTITY work.SignExtender(Behavioral)
PORT MAP(
se_in => tb_se_in,
se_out => tb_se_out
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
tb_se_in <= x"7FFF"; -- 7 is 0100
WAIT FOR 100ns;
tb_se_in <= x"8000"; -- 8 is 1000
WAIT FOR 100 ns;
tb_se_in <= x"FFFF";
WAIT FOR 100 ns;
-- allow to zoom to full view
-- always at the end otherwise program will break
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; |
-- -------------------------------------------------------------
--
-- Entity Declaration for dac
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: dac-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: dac-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity dac
--
entity dac is
-- Generics:
-- No Generated Generics for Entity dac
-- Generated Port Declaration:
-- No Generated Port for Entity dac
end dac;
--
-- End of Generated Entity dac
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity sumador32bitsdisp30 is
Port ( Oper1 : in STD_LOGIC_VECTOR (29 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0));
end sumador32bitsdisp30;
architecture Behavioral of sumador32bitsdisp30 is
begin
Result<=Oper1+Oper2;
end Behavioral;
|
CONFIGURATION mini_ALU_struct_config OF mini_ALU IS
FOR struct
END FOR;
END mini_ALU_struct_config; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lmc is
port(
clk: in std_logic;
rst: in std_logic;
input: in signed(11 downto 0);
output: out signed(11 downto 0) := x"000";
input_warn: out std_logic;
output_warn: out std_logic;
halt_warn: out std_logic
);
end entity;
architecture lmc of lmc is
subtype word_t is std_logic_vector(11 downto 0);
subtype instruction_t is std_logic_vector(3 downto 0);
type memory_t is array(255 downto 0) of word_t;
constant HLT: instruction_t := x"0"; -- halt (coffee break)
constant ADD: instruction_t := x"1"; -- add
constant SUB: instruction_t := x"2";
constant STA: instruction_t := x"3";
constant NOP: instruction_t := x"4";
constant LDA: instruction_t := x"5";
constant BRA: instruction_t := x"6";
constant BRZ: instruction_t := x"7";
constant BRP: instruction_t := x"8";
constant IO: instruction_t := x"9"; -- 901 in, 902 out
signal memory: memory_t := (
0 => x"901",
1 => x"1FF",
2 => x"902",
3 => x"901",
4 => x"2FF",
5 => x"902",
6 => x"901",
7 => x"3F0",
8 => x"901",
9 => x"400",
10 => x"5F0",
11 => x"902",
12 => x"901",
13 => x"70C",
14 => x"5FE",
15 => x"902",
16 => x"901",
17 => x"810",
18 => x"5FD",
19 => x"902",
20 => x"600",
-- data
253 => x"00A", -- fd
254 => x"00B", -- fe
255 => x"005", -- ff
others => x"000"
);
signal ordinal_counter: unsigned(7 downto 0) := x"00";
signal accumulator: signed(11 downto 0) := x"000";
signal instruction_register: word_t := memory(to_integer(ordinal_counter));
signal instruction: instruction_t := instruction_register(11 downto 8);
signal address: unsigned(7 downto 0) := unsigned(instruction_register(7 downto 0));
begin
instruction_register <= memory(to_integer(ordinal_counter));
instruction <= instruction_register(11 downto 8);
address <= unsigned(instruction_register(7 downto 0));
-- output combinatory
input_warn <= '1' when instruction = IO and address = x"01" else '0';
output_warn <= '1' when instruction = IO and address = x"02" else '0';
halt_warn <= '1' when instruction = HLT else '0';
output <= accumulator when instruction = IO and address = x"02" else x"000";
process (clk, rst) is
begin
if rst = '0' then -- le reset est inversé avec KEY1
ordinal_counter <= x"00";
accumulator <= x"000";
elsif falling_edge(clk) then -- l'horloge est inversé avec KEY0
case instruction is
when HLT => -- terminate the program (counter will not increase)
report "Program halted." severity NOTE;
when ADD =>
accumulator <= accumulator + signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when SUB =>
accumulator <= accumulator - signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when LDA =>
accumulator <= signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when NOP =>
ordinal_counter <= ordinal_counter + 1;
when STA =>
memory(to_integer(address)) <= std_logic_vector(accumulator);
ordinal_counter <= ordinal_counter + 1;
when BRA =>
ordinal_counter <= address;
when BRZ =>
if accumulator = 0 then
ordinal_counter <= address;
else
ordinal_counter <= ordinal_counter + 1;
end if;
when BRP =>
if accumulator >= 0 then
ordinal_counter <= address;
else
ordinal_counter <= ordinal_counter + 1;
end if;
when IO =>
case address is
when x"01" => -- 901
accumulator <= input;
when x"02" => -- 902
null; -- gérée dans la combinatoire de l'output
when others =>
assert FALSE report "Illegal i/o instruction." severity ERROR;
end case;
ordinal_counter <= ordinal_counter + 1;
when others =>
assert FALSE report "Illegal instruction." severity ERROR;
end case;
end if;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 );
port ( terminal input : electrical;
signal f_out : out real := 0.0 );
end entity MeasFreq;
----------------------------------------------------------------
architecture ThresDetect of MeasFreq is
quantity vin across input;
begin
detect : process ( vin'above(thres) ) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 );
port ( terminal input : electrical;
signal f_out : out real := 0.0 );
end entity MeasFreq;
----------------------------------------------------------------
architecture ThresDetect of MeasFreq is
quantity vin across input;
begin
detect : process ( vin'above(thres) ) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 );
port ( terminal input : electrical;
signal f_out : out real := 0.0 );
end entity MeasFreq;
----------------------------------------------------------------
architecture ThresDetect of MeasFreq is
quantity vin across input;
begin
detect : process ( vin'above(thres) ) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
|
---- Program Counter ---------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY pc IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
PC_inc: IN STD_LOGIC; -- sinal que indica que o PC deve ser incrementado
PC_load: IN STD_LOGIC; -- sinal que indica que PC deve ser substituido pelo valor em PC_bus
PC_valid: IN STD_LOGIC; -- sinal que indica que o valor de PC deve ser colocado em PC_bus (ou Z se 0)
PC_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
PC_7seg: OUT STD_LOGIC_VECTOR(0 TO 15)); -- barramento de entrada/saida
END ENTITY pc;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF pc IS
SIGNAL counter: INTEGER RANGE 0 to 2**n -1; -- contador em si
SIGNAL counter_vector: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
COMPONENT bcd_to_7seg IS
PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
en: IN STD_LOGIC;
output: OUT STD_LOGIC_VECTOR (0 TO 7));
END COMPONENT;
BEGIN
-- Se o PC_valid = '1', manda o valor do PC pro barramento. Caso contrario, manda Z.
PC_bus <= counter_vector
WHEN PC_valid = '1'
ELSE (OTHERS => 'Z');
counter_vector <= STD_LOGIC_VECTOR(to_unsigned(counter, PC_bus'length));
-- Gera a visualizacao 7seg
counter7seg_0: bcd_to_7seg PORT MAP(counter_vector(3 DOWNTO 0), seg_en, PC_7seg(0 TO 7));
counter7seg_1: bcd_to_7seg PORT MAP(counter_vector(7 DOWNTO 4), seg_en, PC_7seg(8 TO 15));
PROCESS (clk, nrst) IS
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, volta o contador pra 0
IF nrst = '0' THEN
counter <= 0;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
-- A maior prioridade eh do incremento. Se esta em 1, incrementa o PC
IF PC_inc = '1' THEN
counter <= counter + 1;
-- Caso contrario, verifica se eh pra carregar o valor do bus.
ELSIF PC_load = '1' THEN
-- O PC_load deve carregar apenas o endereco, desconsiderando o OPCODE
counter <= TO_INTEGER(UNSIGNED(PC_bus(n-oplen-1 DOWNTO 0))); -- Cast de STD_LOGIC_VECTOR pra INTEGER
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ |
-- $Id: rblib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rblib
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
-- rbus V3 interface: use aval,re,we
-- ... rrilib history removed ...
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package rblib is
type rb_mreq_type is record -- rbus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
init : slbit; -- init
addr : slv8; -- address
din : slv16; -- data (input to slave)
end record rb_mreq_type;
constant rb_mreq_init : rb_mreq_type :=
('0','0','0','0', -- aval, re, we, init
(others=>'0'), -- addr
(others=>'0')); -- din
type rb_sres_type is record -- rbus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
err : slbit; -- error
dout : slv16; -- data (output from slave)
end record rb_sres_type;
constant rb_sres_init : rb_sres_type :=
('0','0','0', -- ack, busy, err
(others=>'0')); -- dout
component rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv8; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus request
SEL : out slbit -- select state bit
);
end component;
component rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rbus_aif is -- rbus, abstract interface
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
);
end component;
-- simbus sb_cntl field usage for rbus
constant sbcntl_sbf_rbmon : integer := 14;
component rb_mon is -- rbus monitor
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
end package rblib;
|
library ieee;
use ieee.std_logic_1164.all;
-- This file corresponds to 4-bit carry ripple adder
entity carry_ripple_adder is
port (
a : in std_logic_vector (3 downto 0); -- First operand
b : in std_logic_vector (3 downto 0); -- Second operand
ci : in std_logic; -- Carry in
s : out std_logic_vector (3 downto 0); -- Result
co : out std_logic -- Carry out
);
end;
architecture behavioral of carry_ripple_adder is
signal c : std_logic_vector(2 downto 0);
component full_adder
port ( ci, a, b : in std_logic; s, co : out std_logic);
end component;
begin
stage0: full_adder port map ( ci, a(0), b(0), s(0), c(0));
stage1: full_adder port map (c(0), a(1), b(1), s(1), c(1));
stage2: full_adder port map (c(1), a(2), b(2), s(2), c(2));
stage3: full_adder port map (c(2), a(3), b(3), s(3), co );
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_engine is
generic (
-- Width of parallel data
width : natural := 8;
-- Delay after NSEL is pulled low, in ticks of clk_i
delay : natural := 2
);
port (
-- Clocking
clk_i : in std_logic;
rst_i : in std_logic;
-- Data
dat_i : in std_logic_vector((width - 1) downto 0);
dat_o : out std_logic_vector((width - 1) downto 0);
-- Control Signals
cpol_i : in std_logic; -- SPI Clock Polarity
cpha_i : in std_logic; -- SPI Clock Phase
div_i : in natural range 2 to width; -- SPI Clock Divider, relative to clk_i
cnt_i : in integer range 1 to (width - 1); -- Number of Bits to Shift
start_i : in std_logic;
done_o : out std_logic;
-- Shift Signals
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic
);
end shift_engine;
architecture Behavioral of shift_engine is
type shift_state_t is (
idle, enable, shift, hold, disable
);
signal state : shift_state_t;
signal miso : std_logic;
signal mosi : std_logic;
signal reg_rx : std_logic_vector((width - 1) downto 0);
signal reg_tx : std_logic_vector((width - 1) downto 0);
signal tx_load : std_logic;
signal shl : std_logic;
signal delay_cnt : integer range 0 to (delay - 1);
signal shift_cnt : integer range 0 to ((2 * width) - 1);
signal spi_delay : integer range 0 to ((2 ** width) - 1);
signal spi_cnt : integer range 0 to ((delay / 2) - 1);
signal spi_cnt_ld : std_logic;
signal spi_clk : std_logic;
signal spi_edge : std_logic;
signal spi_nedge : std_logic;
signal spi_clk_en : std_logic;
begin
spi_delay <= div_i / 2;
rx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
miso <= miso_i;
if (shl = '1') then
reg_rx <= reg_rx((reg_rx'high - 1) downto 0) & miso;
end if;
end if;
end process rx_sr;
dat_o <= reg_rx;
tx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (tx_load = '1') then
reg_tx <= dat_i;
end if;
if (shl = '1') then
reg_tx <= reg_tx((reg_rx'high - 1) downto 0) & '-';
end if;
mosi <= reg_tx(reg_tx'high);
end if;
end process tx_sr;
mosi_o <= mosi;
counter : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (spi_cnt_ld = '1') then
spi_cnt <= spi_delay;
elsif (spi_clk_en = '1') then
spi_cnt <= spi_cnt - 1;
end if;
end if;
end process;
clkgen : process (clk_i)
begin
if (rising_edge(clk_i)) then
spi_edge <= '0';
spi_nedge <= '0';
shl <= '0';
spi_cnt_ld <= '0';
if (spi_clk_en = '1') then
if (spi_cnt = 0) then
spi_cnt_ld <= '1';
if (spi_clk = cpol_i) then
spi_edge <= '1';
if (cpha_i = '1') then
shl <= '1';
end if;
else
spi_nedge <= '1';
if (cpha_i = '0') then
shl <= '1';
end if;
end if;
spi_clk <= not spi_clk;
end if;
else
spi_clk <= cpol_i;
end if;
end if;
end process;
sclk_o <= spi_clk;
fsm : process
begin
wait until rising_edge(clk_i);
case state is
when idle =>
if (start_i = '1') then
done_o <= '0';
tx_load <= '1';
delay_cnt <= delay - 1;
state <= enable;
else
spi_clk_en <= '0';
done_o <= '1';
end if;
when enable =>
tx_load <= '0';
if (delay_cnt = 0) then
shift_cnt <= cnt_i;
spi_clk_en <= '1';
state <= shift;
else
delay_cnt <= delay_cnt - 1;
end if;
when shift =>
if (spi_edge = '1') then
if (shift_cnt = 0) then
state <= hold;
else
shift_cnt <= shift_cnt - 1;
end if;
end if;
when hold =>
if (spi_nedge = '1') then
spi_clk_en <= '0';
delay_cnt <= delay - 1;
state <= disable;
end if;
when disable =>
if (delay_cnt = 0) then
state <= idle;
else
delay_cnt <= delay_cnt - 1;
end if;
end case;
if (rst_i = '1') then
done_o <= '0';
spi_clk_en <= '0';
state <= idle;
end if;
end process fsm;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_engine is
generic (
-- Width of parallel data
width : natural := 8;
-- Delay after NSEL is pulled low, in ticks of clk_i
delay : natural := 2
);
port (
-- Clocking
clk_i : in std_logic;
rst_i : in std_logic;
-- Data
dat_i : in std_logic_vector((width - 1) downto 0);
dat_o : out std_logic_vector((width - 1) downto 0);
-- Control Signals
cpol_i : in std_logic; -- SPI Clock Polarity
cpha_i : in std_logic; -- SPI Clock Phase
div_i : in natural range 2 to width; -- SPI Clock Divider, relative to clk_i
cnt_i : in integer range 1 to (width - 1); -- Number of Bits to Shift
start_i : in std_logic;
done_o : out std_logic;
-- Shift Signals
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic
);
end shift_engine;
architecture Behavioral of shift_engine is
type shift_state_t is (
idle, enable, shift, hold, disable
);
signal state : shift_state_t;
signal miso : std_logic;
signal mosi : std_logic;
signal reg_rx : std_logic_vector((width - 1) downto 0);
signal reg_tx : std_logic_vector((width - 1) downto 0);
signal tx_load : std_logic;
signal shl : std_logic;
signal delay_cnt : integer range 0 to (delay - 1);
signal shift_cnt : integer range 0 to ((2 * width) - 1);
signal spi_delay : integer range 0 to ((2 ** width) - 1);
signal spi_cnt : integer range 0 to ((delay / 2) - 1);
signal spi_cnt_ld : std_logic;
signal spi_clk : std_logic;
signal spi_edge : std_logic;
signal spi_nedge : std_logic;
signal spi_clk_en : std_logic;
begin
spi_delay <= div_i / 2;
rx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
miso <= miso_i;
if (shl = '1') then
reg_rx <= reg_rx((reg_rx'high - 1) downto 0) & miso;
end if;
end if;
end process rx_sr;
dat_o <= reg_rx;
tx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (tx_load = '1') then
reg_tx <= dat_i;
end if;
if (shl = '1') then
reg_tx <= reg_tx((reg_rx'high - 1) downto 0) & '-';
end if;
mosi <= reg_tx(reg_tx'high);
end if;
end process tx_sr;
mosi_o <= mosi;
counter : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (spi_cnt_ld = '1') then
spi_cnt <= spi_delay;
elsif (spi_clk_en = '1') then
spi_cnt <= spi_cnt - 1;
end if;
end if;
end process;
clkgen : process (clk_i)
begin
if (rising_edge(clk_i)) then
spi_edge <= '0';
spi_nedge <= '0';
shl <= '0';
spi_cnt_ld <= '0';
if (spi_clk_en = '1') then
if (spi_cnt = 0) then
spi_cnt_ld <= '1';
if (spi_clk = cpol_i) then
spi_edge <= '1';
if (cpha_i = '1') then
shl <= '1';
end if;
else
spi_nedge <= '1';
if (cpha_i = '0') then
shl <= '1';
end if;
end if;
spi_clk <= not spi_clk;
end if;
else
spi_clk <= cpol_i;
end if;
end if;
end process;
sclk_o <= spi_clk;
fsm : process
begin
wait until rising_edge(clk_i);
case state is
when idle =>
if (start_i = '1') then
done_o <= '0';
tx_load <= '1';
delay_cnt <= delay - 1;
state <= enable;
else
spi_clk_en <= '0';
done_o <= '1';
end if;
when enable =>
tx_load <= '0';
if (delay_cnt = 0) then
shift_cnt <= cnt_i;
spi_clk_en <= '1';
state <= shift;
else
delay_cnt <= delay_cnt - 1;
end if;
when shift =>
if (spi_edge = '1') then
if (shift_cnt = 0) then
state <= hold;
else
shift_cnt <= shift_cnt - 1;
end if;
end if;
when hold =>
if (spi_nedge = '1') then
spi_clk_en <= '0';
delay_cnt <= delay - 1;
state <= disable;
end if;
when disable =>
if (delay_cnt = 0) then
state <= idle;
else
delay_cnt <= delay_cnt - 1;
end if;
end case;
if (rst_i = '1') then
done_o <= '0';
spi_clk_en <= '0';
state <= idle;
end if;
end process fsm;
end Behavioral;
|
-- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: uart_dcfifo_in.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY uart_dcfifo_in IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END uart_dcfifo_in;
ARCHITECTURE SYN OF uart_dcfifo_in IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
rdempty <= sub_wire0;
wrfull <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=7,",
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 5,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
----------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks (cparks13@live.com)
--
-- Create Date: 13:45:12 04/25/2016
-- Module Name: StallModuleControl - Behavioral
-- Target Devices: SPARTAN 3E XC3S500E-4FG320
-- Description:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity StallModuleControl is
Port ( CLK : in STD_LOGIC;
GUESS : in STD_LOGIC;
ACTUAL : in STD_LOGIC;
STALL : out STD_LOGIC);
end StallModuleControl;
architecture Behavioral of StallModuleControl is
signal NUM_STALL_CYCLES : unsigned(2 downto 0) := "000"; -- Maximum of 4
begin
process(CLK)
begin
IF(RISING_EDGE(CLK)) THEN
IF(NUM_STALL_CYCLES > 0) THEN
STALL <= '1';
NUM_STALL_CYCLES <= NUM_STALL_CYCLES - 1;
ELSE
STALL <= '0';
END IF;
IF((ACTUAL AND GUESS) = '1') then -- ACTUAL = '1', GUESS = '1'
NUM_STALL_CYCLES <= "001"; -- Stall for 1 CLK cycle
ELSIF((ACTUAL OR GUESS) = '1') then -- ACTUAL = '1', GUESS = '0' OR ACTUAL = '0', GUESS = '1'
NUM_STALL_CYCLES <= "100"; -- Stall for 4 CLK cycles
END IF;
END IF;
end process;
end Behavioral; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2
OL7PFCCTiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph
KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII
YTwtWH6VQAWKrWw0gQI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt
QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm
9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU
m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+
Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa
SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt
+JQKH1y1F/+RNrZ1eYU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BFKuZqEfqjecGcxpRGmpCDvmWO5m86XHlx1Avi4sYpYvtXIvQdg65YGdV1jpIV3rjwKZHTLGWY/h
WohbbV2nhc+5Ruu6dAeqtH04PeCXz8zphv8vhckLjpwnJT0GWHiaXAcncvq/6wuXR25ASAvhi3Ai
lvDf+vNs8eunn+yE9uSpqndZXDEQrdOREqbbPaHrHScG2A0wHmKCr+QTb2IHKcEfLgWtjt/VCXIv
5krerkdmS143EXlDVZB7mfDSlR6bwswWViVYnH2kDpeepoBCAgyzi+PoFfcxhkn8DGVtdsW89QDd
rLaMLCCjYMVnBfrYxBWw0Bz0mfZcivLyxd+wbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
YipYQho3Y0zdOvNcJ1BUuYyd5pc0Rh/syRh+gLy6hm+lyA54M5wSQ2hPfD8TI9EKi9VNSHv+4JyP
tJjp0+P50R7zZOuQqstMvoegiySWsl+FuL5rMO0HmeaDdAlO869bnln4ebhY3LgErTtdz79H2Tjw
8Y+r0jP4ZeQfbBolBNj8K4avqBB6MJpeTgp6c53IZBHu70hP7EAzr9EL6SvxFTIoOzX3u0JAgtBu
7nxR7lavgwwo3EcpUzAj4mH3uoHpnLbLpREI8QpNoCrST0nHzoIeGv2oTeFFzS8gG853y1QLdrix
lf0j1pCZ2imma66UmxY7Hsi62ZtasofXZqumk0nhKeHtRugZScgbhWfKqk7Aqvrn7+7yba+mDY0h
8x5R9rAUnJh4He0UpHMPCDdTqv6QMDGzsQ0I1WBNhXVpVftUtptlNJSQHF/AsQI0dufguRoPw3mj
Ai/mkVlLS1T2OTFbyw6Lc+8h92jbacosHKGsC7wC4vnxmuNnBOaYTs8yO5IzxgPz28lcYBiBMADm
DJGqcrrXGhbt4opJQoo1JXSCYL/PMfPWqxcQt2XqxBvLiHTo/pi/lql9bhYQ6xuatBmkVWlrTdlR
BYGZCatUQc+uQqfJx+kRUTLB2dR+472N+ZrKxRYX4tGZyTU7jKXgk4FWyGsnlmNpF6ew+1Z3ko1R
ZuGl4+dPZrBoyABi1NUya1QT1uz7uDyCS8ijzKv185MPXjXOqrmTt/1sDmHPSpVI4G0YZugEPkGX
s+ku/uOBEAurExJOuWFW/J0AmR3gbnx48RTJt/K0p0wk/XcF2vUzhSbut/a6RcQ9Ex6nVTYcBGrE
FJ7op4v2ZUnKXv+D+Cx7HkjHcvpzO7VHPn93zFaBzdErm+2EFrG7KaFjLo8rC6EJEzFH+iudzjJF
pRk3WKOjYFPxXbkk3YT1OJIZWUKXGS7SVIKtjK8eY2e3Gc+uHCEs7x7yOGjAqXppk8sF9oYywMZA
D7VrQifsv6DQpnHT2cXEi9YMlo1XXtHOZXRwqvioW4M8F9lTWAwDjeetv8HV5XJX58XpN/Ls8u4d
dOxyce8aAAncZCceLCCfpTnGaEah2RllP/H+43vNi4OO7lVy/QFsCOPwcCpcAUdG8hc2C9m01XDu
1Kr0Qi2FqO1/mLavIYuk6nPCj7VfUqmg7K+cPcflRvL8JJqFUt4l46MShBHjbSt49d/RsmtJxHsQ
MPmBDpRRKwbnsu1YyGzu/Gxck24RFWcGYm0D3K/t495YQLrcPwOpzuAT3A3POKhw5q4fh4ov1XLT
04GQHHB8ZPrXHD2xbreo5FYp54V0QUzAgxnp6JPPNphxaiXlZwfc1tER/znJ6m7jMDyJBKHxieAA
i39OjmIQ1IxTysJjch7DoPUn2fghM8pfMcVc64u7eC6umqCkn83tk782L0wI1S+/55N0P1wBsaxl
yR1Sa8mbi4RM2zku/6iqSiZVCj96uER6Rv5JqE9xKevXGACOkV1ShHKJLFjHmuge/gNj3Ur8aGn/
4Kr30cfo2cnYTEPOJMCgBVqAVKzPRs/hPD7H+MrHDPw2n94bU9k2y4hmX0yP06HPZ6U4tAd45BCu
plrTbh5lWrxMxoPbSgclb9IVTath03jcwzlquPed3H0naZ5HaywBrl7uA5eZj0V7yiVGtR7gQY9O
WXNQR9+jZIo0nMzNXmKoPHFH8OA064xAanN5i+smasVuRINJziSU5c9y4QeAsFVivqD0yF6aZxOI
Y3pmTxfvCAznzK3lD8Xx0aDzYOLrk/1c075I2til4x4Vxfrcw17/5d74ifSRmlpOystpgl6HB31z
dNNSIUkInsYnhOFT0HL/74/T0okFIkO6RTz7W9eVIixTnn1hvCAd4GAU4xx9zKOYT5YDvIC+XPhD
4iLLiKmqwsm+ga+QqLOl0PdSKzz8NntBuB/64g0K6FgwAUm4v4b1IJSuIUwDluB7pfQnfwzod+f+
cywMMbKWIommxQEQg0wHHC4ZJGmXIHmaq5F0VG2XCiI/iok4H33QPQbsOIF9r4107RC/8AmjwSek
FstqPwcnlboDbXPBSGzq4oP0oiUdQesaWyT3GT91q8PBhnSr5NDbGmh7SM3/8MC9hDm7sN0oL/+5
JoytF91n/bs2NpEae7TT5qNkLi6P/XPzZ9tK9aNKXPhMjifEVQupsdgB5X/44rbwd1RZeKnLSeZ/
RY17yREpwDwFX+Cc+V9Mqlf5dZJ52dUSAtT6enchAR9Z6ylkfJt6lCgaB3synvNTaGsQxlVaYm5e
wpHYKWtBMOtL3jgirmgvEP8GleBIvcbMXuZaPaC7lOPBAuCfhscA3cwVKMJSwICP7CGyhZxgGFR6
dg12sBIq2xSs2ksndqV+Buemym4/2jACGk8vo08bbftvkDp4+S8FokbzNHtLdsEGCKDziwZzCjS0
BM1tcWXsXu6LSjRiX33jrriSGFq85OwL/2raCfw2Qzrpbcd08L8nnxt/JeeAZseHaSLPVSPjptH5
YCmuLNPhh3EQWEFN/Fir1IhpQILh3Y0lOTdpZIUQbv8oSaOiNY0j/SHJ45aA7l1Ws3Oog2gZwuoE
JKlOP62NQfFjBHQaeahI3X8iCognBz0bIqrpXkbzJzNF9J/a2WHVTa7QxBkkD8tVMK3wZxKFP1Lu
+F0nH931uEhLPRDhueE6Ii9tSfDz1VNLD7K2YqHKZwIzUfOdkg37QGIKIsrr/ICiv2iA3QcESnFV
P9DGTUhtWjNywJr9Z8elIAWAMBhV5Lp6PG9ludqO1FqWRD2VEfQT5nscDgCYsxWEGn0OoN2B1p5X
UWadDtZccblFFjrLSYhnIK5sErjILBrRfvW5b/aZw7JhPAZYzBgDRinclFi9sqo/eIV95BajtAU8
LsHxp2Rp5hGBZSgS1FyZcMllJ5NLKOeCkASK8NBTpXJW3vEjS4TGlaEcD7McM63khOIGUBbvcjFS
QdWG+gJNVRJDwh9To4T1SExO+K9jtz6KGJexE4TMGlQghxzOTqxyReVYq9DYrn3dA9rAt4i8Q/VO
wDqJ+AuU8QVQTUOm/p6zAAuRT5zErhxXC74NvBFEh29VKuaYCjp4at0r849HsHoZVGBc0CEzL5Ve
WROLmJ2i/9cdveg7YbZIehSGG65w0ffu9clBVsGTEPp4bNDN8HfvkPpxN5rl9Z2rHaA8TA6fVgk7
mZEzLfjw+IbmM9X2/qWk5wqjH4TTSzt8vG80CAKZmZlL4dDvGPEZNFELLqSxoLa/e+xFeA8SJxg/
vyc/Kq+fDm9Ehz83SaOFpm52Z++plU+hkMmhDESEVru+QGQHq06ILXgvikFjkBNgic9saD3Kn/Ib
ttFH6MVhzhlGBD1QG2TLcPdmPF0KvKP4oeH71nR1W+DiFhZye69ZbQtUeBYDD4YYb5bUYpgMGHd/
qptHs2z8cFRFHhvmt4znDt1ucSJ3BQnqV9S/ZyQSlIe1Uen4tIheZosSf1Wu8VzutkNsDv0Kwuhk
JdWIL/l5OGqzNYzEaVWXOb+TfSSJa++WpXP8LeIfN5JfTIrG6CHBvB5+Y25JsnJUnbFrDTOI+Xy2
ycp/6GsKuYCbVQeAuhytmVv9PWcqWmDhPmni5/A562hFHpn8+Z07h0gPF6IiKFrskQhyn4CJqjjX
Kjtb1k/ukrlSSmXRpRho0MM/A3vZW64EbZVgcynzZ9e5glxmX5HfhvkZmjc+1TImw5GXeevqhfRq
z+vXJ3vn/oOHJT+ioSxnChy4k0TBqjkyf8Cj2UGYoZvAeDPii2zAqrOF9cYxoq2B43et5Kirdz/w
WiBUya5OMfRR1FjtQcWX+OqTDFPTfl9dnfuvU9ZS6m/Limv3i6QGVnoWAzwZF2iT2ohf6zpAAgSl
x0req4Yaq0ScpfO6Up8fqONgMJSbwW/599RDXn7rbTxyxtWG8nvz1QJoV+Pcz8iWRDm8l6VJ0/5E
1phrQNhEe7UZ/Y9QFCldGcQ3nGXlO8pKOx1yjCKkcLgkIO6ArdvqXHSffljEvp/qpJ5F6l/QAo97
gHYfFCEJUwA1A+C2yaByPjocORNAVndoY8rAqa8700AFgq+PnQ2Jg2uGJ8dGIXe0SipF79CyAEty
DLHDDflfIwv00PLJ9b/+ERP6n2CE94ngO5Mm23NviwiU6PSFnQuhwtl603M2UFSW37outksK1wfp
CvjJYTw1f+t5llqv6hB7YclYqyLZlXjWw2Ac+dHwpKLjpoLSIGOmb0vUMbnBjsWLKrQfau0dip5S
qoOqIcn6CEZvFjQwBnwJD61GHe5wg4D+2y23pI82MesNw/9AITDd4kwt+ecU2ozSHduweu3C4i7s
RhiuAmgUtgcH/KRr9YKU8nAWrnj3+4sLkV9qLJPOx89vE29z5R7JTZ9zm3ECQkHOgd71CgUGGF3Q
FHvBbuT27PqeA+sRqReT9ZZ6Um7DBbZ8sLxqZ8G31ULNtYQMjsHI/ROh7eoaB2L0I5ao5BVVeN5/
Ag2vNSz/N+uW7iTst4KmC/32vGAP5T2aN56iP4URB0e+nmNc83C6oDfL3C6dt2v/Q4U+k4FMSPDx
SW422tlsmzQlayjN5AY8C0u2V7uWLcKoNGmDSyAAmiPnkcX/BS808aipnMq6lovQYruuqyRM4Wp8
5nBCkMYruEZnrV9SKVmxHyribcLm3EMIEiFqpHgFkXh9f2fPDeLxTD+x96XOD0DZbRIqxkksKmpq
aPaHG/CHcWyUqIrCAqJRDMTALdlM5VeU+MLuGfkNaI8uLU9wt1m2LWrZrYDiLp+eByEpKSKdY/nD
T9IVqmcXyrV5jQ62ebf2aWTDHdw/DAEu2JvwNDoc2K+j57FIN49lwZ4m5Oz35UYDIN++jdZ9EqSW
zJa/JNRbK4Zv6PESVe7u5jMOcrfyVBU7+OSLT2sRuBQkxgg/6wCdXnz0XA5xK7OQdRwmLTXz3sDk
+xhI1uybi8G2tI+StNsVH6BMwvBVfnCoOVO44ElB50VCS/jfTS/iNr8Jm7KK4oQNPF9Tcy0mTCXW
8IsnBWfOMNGPS2QO+YjnwN8DMLCeZ3wjdVBwL7e7elkDhBgbrjbqWckCd/BoLYMGeOvU7zpLqnPO
46fG4nmZBXZYh/l6h9oZxl2zX3qbxspRs9shbPd+ftS0oH0XoCCCLIzlwLRSU/Q3fcWgtSH3U1CS
CtYl1ee+W2Q/rXYlX9wc9A5Go9DjqVfuZNQgOZkRnbqWHsbA6diR4gOQVP5b0BlJWjuTCXu7Jw4F
6XZzykRuF6Rf8o7uDTQ4uqqZuRtO8zrDfRYAevZhaYlPu3PR1jFI71XIwigUeD5h88t5Zjbspx4y
A6Ow1E7S0/PBMVJ/r1a1OvdHvP5KTMktJ/bDcV9dWo+LwbOkXzsynSCq8kwf6zjtQHpDdqYoZwzE
9i5zGdlyKD4FXGNoDGv0dcxm89tK/1swQok8fi7LHF40o4YGq9xyY3YeqTM2bbkSJt444dEulrKM
x5ozW/OcIUrwrA6OgpBOUfxhIe6S2m1w42Ik72WJ6qrsbympIsDvE0jEpEUHMNBuiXITnK/OqnLl
ERUjK6+U5PaGdaqh0bjFmNZiX1cocH3X79LjecSIn13DbU5rqiAlZhJSloLwDVLZPIsvRvbZIXSn
ZXjYgbTrZLV8SVg4JvjGWlMAvK/YfmXW40JP3JHuBEyYbXu36jRRC7AhB1usF3HeCw0Rw+IqDs7u
jOSX9Y9pDJbcYiolRK+xDCRweRonRhLVEnZrFYN4coPY/1K3mnunq7V20R1W4vBshiZQKyKEDRqA
jnOvCxOQyRAnS9gBekEfsVCgeGBOzs3HT3sFNrj+UeTLWFhUS0bBxlyZ00LQvTcILczp+u7hpGHa
3VrdZ0orU4I+ZKCsnLFr3Vg4AH126akAOBGv+xll6za/PLn7mm3xyrBhVsnxI8KLtF+H1tO4n7A9
JgNzaR3D/CYOiaKUlMKRXH3uQTDnGImv4u4++9b/HTCKU1yWsrY9k7PjDZ49X0WSp/Hr+CDvMwOn
7SibYGnk6tQadL5QV5EiR5+jTRDH7Mc3peXhvN3vn2rBepuzIQ5NBagyDRuG+a+f3el9mDiuJpF5
uS9RBCBe0IXnOUsTEoI4e/s3j40/0qxjHtQ4kelRJfbQkmD/951U/5Q3SJfLkpP5hApV2FtPEB7e
rurY69DDdPL+rZn+AwP1dd/+XCLvNIlhgKB1eYuAuJx/VekvNsaJH0JK5zesa32NHadoSpbQWJAI
aHCLtpBIzYe2lIcGKTJcaw77E/+28wHS1RILm8HZDrcUdfIuAbm6Cs/v98xmOabJmaXH5aaSicJf
4smewmO08lGFa717H6U+DZg4hYskK5HJ/ynjnHbxjdb8NNwYrdrSxG5mgxhj+RjBhXq1vy2wM1iR
0mfM3+xU6demY4eEwLlJQoAx5L6ajpE7rePMD1wfaB+NmwQBBQnGMnHzXL16dtSR6QeYhik57DLP
c0A+DJU9JD0JahlI1yMbT+YHtIPM2f/zMsyhwS+p+PGndmkMlBHlovFTT7qhk3gMPgckHsZm7sxt
SgrntlAa1YBY/RuKOzxNFpSJkdra4ALTbbmuIYpQGrAYYWcUX9vQhbH9I64sjK1bT/24SXOslhSI
WnLlaQcS+/BlOAlG3+0eKiekfQP83benhoAXkvtt4u0ujfR/4mZyf70AMRrNJApmopnrnr+i6lQF
F9/RMDDheQRWhqSDNls52cY1sfogP+B3/issnBcKWVhhAT2aeRRz/spZm2DhTBWtNkynwLGmpGZH
bs3aAMOzYP1/vhUPPBL9osrq3jKOxAWegoiDySCY+NKocJPYiqW+/GtlUHeqxqe6wo2OTmsKn9eW
qYPzE1LbdjZ9JSXR4Y0K3OkrlLKo0NjoF4yHocYqxRAoLGB7UKj/cbfmVftPn4hrk0WrFaJWI50J
Lm39AC0eEhR2FQ2z/j2sz+xr2ng5Vv2IIpE+wwR3AQ7JJqOF2nUEjHl6f5a+agTPMiaAMMvYCWkr
kd6pYWZJW9wBUeo3nr8y4fo0H/BCL9d5VMdyAvLbsSmxxf6nZ8J7mfCptDr63UgalnhDk+CwUeR0
muyPAaO+YcRHYc+mKgORiX3QMIirUwXLaLxv3DM9bzMbGxUBQQVcpY3fRX5ydWW9q9rGG5+Um6zX
8mrX1WMohPEMRCHuXM9yHkwXqj1b7/LtyOX96mIBiVDer/A6GlTxaqhoOXQ+nGgHHnie+EoZ5Ecb
mIgO8XN7GfIglgM4E2MT36uux/niXiBordvYI17dlDfdxBvqlD9A0SXpVCLp4HFa4c4H1y1cwRpr
jdP0Rwgaxvf7CAW0HLKfDo9dPHhYrgMg9tVylo/VB8HbgulDdJVDgc3u1UMg1pKE+tBNXspfyFQd
jgexuVLrhR08HxG75rcCquMd34GQjHt3TY7JsAm0ag96njZywis5EjB8+dSjyundUSLYXN2mHq6E
/942tRLCef/2f+TPnhKec3mFk5ET8zbs1r8fxtXVx0ZPQxoePPeNjU9+eNNU/Z2ChW71W9bggZvk
KtS0J6zJm9EGTmFyrDMWpkiwNToxd2Kdt/+OoOSnA2S5yWqm+tIi674KCVl+BQ3ccnBZm7vhjZ29
HHLKB4fuJqxQrTZwRPr9pDg1+Zm7++Sg3t/RKctOedsNroYoA+BgCR+POYWZfP8q8xqeWKhINbYD
KAUmuguM1KWwEoQ49/5fbjKS0y+78/8k2kNoK1D2PPSNEQUcnlKgEwFVPcSl05OUwPK65xZ85ieT
WkhNbWeERbrbiIM8AYcVu+moIf4WmntGzSEcRRNeewFKwwYSit+ukAo9G3KYSb43G6e+EKsNZHE2
dJxUY+a7XHuuMeydeOc1XecjqgtL32HFxRjoqqwn3FZoad16084Tl38I4WS80R6o6wxeanprtMTh
2VC97EX72m0nIP7KPgFIYe1wC9vDZ+n/0oZ9fozNHEH+mvnzcVd/J4uuA4i2BSIl6F0uE4+NAtHN
yEV/ExKfz4kvQW24sM2GDpTNwOYdWr5kE+09vt/CRfn9XXT3Hxym712+m0nt3JGmg5iFtwlBXJy5
rWxx68la4QRb4vtOdBrmo9vp2+ehLFc1J5EyWUg5GP9TPE24cZfv210TcIubmf3ei6MOVLezdqCD
XoG90uIeX/uyAsvrryo2quIUIF0AbGr8Xil0yEFsZVJQAmealnY/WFrVUzt37dGG22ppBgJjZLAX
xCJMwOPQ1ZEI+oO+AJjmBatm6VaUfNXTrJb6l3oOtt+uMvxzuut1YMfCQ1CGPbw1zB48jzqFwubI
ijFwPjbFmOSfG6twuyNjKAAmb+F0J1BubspzyRtSXJPe9tQI/15rKL84g4EI049SVIX9a903S1e1
CyHZzk19CiNdU5yewP9ITvGSWlCRCSICqKIQxep78hPJluoTAOh79PDnafj+h+S5E7ch8Yi81S8k
mNyNPEWyix8FLZ5+0KL2xP6p7qIhNQEK7nvpsHhhWwakkJ4hWdkGDp601PR9yfiuI2ZootGmGAwV
pwivgNrjN6DuQghdNh2ME/zeWQ+VV4XCVrpa9JVsKPJlWviBCb6wONcO4z7AjCima0Kp0b333Iq8
OrWxqHTzrPl+14kKD4VG7nNyTb63zGyL2QOUijP9k4Gv8pHw7PkHNeS5KIf1oDjTK6vgMTJPatEs
GGvcxGJh8iAa+c3S5GMtAy2UJYfKL7m5XUUTv728ovLh/5L9twFx03VIJKYIRAWMKzqy9V11k5O/
waHMTwb/gIhwWHlfXh5G/QLhVwU8nkqlQUuPckPO6Garees7vzJKKV7KOZCwKtml/G9UYosKYnC0
EFYkoizaYVJ9yF1QYAjERDGuvTZ/aV/ZN7fOzbId6Xhap8HoxARa//2BvXzVIMsjTIbCO+HoU/gb
NoDU0LkAcnj3ONDODg239kZIWFig3kQ+XAH3YinwlkB4pshsYWxkwQinWbuw8qItT07ZtEIv1aKw
OKCeL+S+brh2iZcgi6BFgHhr8i6PZd75SWHiQZrad0GVMnNPPxWOPkrhqX8qRRwL4hUiawESCUNv
oEDOtS1118RupGmlrkX3gC2BdoSgKJfKKZlOjJ5jakU4gVeCgTBbvbdsXLpD28HDO9vc6BxdMFFK
gi4nmM595tTuGfFmhuiHPjqIwJJsyVGVotcBbbz9f0PgNMY2kDMYBBOhaP3/JXfIbnexYB1mEROe
FhqHViCTGEM2A2dss3PtLVhPj/YO0iuBf0Y8bvFoZYMLyZDr+ODLnOfegar6dfoy3I7WT7OIUDEs
spu+oVGb+hbgXHd45+GsNaD2zqI/BJeiNM6j2AnX27e+ckBHZDRpFCLOqThVNQzg97oF3n3AXM71
g5KjzjRUIhAHML+GuGwaZpbElbScV7CpgI6TFi60126MkPTE9nbfFvkA/eRMdIy7wE0SaHRnhV/b
nU+kt5hxJQY63WEYGNH6lRW4gdWRP7f76WmzbkZODc54T9uwhjNkzOAtPid3LIM+5hFkTkxZUwwD
bUWcHtB3N/y5i8QC1V7NBBMTQ640SamAdnlGODhLxAQ1DsfQ0abkpHKITVa6IgG6Ge/V3oCJ1KKt
epiCyt1WD7Lh1SQUVRFwW39iCy52Jp3CtJ6wWBp/R9+aepfl3zXkXaJ3MKmdHi34aCtAB+EPX+MO
/mTzg4yBDFrokwGrk7c4GRMDrPLWIWdZX9Hh+IOQnIB8aVP/5yl/NQSxpr+cO42/Uf6ybZY4hjer
f2j9JhvvTIGD+NjNf5q203zkrLEeWiNuu0ku8mmLE3cpo89M5UM/LncGwuJc3TLz7xynpkBX6Z9B
EUM7sOBbFKjwwNdp4vqeYcDxEzVUNXC593b3YzW50QuEpKkuy/cnMxSPHVSe04zq61NVTrvBYPYs
YYXHTU42zzpS2sfbYUYAQSIC56Y0KDj0zhkE1kMettVIQKfuuSOFNubwju2dIBDm9I3WItPibNGG
hDqiB33qmLLOpjMZzgcHQruZ6lja6Y04t+Un2YhmQiF0zInlCT+wcVSWADby1D5vfvLbEXdo0jYT
YxPrYZpNgATsqUh0vf2loxOBY73ZgM04Tz8WCQyj6kvWQ23JFatHb3mztE5WY/COIfjZzCM69Gt8
BiL1J5741DYKDGNmaOHlFxM701VHFKabHZbj3S2DgOBUwawxFTb4h8HwjcNOPzi861eRaGARB+l4
w82bxOgdroOpDrxi4h1obQl91d5YW4mig8Rc0Qoqg4ZJ8zjnWbiwrV1VX+gn+KezmbKSrFfr0m3z
JJSepO13ElK7SQybWbGkajnNfud7OL144mXlFtDnxFTb7iU6AUQBPMD3hgE2FrHmANw92+i7aiN7
sWb/N7uz+Oqah6RfzNfSitWcMuliNX0PQVW3wSYs45Dy0/osJOoFt9HvXFKfCe60UerkeREnWUZz
vCnLFQcnrL6wNJPqZFP7o5UE4vTBWwbhhRQV0W2BjnSTOZyFqE1gW6J4umb6MSeztJP/2YkbJ/11
2nUtuOLOSNlgYImZB+lKSaDEAlTHHmRly1MeXO/3DEGHmYL6lxs0Jek6tm+AmHjeaFGm632pmW3q
if1PNt1BM6AIom5lJjMk2MePyU5NKeSuQ9nbmTN/yzRZ17V4GSTt17MLIMU0UldUHNfdiwr5vsP/
Ye7Oc6uAwkeoMBZZ/9jbDOU93/vtLFii1n8mSkxW+iPRjih6ueoRra0NPv8Dm1U4nq8Nsq/iTkgm
zXuEdvHJMyX/2UUCNSSEh4sYksJKy7KhDb3F8fkC/p6gq4Qgo6oG8v/Gl3q4c1vW5B/Yn8ywyz1L
bLfItrsqSOm8sW23ndaYKcVALa9VGfjn1S0zY2/l7FViEwWeQBVAGgbNP/lsY1I7vTeEIleulNWu
6LFZ939XPgmq6ivVj8SCk55F3jNVCUv/tTklPSyrKWn7KRO4d7cXb907fWbLvbEFA0H7UON4TI5G
1h4aJU2+DYcOKPYQ2sgtYrz2FrD7h0uRnOKJirpozm9qwa3577/qYHN4e8QSNnrShGSK31jMp05J
unQ5s3won28pWtCsIOVPE5iyJN9fsP4zM/gjMa+WdOBKPBdbOVkssjop1e2doJZ8BBqAJgew2tkk
2vIxeS8P/oOLclWfwr9mReCehXqRRzlBitRyppevy/J0VPYGCGbFmaDJjJCqmvSFpp3OJpQr+lqy
bJZ2BizaoTRSOEKnEMvnSNQ9+YGdRuTKxj158ys8knAGmMhHaELddFlQvLXTiaCLiDNmIhPav16y
Hai+J0pLSMGEbgkmspYlZysRASoq1JVvg8vvYbbzIuQVALPRtYXjNVKlJ7zX+hLJXsvy0e8nsq3U
YAHLaYJlvQaaMzyOxtrfc+LWfvFlntwCVEa/Oz+O+zGWchh32d1RtTMrS+1/s3reMWfgqX3ejKsx
5swl+uyHn/3MkQWvk4W075gHIJ97DR9MJSK492eK3qegKUiCGDsEOGyWqGF3D/NefB0SSrRZ65UL
OrtRt8pB74+3bXbYPwi5mWs6GyYXp/nb0X2AJAsbKnq3VzeBFH49m66MWz+VMtA6e/GLp9lDLHVt
O4mTyjCQSOyD4JEbhRQwX1gP4zjmepvBa+ZNvW+GRWiY09pWYaXZuV4qBBm3YCyK/ghGc75BUA6A
3NppoRCVeB3aIS3scdBrmd9P35jrTf3rFS+p5hbGgiQqeim5hi2s5n7SI+cYMvi3uovO7sVFnBku
17FWI2VohmtAZ/WD0oRm0W++j5JdfS6kUEIQMPC1gkxb1WnN330avi+f1VLDdW7m0whI5PcuAYcj
GNaF3cZoOpoRWbg25dbmYEb7cIbTfoJhpFppZVmD30DoRchMbB9bXtqUqOarN1hjs32DUDyeNIqO
Mn7Nh+fOFd5o/EMFF5S+pny23o/DBtShehL1ceuE0CCLGrxEtg2imPr0qEHtJCgdOrmnPIsl8IEh
35ZtvY2Tph3WdWC8oTzJhkCWcb09fN5CKH5ZyahzoeUtFm+hhXp/+yciZGAUZwzydrPebx69bO5Q
AMbSCWH0u2Fai87FDU32ehgXOGd/gTt5s5kr1zawG1FEXnq4XYwnaOVSrpNurjd3Sonbf4VQLJ8D
uexXRrvcCkKTgAht3s8W7g9LFdGIkYAS84y4yGdvky6LdBlosuiSTmhV4MNgXtHHrjcGUKiaSvWC
2Wp10R41OUCdzKxjTrIrmWSuPmSCtxZAr9oddmNLv/FCDTObUyegJeuxS41tt104oua4kFTW/hL+
A01iFVnCKNIUNaYL9mNv49fa0l5j9F/p8nU3npFDUbdMNpMQSUkk2p7ZAosaDTsW+gu4JvUoPBFT
yRCR8vQeZyRj+STLodZFuDH5o/fLYV6g6WKOu7lsA51cdzEciZvd9Lb1bwJiWeKLoqh6JgMIJenK
rMGC8PDTlue2/2MNGUnAymVXQAORFsivMfkrF8iFMxvOpcw/KYQBFY3tei4jXUbeaRLwPscUDuH2
IwWd5mAV3wcID1cDTcAv1YSfea2FRbOu183DjKndB9kkVt6byGjMIVoo/X8ZZHc3Bh2Wm7UhTy1u
FUw5YFNoAZQmVhKo5ZZybpYayT4Em2CIOxQdDkb7I9p4gxuRUjZVRdXCHEsr+JU/qqj26cq+zozO
Ua0JsHkGSHXsM64SfuhxdaEwPEzURkrw4s7ZWnFvQ3b23wBb16nfXkrG8jP8iE7upQ+b6pxGlb+B
mNaVaFODkctr4rNLEs0FLfrNtxRaoth95rGzpM4hNwoX3/ZJEKBKLkIW0r5/Ijj+5b5IubGUPqjd
k1GGJm2+xpBVdR3bSsBKZ4DLAOKeMu2VKKmmP7ORZon4JI+L5Tn+GevJt+CKjSat2rus07SZbcc2
jqUGHgTAcO94Klc8uUCwMHHB6n2bj4UT/MaF3rhWNCExEp+qr3opgfpyM55I9ED7/i1GY0EYVPgJ
Ap9oVV3rwH+o2+yrOcWZfc6GMoq74aF8JslIULVM+2qf0DojoFJKW5SqLw5yoPTr0KUVuqABdGFx
Yspu1tIUcfFbJyrPA0RRzu1QLpuvI42psuWBJeFkA0GQHIVORFPWstxsTcalya8cdPdU3v+iltpl
v/SMP3H1Vl4YrgPZn3OhfmyZjF3v8N2HxNujIC/OsWOVeUfdSAPJH9x/U4MdpygcA5KmezYvKeRP
xB/giq5JBQg5H5Ujf76lM39+h2PeUb4iwtaS9UEeHBuM05PL9aPFhCKe4D1dHolZgEh6eSa7TRUA
4DoHLQ7olIsBirWz69ep5WkIVSONjIEPswmvovc2mn3NiYnkfU3Gkog5J6v5OvMWQNJFuGbXogGn
9HHiaLgh9hUbczpmozH/nKUbPVwDpw0NYtIb5ADETd/GSdx9QZ7O3P5OC5Pqirmsu4+sPKYqdod+
GbIZVOyC+HUl6WoGFA6itaX6brdi8kfvMs5uZLboDf5tM6b8qTq+zESQsrpKaEw7Nd7n5RQQpKDp
yE7Bg6RYXcygwmu6+4V5AaPLvwL7uODKb23D4tGXjFwpp9zaTz+89l+snEQbdFU3ohmw/yyz/EMu
5mRqE+mXyOQBSdAe9r0XlsCOgqc61AKfH9xk3WPhUaGBeG/OWg0AXtjsSdDXyNUw6TlMstvMfsjI
toVFU8MPbotZt3OeZDFvS6allPu3Nm2/VcCpo95lpf9loVBH+tWvzeiRTN2wASYI7/aUJb5DROli
gtEtTz2Lr674nCqQVV6GytTtsYXqtDoakYFEKbtRjtxUM0DpCaEYvaLOivvnqbFqfmW3eoHUuvjj
ci0+TV0fjtWJwYpq+gDoxj7YK1hYXQg5bfSLYbd8128+6gS5z5P4ZPCp9ht0dsXKZ8TA76qRuPhC
xrprLRJpaN5HCmUvvh9uriWmR5sKGDOmrBIk7EjjbxCbSlU6f3zBg93EhAMiOy+e7JrP8Ya9kB6i
GYtvafyFEuMAAZ68oYwxC5XTUm3G+yKqf3NMcasfdITk+wFDp0ZcwsekmyOn3b+V4kftznm/9YsV
oO1u0Pfxw83r2WWXY0HbBKUG8OWky0cpe8uEF42mfplugX+PkS8ecki8Cbj0fY+5OpAag9ztdK3H
9Iysutz6eNtUSSQ3TIMPPUf1EFpIfE4paPGwqmQPkC3G+b+cwGIFap6a+iNQQCE/I0zGvxnRZlx0
PcPafonOBy/7TnGHIZOoVGNO253BRJWIp1szJCpPLkSLRkKmx8VFHwG/5e7v7wWnVypYfxcTRPg8
Q828dUlzi7G+VmkvaE31YV+gqehUlf/15kYZVBwq7zxZL2BrwYKPw4wKrVunBD6p3ohL+jXgbxer
PjLE9iqADB7+eImMnxDtCluonDrjYniKpW1LxuIniZO3su2XoRY5pOvjX6C5QisH3aoR/8TJkdfM
fN3xgI3P8vLdAfwFYCQUnHfZTVyEqmL+kaRyUA3NrPMpGgpfqPtj7gYewn3Hv0ZhOyYz23/jcSFM
htS5iFfqIhyHVKw0UKl5KZM9IE4g3y3IVGjS0U9lKrDumFGDeAZ1wtADTsx9cz2OVDGDuoFEjUMe
cB+tEqHe3SAIOckGyfWrO1DWyrT646ucOyX7blIBh0pq9Z8ddeOKHCw7BbEaT19XYUSzl7Ofa2tz
yTdgLURytTh2IV7q/YfIL4htgouJ+wXIJNYS+6OT3dFIozUaI7R/3o8iHmokYtYR3tZ+M/TzVIcO
Wzdpnwlv8aGyMxtFOoe8Hch+EihjyyuwLrk5gUiiHWWXU8Ml4WQN2CVKTlBw52egmPjGl1e7hdio
FiLCFnBVYbwrdbCEZeIJpHkMVBqjtPhKVrl8GC/zPUpKbMxuS6a0v1qNJgqJnLcm1DG+A4rGFfGj
uJvIUvTyyHlfI+qPo6q2cxcm0U4+vI5adCGN/7N/rqwbbP/f1Ba9THvJSQugIGhh7oD3YkbE1/zt
6xVBu5Fv1+iu/aFl/VkMhYBPiKsgY7ItdBKQuslIP1Ks8aouc4yXd4HoxHn29mki3Lv6z5gBGtpO
QxFH6FPH85u53e1Ddgk/1iRUw8g8oEcerLWpdN0/X27ET0zzjNrDG8COonL3ODpIrAHTfZmYc2cC
Gv+7xCxsu5h+WCWl8UL+kyB3jP9GbJys3lnodpQbnEzHTVu2Ihpso7/2TEHuS/yYOnLahoywah9i
m06eBcHH7Ss8a4jXSIW+dwQgeEMdg0IJFoP+s+322GxuZ8Uv2hfXrs6f7GdalQdTHcGY/QuRH9GN
Pz6soelvpus6bbJjd/AEbTX7eKOS66DKvjYb4PS/i4TTWoPiStCgrzSjjxdJRsIJmIf2PMu5x5Jy
wjW6wZ1H43wiWGOwNy4RW+75l9cHl4qnlCmVj0K3ZPT6j/hQk2BT2b4rBVI4G4+Oyw/GGZL1O0AT
WC6NIciKZ16Y+bLmWypwuDn6QFIfL1p/S6zSMsbmvYMne4E8m5GSqH8OG1leBnuphCZGEGfd3+k/
MIslmo6iInF9Ib8kG2kBA69xBNNBqsyeiAmeGFiu1IeWJBcDutwilIHK7txjHwJTJLPD5IUFU9oc
qqDNP34YfvlP6Iwd7EifSF/3R41ri0AtDKFx376VY3Pdh++A9TCQntwBgQq4/iUptTNugakkSN2K
NTpMTS1q06w+6DjVVJy42CVlngYKXHxx5G5ECLQqA4dbyh2Zp/iG6mi+VPrPx8r7P/Sos7CoiP5b
ZI0Aywu6B5auRfvh0Ta3XmZpCae6dXSQfc+dqZ1f9AW0ms0sqNe8ZBq30ML0jEiOLgiXWyfATeLI
FV+z00O1LspHuttHYVtV/uudwBzhyA0wC+qifzMlUuTY/2eLBZGe1sATwQP+wF2mpCi+4x4MzHen
rKrBwc95W8qA/nARNC26giyGPn8KTaTAG41huudPo0q2b8GoWnNeGbnrcOaShY+/XQtz8vm6kMKN
MZu+8IQyVR3a7M95Mgi4VDtNRxpfFvEjUa5qoAy3Sk2fRsGI0ArGY/O1x7R/GjtlqlFuPX4QeWCd
rmwerj/1R+Htd5CyqIEQlJJMc0U+Wo9rJFlE4hx+ADFsb6iGkVY4eJFFu64Zt05FWnLF0EclikyI
3QG3AsG56sK0IvBpA5zbXacwqdeIoLyzGwV7AHc+07sr5H66t9lblKJXoiDRHOQ8bqj22TuknxbF
/zxPCOo4HM1kZuHL+4VNSWYVtZ0YOGMbUjXMYz44wU8iTO60F2ANO/Kf7AVaI2dMwvz9qG+HQHiu
jBkFctghK3hPSsLSNPANPA6RP4maOd7/w4jLiquxf/1LTJc32Uq1pROPdIIzPCxKzqnW4srLemUQ
crJs4wCoQ9ZfDGI2eeQLofGq82oIKyj/Q0QG26Ydo61r93U5+mz7LBXotrntJI4ExJpUl2LBaJSR
IgtnJnowbuBCH/u8jm21fR4VnLz5Ud2OAI5MG+eQcxTlLSOLrm1Wd56hbrsh5jiMD27PD1HHIGK0
elLwT5xo6uUP2keGctjEMIl+Fps+sxUppy4S5lstiq667L3Rg2RlB8yvtc/lPYDG2RKlAm9JKUKO
j+K1rdw9tjUbFZz+aOOq/T38Yh1J/2+3fo7Y62r0t5eQKBUSyIwRaIm1TsQn0TOlgxGcWzkVSACo
U0Fr7ak08sknSeixwwN3CU2W7CyIkcYfMwe8Gj0tsON5eHTcoAt8MyWwk2vVGEqQWgDtK+6jS9yq
vyaKR+4ud4HyFnW/TIiuSkqI0PiLmy+AtmjIu3wu6Snsksz0BZ5Ti2nDlv1GPzyI6L49e4iyjW40
lF57uQuTC4duaK9+8FdWFntk6DZHEwIHpa/uC3vFz4LVg2DkIYQmksQFeyWK62sBhrwBZ3PUosJW
FMPC3HQZ/12N/e+XXwbOjYXlCw6UdWZnAG2NgWw39atfIKuiu1WziNuzgAVZ+LLT8rm11+odC1Vu
1CFCwwHpHyT87Rznd5LQf5/G6CO1M8lRtG0YnMQmVWK0vj1ldtE+Z/UmuKMrhiJDfuIC5wzfP6Zr
RBmKLvfa1cX5PrIjKjKxXeWfiO3+WiWrL0h2IZSRI9ogoySUqHNEAE3iOKGL1P2uDarMDxmBS51V
YzaekgIo2LCr90n/OQzJSmN6FZgy0gz6od8u1YEwLL4hRZjUjneaaOp2mq0W187pYrhhU3gc3gpc
pH7wq7PLqtNAdanGLR6j3O4TEW7cOpTr06cM8Ls/Zj9pfvQodlr0OWrtPuC3H2oG7RAODs+g1aqN
4+BLfFd8g7bP1RMsxX73s1asyDS0jWVPAbF6bHEIDzgJGc1qOMBgUqQU92fDhl4Y5g1i/g89I5Yc
9QnmWPtlNsy2lImY3vfu+B72mnYZvUM9SgpAjIciAxw+iabSiR/uqaGmDqHdtfzEwwrR4g9pMYrZ
sQ58OtW12qyahXUes1fctAFBaWwePq71t1vv4PA7UoitcWxW0Cnd5BfUX4nzmjgVNSdj9LkPs1Bk
G8adsRTLfm7soYiRCVSRj6s0a4bumqWMKBT14dipNoTMQy/E1IT1FLNY9p/pwp/uft8JYR7RXgBQ
Mnq6OkZLQD1yo+tzY9J+BScRQRvxxSdBU/4BA6y0KbMaVAGIGD2MKso/zvgbao93TcjBtFz5sLGC
chgNLYqnKBLt8ZDmj+himWSzLCRcSO7nFS02jIZT165umqdiCnv4gAQGxvfeYdGUaFk350czqxjp
vVUaLC1yJ+XTfnsf28s5ENjtU14zZsMPzD8aaMlqKoOz4MOtqQxkBQWDjmt1tQlx1DQ0NT6jLc3a
EQQoZir/5Bdfj7W4SVEm1LxWumZWOSiuVRlLxo0g3ZyocAG2HBJbSBNq+7Jf5ODTMHCcjpMVulmd
2bd1Gs+CXuOEMrUCwRnZOOtqCR9UXJmkQqr2XgPyVsO5Zjw3f3z2DMxS0zzeWBL7Y5JC3lU3s9VZ
0S4ah+Kpn1ii9tZ5o1/deQN+svbL6VfRYZPq95+mIi+fu1giImiKR0gdCvKZm7zC20+1uJFBeCft
kAKGbLr7VqEgyyK5wV34HdaTOp6jnXbUa2tG3sIMRP4rtCv+X9UadZxSb6+ys+g5F6Q+SQ176RHs
MHNAWMYlm72aIzM97pEB3GZ6TQoHqNTcR+1LTLPwLK+pBPvjY8Hk355zpMrVA6bmal9vrxDs7B3y
U2e6C0ofqkgms60AGyJng9ydZ46kKCWybRdpQALdH/FUXnNC6dFRx3HZwQAy4JcrcboxMvGvxUZv
aqlCwL04z7N/xLg87eBtpWOiUQ6V5y36sVorObNCXx+GVtowpiFHCPAk2xGsUFlEv2YpFX7swD/u
SAH65YDgQNlF39nLAeBnzRvuvZwMOeUF8OPWTC6vMsn98j1u93NG9AG1UbRUipMf6+Ihw08tvq2N
94UUvk5MHzGzkOmSkH7qN1wF93tKZm0q3LGmChx9VMVHJtDg6dmzQ8ZzUsBHCFFudnqqz+gPpaNm
22qBDooDKvHVuJIPbmq2FWd9OQ5Ta/A0imX3+El58RdAPN8tEiZsgIz9FKVA4Yr0l5tvwNwBnk2k
2pAyhA2HJ/Pv5zJNgeXqHw2phYFr5nJRDwW64CW+YU1ZkL3ulWiIgnoybMOTPnZKAlYaWKrqv0Pp
H9IFKCDjBigdknflwEb4zeAm1HGUNlcR6bv3Qh11nO8oOE0EtVbBQXJ7yb3F+6fwSlErtTGbMGMz
VQSqgFBXL+XT2pZXwH5d/T1/KPfXji7TyNqJVcIf51hMgnjQMtc380KgMMeyVDEPsJnTtjNSrkjM
SmUvy/dBbgJFWpHUd21TYlCbO1aiiej93AG7xtYMc+b5yGmZ0gqAcZTIgLkU0U2om5BD2xRCtFwp
HfWdkxKGATPsS/y28pPAroViG8FCOq8+iatZGvDrbpdpMpLpDriF/ijP3z1EqF5DBnVQq4zgF55C
AzW+Mrs/tq5IaSBJC9PX5u5gWMLMbt+70+xixE/Db16NA5MWUIIVoJDwspdy2PmJqu6e5ki28v+d
hMD2KKXe4VWb5pNXtNcbuiIeqeXOgUR++GbtN7rO5nZsmb8o2yKPeGdrClnAjlJUbKMkDN0IGkgk
30LE7f3pAWipUA3BYTSg5RDUyFVc6wGAVorMZ3JD+HwMXujzKE6plhredEiG/UK+o/m7bV/LYRg0
/pqk1uMXUp5qDMGBeBrncBxvGx1fx+8jJ8iPIgkGOGNTybGR6aV4kXg12f65Csn8CaVn2ce1PtNl
hG4okFYSj1Qc1wTEPebmDV2YCab/VjuSKIg8WXYNsOpCp9iAkpD4tQJxU9LQnkkfcD7/QT0D/tkf
ASnX9AhsIQXFKorgpEmvKDfgGydBTFy1XFUVZyvKzAXboYVCeSVBe3LobsXEdJisART3zrJ/6d2f
nHdbER/jyiJcDsXPhChOipP6znzTOMtdz8RB1BdKeHW9w+66ODe2YOsZ+sBBX7VocBXIHXuSowx7
s2tyVMzy6jplvYyIgLXnax7UilUkZJu/rOhPRwKfaz7I0BGEExaSWW+mQRifrTUILb0nQPjR/t+v
BZ4zKKf5jAM7QFRxT/m9F4ZO+vKRX5luBWfOjzmeOAyud4tgT9OUZrJKC9egFdmpuzpSprXAF54m
qrQANwujikxf9aREYMN6W2PcSIOI0pKnp0CE6Rd3aOAws7GKa+nzYD7leQmJ5d+TYZLSKGzsTehx
aBOduxYz4CeXUcLP8Pb5G+dRP7Zf3K9Mbj5qwYOLBAN8gNEiEQeLs6vFa0H9RvthRA1r9btg/zTO
LR3SxjM0TO8MRR74R9zdqpgvqclr7fMC8iByO2jwLScKUoYrqdnVU0DMOk51sWr+rGXR5OC+deUP
hfjXo6jX6h8j66Ld5Fwr1UYIKfTX5/k2+zI8plXAklF9YkBIhJ+QPfT2GnU9L97W3M+vkfBjOXl4
L52Bnw4uChIFzagidjKyFE2vb4i3MyA9mVjT5LMmL3fRITfyH9EBw9kyrt4hTYeDzez79vNWmeiR
M4OSKQEe7jJTtrjXtX+mlLCWbAFw5xeXgYYL8IpaSTdvOMN0PwlID5SelMMM/8xi8R0hwIslh1SK
r6CP3f3CwpbVIQgE99MfXFkBfivoVfbWeZxfkcckw7H4lJfn0LxsJvq4UdYcd+DNdagO5qxX+BR7
qApSgDsRkLB84YAvfL6an3FfQUUC1FwX6x0kkBEV3gGj6XtEqqMT6KnRVyJxNVeU96d6BTaQOiAT
8bdai4FXDE6s6tcRIlcLh/sNaXO6iTaGi1Yhzka81Sq9ebor6VBkJUDnN8Xg03k7P3dNisCtOkQo
gOME2bSj4UOxk/e1ti6fXfxPzDCiCis25qIDpZ+Xl0jVt45i0eOrGLI0JSbF/z7ky9tUymqZzS3t
TXuSNPHNEvS25DRuNypCHj0B9dv7CFQIy6fiTff8tFk/xXQqRiHS3IELQF44pIGXiIuOar/howjq
K7ZdZdN7aUv+GsiL5izidEXVcza1aF32sNuW88KTMeDpxhDLaNcgSZhkz4Ms0ci7cvLEXrBi4GKk
BwfirJSkfa099qogTndYFWqaUt9GyskPMoiLvPexTx7FMSlTo0KKgrBMTbe7rVJMl0stZcAp0rLO
x4nQr9e6z/M+SPF+cvcARB6h0dfK58BTmMBsKIOiZdihFjKCCcWOAKTSsYiNK/egshISgRrqNTL7
LGIoEhBfEqttE7XC6kCf7/GKigzBEZou/LmbcwmmhFRRjqZUxSeHF5Zeamn3lM+0T4nun14IwzQY
VeM5qfVYHONQXumXilteDqLIYc9Ome3XakyB7oqAT8j5pksVndyqKBrdW0IF3FZxm/6+wpnJTDXH
ghzoQzMb1BP+DJXIwmgnErmc5SgeOZlIMGuHPYXHz/4XIwQFAYkVnJQymTZwna7LVDVsi1TlX3h4
TU1VCod0BkKCxVx53WBkPuh5i1rL43lcmVO7WIe7Dr3Wt87nnFyvy6ssdeUKgqfb0XcBd/tXRpD5
CaRTC6DtwsZs7EebtiNl+mHpUtKoesvuebTWQsiqYu8CY+3W3z6gSaukeETMCel7gTQA+TUAdDr4
gbHxdZul/OdXIRciJmKKtMJsuT+hykoNRa3jkjg8WZ/k6Cu+pdrfKsKEbXmP5+MOtrzJW9rY5LQa
tI5OzZHTBvXVxRjrT28Eb6If651aNwRkVxArCTkULfZUg2uuz+VlHE3hPmvgETeCmj3wOwIKqf97
viQ9i/00dsTOVaLS9WpsDN17LBB0M/hOURQT5p+d0EJWT8fT+rC5siwBlaqH52trhquKDDUy/UV/
xMsA8D22392j5O78P0B0FncTHMvVzYakAdBJkF1F+dE/I5r03Gu5y3mWK2xgb+9Vbpmun5Yz+Tpn
aoKceRFWWYBLuCF1CQP0CeD/kegAhxaKoEFGVBFt4VS1A2P9H2MzRE3wViqc6QRZWDOyxvc7m4bo
JphIV/1YE4ljhRqcDTeGEzb4rxcVmYvtC3rOld8jpcVsYxFUZ5srZHPo3w2vOUbWjLO3DPxUoCDp
lfs6mjJr2ZUTUFH5MT9Su2hzeCkukhFucBFh6vkibyE10MBSd3lJABS8C6YZ469IbJ3a4ngvUOC+
vIEj5G+C/xGM59+G8CT5q1GCKXvqSuuCvtFRwJWmFRZg03aoFDi+E3lIlQwS9VyDi69/Ha9Lb2AD
iygU0qipv+gpAAWFwLys/E+l/SP2upOsyt1hCeSgw3TM0hGIO2G/jF16Q0wpQTFc8nTU4mHW/6Ln
BqLlSDJuODUXE6zpaLxJeP4B8kNSyDovVRlaCgwQkov+kbJDIBBjL1JpI+aDKpjJA8yeFnKSVstS
cR196SbKmG8sb/1RzR7Z6VFKyC8Vf1DnUXC19tCKTFCYY03FpxxX7HPzqDzyQdvGwjOyTjoV5UrG
Q1OvZvIFsubkHQVX6AJ9LtBDbPi5SCft/xqb3hz4dZ6Ne6XVkv1EkPlui2iTuIkmEJHyF2rIuD7B
IVtd19xZ5iyXitkCju1iWCVCBsyFOjKsz79kYH4F0IA7uiyOqOxGDVYrAxXi7JnWPFN8b1+ofJSg
v5Hr5UH/V61aenxKbjdoBloUfKQXs09YI0njydkd4c1HVSVgVfGcKIr9RnG1IhtvButVbyLQ6ghg
hO/LDEV7unEGgYuX6ztcOFAVxUiJ4V+6rBtgng7UXpuA4hYAgt2PO3z+QnbYEzalPKvhxwQHbhHm
cYhA3PCscnUavhlQYkgW2h34zYjk4+ocLVmglCwSNTbxQu537HR3sUaXPJehTmVsyIHQzFbDcFnF
KLV8NsZcbUXdLt/mzVxLE1jVsWmLL1N9DBcJGoq5XCzF5brUTzdjFNwZVU9docsEHbDjkTHUZzlP
f44DqU869BUkpOoCaJIpj5/FVLeUI7aO0QkysUr9H3mMzREQxLkI+soWwwrNniFpLf3OzDuyFq5A
iBvuzt7Ts2d5wmVfEIZX6IQ0kWNGxd8OawJwCgoGxHniarRFzFpkh4Ij4+x8NzxRkfyd1bZZ6G2h
6E9LIlhJFXRKPvLFvkE1XaKAZW6L4OlbZY+dYc9wqpoOQfNVVfRLdwP3mMoPs8eU06Dl5K5gY7DP
+k2/NT7w9zx/+Fbh+KP2hehLfDfZU+6x2IEZ7MvJCGK2Y/K1Q0w8+z0IGcQkPVy8lkgbTfJwEFBP
HpI+QEug41RrXCAcGyXv2byd/lxgWSo6xz6UP/vWBKhpLAjo4qAYKTeTtXF/FRw0EFYc1Auo3qUb
62x8o67bYBUZzqWTWTT7Ku1knFuXJ88qVokwshaqZfI62KwnKoquDXtHCnr+SsymjiaEDrcaSFBR
ZcMoeTHnS1zDpdnbPPT+weXsD5bek9UDLjkHW5hrF/Mw11lM0bp0Ar52eA07Ob5SMTlOPbnL6T3f
JUayb0S08tpq7gG9q0gMRltUEbQaBpqlgKP8ALSjJ92GxYhTaio8RxRV0pCZZ2dbEnOhkigMTj/6
JNA9E6yS68ZMoAhDGZ/Fi4imfvuhaFGmGtoZNSgpERcmx22J5OLpa6Z2WTJFB1+/oVPV7kZjQYfc
S5NmRBY0s9pPguQADkqq0YBKBcg/LgYZMDoCat0g8NA6AAHmgy6SH6HX4oVMWpqFsCzlQz/LPq1W
SdStPJx7F7YwBtLG6Dk6bt2Mt/dUNpu58W2Qqbu/1vyG8B9HasRhELV7psh24b+ED6hLeeTrIcyh
ee9jjEdW8u0T4g9TzDtKOsIXejiL2lQp8FCJ7IpxZs5ocTnHAh0UopNhSSEwYh0m91t35NSXIecl
EgIibEXF5JOrISpHNtTRpztc74fX3edd9snJapnZE92hGOQos4K6jDwKnRZ2VxsLSSlCYcsL1rP/
tDQ1MAWgMuBHIpR4XBDNFtOHbn1PV21DuqSNVqCfEqW3oaAE5Xi+XtcBDxkIflwHGytq9LWyv0kb
ZSTSkaowbR2y3ipWBTXWeKP3iV+72C9FrwEq53NffwTxwjgXWkb6G02GTN/h6liLN/suv0Q7ywjs
wvV3xPeFShF/uxDLs0iw/zycqXpTT7SMOiwPWCfop/vnaTdL+ENBzDmEW0cmocdeSAR3IGkfn0gu
NYh+9XEMPqoOsINc3VpNXiqtTWarog3U64AaUo4Sw8Yb+Ks67OhQ0a1F6T62XFpN5g6O0oubsX3/
POA6PV2y2HTR2jeIvNXCxFG6/cDesff+1QJVJ9d7ELAP7cUJkagmTC/ND6Hmmpd17npY2XjsTMsR
+mu/WwR/fX/Q6hpiAX3NQDQ/D878jYL8tNVc7XXhqvWQZ/TRQe9U6eBFDuOyRgsL4ynCMBf5MAGx
V4ha7nZ1q5jQ72fkrN7/ezqf/Gyh2heAWxYBa9KOLDpXmGO4cWHMdUaJGMA91qiBddNUIHZ0aEix
cPUxGWWuoZNLo0/SCfyxupsWXglKPfCOvmsOXQS3a1SoL/G67ts3KaajiACYBWjDeyO/H3pl7Fv8
kYan697bHVbEsx1SIV9qXxTB7q2pJuJImRLPDDsajLKkx8kWERV6GPEc4qGPjX7f/t5QCB0/n0d3
iYJeOV88/ewKZdxP/g4dLfkmRK9pEIgMUo+oy+pu2yRP+IXekD1t4je5XBUrAQ9+kDfty2GGEAjc
TnSV+xuI7GptX021w8nw+KYEPz7UOJBESh9dVqLN5xBY6QVT8IItMnkTOclM/hyzCB3dija5fQzn
jaMwbL5GpCBhaVRH40psPDtTGADDdIXNrWk0yeLynEtOKTklqxNPHCRKQqlAmijwqNuoNnkm2lt3
vPAA72U/YnMRWG/Xnm1BN8HErE9U0OkaTb5dYVkTVScqVoA6SYff/K7KtSBt8zOgctbwTI89/UzH
sreJ6hz0onLUOHJnN+qlhwJdp+5twkUlHDE2xy8xXwTGhWgupOKvrCamKVk4TVe2IQ1R6nN+tskO
Z2J5o9ejZwY307KbK0H5nbDLux3j0lcKtshdLfGgTrswCXmBg6VxZELcNoLiAbQq76w2iDDOjg+Q
8WBp3haeMVHjZDSi0pMWmxE0tjnZnLBulajQ8ixMcYW79UsWE0bYwWAcV9ckaCNSYuH7XL6C+5YW
a1aB/kHIqz5FzwhDOt0m1NJfjiLseBTCw7VBOe9bpuIWc9ii0DAO9eINDY9j+Kkx/vydu8xkuHRP
dOxteWuyFOGOPRQWX6nLgHh/JQe9XW4sx3wx3J6j5HCd8558sFaGRWNMLs+Uz8chJLWujOz4nZJN
c+KnIxCGd2Zlqv8IGAJjyDHJXLV/uWdvwLXyCV5BD8g49MAKFrbLkpeN8s/zyV09QDdu+blfB9j4
TSBFoIwCTqx1dmlfoQ8QU1Xqnw==
`protect end_protected
|
-- $Id: led_pulse_stretch.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: led_pulse_stretch - syn
-- Description: pulse stretcher for leds
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end entity led_pulse_stretch;
architecture syn of led_pulse_stretch is
type regs_type is record -- state registers
seen : slbit; -- DIN seen
busy : slbit; -- POUT busy
end record regs_type;
constant regs_init : regs_type := (
'0', -- seen
'0' -- busy
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, DIN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if CE_INT='1' then
n.seen := DIN;
n.busy := r.seen;
else
if DIN='1' then
n.seen := '1';
end if;
end if;
N_REGS <= n;
POUT <= r.busy;
end process proc_next;
end syn;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: This BFM is only intended as a simplified UART BFM to be used as a test
-- vehicle for presenting UVVM functionality.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library std;
use std.textio.all;
--=================================================================================================
package uart_bfm_pkg is
--===============================================================================================
-- Types and constants for UART BFMs
--===============================================================================================
constant C_SCOPE : string := "UART BFM";
constant C_DATA_MAX_LENGTH : natural := 8;
constant C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR : string := "; ";
type uart_expect_received_data_array is array (natural range<>) of std_logic_vector(C_DATA_MAX_LENGTH-1 downto 0);
type t_bfm_error_injection is record
parity_bit_error : boolean;
stop_bit_error : boolean;
end record t_bfm_error_injection;
constant C_BFM_ERROR_INJECTION_INACTIVE : t_bfm_error_injection := (
parity_bit_error => false,
stop_bit_error => false
);
type t_uart_bfm_config is record
bit_time : time; -- The time it takes to transfer one bit
num_data_bits : natural range 7 to 8; -- Number of data bits to send per transmission
idle_state : std_logic; -- Bit value when line is idle
num_stop_bits : t_stop_bits; -- Number of stop-bits to use per transmission {STOP_BITS_ONE, STOP_BITS_ONE_AND_HALF, STOP_BITS_TWO}
parity : t_parity; -- Transmission parity bit {PARITY_NONE, PARITY_ODD, PARITY_EVEN}
timeout : time; -- The maximum time to pass before the expected data must be received. Exceeding this limit results in an alert with severity ‘alert_level’.
timeout_severity : t_alert_level; -- The above timeout will have this severity
num_bytes_to_log_before_expected_data : natural; -- Maximum number of bytes to save ahead of the expected data in the receive buffer. The bytes in the receive buffer will be logged.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the UART BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the UART BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the UART BFM
id_for_bfm_poll_summary : t_msg_id; -- The message ID used for logging polling summary in the UART BFM
error_injection : t_bfm_error_injection;
end record;
constant C_UART_BFM_CONFIG_DEFAULT : t_uart_bfm_config := (
bit_time => -1 ns,
num_data_bits => 8,
idle_state => '1',
num_stop_bits => STOP_BITS_ONE,
parity => PARITY_ODD,
timeout => 0 ns, -- will default never time out
timeout_severity => error,
num_bytes_to_log_before_expected_data => 10,
match_strictness => MATCH_EXACT,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
id_for_bfm_poll_summary => ID_BFM_POLL_SUMMARY,
error_injection => C_BFM_ERROR_INJECTION_INACTIVE
);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
------------------------------------------
-- uart_transmit
------------------------------------------
-- - This procedure transmits data 'data_value' to the UART DUT
-- - The TX configuration can be set in the config parameter
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- uart_receive
------------------------------------------
-- - This procedure reads data from the UART DUT and returns it in 'data_value'
-- - The RX configuration can be set in the config parameter
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- uart_expect
------------------------------------------
-- - This procedure reads data from the UART DUT and compares it to the data in
-- 'data_exp'.
-- - If the read data is inconsistent with the 'data_exp' data, a new read will
-- be performed, and the new read data will be compared with 'data_exp'.
-- This process will continue untill one of the following conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_receptions'
-- c) The time spent reading is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_receptions' is set to 0, it will be interpreted as no limitation on number of reads
-- - The RX configuration can be set in the config parameter
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- odd_parity
------------------------------------------
-- - This function checks if the data parity is odd or even
-- - If the number of '1' in the 'data' input is odd, '1' will be returned
-- - If the number of '1' in the 'data' input is even, '0' will be returned
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body uart_bfm_pkg is
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic is
begin
return xnor(data);
end odd_parity;
---------------------------------------------------------------------------------
-- uart_transmit
---------------------------------------------------------------------------------
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_transmit";
constant proc_call : string := proc_name & "(" & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
alias stop_bit_error is config.error_injection.stop_bit_error;
alias parity_bit_error is config.error_injection.parity_bit_error;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- check if tx line was idle when trying to transmit data
check_value(tx, config.idle_state, FAILURE, proc_call & " Bus was active when trying to send data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
tx <= not config.idle_state;
wait for config.bit_time;
for j in data_value'low to data_value'high loop
tx <= data_value(j);
wait for config.bit_time;
end loop;
-- Set parity bit
if (config.parity = PARITY_ODD) then
tx <= odd_parity(data_value);
elsif(config.parity = PARITY_EVEN) then
tx <= not(odd_parity(data_value));
end if;
-- Invert parity bit if error injection is requested
if parity_bit_error = true then
if (config.parity = PARITY_ODD) then
tx <= not(odd_parity(data_value));
elsif(config.parity = PARITY_EVEN) then
tx <= odd_parity(data_value);
end if;
end if;
if (config.parity /= PARITY_NONE) then
wait for config.bit_time;
end if;
-- Set stop bits
if stop_bit_error = false then
tx <= config.idle_state;
else
-- Invert stop bit if error injection is requested
tx <= not(config.idle_state);
--Will return to idle/normal stop bit after 1 bit time
tx <= transport config.idle_state after config.bit_time;
end if;
wait for config.bit_time;
if (config.num_stop_bits = STOP_BITS_ONE_AND_HALF) then
wait for config.bit_time/2;
elsif(config.num_stop_bits = STOP_BITS_TWO) then
wait for config.bit_time;
end if;
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- uart_receive
---------------------------------------------------------------------------------
-- Perform a receive operation
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant start_time : time := now;
-- local_proc_* used if uart_receive is called directly from sequencer or VVC
constant local_proc_name : string := "uart_receive";
constant local_proc_call : string := local_proc_name & "()";
-- Helper variables
variable v_transfer_time : time;
variable v_proc_call : line; -- Current proc_call, external or internal
variable v_remaining_time : time; -- temp variable to calculate the remaining time before timeout
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_terminated : boolean := false;
variable v_timeout : boolean := false;
begin
-- check whether config.bit_time was set properly
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
data_value := (data_value'range => 'X');
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If timeout enabled, check that timeout is longer than transfer time
if config.timeout /= 0 ns then
v_transfer_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_transfer_time := v_transfer_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
check_value(v_transfer_time < config.timeout, TB_ERROR, "Length of timeout is shorter than or equal length of transfer time.", C_SCOPE, ID_NEVER, msg_id_panel);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'uart_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing uart_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name & ". ");
end if;
-- check if bus is in idle state
check_value(rx, config.idle_state, FAILURE, v_proc_call.all & "Bus was active when trying to receive data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait until the start bit is sent on the bus, configured timeout occures or procedure get terminate signal
if config.timeout = 0 ns then
wait until (rx = not config.idle_state) or (terminate_loop = '1');
else
wait until (rx = not config.idle_state) or (terminate_loop = '1') for config.timeout;
end if;
if terminate_loop = '1' then
if ext_proc_call = "" then
log(ID_TERMINATE_CMD, v_proc_call.all & "=> terminated." & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- termination handled in calling procedure
end if;
v_terminated := true;
end if;
-- if configured timeout, check if there is enough time remaining to receive the byte
if config.timeout /= 0 ns and not v_terminated then
v_remaining_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_remaining_time := v_remaining_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if now + v_remaining_time > start_time + config.timeout then
-- wait until timeout
wait for ((start_time + config.timeout) - now);
if ext_proc_call = "" then
alert(config.timeout_severity, v_proc_call.all & "=> timeout. " & add_msg_delimiter(msg),scope);
else
-- timeout handled in upper module
end if;
v_timeout := true;
end if;
end if;
if not v_terminated and not v_timeout then
-- enter the middle of the bit period
wait for config.bit_time/2;
check_value(rx , not config.idle_state, FAILURE, v_proc_call.all & " Start bit was not stable during receiving. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait for data bit
wait for config.bit_time;
-- sample the data bits
for i in 0 to config.num_data_bits-1 loop
v_data_value(i) := rx;
-- wait for middle of the next bit
wait for config.bit_time;
end loop;
-- check parity, if enabled
if config.parity = PARITY_ODD then
if rx /= odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
elsif config.parity = PARITY_EVEN then
if rx /= not odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
end if;
-- check the stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect stop bit received. " & add_msg_delimiter(msg),scope);
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for config.bit_time/2 + config.bit_time/4; -- middle of the last half. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second half stop bit received. " & add_msg_delimiter(msg),scope);
end if;
elsif config.num_stop_bits = STOP_BITS_TWO then
wait for config.bit_time; -- middle of the last bit. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second stop bit received. " & add_msg_delimiter(msg),scope);
end if;
end if;
-- return the received data
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. uart_expect)
end if;
end if;
DEALLOCATE(v_proc_call);
end procedure;
----------------------------------------------------------------------------------------
-- uart_expect
----------------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1; -- 0 = any occurrence before timeout
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant start_time : time := now;
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_num_of_occurrences : natural := 0;
variable v_check_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_timeout_ok : boolean;
variable v_config : t_uart_bfm_config := config;
variable v_received_data_fifo : uart_expect_received_data_array(0 to v_config.num_bytes_to_log_before_expected_data-1) := (others => (others =>'0'));
variable v_received_data_fifo_write_idx : natural := 0;
variable v_received_output_line : line;
variable v_internal_timeout : time;
variable v_alert_radix : t_radix;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- if timeout = -1 function was called without parameter
if timeout = -1 ns then
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
assert (v_internal_timeout >= 0 ns) report "configured negative timeout(not allowed). " & add_msg_delimiter(msg) severity failure;
-- Check for v_internal_timeout = 0 and max_receptions = 0. This combination can result in an infinite loop.
if v_internal_timeout = 0 ns and max_receptions = 0 then
alert(ERROR, proc_name & " called with timeout=0 and max_receptions = 0. This combination can result in an infinite loop. " & add_msg_delimiter(msg),scope);
end if;
if v_internal_timeout = 0 ns then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences. " & msg, scope, msg_id_panel);
elsif max_receptions = 0 then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
else
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences and " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
end if;
-- Initial status of check variables
v_check_ok := false;
v_timeout_ok := true;
if max_receptions < 1 then
v_num_of_occurrences_ok := true;
else
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Setup of v_config with correct timeout
v_config.timeout := v_internal_timeout;
-- Check operation
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Receive and check data
uart_receive(v_data_value, msg, rx, terminate_loop, v_config, scope, msg_id_panel, proc_call);
for i in 0 to v_config.num_data_bits-1 loop
-- Allow don't care in expected value and use match strictness from config for comparison
if data_exp(i) = '-' or check_value(v_data_value(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
-- Place the received data in the received data buffer for debugging
-- If the FIFO is not full, fill it up
if v_received_data_fifo_write_idx < v_config.num_bytes_to_log_before_expected_data then
v_received_data_fifo(v_received_data_fifo_write_idx)(v_data_value'length-1 downto 0) := v_data_value;
v_received_data_fifo_write_idx := v_received_data_fifo_write_idx + 1;
else
-- If the FIFO is full, left shift all input and append new data
for i in 1 to v_config.num_bytes_to_log_before_expected_data-1 loop
v_received_data_fifo(i-1) := v_received_data_fifo(i);
end loop;
v_received_data_fifo(v_received_data_fifo_write_idx-1)(v_data_value'length-1 downto 0) := v_data_value;
end if;
-- Evaluate number of occurrences, if limited by user
if max_receptions > 0 then
v_num_of_occurrences := v_num_of_occurrences + 1;
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Evaluate timeout if specified by user
if v_internal_timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := now < start_time + v_internal_timeout;
end if;
end loop;
-- Concatenate the string FIFO into a single string with given separators
for i in 0 to v_received_data_fifo_write_idx-1 loop
write(v_received_output_line, to_string(v_received_data_fifo(i), HEX, SKIP_LEADING_0, INCL_RADIX));
if i /= v_received_data_fifo_write_idx-1 then
write(v_received_output_line, C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR);
end if;
end loop;
if max_receptions > 1 then
-- Print the received string of bytes
log(v_config.id_for_bfm_poll_summary, "Last "& to_string(v_received_data_fifo_write_idx) & " received data bytes while waiting for expected data: " & v_received_output_line.all, scope, msg_id_panel);
end if;
if v_check_ok then
log(v_config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time),ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(config.timeout_severity, proc_call & "=> Failed due to timeout. Did not get expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(v_internal_timeout,ns) & ". " & add_msg_delimiter(msg), scope);
elsif not v_num_of_occurrences_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_data_value, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
if max_receptions = 1 then
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences, received value " & to_string(v_data_value, v_alert_radix, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope);
else
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
else
alert(warning, proc_call & "=> Failed. Terminate loop received. " & add_msg_delimiter(msg), scope);
end if;
DEALLOCATE(v_received_output_line);
end procedure;
end package body uart_bfm_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_pulling_width_adapter is
generic (
-- all cusp function units have these
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
-- configuring the input and output widths
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
-- cusp system clock, reset
clock : in std_logic;
reset : in std_logic;
-- interface to cusp
ena : in std_logic := '1';
-- input side
input_data : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
-- output port
output_data : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_pulling_width_adapter is
-- the number of output words which will fit (wholly) into an input word
constant N : integer := IN_WIDTH / OUT_WIDTH;
-- enough buffers to store N output words
type buffers_type is array(integer range <>) of std_logic_vector(OUT_WIDTH - 1 downto 0);
signal buffers : buffers_type(N - 1 downto 0);
-- a counter counts how many output words we can serve without pulling from the input
signal outputs_waiting : std_logic_vector(N - 1 downto 0);
signal perform_pull : std_logic;
signal perform_pull_delay0 : std_logic;
signal perform_pull_delay1 : std_logic;
signal perform_discard : std_logic;
signal perform_discard_delay0 : std_logic;
signal perform_discard_delay1 : std_logic;
signal outputs_waiting_delay0 : std_logic;
signal outputs_waiting_delay1 : std_logic;
begin
-- check validity of inputs
assert OUT_WIDTH <= IN_WIDTH
report "Currently only narrowing output adapters are supported"
severity ERROR;
-- always output buffer zero
output_data <= buffers(0);
-- input_en is derived combinationally, but only very simply
need_input <= pull and pull_en and outputs_waiting(0);
perform_pull <= pull and pull_en;
perform_discard <= discard and discard_en;
-- every time pull is triggered the counter rotates round and:
-- if there are no words stored, input is pulled and captured
-- if there are words stored, the stored words are shifted
-- either way there should be a new word in buffers(0) on the next cycle
-- discard en just causes any outputs waiting to be discarded
respond_triggers : process (clock, reset)
begin
if reset = '1' then
buffers <= (others => (others => '0'));
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
perform_pull_delay0 <= '0';
perform_pull_delay1 <= '0';
perform_discard_delay0 <= '0';
perform_discard_delay1 <= '0';
outputs_waiting_delay0 <= '0';
outputs_waiting_delay1 <= '0';
elsif clock'EVENT and clock = '1' then
if ena = '1' then
if perform_pull = '1' then
-- either way, rotate outputs waiting around to decrease the number of
-- outputs waiting, or replace 0 with MAX
outputs_waiting <= outputs_waiting(0) & outputs_waiting(N - 1 downto 1);
elsif perform_discard = '1' then
-- discard causes what is effectively a reset
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
end if;
-- delay the control signals by the latency of the read (2 cycles)
perform_pull_delay0 <= perform_pull;
perform_pull_delay1 <= perform_pull_delay0;
perform_discard_delay0 <= perform_discard;
perform_discard_delay1 <= perform_discard_delay0;
outputs_waiting_delay0 <= outputs_waiting(0);
outputs_waiting_delay1 <= outputs_waiting_delay0;
if perform_pull_delay1 = '1' then
if outputs_waiting_delay1 = '1' then
-- currently no outputs waiting, so this output request will
-- have to be serviced by passing a request for a whole new
-- input word to the input port
-- driving need_input high is dealt with combinationally, so
-- all that needs to be done here is capture the resulting
-- output
-- THE ASSUMPTION IS THAT WHATEVER IS DRIVING THE INPUT HAS
-- A TRIGGER TO DATA DELAY OF ZERO
for i in 0 to N - 1 loop
buffers(i) <= input_data((i + 1) * OUT_WIDTH - 1 downto i * OUT_WIDTH);
end loop;
else
-- currently have outputs waiting, so just shift the buffers
-- around to prepare output for the next clock cycle
for i in 0 to N - 2 loop
buffers(i) <= buffers(i + 1);
end loop;
end if;
elsif perform_discard_delay1 = '1' then
-- discard causes what is effectively a reset
buffers <= (others => (others => '0'));
end if;
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_pulling_width_adapter is
generic (
-- all cusp function units have these
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
-- configuring the input and output widths
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
-- cusp system clock, reset
clock : in std_logic;
reset : in std_logic;
-- interface to cusp
ena : in std_logic := '1';
-- input side
input_data : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
-- output port
output_data : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_pulling_width_adapter is
-- the number of output words which will fit (wholly) into an input word
constant N : integer := IN_WIDTH / OUT_WIDTH;
-- enough buffers to store N output words
type buffers_type is array(integer range <>) of std_logic_vector(OUT_WIDTH - 1 downto 0);
signal buffers : buffers_type(N - 1 downto 0);
-- a counter counts how many output words we can serve without pulling from the input
signal outputs_waiting : std_logic_vector(N - 1 downto 0);
signal perform_pull : std_logic;
signal perform_pull_delay0 : std_logic;
signal perform_pull_delay1 : std_logic;
signal perform_discard : std_logic;
signal perform_discard_delay0 : std_logic;
signal perform_discard_delay1 : std_logic;
signal outputs_waiting_delay0 : std_logic;
signal outputs_waiting_delay1 : std_logic;
begin
-- check validity of inputs
assert OUT_WIDTH <= IN_WIDTH
report "Currently only narrowing output adapters are supported"
severity ERROR;
-- always output buffer zero
output_data <= buffers(0);
-- input_en is derived combinationally, but only very simply
need_input <= pull and pull_en and outputs_waiting(0);
perform_pull <= pull and pull_en;
perform_discard <= discard and discard_en;
-- every time pull is triggered the counter rotates round and:
-- if there are no words stored, input is pulled and captured
-- if there are words stored, the stored words are shifted
-- either way there should be a new word in buffers(0) on the next cycle
-- discard en just causes any outputs waiting to be discarded
respond_triggers : process (clock, reset)
begin
if reset = '1' then
buffers <= (others => (others => '0'));
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
perform_pull_delay0 <= '0';
perform_pull_delay1 <= '0';
perform_discard_delay0 <= '0';
perform_discard_delay1 <= '0';
outputs_waiting_delay0 <= '0';
outputs_waiting_delay1 <= '0';
elsif clock'EVENT and clock = '1' then
if ena = '1' then
if perform_pull = '1' then
-- either way, rotate outputs waiting around to decrease the number of
-- outputs waiting, or replace 0 with MAX
outputs_waiting <= outputs_waiting(0) & outputs_waiting(N - 1 downto 1);
elsif perform_discard = '1' then
-- discard causes what is effectively a reset
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
end if;
-- delay the control signals by the latency of the read (2 cycles)
perform_pull_delay0 <= perform_pull;
perform_pull_delay1 <= perform_pull_delay0;
perform_discard_delay0 <= perform_discard;
perform_discard_delay1 <= perform_discard_delay0;
outputs_waiting_delay0 <= outputs_waiting(0);
outputs_waiting_delay1 <= outputs_waiting_delay0;
if perform_pull_delay1 = '1' then
if outputs_waiting_delay1 = '1' then
-- currently no outputs waiting, so this output request will
-- have to be serviced by passing a request for a whole new
-- input word to the input port
-- driving need_input high is dealt with combinationally, so
-- all that needs to be done here is capture the resulting
-- output
-- THE ASSUMPTION IS THAT WHATEVER IS DRIVING THE INPUT HAS
-- A TRIGGER TO DATA DELAY OF ZERO
for i in 0 to N - 1 loop
buffers(i) <= input_data((i + 1) * OUT_WIDTH - 1 downto i * OUT_WIDTH);
end loop;
else
-- currently have outputs waiting, so just shift the buffers
-- around to prepare output for the next clock cycle
for i in 0 to N - 2 loop
buffers(i) <= buffers(i + 1);
end loop;
end if;
elsif perform_discard_delay1 = '1' then
-- discard causes what is effectively a reset
buffers <= (others => (others => '0'));
end if;
end if;
end if;
end process;
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
we : in std_logic_vector(7 downto 0);
adr : in std_logic_vector(1 downto 0);
oe : in std_logic ;
Y0,Y1,Y2,Y3 : out std_logic_vector (7 downto 0)
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(oe,adr) is
begin
if oe = '1' then
if adr="00" then
Y0<=we; Y1<="11111111"; Y2<="11111111"; Y3<="11111111";
elsif adr="01" then
Y0<="11111111"; Y1<=we; Y2<="11111111"; Y3<="11111111";
elsif adr="10" then
Y0<="11111111"; Y1<="11111111"; Y2<=we; Y3<="11111111";
elsif adr="11" then
Y0<="11111111"; Y1<="11111111"; Y2<="11111111"; Y3<=we;
end if;
elsif oe='0' then
Y0<="11111111"; Y1<="11111111"; Y2<="11111111"; Y3<="11111111";
end if;
end process;
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_14.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity test_bench is
end entity test_bench;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture initial_test of test_bench is
use work.stimulus_types.all;
-- . . . -- component and signal declarations
-- not in book
signal dut_signals : std_logic_vector(0 to stimulus_vector_length - 1);
-- end not in book
begin
-- . . . -- instantiate design under test
stimulus_generation : process is
use work.stimulus_element_ordered_collection_adt.all;
variable stimulus_list : ordered_collection := new_ordered_collection;
variable next_stimulus_position : position;
variable next_stimulus : stimulus_element;
variable position_is_null : boolean;
begin
insert(stimulus_list, stimulus_element'(0 ns, "0XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(200 ns, "0000110110"));
insert(stimulus_list, stimulus_element'(300 ns, "10001ZZZZZ"));
insert(stimulus_list, stimulus_element'(50 ns, "1XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(60 ns, "1ZZZZZZZZZ"));
-- . . .
-- not in book
insert(stimulus_list, stimulus_element'(100 ns, "----------"));
search(stimulus_list, 100 ns, next_stimulus_position);
delete(next_stimulus_position);
get_element(next_stimulus_position, next_stimulus);
-- end not in book
find_first(stimulus_list, next_stimulus_position);
loop
test_null_position(next_stimulus_position, position_is_null);
exit when position_is_null;
get_element(next_stimulus_position, next_stimulus);
wait for next_stimulus.application_time - now;
dut_signals <= next_stimulus.pattern;
advance(next_stimulus_position);
end loop;
wait;
end process stimulus_generation;
end architecture initial_test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_14.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity test_bench is
end entity test_bench;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture initial_test of test_bench is
use work.stimulus_types.all;
-- . . . -- component and signal declarations
-- not in book
signal dut_signals : std_logic_vector(0 to stimulus_vector_length - 1);
-- end not in book
begin
-- . . . -- instantiate design under test
stimulus_generation : process is
use work.stimulus_element_ordered_collection_adt.all;
variable stimulus_list : ordered_collection := new_ordered_collection;
variable next_stimulus_position : position;
variable next_stimulus : stimulus_element;
variable position_is_null : boolean;
begin
insert(stimulus_list, stimulus_element'(0 ns, "0XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(200 ns, "0000110110"));
insert(stimulus_list, stimulus_element'(300 ns, "10001ZZZZZ"));
insert(stimulus_list, stimulus_element'(50 ns, "1XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(60 ns, "1ZZZZZZZZZ"));
-- . . .
-- not in book
insert(stimulus_list, stimulus_element'(100 ns, "----------"));
search(stimulus_list, 100 ns, next_stimulus_position);
delete(next_stimulus_position);
get_element(next_stimulus_position, next_stimulus);
-- end not in book
find_first(stimulus_list, next_stimulus_position);
loop
test_null_position(next_stimulus_position, position_is_null);
exit when position_is_null;
get_element(next_stimulus_position, next_stimulus);
wait for next_stimulus.application_time - now;
dut_signals <= next_stimulus.pattern;
advance(next_stimulus_position);
end loop;
wait;
end process stimulus_generation;
end architecture initial_test;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.